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Influence of mechanical bending and temperature on the threshold voltage instability of a-Si:H thin-film transistors under electrical stress
Solid-State Electronics 63 (2011) 55–59
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Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Influence of mechanical bending and temperature on the threshold voltage instability of a-Si:H thin-film transistors under electrical stress S.W. Taso a, T.C. Chang a,b,c,⇑, M.C. Wang d, S.C. Chen b, J. Lu b,c,e, C.F. Weng b, Y.F. Wei b, W.C. Wu b, Y. Shi e a
Department of Photonics, National Sun Yat-sen University, Kaohsiung 804, Taiwan, ROC Department of Physics, National Sun Yat-sen University, Kaohsiung 804, Taiwan, ROC c Center for Nanoscience and Nanotechnology, National Sun Yat-sen University, Kaohsiung 804, Taiwan, ROC d Physics Division, Institute of Nuclear Energy Research, Taiwan, ROC e Department of Physics and National Laboratory of Solid State Microstructures, Nanjing University, Nanjing 210093, People’s Republic of China b
a r t i c l e
i n f o
Article history: Received 23 November 2010 Received in revised form 15 March 2011 Accepted 8 May 2011 Available online 1 June 2011 The review of this paper was arranged by Dr. Y. Kuk
a b s t r a c t This paper studies the electrical characteristics of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) under flat and bending situations after AC/DC stress at different temperatures. Stress temperature was varied from 77 K to 400 K, and threshold voltage shifts were extracted to analyze degradation mechanisms. It was found that high temperature and mechanical bending played important roles under AC stress, with an enhanced stress effect resulting in a more serious degradation. This study also discusses the dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress. Ó 2011 Elsevier Ltd. All rights reserved.
Keywords: Amorphous silicon thin-film transistors Bending Stress
1. Introduction
2. Experiment
Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used as switching devices in active matrix liquid crystal displays (AMLCDs). Recently, portable communication systems fabricated on flexible substrates, including electronic paper, smart labels, displays for vehicles, and portable electronic devices, have become an important area of growth [1,2]. Previous reports [3–9] have studied the characteristics and instability of aSi:H TFTs under mechanical bending. However, the relationship between this instability under mechanical bending and AC stress frequencies has not been studied clearly. Therefore, clarifying the degradation mechanism for the electrical instability of a-Si:H TFTs under mechanical strains at different frequencies is quite valuable to the development of flexible electronics. In this work, a-Si TFTs were stressed using DC/AC signals under flat and bending situations to investigate the stress mechanism. In addition, to further clarify instability mechanisms, a-Si TFTs were also stressed at various temperatures from 77 K to 400 K.
Inverted-staggered back-channel-etched (BCE) a-Si:H TFTs were fabricated on a 50-lm-thick stainless steel foil substrate. The process temperature was fixed at 463 K. The detailed device fabrication process is as follows. Type-304 stainless steel foils were polished through a chemical–mechanical polishing process to reduce the surface roughness of the as-received stainless steel foils. To increase the device yield, a 500-nm-thick SiO2 planarization layer was coated on the foil surface by plasma-enhanced chemical vapor deposition (PECVD) to reduce the surface roughness from 10 nm to 5 nm. Then, 300 nm-thick Cr was sputtered and patterned as a gate electrode on the stainless steel foil substrate followed by a 300 nm-thick silicon– nitride (SiNx) layer, a 200 nm-thick a-Si:H active layer and a 50 nmthick n+-a-Si:H layer deposited by PECVD. After the definition of an aSi:H active region with lithography and dry etching processes, 300 nm-thick Al was evaporated and patterned as the source/drain electrode. The n+-a-Si:H layer in the TFTs channel region was etched using a source/drain pattern as a mask after the electrodes had been formed for the TFTs. The characteristics of TFT devices were L = 10 lm and W = 12 lm. For DC/AC stress performed under a flat situation, i.e., there was no external mechanical bending applied to the device, the TFT was termed as a flat TFT. Conversely, DC/AC stress performed under mechanical bending produced bended TFTs. Electri-
⇑ Corresponding author at: Department of Physics, National Sun Yat-sen University, Kaohsiung 804, Taiwan, ROC. Tel.: +886 7 5252000x3708; fax: +886 7 5253709. E-mail address: [email protected] (T.C. Chang). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.05.003
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cal stress temperature was ranged from 77 K to 400 K. The electrical characteristics before and after stress—including bending stress, where TFTs were subsequently flattened for measurement—were measured under a flat situation at 300 K in order to investigate the effects of bending and temperature on degradation. Fig. 1 shows a schematic cross section and top view of the bending direction of a-Si:H TFT. The a-Si:H TFTs on the stainless steel foil were strained by outward (tensile) cylindrical bending using an aluminum mold with a radius of 10 mm. The outward bending produced tensile strain, defined as positive radius, Rp (Rp = 10 mm). The strain to the top surface was estimated at approximately 0.0026, according to previous studies [3,10]. The bending direction reported in this study was parallel to the source/drain current path. Furthermore, an Agilent 41501B pulse generator and an Agilent 4156C semiconductor parameter analyzer were used to stress the TFTs and measure the transfer characteristics after DC and AC gate bias stresses. The peak voltage (Vp) was 15 V and the base voltage (Vb) was 0 V for the AC signal. The DC stress condition was kept at 15 V. Each stress time was 1000 s. The stress signal was exerted on the gate terminal, with source/ drain terminals grounded during stress duration. In addition, all the transfer characteristics (ID–VG) before and after stress were measured at VD = 1 V, VD = 10 V under a flat situation. Threshold voltage is defined as the ID–VG curve determined from Ion extrapolation in the linear region, where VD = 1 V. Threshold voltage shift (DVt) is defined as Vt2–Vt1, where Vt1 is the threshold voltage before stress and Vt2 is the threshold voltage after stress. 3. Results and discussion Fig. 2 shows the threshold voltage shift (DVt) of flat (circle) and bended (square) a-Si:H TFTs at different DC stress temperatures (T). Clearly, the DVt in both TFTs increases as temperature rises, showing a similar trend to that found in previous report [11]. According to the report, there are two prominent instability mechanisms in a-Si TFTs, namely, the state creation in the a-Si:H and the charge trapping in the SiNx gate insulator. The temperature-dependent threshold voltage shift with a low DC gate bias stress is mainly dominated by state creation. The weak temperature-dependent threshold voltage shift with a larger bias stress is mainly dominated by charge trapping. Accordingly, in this work, the main degradation mechanism is state creation in both of the flat and bended a-Si:H TFTs. The DVt of flat (triangle up) and bended (triangle down) a-Si:H TFTs at different AC stress temperatures is also shown in Fig. 2. AC stress is performed with a gate voltage (VG) pulse from base to peak
Fig. 1. Schematic cross section and top view of a-Si:H TFTs. The arrows indicate the bending direction parallel to the source/drain current path.
Fig. 2. Temperature (T) versus threshold voltage shift (DVt) of a-Si:H TFTs under tensile bending and flat after DC stress and AC stress.
voltage of 0 V (Vb) to 15 V (Vp) and a signal frequency (f) of 100 Hz, where rising time (Tr) and falling time (Tf) are fixed at 100 ns. In addition, the duty ratio is kept at 50%, and is defined as the percentage of time at peak voltage in a signal time period. Compared with the flat TFT, the DVt of bended a-Si:H TFTs after AC stress abruptly increased at 400 K. This result is clearly different from that after DC stress. In order to clarify the reason for this marked difference, threshold voltage shifts for flat a-Si:H TFT devices after both AC (triangle up) and DC (circle) stress are discussed. Clearly, the DVt after DC stress is higher than after AC stress. To analyze the reasons for this, the AC stress signal has been separated into four parts as shown in Fig. 3a, which are the time of base voltage (TVb), the time of peak voltage (TVp), Tr and Tf. Because the device is not stressed during TVb (Vb = 0 V), the actual stress time under AC stress is the accumulated sum of TVp, Tr and Tf. Degradation, however, does not occur during all these time intervals. According to a previous work [12], the shifts of threshold voltage are independent of AC frequencies but dependent on the duty ratio. These results reveal that degradation only occurs during TVp, but not during Tr and Tf. Additional support can be found from the fact that DVt increases with an increase in duty ratio for positive AC bias stress, because a larger duty ratio has a longer TVp. As a result, in this work, Tr and Tf will not affect the DVt for flat a-Si:H TFT devices. In addition, Tr and Tf are kept quite short, and thus are insignificant compared to TVp. Therefore, the accumulated sum of TVp is the major effective stress time under AC stress. Comparing AC and DC effective stress time, AC effective stress time is half of DC entire stress time, and is shown as the red region in Fig. 3a. Consequently, DVt after AC stress is less than that after DC stress due to a shorter effective stress time. Temperature versus DVt of a-Si:H TFTs under tensile bending after DC (square) and AC (triangle down) stress is compared in Fig. 2. The DVt under AC stress condition is still less than that under DC at 77 K, 200 K and 300 K. Surprisingly, the DVt shows an entirely different nature at 400 K, such that the DVt under AC condition is more severe than under DC. This phenomenon indicates that the degradation is dominated by a different effect at high temperature. Here, DVt is not affected merely by effective stress time (i.e. the accumulated sum of TVp). Since the phenomenon is not observed under the flat condition under AC stress (triangle up) at 400 K as shown in Fig. 2, obviously the bending effect plays an important role. Rather than the accumulated sum of TVp being the main influence on DVt, the accumulated sum of Tr and Tf which is affected by the signal frequency becomes most influential. In order to analyze this anomalous phenomenon, the a-S:H TFTs are stressed with different frequencies. Fig. 4a shows the gate voltage versus drain current of a-Si:H TFTs after different stress frequencies under the
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Fig. 3. (a) Waveform and definition of the AC signal and comparison of AC and DC effective stress time. Effective stress time is indicated in red. (b) Rising time (Tr) and falling time (Tf) as additional effective stress time during AC stress under bending at 400 K. Effective stress time is indicated in red and blue. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
Fig. 5. Hydrogen and Si–Si bond reaction mechanism.
Fig. 4. (a) Transfer characteristics (ID–VG) of a-Si:H TFTs after stress at different frequencies under bending at 400 K. (b) Comparison of stress frequency versus DVt for bended a-Si:H TFTs.
bending situation at 400 K. As can be clearly seen, the DVt of a-Si:H TFTs after stress with 200 Hz is larger than that at 100 Hz. Here the stress condition of f = 200 Hz is the same as that of f = 100 Hz (VG = 15/0 V, Tr = Tf = 100 ns, duty ratio = 50%, and stress time = 1000 s.). Therefore, the accumulated sum of Tr and Tf is double of f = 100 Hz. The threshold voltage shifts after 400 K DC stress and after 400 K AC stress at 100 Hz and 200 Hz frequencies are shown in Fig. 4b. The DVt after AC stress is larger than that after DC stress and increases as AC stress frequency increases. This suggests that Tr and Tf of the AC stress signal become effective under the bending
situation at 400 K and affect the DVt, which are shown as the blue regions in Fig. 3b. Therefore, the effective stress time is the accumulated sum of TVp, Tr and Tf under the bending situation at 400 K. Fig. 5 depicts an a-Si:H film composed of Si–Si normal bonds, weak bonds, dangling bonds and Si–H hydrogen passivated bonds [13]. Because the threshold voltage shift is mainly caused by generation of traps, the related mechanisms should be considered, including reactions between H atoms and Si–Si weak bonds and between electrons and Si–Si weak bonds. There are two types of reaction mechanisms between hydrogen atoms and Si–Si weak bonds [14–16]. One is doubly hydrogenated silicon bonds (SiH HSi) that react with weak Si–Si bonds to form two defect states (2(SiH DSi)) where D is a dangling bond, which increases the number of deep states, therefore increasing the threshold voltage. The other reaction is the related recovery mechanism that occurs when one of the H atoms flips back to (SiH DSi) to passivate the dangling bonds, thereby hydrogenating it once more. The two DSi reform a weak Si–Si bond, and the two dangling bonds are annihilated. This causes the reduction of the threshold voltage by decreasing the deep states. The activation energy of the 2(SiH DSi) state transferring to ((SiH HSi) + Si–Si) state is higher than for the reverse [17]. Accordingly, the dangling bonds are produced easily while external energy is applied.
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Fig. 6. Illustration of AC stress mechanisms. (a) At VG = 0 V, there are no electrons in channel. (b) At VG = 15 V, electrons enter channel. (c) At VG = 15 V and returning to 0 V, the electrons leave the channel and obtain kinetic energy in the region of a strong electric field near the drain/source junction.
Another mechanism responsible for dangling bond formation is the reaction between electrons and Si–Si weak bonds. According to previous report [18], the rate of creation of dangling bonds depends on the number of electrons with enough kinetic energy, the density of Si–Si weak bonds, and the energy barrier to break Si–Si weak bonds. Accordingly, electrical stressed a-Si:H TFTs under mechanical bending have larger threshold voltage shift (i.e. more dangling bonds), possibly resulting from the increase of electron mobility, the increase of density of Si–Si weak bonds, or a lowering of energy for breaking Si–Si weak bonds. That is, electrons with higher mobility under tensile strain have higher kinetic energy to break Si–Si weak bonds. In addition, such results imply that mechanical bending increases the density of Si–Si weak bonds and lowers the energy for breaking the Si–Si weak bonds. However, the increase of electron mobility under tensile strain is less than 5% [7]. It seems not to have much effect on the threshold voltage shift. Reasonably, it can be concluded that mechanical bending actually increases the density of Si–Si weak bonds and lowers the energy for breaking the Si–Si weak bonds. At high temperature, the energy provided from a heating source will broaden the band-tail states to increase the number of Si–Si weak bond [19]. Hence, more dangling bonds (deep states) are generated by hydrogen reacting with additional Si–Si weak bonds, resulting in the incremental change of DVt under identical stress condition. In addition, under mechanical bending, the energy for breaking Si–Si weak bonds is lowered further and the density of Si–Si weak bonds increases. Thus, it is easier for Si–Si weak bonds to react with hydrogen to produce defect states (SiH DSi). Mechanical bending and high temperature conditions together, therefore, produce DVt values that are higher than for the flat situation after stress, which can be confirmed in Fig. 2. In addition to the H reaction degradation mechanism, another mechanism affects the AC stress/high temperature degradation. Degradation of TFTs after AC stress has been reported as being due to the reaction between electrons and Si–Si weak bonds [20–23]. Fig. 6a–c is the schematic of how AC stress leads to the deterioration of device characteristics. When VG = 0 V, there are no electrons in the channel (Fig. 6a). As VG increases to 15 V, numbers of electrons flow into the channel from both the source and drain of the TFT device (Fig. 6b). As VG returns to its low (VG = 15–0 V), the potential barrier between the gate and the source/drain becomes high, and the electrons leave the channel
(Fig. 6c). The energy band diagram then returns to the initial state (VG = 0 V) (Fig. 6a). In general, for poly-Si TFTs, electrons will obtain kinetic energy from a strong electric field in the drain/source junction and then break the Si–Si bonds during process depicted in Fig. 6c [20–23]. For flat a-Si:H TFTs, electron mobility is too small that electrons cannot obtain enough kinetic energy to cause impact ionization in the drain/source depletion region under AC stress. Thus, the DVt of flat a-Si:H TFTs under AC stress is independent of the accumulated sum of Tr and Tf. However, as the bended a-Si:H TFT is stressed at 400 K, thermal energy and mechanical bending reduce the Si–Si bond strength resulting in the increase of weaker Si–Si bonds, increasing the likelihood of dangling bonds formed by impact-ionization in the drain/source depletion region. In this work, both the effective stress time and the AC stress frequency were found to be factors in degradation of the bended a-Si:H TFT. Therefore, the DVt of bended a-Si:H TFTs after AC stress were significantly larger than for flat TFTs at high temperature.
4. Conclusion The threshold voltage shifts of a-Si:H TFTs under flat and bending situation after AC/DC stress at different temperatures were studied. It was found that the threshold voltage shifts under flat situation were only dependent on the effective stress time (i.e. the accumulated sum of TVp) during DC and AC stress and did not exhibit the same phenomenon as under bending situation. Under bending, the accumulated sum of Tr and Tf also contribute to degrade threshold voltage at high temperature, because both thermal energy and mechanical bending reduce the Si–Si bond strength. In addition, there are two contributive mechanisms of dangling bond formation. First, hydrogen reacts with weak Si–Si bonds in an aSi:H layer. Second, electrons act to break weak Si–Si bonds in the drain/source depletion region.
Acknowledgment This work was partially supported by the National Science Council of the Republic of China under Contract Nos. NSC-992120-M-110-001 and NSC-97-2112-M-110-009-MY3.
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Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Influence of mechanical bending and temperature on the threshold voltage instability of a-Si:H thin-film transistors under electrical stress S.W. Taso a, T.C. Chang a,b,c,⇑, M.C. Wang d, S.C. Chen b, J. Lu b,c,e, C.F. Weng b, Y.F. Wei b, W.C. Wu b, Y. Shi e a
Department of Photonics, National Sun Yat-sen University, Kaohsiung 804, Taiwan, ROC Department of Physics, National Sun Yat-sen University, Kaohsiung 804, Taiwan, ROC c Center for Nanoscience and Nanotechnology, National Sun Yat-sen University, Kaohsiung 804, Taiwan, ROC d Physics Division, Institute of Nuclear Energy Research, Taiwan, ROC e Department of Physics and National Laboratory of Solid State Microstructures, Nanjing University, Nanjing 210093, People’s Republic of China b
a r t i c l e
i n f o
Article history: Received 23 November 2010 Received in revised form 15 March 2011 Accepted 8 May 2011 Available online 1 June 2011 The review of this paper was arranged by Dr. Y. Kuk
a b s t r a c t This paper studies the electrical characteristics of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) under flat and bending situations after AC/DC stress at different temperatures. Stress temperature was varied from 77 K to 400 K, and threshold voltage shifts were extracted to analyze degradation mechanisms. It was found that high temperature and mechanical bending played important roles under AC stress, with an enhanced stress effect resulting in a more serious degradation. This study also discusses the dependence between the accumulated sum of bias rising and falling time and the threshold voltage shifts under AC stress. Ó 2011 Elsevier Ltd. All rights reserved.
Keywords: Amorphous silicon thin-film transistors Bending Stress
1. Introduction
2. Experiment
Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used as switching devices in active matrix liquid crystal displays (AMLCDs). Recently, portable communication systems fabricated on flexible substrates, including electronic paper, smart labels, displays for vehicles, and portable electronic devices, have become an important area of growth [1,2]. Previous reports [3–9] have studied the characteristics and instability of aSi:H TFTs under mechanical bending. However, the relationship between this instability under mechanical bending and AC stress frequencies has not been studied clearly. Therefore, clarifying the degradation mechanism for the electrical instability of a-Si:H TFTs under mechanical strains at different frequencies is quite valuable to the development of flexible electronics. In this work, a-Si TFTs were stressed using DC/AC signals under flat and bending situations to investigate the stress mechanism. In addition, to further clarify instability mechanisms, a-Si TFTs were also stressed at various temperatures from 77 K to 400 K.
Inverted-staggered back-channel-etched (BCE) a-Si:H TFTs were fabricated on a 50-lm-thick stainless steel foil substrate. The process temperature was fixed at 463 K. The detailed device fabrication process is as follows. Type-304 stainless steel foils were polished through a chemical–mechanical polishing process to reduce the surface roughness of the as-received stainless steel foils. To increase the device yield, a 500-nm-thick SiO2 planarization layer was coated on the foil surface by plasma-enhanced chemical vapor deposition (PECVD) to reduce the surface roughness from 10 nm to 5 nm. Then, 300 nm-thick Cr was sputtered and patterned as a gate electrode on the stainless steel foil substrate followed by a 300 nm-thick silicon– nitride (SiNx) layer, a 200 nm-thick a-Si:H active layer and a 50 nmthick n+-a-Si:H layer deposited by PECVD. After the definition of an aSi:H active region with lithography and dry etching processes, 300 nm-thick Al was evaporated and patterned as the source/drain electrode. The n+-a-Si:H layer in the TFTs channel region was etched using a source/drain pattern as a mask after the electrodes had been formed for the TFTs. The characteristics of TFT devices were L = 10 lm and W = 12 lm. For DC/AC stress performed under a flat situation, i.e., there was no external mechanical bending applied to the device, the TFT was termed as a flat TFT. Conversely, DC/AC stress performed under mechanical bending produced bended TFTs. Electri-
⇑ Corresponding author at: Department of Physics, National Sun Yat-sen University, Kaohsiung 804, Taiwan, ROC. Tel.: +886 7 5252000x3708; fax: +886 7 5253709. E-mail address: [email protected] (T.C. Chang). 0038-1101/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2011.05.003
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cal stress temperature was ranged from 77 K to 400 K. The electrical characteristics before and after stress—including bending stress, where TFTs were subsequently flattened for measurement—were measured under a flat situation at 300 K in order to investigate the effects of bending and temperature on degradation. Fig. 1 shows a schematic cross section and top view of the bending direction of a-Si:H TFT. The a-Si:H TFTs on the stainless steel foil were strained by outward (tensile) cylindrical bending using an aluminum mold with a radius of 10 mm. The outward bending produced tensile strain, defined as positive radius, Rp (Rp = 10 mm). The strain to the top surface was estimated at approximately 0.0026, according to previous studies [3,10]. The bending direction reported in this study was parallel to the source/drain current path. Furthermore, an Agilent 41501B pulse generator and an Agilent 4156C semiconductor parameter analyzer were used to stress the TFTs and measure the transfer characteristics after DC and AC gate bias stresses. The peak voltage (Vp) was 15 V and the base voltage (Vb) was 0 V for the AC signal. The DC stress condition was kept at 15 V. Each stress time was 1000 s. The stress signal was exerted on the gate terminal, with source/ drain terminals grounded during stress duration. In addition, all the transfer characteristics (ID–VG) before and after stress were measured at VD = 1 V, VD = 10 V under a flat situation. Threshold voltage is defined as the ID–VG curve determined from Ion extrapolation in the linear region, where VD = 1 V. Threshold voltage shift (DVt) is defined as Vt2–Vt1, where Vt1 is the threshold voltage before stress and Vt2 is the threshold voltage after stress. 3. Results and discussion Fig. 2 shows the threshold voltage shift (DVt) of flat (circle) and bended (square) a-Si:H TFTs at different DC stress temperatures (T). Clearly, the DVt in both TFTs increases as temperature rises, showing a similar trend to that found in previous report [11]. According to the report, there are two prominent instability mechanisms in a-Si TFTs, namely, the state creation in the a-Si:H and the charge trapping in the SiNx gate insulator. The temperature-dependent threshold voltage shift with a low DC gate bias stress is mainly dominated by state creation. The weak temperature-dependent threshold voltage shift with a larger bias stress is mainly dominated by charge trapping. Accordingly, in this work, the main degradation mechanism is state creation in both of the flat and bended a-Si:H TFTs. The DVt of flat (triangle up) and bended (triangle down) a-Si:H TFTs at different AC stress temperatures is also shown in Fig. 2. AC stress is performed with a gate voltage (VG) pulse from base to peak
Fig. 1. Schematic cross section and top view of a-Si:H TFTs. The arrows indicate the bending direction parallel to the source/drain current path.
Fig. 2. Temperature (T) versus threshold voltage shift (DVt) of a-Si:H TFTs under tensile bending and flat after DC stress and AC stress.
voltage of 0 V (Vb) to 15 V (Vp) and a signal frequency (f) of 100 Hz, where rising time (Tr) and falling time (Tf) are fixed at 100 ns. In addition, the duty ratio is kept at 50%, and is defined as the percentage of time at peak voltage in a signal time period. Compared with the flat TFT, the DVt of bended a-Si:H TFTs after AC stress abruptly increased at 400 K. This result is clearly different from that after DC stress. In order to clarify the reason for this marked difference, threshold voltage shifts for flat a-Si:H TFT devices after both AC (triangle up) and DC (circle) stress are discussed. Clearly, the DVt after DC stress is higher than after AC stress. To analyze the reasons for this, the AC stress signal has been separated into four parts as shown in Fig. 3a, which are the time of base voltage (TVb), the time of peak voltage (TVp), Tr and Tf. Because the device is not stressed during TVb (Vb = 0 V), the actual stress time under AC stress is the accumulated sum of TVp, Tr and Tf. Degradation, however, does not occur during all these time intervals. According to a previous work [12], the shifts of threshold voltage are independent of AC frequencies but dependent on the duty ratio. These results reveal that degradation only occurs during TVp, but not during Tr and Tf. Additional support can be found from the fact that DVt increases with an increase in duty ratio for positive AC bias stress, because a larger duty ratio has a longer TVp. As a result, in this work, Tr and Tf will not affect the DVt for flat a-Si:H TFT devices. In addition, Tr and Tf are kept quite short, and thus are insignificant compared to TVp. Therefore, the accumulated sum of TVp is the major effective stress time under AC stress. Comparing AC and DC effective stress time, AC effective stress time is half of DC entire stress time, and is shown as the red region in Fig. 3a. Consequently, DVt after AC stress is less than that after DC stress due to a shorter effective stress time. Temperature versus DVt of a-Si:H TFTs under tensile bending after DC (square) and AC (triangle down) stress is compared in Fig. 2. The DVt under AC stress condition is still less than that under DC at 77 K, 200 K and 300 K. Surprisingly, the DVt shows an entirely different nature at 400 K, such that the DVt under AC condition is more severe than under DC. This phenomenon indicates that the degradation is dominated by a different effect at high temperature. Here, DVt is not affected merely by effective stress time (i.e. the accumulated sum of TVp). Since the phenomenon is not observed under the flat condition under AC stress (triangle up) at 400 K as shown in Fig. 2, obviously the bending effect plays an important role. Rather than the accumulated sum of TVp being the main influence on DVt, the accumulated sum of Tr and Tf which is affected by the signal frequency becomes most influential. In order to analyze this anomalous phenomenon, the a-S:H TFTs are stressed with different frequencies. Fig. 4a shows the gate voltage versus drain current of a-Si:H TFTs after different stress frequencies under the
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Fig. 3. (a) Waveform and definition of the AC signal and comparison of AC and DC effective stress time. Effective stress time is indicated in red. (b) Rising time (Tr) and falling time (Tf) as additional effective stress time during AC stress under bending at 400 K. Effective stress time is indicated in red and blue. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
Fig. 5. Hydrogen and Si–Si bond reaction mechanism.
Fig. 4. (a) Transfer characteristics (ID–VG) of a-Si:H TFTs after stress at different frequencies under bending at 400 K. (b) Comparison of stress frequency versus DVt for bended a-Si:H TFTs.
bending situation at 400 K. As can be clearly seen, the DVt of a-Si:H TFTs after stress with 200 Hz is larger than that at 100 Hz. Here the stress condition of f = 200 Hz is the same as that of f = 100 Hz (VG = 15/0 V, Tr = Tf = 100 ns, duty ratio = 50%, and stress time = 1000 s.). Therefore, the accumulated sum of Tr and Tf is double of f = 100 Hz. The threshold voltage shifts after 400 K DC stress and after 400 K AC stress at 100 Hz and 200 Hz frequencies are shown in Fig. 4b. The DVt after AC stress is larger than that after DC stress and increases as AC stress frequency increases. This suggests that Tr and Tf of the AC stress signal become effective under the bending
situation at 400 K and affect the DVt, which are shown as the blue regions in Fig. 3b. Therefore, the effective stress time is the accumulated sum of TVp, Tr and Tf under the bending situation at 400 K. Fig. 5 depicts an a-Si:H film composed of Si–Si normal bonds, weak bonds, dangling bonds and Si–H hydrogen passivated bonds [13]. Because the threshold voltage shift is mainly caused by generation of traps, the related mechanisms should be considered, including reactions between H atoms and Si–Si weak bonds and between electrons and Si–Si weak bonds. There are two types of reaction mechanisms between hydrogen atoms and Si–Si weak bonds [14–16]. One is doubly hydrogenated silicon bonds (SiH HSi) that react with weak Si–Si bonds to form two defect states (2(SiH DSi)) where D is a dangling bond, which increases the number of deep states, therefore increasing the threshold voltage. The other reaction is the related recovery mechanism that occurs when one of the H atoms flips back to (SiH DSi) to passivate the dangling bonds, thereby hydrogenating it once more. The two DSi reform a weak Si–Si bond, and the two dangling bonds are annihilated. This causes the reduction of the threshold voltage by decreasing the deep states. The activation energy of the 2(SiH DSi) state transferring to ((SiH HSi) + Si–Si) state is higher than for the reverse [17]. Accordingly, the dangling bonds are produced easily while external energy is applied.
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Fig. 6. Illustration of AC stress mechanisms. (a) At VG = 0 V, there are no electrons in channel. (b) At VG = 15 V, electrons enter channel. (c) At VG = 15 V and returning to 0 V, the electrons leave the channel and obtain kinetic energy in the region of a strong electric field near the drain/source junction.
Another mechanism responsible for dangling bond formation is the reaction between electrons and Si–Si weak bonds. According to previous report [18], the rate of creation of dangling bonds depends on the number of electrons with enough kinetic energy, the density of Si–Si weak bonds, and the energy barrier to break Si–Si weak bonds. Accordingly, electrical stressed a-Si:H TFTs under mechanical bending have larger threshold voltage shift (i.e. more dangling bonds), possibly resulting from the increase of electron mobility, the increase of density of Si–Si weak bonds, or a lowering of energy for breaking Si–Si weak bonds. That is, electrons with higher mobility under tensile strain have higher kinetic energy to break Si–Si weak bonds. In addition, such results imply that mechanical bending increases the density of Si–Si weak bonds and lowers the energy for breaking the Si–Si weak bonds. However, the increase of electron mobility under tensile strain is less than 5% [7]. It seems not to have much effect on the threshold voltage shift. Reasonably, it can be concluded that mechanical bending actually increases the density of Si–Si weak bonds and lowers the energy for breaking the Si–Si weak bonds. At high temperature, the energy provided from a heating source will broaden the band-tail states to increase the number of Si–Si weak bond [19]. Hence, more dangling bonds (deep states) are generated by hydrogen reacting with additional Si–Si weak bonds, resulting in the incremental change of DVt under identical stress condition. In addition, under mechanical bending, the energy for breaking Si–Si weak bonds is lowered further and the density of Si–Si weak bonds increases. Thus, it is easier for Si–Si weak bonds to react with hydrogen to produce defect states (SiH DSi). Mechanical bending and high temperature conditions together, therefore, produce DVt values that are higher than for the flat situation after stress, which can be confirmed in Fig. 2. In addition to the H reaction degradation mechanism, another mechanism affects the AC stress/high temperature degradation. Degradation of TFTs after AC stress has been reported as being due to the reaction between electrons and Si–Si weak bonds [20–23]. Fig. 6a–c is the schematic of how AC stress leads to the deterioration of device characteristics. When VG = 0 V, there are no electrons in the channel (Fig. 6a). As VG increases to 15 V, numbers of electrons flow into the channel from both the source and drain of the TFT device (Fig. 6b). As VG returns to its low (VG = 15–0 V), the potential barrier between the gate and the source/drain becomes high, and the electrons leave the channel
(Fig. 6c). The energy band diagram then returns to the initial state (VG = 0 V) (Fig. 6a). In general, for poly-Si TFTs, electrons will obtain kinetic energy from a strong electric field in the drain/source junction and then break the Si–Si bonds during process depicted in Fig. 6c [20–23]. For flat a-Si:H TFTs, electron mobility is too small that electrons cannot obtain enough kinetic energy to cause impact ionization in the drain/source depletion region under AC stress. Thus, the DVt of flat a-Si:H TFTs under AC stress is independent of the accumulated sum of Tr and Tf. However, as the bended a-Si:H TFT is stressed at 400 K, thermal energy and mechanical bending reduce the Si–Si bond strength resulting in the increase of weaker Si–Si bonds, increasing the likelihood of dangling bonds formed by impact-ionization in the drain/source depletion region. In this work, both the effective stress time and the AC stress frequency were found to be factors in degradation of the bended a-Si:H TFT. Therefore, the DVt of bended a-Si:H TFTs after AC stress were significantly larger than for flat TFTs at high temperature.
4. Conclusion The threshold voltage shifts of a-Si:H TFTs under flat and bending situation after AC/DC stress at different temperatures were studied. It was found that the threshold voltage shifts under flat situation were only dependent on the effective stress time (i.e. the accumulated sum of TVp) during DC and AC stress and did not exhibit the same phenomenon as under bending situation. Under bending, the accumulated sum of Tr and Tf also contribute to degrade threshold voltage at high temperature, because both thermal energy and mechanical bending reduce the Si–Si bond strength. In addition, there are two contributive mechanisms of dangling bond formation. First, hydrogen reacts with weak Si–Si bonds in an aSi:H layer. Second, electrons act to break weak Si–Si bonds in the drain/source depletion region.
Acknowledgment This work was partially supported by the National Science Council of the Republic of China under Contract Nos. NSC-992120-M-110-001 and NSC-97-2112-M-110-009-MY3.
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