Simulation of the lateral electrical field for the analysis of threshold voltage instabilities of suspended-gate field-effect transistors

Sensors andActuators $ 12( 1993)231-235

231

Simulation of the lateral electrical field for the analysis of threshold voltage instabilities of suspended-gate field-effect transistors Z. Ger~tsch~w,

IX ~~panski

and P. Ko~~~ky

lnstitut fir Festk~rpere~ektron~, Fakult& $2 ~ektrotec~~

und ~n~o~atio~t~~,

Teehniwhe Universitiit Hnenau,

D-98684 Ihnenuu (Germany)

I. Eisele and B. Flietner Imtitutfk Physik, F’ttcit fiir E~ktrotechn~,

Unkwsit& der Bundeswehr hfiinckerz, D-855377&&berg

{Germany)

(Received July 13, 1992;in revised form. January 13, 1993;accepted February 5, 1993)

Abstract The adsorption at the open insulator surface under the air gap of suspended-gate field-effect transistors (SGFETs), which leads to mobile charges, and their r~~bution due to lateral clectrica~field strengths are two of the reasons for the threshold voltage ins~bility of these gas sensors. A two-dimensional computer simulation has been carried out to determine the lateral electrical field in the device, especially in the gate insulator area. The evaluation of the modelling results has led to useful conclusions about the design optimization of the sensor and its operating

conditions.

The basic principles of using field-effect transistors (FETs) as gas sensors are well known [ 11. One approach is the fabrication of a suspended gate on a metal-ins~ator-~~conduc~r (MIS) device [2,3]. An air gap is formed between the gate and the insulator with a spacer technology. The desired chemical response originafes from the chemisorption or pbysisorption of gaseous species at the sensitive layer, which is located directly underneath the gate metallization. Figure 1 shows a schematic diagram of one of these devices. They are ~stin~shed by a short response time, a high sensitivity and the possibility of simultaneous integration in signal-processing circuits.

According to the sensitive layer us&, we observe in the test samples so far produced and measured a response to oxidizing and reducing gases such as NO?, H2 and NH, [4]. Apart from these advantageous properties, however, we have also found a drift in some of the transistor parameters. A measured drift of the channei conductivity of a SGFET after a gate-to-source voltage step from 0 to 1 V at a constant drain-to-source voltage, temperature, gas flow and gas compound is shown in Fig. 2. These drifts are caused by threshold voltage instabilities. In this paper we give some e~p~nations of this

I

I20 10

t 0

Fig. 1. Schematic diagram of a SGFET gas sensor.

20

L

40

60

I

80

I

0

100 120 time [mini

Fig. 2. Measured drift of the channel condukvity of a SGFET (W/L = 1) after a gate-to-source voltage step.

@ 1993 - Elsexkr Sequoia.All rights reserved

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phenomenon. In ref. 5 a connection is shown between the electrical field distribution in the transistor and its instabilities, caused by the motion of mobile charges in the gate insulator layers, at their interfaces and on the open insulator surface.

2. Modelling of the field strengths in a SGFET

Si

Since one reason for the drift, according to ref. 5, was supposedly the lateral electrical field strength, twodimensional computer modelling has been carried out. The simulation programs MINIMOS [6], from the TU Vienna, and BLOCKSIM [7], which has been developed at the Research Group for Solid-State Electronics at the TH Ilmenau, have been used. Both programs solve the basic semiconductor equations using the finite-difference method. MINIMOS solves the Poisson eqn. (l), and the two continuity eqns. (2) and (3); BLOCKSIM solves the Poisson equation for the blocking state of the electronic devices:

lator

insu-

divsgradcp=

-e(p -n +N,+ -NA-)

(1)

an

at = div J. + G - R ap=-&vJ

at

P+G-R

(3)

where n,p are the carrier concentrations; J,,, Jp the particle current densities of electrons and holes; G, R the generation and recombination rates; E the dielectric constant; cp the electric potential; e the elementary charge; and NA-, ND+ the concentrations of ionized acceptors and donors. BLOCKSIM has the advantage of an exact description of the gate area with the multilayer insulator and the specific shape of the SGFET gate electrode, while MINIMOS does not offer this possibility. The simulation has been carried out for a device with a double insulator layer consisting of 100 nm Si02 and 100 nm S&N,, with a 300 nm air gap, a ratio WL = 1 (channel width = channel length = 20 pm) and a threshold voltage Vth= - 1.6 V. Palladium was used as the sensitive layer.

Fig. 3. Lateral field strength v,, = 2 v (c, see text).

in a SGFET

at Vds= 3 V and

nounced. It rises to - 17.7 kV/cm immediately under the Si-SiOl interface. This field strength spreads in the gate insulator and amounts to -7.1 kV/cm at the open insulator surface (Fig. 3(c)). 3.2. Lateral field strength at the open side edges of the gate electrode Figure 4 shows a lateral component of the electrical field strength occurring due to the inhomogeneous potential field behaviour at the open side edges of the gate electrode. This field strength spreads into the gate insulator. The result of the simulation of this field at the open insulator surface for a gate voltage I’,%= 2 V and a drain-to-source voltage V,,, = 2 V is represented in Fig. 4. The field strengths have a symmetrical distribution at both gate sides. There are maximum values at 2.8 and -2.8 kV/cm, which are located directly under the open side edges of the gate electrode. These field strengths are caused by the voltage between the gate and silicon bulk and therefore decrease near the drain. The field fades away outside the gate

2 1 0 -1 -2

3. Simulation results 3.1. Lateral jield strengths due to supplied drain-to-source voltage Figure 3 shows the results of the simulation of the field strength distribution in the device, which is caused by the supply of a drain-to-source voltage VdS= 3 V. There are two field-strength peaks, the peak at the drain side end of the channel being particularly pro-

25

y [ml

”

-5

Fig. 4. Lateral field strengths on the side edges of the gate electrode of a SGFET on the open insulator surface at Vdn= V, = 2 V (a, b, see text).

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electrode in the lateral direction in a distance a = 4 )Irn (Fig. 4). There are field strengths below the gate electrode up to b = 0.5 pm (Fig. 4) from the side edges. 3.3. Lateral field strength due to the steps in the shape of the structure layers There are steps in the shape of several layers, which

are caused by the design and technology of the SGFET. Figure 5 demonstrates this fact: (I) a 80 run step at the silicon surface and in the above layers originates from the different oxide growth during the field oxidation of p and n+ silicon [4]. (II) a 40 nm step at the silicon surface originates from silicon consumption during the gate oxidation. (III) a 600 nm step in the gate electrode at the transition onto the field oxide [4]. (IV) a 300 nm step in the gate electrode, caused by the transition of the metallization onto the spacer, which is etched to achieve the air gap. In order to describe the lateral field at these places, a two-dimensional simulation of the structure from Fig. 5 has been carried out with the BLOCKSIM program for a gate-to-source voltage V, = 2 V. Figure 6 shows the results of this calculation. The lateral field strengths, which originate at steps (I) and (II), are small enough to be neglected. A high field strength of 75 kV/cm occurs at step (III) at the transition of the gate metallization

onto the field oxide. The

I-I gate

SiO2

III

S& 1

IV$r

gap ‘I

II source

n+ Si

i

P

I

Fig. 5. Shape of the layers at the connection of the gate electrode with the insulator of a SGFET.

Fig. 7. Lateral field strength caused by the pn junctions of a SGFET source and drain at V, = 0 V; the gate electrode was disregarded.

lateral field strength at step (IV) amounts to - 72 kV/cm and spreads directly around the open insulator surface and the transistor inversion channel. 3.4. Lateral field strength caused by the diyision voltage of the pn junctions at the source and drain regions Relatively highly doped pn junctions are caused by manufacturing the source and drain regions of the SGFET [4]. The calculated diffusion voltage is 0.8 V. The results of the simulation of the lateral field strength at the pn junctions and their spread into the gate insulator are shown in Fig. 7. The field strength occurs becahse of the pn junctions from the n+ diffusion regions. It spreads directly under the Si-SiO? interface in the lateral direction. This calculation has been carried out at V,, = DV, the gate electrode was not taken into account and a thicker gate insulator layer was assumed so that the complete field spreading could be shown. The field strength peaks at the open insulator surface amount ‘to 4.5 kV/cm at the source and -4.5 kV/cm at the drain.

4. Discussion

Fig. 6. Lateral field strength at the metallization steps at the connection of the gate electrode with the insulator of a SGFET at v,. = 2 v.

The results of the simulation of Section 3.1 show, on the one hand, that the lateral field strength in the device increases with the drain-to-source voltage and, on the other hand, that it spreads better in the gate insulator at higher V,, because of the reduction by the partly screening inversion channel. This explains the better drift behaviour of the sensor during operation at a lower drain-to-source voltage, which is applied according to impulse or a.c. measurement methods [5].

234 field

implantation

~

field

implantation

Fig. 8. A SGFET with a gate electrode that overlaps the channel stop region. The lateral field strengths calculated by the simulation of the open side edges of the gate electrode (Sec-

tion 3.2) can lead to a transport and r~istribution of charges in the gate insulator region, too, and so they can cause a variation of the conductivity at the sides of the inversion channel. This results in a threshold voltage drift of the transistor. So it is proposed to widen the gate electrode about the channel, so that it overlaps the channel stop region by 2-3 pm. In this way, effects of changing and moveable charges in the gate insulator are unable to influence the transistor channel. Figure 8 shows a schematic example of the design bf a structure like this. The electrical field strength of 7.5kV/cm, which occurs at step (III) (Figs. 5 and 6) spreads only in SQ and Si,N, and, therefore, cannot contribute greatly to a transistor threshold voltage drift. The high values of the lateral field strength, which arise at step (IV) (Figs. 5 and 6) and the fact that it spreads directly in the air gap determine the strong influence of field strength on the transistor threshold voltage. The extent of this field strength also depends on the applied gate-to-source and gate-to-drain voltages, so we have to keep these voltages low during operation of the device. The lateral field strengths are removed from the transistor channel by shifting this step onto the field oxide (Fig. 9), and so they cannot affect the threshold volta@. The results of the sim~ation described in Section 3.4 also show that the lateral field strengths caused by the

pn junction spread into the gate insulator and that they can lead to a charge motion. The field strength distribution of Fig. 7 has been calculated for the case in which there is no inversion channel. A screening effect of the inversion layer has been observed in the calculations, which take it into account, so that the electrical field strength can only slightly spread into the gate insulator. The field strengths that result from the pn junctions are always effective, even when there is no voltage applied to the device. We therefore propose producing the SGFET as a depletion transistor so that the screening effect of the inversion layer can also be used when the device is not in operation.

5. concltious The results achieved by the computer simulation show the existence of electrical field components in a SGFET which could influence the mobile charge in the gate insulator region. In this article a detailed discussion has been given about the possibilities of changing the device desigu and using conditions to optimize the electrical behaviour of the sensor. The proposed improvements can lead to minimal drift of the electrical chamcte~ti~s, especially a minimizing of the th~hold voltage drift as far as it is caused by fringing fields.

References 1 I. Lundstrlim, Hydrogen-sensitive MOS-structures. Part 1: principles and applications, Sensors and Actuarors, I (1981) 403-426. 2 H. Lorenz, M. Peschke, H. Riess, J. Janata and I. Eisele, New

suspended-gate FET technology for physical deposition of chemically sensitive layers, Sensors and Actuators, AZI-A23

(1990) 1023-1026. 3 I. Eisele, and H.-D. Liess, Mikro~~e~k,

4 5

6 7

FeIdeffekt~ansistoren mit Luftspalt, ~~~~e~tron~, 4 (5) (1990). M. Peschke, Thesis, Un~ve~it~t der B~~s~hr Miinchen, 1990. H. Riess, We&, Universitiit der Bundeswehr Miinchen, 1991, W. Hiinsch and S. Selherherr, MINIMOS 3: A MOSFET-simulater that includes energy balance, IEEE Trans. Electron. Devices, ED-34 (1987) 1074-1078. BLOCKSIM Program (2DSimulator), Technische Hochschule Ihnenau, Institut fiir Festkiirperelektronik, 1987.

Biographies

Fig. 9. Schematic plot of a SGFET with a connecting surface of the gate electrode on the field oxide.

Zenko GeTg~~~cke~was born in Pasardshik, Bulgaria, on August 4th, 1962. He obtained an electrical engineer’s degree in 1988 from the Technische Universitilt Ilmenau. Now he attends the Technische Universitit Ihnenau, Institute of Solid-State Electronics, with a

235

view to receiving a doctorate in electrotechnics. He is involved in research on chemical sensors based on semiconductor devices. Dagmar Schipanski is professor of solid state electronics and head of the Faculty for Electrotechnique and Information Technique at the Technische Universitit Ihnenau. She obtained an engineer’s degree in applied physics in 1967 and undertook graduate study in the Institute of Semiconductors of the Academy of Science Novosibirsk in 1972. She received a doctorate in 1976 and her habilitation in. 1985 from the Technisthe Universitiit Tlmenau. She was appointed as a university lecturer in the Physics and Technology of Electronic Devices group. Her scientific topics are ionic and electronic conductivity in insulator layers of microelectronics, electronic interface analysis, smart power circuits, SLIC circuits and device simulation. Peter Kornetzky was born in Rudolstadt, Germany, on September lst, 1961. He received an electrical engi-

neer’s degree in 1988 and a doctorate in 1991 from the Technische Universitat Ilmenau. Since 1990 he has been working there as a research assistant at the Institute of Solid State Electronics on different aspects of chemical sensors based on semiconductor devices. lgnaz Eisele received the Dr. rer. nat. from the Technische Universitat Miinchen in 1972. From 1972 until 1980he worked at the Siemens Research Laboratories in Munich and in 1980 he became a professor of material science at the Universitat der Bundeswehr Miinchen. His research interests are silicon MBE (molecular beam epitaxy) for nanoelectronic applications and chemical sensors based on semiconductor devices. Bertrand Flietner received his diploma in physics from the University of Leipzig in the field of theoretical semiconductor physics in 1989. He is currently working towards his Ph.D. thesis at the Universitiit da Bundeswehr Mtinchen. His interests include chemical sensors based on semiconducting materials.