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Threshold-voltage variability analysis and modeling for junctionless double-gate transistors
Microelectronics Reliability 74 (2017) 22–26
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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Threshold-voltage variability analysis and modeling for junctionless double-gate transistors Chun-Yu Chen a, Jyi-Tsong Lin a, Meng-Hsueh Chiang b,⁎ a b
Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 804, Taiwan Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
a r t i c l e
i n f o
Article history: Received 11 October 2016 Received in revised form 29 April 2017 Accepted 2 May 2017 Available online xxxx Keywords: Threshold voltage variation Random discrete doping Random dopant fluctuation Double-gate transistor
a b s t r a c t This paper presents a detailed analysis on the variation sources in junctionless double-gate transistors using numerical device simulation. Comparison with conventional ultra-scaled devices is also included in the study. When channel thickness is reduced to 10 nm or below, thickness variation becomes a significant source of threshold voltage variation even though random dopant fluctuation has been considered the most significant one, especially in the highly doped junctionless channel. When accounting for volume inversion in the thin silicon film, we propose a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Our study suggests that when TSi is less than 4 nm, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement. © 2017 Elsevier Ltd. All rights reserved.
1. Introduction Multiple-gate transistors are emerging in the pathway toward ultimate CMOS scaling due to their excellent gate controllability and high current drivability [1]. However, for continuous scaling, precise doping profile is required but becomes very challenging in small device dimension. Recently, the junctionless MOSFET with a same type of semiconductor throughout the whole silicon (without source/drain junction), which behaves like a resistor [2], was proposed. The junctionless transistor technology with channel length of 3 nm has been reported [3]. For such small channel length, good Ion/Ioff ratio was still achieved. However, the high doping density in the channel raises the issue of random dopant fluctuation (RDF). The question is if RDF is really a critical issue. This paper addresses such issue and provides the insight to threshold voltage variation. Besides RDF, is there any other variation that may surface eventually and even become predominant in ultimate scaling? Are the junctionless double-gate transistors more susceptible to the variations than conventional devices are? In this work, we look into other sources of variations and compare their impacts on junctionless transistors and conventional counterparts. This paper presents a macroscopic study of threshold voltage variation in junctionless double-gate transistors using random discrete doping (RDD) simulation approach [4–7]. Uniform probability was assumed for the dopant atoms located in the channel. On the basis of statistical doping profiles, device simulation was performed by solving drift-diffusion equations with a modified local density approximation, which is ⁎ Corresponding author. E-mail address: [email protected] (M.-H. Chiang).
http://dx.doi.org/10.1016/j.microrel.2017.05.002 0026-2714/© 2017 Elsevier Ltd. All rights reserved.
used mostly in bulk devices for quantum confinement. The modified local density is an alternative quantum mechanical model that is capable of calculating the confined carrier distributions and can be applied to inversion and accumulation for both electrons and holes [8]. Simulated device fluctuation due to RDD was compared with suggested specs in ITRS [1]. Besides RDF, other fluctuation parameters including film thickness, oxide thickness, and channel extension are accounted for as well. In order to estimate the threshold voltage variations given the aforementioned parameters, analytical modeling approach based on effective channel thickness is proposed. This paper is organized as follows. Section 2 introduces the simulation technique for studying the effects of random doping in the double-gate channel. Section 3 presents comprehensive analysis and extends simulated fluctuations to process variation. Insight into impact of film thickness variation in junctionless double-gate transistors is provided. While accounting for process variation, a compact modeling approach is presented for device design application. Finally, conclusions are drawn. 2. Random discrete doping for double-gate transistors In this section, we first evaluate the impact of random discrete doping on device characteristics. Our study of variability for emerging double-gate devices is focused on the sub-22 nm regime [1]. Fig. 1 shows the basic double-gate MOSFET structure used in TCAD simulation. To present a study on performance projection for CMOS logic, the physical device dimension and bias condition were chosen following the highperformance technology requirements in ITRS [1]. The gate length (L) of 17 nm, thickness (TSi) from 3 nm to 8 nm, and gate oxide (TOX)
C.-Y. Chen et al. / Microelectronics Reliability 74 (2017) 22–26
23
Fig. 1. 2-D view of the double-gate transistor device where the random discrete dopant atoms are modeled as bricks in the silicon channel.
from 1.17 nm to 3 nm with VDD of 0.81 V were used for the simulated structures. Ideal uniform doping level 1 × 1019 cm−3 was assumed [2] for the channel and the source/drain. The reason of slightly low source/drain doping is that when the junctionless MOSFET has the same doping level as that of the conventional MOSFET (~1020 cm−3), the transistors can't be turned-off at VGS = 0 V as the junctionless one has a same doping level in the channel and source/drain [9]. FermiDirac statistics and drift-diffusion transport with a modified local density approximation of quantum model for carrier confinement were included in simulation. Lombardi mobility was adopted in low filed mobility model [10]. Though our work is presented for conventional gate oxide with SiO2, the modeling approach is also applicable to high-k dielectrics via same equivalent oxide thickness (EOT). Another variation associated with gate edge roughness at extensions region (λ) [5] introduces the effective gate and drain bias variations and also has an impact on threshold voltage. When λ increases, the channel current is reduced due to increased channel resistance. In this work, although RDF in source/drain is not discussed in detail, a similar channel current reduction is shown when RDF in source/drain is included in our simulation, also as predicted in [11,12]. When accounting for RDF in source/drain, the source/drain resistance becomes more significant. In this particular RDF statistics, it is only in source/drain region. However, the RDF impact on Vt variation is not as important; the predicted worst ΔVt is only 6.04 mV (at VDS = 50 mV) and 4.47 mV (at VDS = 0.81 V). To further resolve the issues induced by RDF efficiently, a macroscopic simulation methodology has been used in conventional planar and non-planar MOSFETs [13–15]. Such methodology is applicable to the intrinsic body of non-bulk transistors. In order to simulate the discrete distribution of impurity atoms, we divided the double-gate channel into many cubes of equal volume. If N impurity dopant atoms are located in the cubes, one can use following equation [13] 3
N ¼ l NA
ð1Þ
Fig. 2. Occurrence frequency for random discrete dopant number in a Gaussian distribution.
channel length and film thickness variations for junctionless doublegate transistors at VDS = 50 mV. As expected, when the channel length is reduced, the junctionless double-gate transistor turns on faster due to short-channel effects (SCEs). On the other hand, the junctionless devices cannot be turned off if the channel is thicker than 12 nm in which the channel is not depleted and majority carriers (electrons) already conduct the current at VGS = 0 V. Fig. 4 shows IDS-VGS characteristics of junctionless double-gate transistors in 100 RDF cases. Taking RDD into account, we simulated the 100 devices with nominal TSi = 8 nm. Fig. 5 shows the calculated Vt variation with respect to continuous doping (Vt = 0.14 V) where the curve is fitted for normal distribution. The predicted standard deviation (σVt) of Vt variation is 24.43 mV. The trend of predicted Vt distribution shows a bump at its tail which was also shown before in the variationaware VLSI design [17,18] with a non-Gaussian distribution. The bump comes from the nonlinear conversion of RDF into a non-Gaussian Vt distribution in the junctionless channel. For the RDD variation, when the dominant dopants are located near the center of the channel, Vt is increased substantially (ΔVt N 40 mV), and thus a second grouping in higher Vt range is shown. Such behavior is particularly significant in the junctionless accumulation-mode devices as the majority carriers, instead of inversion carriers, are located away from the surfaces. While the doping level is increased, σVt is increased as well, as shown in Fig. 6 (σVt = 55.71 mV at 2 × 1019 cm−3 vs. 24.43 mV at 1 × 1019 cm−3). Besides doping dependence, Fig. 7 shows that Vt variation tends to distribute over a wider range for thicker EOT as σVt is increased from 24.43 mV (EOT = 1 nm) to 34.80 mV (EOT = 2 nm). When channel doping is increased, the number of dopant atoms in silicon channel also increases, thereby resulting in larger RDF-induced threshold voltage variation. As EOT increases, the gate control is reduced and hence threshold voltage variation tends to be larger. Besides RDF, we have also checked the statistical variations due to nonuniform channel and oxide thickness and found that their impacts are not as significant as
to estimate the doping density (NA) with given N. As shown in Fig. 1, the side length of the cube is set to 1 nm and then NA is found following Eq. (1). To ensure modeling validity, we also examined the dependence of accuracy on cube size to confirm its independence. However, our simulation is done in a 2D basis and is extended artificially to another dimension in simulation to come out a 3D volume. The extended dimension is assumed to have a depth of 1 μm (much longer than 1 nm), and in turn it gives a more reasonable doping range. In our simulation, the distribution probability only accommodates dopant number (N) N 20, as shown in Fig. 2. The same RDD probability of Sano's method [7] follows a Gaussian distribution [4] in the range from N = 20 to 40, as shown in Fig. 1. 3. Comprehensive analysis to account for additional fluctuations In this section, we first investigate threshold voltage (Vt) variation in random discrete doping. Vt is extracted by the constant-current method [0.1 μA(W/L)] [15,16]. Fig. 3 shows the simulated Vt contour plot over
Fig. 3. Predicted Vt contour plot over channel length and film thickness variations for junctionless double-gate transistors at VDS = 50 mV.
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Fig. 4. Simulated IDS versus VGS characteristics of junctionless double-gate transistors in the 100 RDF cases at VDS = 0.81 V.
RDF's. Even for the combined thickness variation of 0.25 nm, only a small variation (~10 mV) in threshold voltage is predicted. 3.1. Variability in junctionless double-gate transistors Besides doping fluctuation, other process related parameters also exhibit variation in actual technology, and must be taken into account to ensure reliable device characteristics. In this section, we present a comprehensive analysis and benchmark the junctionless devices with conventional ones. For our study, the nominal transistor dimension was defined as follows: gate length (L) of 17 nm, nominal TSi of 8 nm, and TOX of 1.17 nm following ITRS [1], as indicated in Fig. 1. The channel was assumed undoped, and the source/drain was heavily doped (1 × 1020 cm−3). Same models as used for junctionless transistors were adopted in device simulation. To gain insight into process variations of emerging double-gate transistors using junctionless structure, we evaluate the impact of channel thickness scaling on device I-V characteristics. Fig. 8 shows IDS-VGS characteristics of junctionless doublegate NMOS and PMOS. The device simulation was calibrated to [3] to meet Ioff and Ion. Ioff's of both junctionless and conventional cases are comparable via gate work function adjustment for fair comparison. Fig. 9 shows Vt variation for TSi from 3 nm to 8 nm. Vt of NMOS decreases as TSi increases since it becomes harder to deplete the carriers or to turn the device off in the off regime. The threshold voltage for conventional double-gate NMOS is defined as Vt = VFB + 2ψB − Qd / 2Cox where VFB is flatband voltage, ψB is bulk potential, Cox is oxide capacitance, and Qd is depletion charge (=− qNATSi). For junctionless NMOS, the 2ψB term goes to ~0 as it is biased near accumulation. Note that due to quantum mechanical confinement the conventional surface-inversion charge based analysis needs a correction, and an updated threshold voltage model for junctionless devices is discussed in the next section. Since Qd term is negligible for conventional MOSFETs with an undoped channel, TSi dependence of Vt is weaker. Fig. 10 shows TOX variation
Fig. 5. Calculated threshold voltage variation from 100 RDF cases with respect to continuous doping (extracted at VDS = 0.81 V).
Fig. 6. Predicted threshold voltage variation for different channel doping levels (VDS = 0.81 V).
from 1.17 nm to 3 nm. Again, due to negligible Qd, Cox dependence of Vt for conventional devices is less significant. In addition, decreasing TOX results in reduced SCEs and hence higher Vt. When TOX is 2.1 nm, the NMOS and PMOS have the same Vt. We have not considered nonuniform channel and oxide thickness. However, similar works have been done in [19–21]. Regarding gate work function variation in process [4], the work function variation within 200 mV is commonly seen in metal gate due to uncertainty in grain orientation [24]. As compared with conventional ultra-scaled devices, junctionless devices are more sensitive to channel thickness and gate work function variations [25]. In addition, while accounting for gate edge roughness variation which alters the effective channel length (from source to drain junction), the channel extension region (from the channel center to source/drain contact), as indicated in Fig. 1, also causes a significant impact on drive current. The parasitic resistance increases with increasing extension length [24]. 3.2. Variability modeling To provide design implications while accounting for process variation, a compact modeling approach is needed without intensive numerical simulation. We include the TSi and TOX impacts on the threshold variability modeling. As discussed above, when TSi decreases, the electrical characteristics of junctionless MOSFETs improve. Fig. 11 shows the electron distribution in different film thicknesses at VDS = 50 mV and VGS = VDD. For small TSi, volume inversion is more significant. To understand the physical insights into device design criterion, analysis for junctionless MOSFETs based on the concept of fully depleted substrate is presented using the following equation [22,23]: VTH ¼ VFB ‐
qNSi T2Si qNSi TSi TOX − 8εsi 2εox
ð2Þ
where VFB is flatband voltage, εsi is permittivity of silicon, εox is permittivity of oxide, NSi is constant doping concentration, TOX is the thickness
Fig. 7. Predicted threshold voltage variation for two different EOTs. (VDS = 0.81 V).
C.-Y. Chen et al. / Microelectronics Reliability 74 (2017) 22–26
Fig. 8. Simulated IDS versus VGS characteristics of junctionless and conventional doublegate NMOS and PMOS at same leakage current.
Fig. 9. Predicted threshold variations for channel thickness variations in junctionless and conventional NMOS and PMOS. The ΔVt is calculated from the deviation of Vt from the average value.
of gate dielectric, and TSi is film thickness. Since volume inversion due to quantum confinement has to be accounted for, we have to extract a meaningful TSi to be applied to the model which was developed in a classical sense. By integrating the electron density along the film (as shown in Fig. 11), we can extract an effective TSi when most of electrons (estimated up to 80%) are covered, implying the excluding of the augment of virtual gate oxide from the fact that electrons distribute away from the surface. The effective TSi is found from the integral of electron distribution (n): ZTsi ndx ¼ Q i
q
ð3Þ
0
Fig. 10. Predicted threshold variations for oxide thickness variations in junctionless and conventional NMOS and PMOS. The ΔVt is calculated from the deviation of Vt from the average value.
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Fig. 11. Predicted electron distributions across the film (surfaces to surfaces) for junctionless transistors of different film thicknesses (distance normalized to TSi = 8 nm). The percentage in y axis is for electron occupation at each location with respect to total electron density.
Fig. 12. Comparison of TCAD simulation and proposed model for oxide variation from 1.17 nm to 3 nm.
where Qi is the areal inversion charge and n represents for the electron distribution for calculating quantum effect. Eq. (3) is used to demonstrate how to link the model to the physical insight of electron distribution in a thin film effectively. In fact, for very thin silicon film, due to bulk inversion, it is still good to just use physical silicon thickness in the model without the need of numerical simulation. To provide a useful model for estimating effective TSi, one can use the empirical approximation: effective TSi ≈ 0.81 × TSi − 1.61 based on TCAD data over a wide range of channel thickness. Using the calibrated effective TSi for model calculation, Fig. 12 shows comparison of TCAD simulation and proposed model for gate oxide variation from 1.17 nm to 3 nm. As can be seen, threshold roll-off is predicted for thick oxide. Fig. 13 shows comparison of TCAD simulation and proposed model for film thickness variation from 3 nm to 17 nm. A
Fig. 13. Comparison of TCAD simulation and proposed model for film variation from 3 nm to 17 nm.
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facilities. This work is supported in part by the Ministry of Science and Technology of Taiwan and Advanced Optoelectronic Technology Center of National Cheng Kung University. References
Fig. 14. IDS versus VGS characteristics of junctionless double-gate transistors in different TSi's (VDS = VDD (0.81 V)).
wide range of Vt variation is predicted, implying the necessity of precise film thickness control [24]. To gain insight into the fundamental in film variation, we can integrate the channel carries and obtain the carrier areal density. As shown in Fig. 11, when TSi is less than 4 nm, electrons move to the center of the film [26] due to quantum confinement, and Vt becomes less dependent. It should be also noted that when TSi is reduced, the source/drain resistance may increase and have a negative impact on the current, as shown in Fig. 14. 4. Conclusions We have presented a detailed assessment of random discrete dopant fluctuation for junctionless double-gate transistors at the sub-22-nm technology node using numerical device simulation. As compared with conventional ultra-scaled devices, junctionless devices are more sensitive to channel thickness. However, our study suggested that when TSi is less than 4 nm, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement. When accounting for volume inversion in the thin silicon film, we proposed a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Acknowledgements Authors are grateful to the National Chip Implementation Center and National Center for High-Performance Computing for computational
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Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Threshold-voltage variability analysis and modeling for junctionless double-gate transistors Chun-Yu Chen a, Jyi-Tsong Lin a, Meng-Hsueh Chiang b,⁎ a b
Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 804, Taiwan Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
a r t i c l e
i n f o
Article history: Received 11 October 2016 Received in revised form 29 April 2017 Accepted 2 May 2017 Available online xxxx Keywords: Threshold voltage variation Random discrete doping Random dopant fluctuation Double-gate transistor
a b s t r a c t This paper presents a detailed analysis on the variation sources in junctionless double-gate transistors using numerical device simulation. Comparison with conventional ultra-scaled devices is also included in the study. When channel thickness is reduced to 10 nm or below, thickness variation becomes a significant source of threshold voltage variation even though random dopant fluctuation has been considered the most significant one, especially in the highly doped junctionless channel. When accounting for volume inversion in the thin silicon film, we propose a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Our study suggests that when TSi is less than 4 nm, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement. © 2017 Elsevier Ltd. All rights reserved.
1. Introduction Multiple-gate transistors are emerging in the pathway toward ultimate CMOS scaling due to their excellent gate controllability and high current drivability [1]. However, for continuous scaling, precise doping profile is required but becomes very challenging in small device dimension. Recently, the junctionless MOSFET with a same type of semiconductor throughout the whole silicon (without source/drain junction), which behaves like a resistor [2], was proposed. The junctionless transistor technology with channel length of 3 nm has been reported [3]. For such small channel length, good Ion/Ioff ratio was still achieved. However, the high doping density in the channel raises the issue of random dopant fluctuation (RDF). The question is if RDF is really a critical issue. This paper addresses such issue and provides the insight to threshold voltage variation. Besides RDF, is there any other variation that may surface eventually and even become predominant in ultimate scaling? Are the junctionless double-gate transistors more susceptible to the variations than conventional devices are? In this work, we look into other sources of variations and compare their impacts on junctionless transistors and conventional counterparts. This paper presents a macroscopic study of threshold voltage variation in junctionless double-gate transistors using random discrete doping (RDD) simulation approach [4–7]. Uniform probability was assumed for the dopant atoms located in the channel. On the basis of statistical doping profiles, device simulation was performed by solving drift-diffusion equations with a modified local density approximation, which is ⁎ Corresponding author. E-mail address: [email protected] (M.-H. Chiang).
http://dx.doi.org/10.1016/j.microrel.2017.05.002 0026-2714/© 2017 Elsevier Ltd. All rights reserved.
used mostly in bulk devices for quantum confinement. The modified local density is an alternative quantum mechanical model that is capable of calculating the confined carrier distributions and can be applied to inversion and accumulation for both electrons and holes [8]. Simulated device fluctuation due to RDD was compared with suggested specs in ITRS [1]. Besides RDF, other fluctuation parameters including film thickness, oxide thickness, and channel extension are accounted for as well. In order to estimate the threshold voltage variations given the aforementioned parameters, analytical modeling approach based on effective channel thickness is proposed. This paper is organized as follows. Section 2 introduces the simulation technique for studying the effects of random doping in the double-gate channel. Section 3 presents comprehensive analysis and extends simulated fluctuations to process variation. Insight into impact of film thickness variation in junctionless double-gate transistors is provided. While accounting for process variation, a compact modeling approach is presented for device design application. Finally, conclusions are drawn. 2. Random discrete doping for double-gate transistors In this section, we first evaluate the impact of random discrete doping on device characteristics. Our study of variability for emerging double-gate devices is focused on the sub-22 nm regime [1]. Fig. 1 shows the basic double-gate MOSFET structure used in TCAD simulation. To present a study on performance projection for CMOS logic, the physical device dimension and bias condition were chosen following the highperformance technology requirements in ITRS [1]. The gate length (L) of 17 nm, thickness (TSi) from 3 nm to 8 nm, and gate oxide (TOX)
C.-Y. Chen et al. / Microelectronics Reliability 74 (2017) 22–26
23
Fig. 1. 2-D view of the double-gate transistor device where the random discrete dopant atoms are modeled as bricks in the silicon channel.
from 1.17 nm to 3 nm with VDD of 0.81 V were used for the simulated structures. Ideal uniform doping level 1 × 1019 cm−3 was assumed [2] for the channel and the source/drain. The reason of slightly low source/drain doping is that when the junctionless MOSFET has the same doping level as that of the conventional MOSFET (~1020 cm−3), the transistors can't be turned-off at VGS = 0 V as the junctionless one has a same doping level in the channel and source/drain [9]. FermiDirac statistics and drift-diffusion transport with a modified local density approximation of quantum model for carrier confinement were included in simulation. Lombardi mobility was adopted in low filed mobility model [10]. Though our work is presented for conventional gate oxide with SiO2, the modeling approach is also applicable to high-k dielectrics via same equivalent oxide thickness (EOT). Another variation associated with gate edge roughness at extensions region (λ) [5] introduces the effective gate and drain bias variations and also has an impact on threshold voltage. When λ increases, the channel current is reduced due to increased channel resistance. In this work, although RDF in source/drain is not discussed in detail, a similar channel current reduction is shown when RDF in source/drain is included in our simulation, also as predicted in [11,12]. When accounting for RDF in source/drain, the source/drain resistance becomes more significant. In this particular RDF statistics, it is only in source/drain region. However, the RDF impact on Vt variation is not as important; the predicted worst ΔVt is only 6.04 mV (at VDS = 50 mV) and 4.47 mV (at VDS = 0.81 V). To further resolve the issues induced by RDF efficiently, a macroscopic simulation methodology has been used in conventional planar and non-planar MOSFETs [13–15]. Such methodology is applicable to the intrinsic body of non-bulk transistors. In order to simulate the discrete distribution of impurity atoms, we divided the double-gate channel into many cubes of equal volume. If N impurity dopant atoms are located in the cubes, one can use following equation [13] 3
N ¼ l NA
ð1Þ
Fig. 2. Occurrence frequency for random discrete dopant number in a Gaussian distribution.
channel length and film thickness variations for junctionless doublegate transistors at VDS = 50 mV. As expected, when the channel length is reduced, the junctionless double-gate transistor turns on faster due to short-channel effects (SCEs). On the other hand, the junctionless devices cannot be turned off if the channel is thicker than 12 nm in which the channel is not depleted and majority carriers (electrons) already conduct the current at VGS = 0 V. Fig. 4 shows IDS-VGS characteristics of junctionless double-gate transistors in 100 RDF cases. Taking RDD into account, we simulated the 100 devices with nominal TSi = 8 nm. Fig. 5 shows the calculated Vt variation with respect to continuous doping (Vt = 0.14 V) where the curve is fitted for normal distribution. The predicted standard deviation (σVt) of Vt variation is 24.43 mV. The trend of predicted Vt distribution shows a bump at its tail which was also shown before in the variationaware VLSI design [17,18] with a non-Gaussian distribution. The bump comes from the nonlinear conversion of RDF into a non-Gaussian Vt distribution in the junctionless channel. For the RDD variation, when the dominant dopants are located near the center of the channel, Vt is increased substantially (ΔVt N 40 mV), and thus a second grouping in higher Vt range is shown. Such behavior is particularly significant in the junctionless accumulation-mode devices as the majority carriers, instead of inversion carriers, are located away from the surfaces. While the doping level is increased, σVt is increased as well, as shown in Fig. 6 (σVt = 55.71 mV at 2 × 1019 cm−3 vs. 24.43 mV at 1 × 1019 cm−3). Besides doping dependence, Fig. 7 shows that Vt variation tends to distribute over a wider range for thicker EOT as σVt is increased from 24.43 mV (EOT = 1 nm) to 34.80 mV (EOT = 2 nm). When channel doping is increased, the number of dopant atoms in silicon channel also increases, thereby resulting in larger RDF-induced threshold voltage variation. As EOT increases, the gate control is reduced and hence threshold voltage variation tends to be larger. Besides RDF, we have also checked the statistical variations due to nonuniform channel and oxide thickness and found that their impacts are not as significant as
to estimate the doping density (NA) with given N. As shown in Fig. 1, the side length of the cube is set to 1 nm and then NA is found following Eq. (1). To ensure modeling validity, we also examined the dependence of accuracy on cube size to confirm its independence. However, our simulation is done in a 2D basis and is extended artificially to another dimension in simulation to come out a 3D volume. The extended dimension is assumed to have a depth of 1 μm (much longer than 1 nm), and in turn it gives a more reasonable doping range. In our simulation, the distribution probability only accommodates dopant number (N) N 20, as shown in Fig. 2. The same RDD probability of Sano's method [7] follows a Gaussian distribution [4] in the range from N = 20 to 40, as shown in Fig. 1. 3. Comprehensive analysis to account for additional fluctuations In this section, we first investigate threshold voltage (Vt) variation in random discrete doping. Vt is extracted by the constant-current method [0.1 μA(W/L)] [15,16]. Fig. 3 shows the simulated Vt contour plot over
Fig. 3. Predicted Vt contour plot over channel length and film thickness variations for junctionless double-gate transistors at VDS = 50 mV.
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Fig. 4. Simulated IDS versus VGS characteristics of junctionless double-gate transistors in the 100 RDF cases at VDS = 0.81 V.
RDF's. Even for the combined thickness variation of 0.25 nm, only a small variation (~10 mV) in threshold voltage is predicted. 3.1. Variability in junctionless double-gate transistors Besides doping fluctuation, other process related parameters also exhibit variation in actual technology, and must be taken into account to ensure reliable device characteristics. In this section, we present a comprehensive analysis and benchmark the junctionless devices with conventional ones. For our study, the nominal transistor dimension was defined as follows: gate length (L) of 17 nm, nominal TSi of 8 nm, and TOX of 1.17 nm following ITRS [1], as indicated in Fig. 1. The channel was assumed undoped, and the source/drain was heavily doped (1 × 1020 cm−3). Same models as used for junctionless transistors were adopted in device simulation. To gain insight into process variations of emerging double-gate transistors using junctionless structure, we evaluate the impact of channel thickness scaling on device I-V characteristics. Fig. 8 shows IDS-VGS characteristics of junctionless doublegate NMOS and PMOS. The device simulation was calibrated to [3] to meet Ioff and Ion. Ioff's of both junctionless and conventional cases are comparable via gate work function adjustment for fair comparison. Fig. 9 shows Vt variation for TSi from 3 nm to 8 nm. Vt of NMOS decreases as TSi increases since it becomes harder to deplete the carriers or to turn the device off in the off regime. The threshold voltage for conventional double-gate NMOS is defined as Vt = VFB + 2ψB − Qd / 2Cox where VFB is flatband voltage, ψB is bulk potential, Cox is oxide capacitance, and Qd is depletion charge (=− qNATSi). For junctionless NMOS, the 2ψB term goes to ~0 as it is biased near accumulation. Note that due to quantum mechanical confinement the conventional surface-inversion charge based analysis needs a correction, and an updated threshold voltage model for junctionless devices is discussed in the next section. Since Qd term is negligible for conventional MOSFETs with an undoped channel, TSi dependence of Vt is weaker. Fig. 10 shows TOX variation
Fig. 5. Calculated threshold voltage variation from 100 RDF cases with respect to continuous doping (extracted at VDS = 0.81 V).
Fig. 6. Predicted threshold voltage variation for different channel doping levels (VDS = 0.81 V).
from 1.17 nm to 3 nm. Again, due to negligible Qd, Cox dependence of Vt for conventional devices is less significant. In addition, decreasing TOX results in reduced SCEs and hence higher Vt. When TOX is 2.1 nm, the NMOS and PMOS have the same Vt. We have not considered nonuniform channel and oxide thickness. However, similar works have been done in [19–21]. Regarding gate work function variation in process [4], the work function variation within 200 mV is commonly seen in metal gate due to uncertainty in grain orientation [24]. As compared with conventional ultra-scaled devices, junctionless devices are more sensitive to channel thickness and gate work function variations [25]. In addition, while accounting for gate edge roughness variation which alters the effective channel length (from source to drain junction), the channel extension region (from the channel center to source/drain contact), as indicated in Fig. 1, also causes a significant impact on drive current. The parasitic resistance increases with increasing extension length [24]. 3.2. Variability modeling To provide design implications while accounting for process variation, a compact modeling approach is needed without intensive numerical simulation. We include the TSi and TOX impacts on the threshold variability modeling. As discussed above, when TSi decreases, the electrical characteristics of junctionless MOSFETs improve. Fig. 11 shows the electron distribution in different film thicknesses at VDS = 50 mV and VGS = VDD. For small TSi, volume inversion is more significant. To understand the physical insights into device design criterion, analysis for junctionless MOSFETs based on the concept of fully depleted substrate is presented using the following equation [22,23]: VTH ¼ VFB ‐
qNSi T2Si qNSi TSi TOX − 8εsi 2εox
ð2Þ
where VFB is flatband voltage, εsi is permittivity of silicon, εox is permittivity of oxide, NSi is constant doping concentration, TOX is the thickness
Fig. 7. Predicted threshold voltage variation for two different EOTs. (VDS = 0.81 V).
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Fig. 8. Simulated IDS versus VGS characteristics of junctionless and conventional doublegate NMOS and PMOS at same leakage current.
Fig. 9. Predicted threshold variations for channel thickness variations in junctionless and conventional NMOS and PMOS. The ΔVt is calculated from the deviation of Vt from the average value.
of gate dielectric, and TSi is film thickness. Since volume inversion due to quantum confinement has to be accounted for, we have to extract a meaningful TSi to be applied to the model which was developed in a classical sense. By integrating the electron density along the film (as shown in Fig. 11), we can extract an effective TSi when most of electrons (estimated up to 80%) are covered, implying the excluding of the augment of virtual gate oxide from the fact that electrons distribute away from the surface. The effective TSi is found from the integral of electron distribution (n): ZTsi ndx ¼ Q i
q
ð3Þ
0
Fig. 10. Predicted threshold variations for oxide thickness variations in junctionless and conventional NMOS and PMOS. The ΔVt is calculated from the deviation of Vt from the average value.
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Fig. 11. Predicted electron distributions across the film (surfaces to surfaces) for junctionless transistors of different film thicknesses (distance normalized to TSi = 8 nm). The percentage in y axis is for electron occupation at each location with respect to total electron density.
Fig. 12. Comparison of TCAD simulation and proposed model for oxide variation from 1.17 nm to 3 nm.
where Qi is the areal inversion charge and n represents for the electron distribution for calculating quantum effect. Eq. (3) is used to demonstrate how to link the model to the physical insight of electron distribution in a thin film effectively. In fact, for very thin silicon film, due to bulk inversion, it is still good to just use physical silicon thickness in the model without the need of numerical simulation. To provide a useful model for estimating effective TSi, one can use the empirical approximation: effective TSi ≈ 0.81 × TSi − 1.61 based on TCAD data over a wide range of channel thickness. Using the calibrated effective TSi for model calculation, Fig. 12 shows comparison of TCAD simulation and proposed model for gate oxide variation from 1.17 nm to 3 nm. As can be seen, threshold roll-off is predicted for thick oxide. Fig. 13 shows comparison of TCAD simulation and proposed model for film thickness variation from 3 nm to 17 nm. A
Fig. 13. Comparison of TCAD simulation and proposed model for film variation from 3 nm to 17 nm.
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facilities. This work is supported in part by the Ministry of Science and Technology of Taiwan and Advanced Optoelectronic Technology Center of National Cheng Kung University. References
Fig. 14. IDS versus VGS characteristics of junctionless double-gate transistors in different TSi's (VDS = VDD (0.81 V)).
wide range of Vt variation is predicted, implying the necessity of precise film thickness control [24]. To gain insight into the fundamental in film variation, we can integrate the channel carries and obtain the carrier areal density. As shown in Fig. 11, when TSi is less than 4 nm, electrons move to the center of the film [26] due to quantum confinement, and Vt becomes less dependent. It should be also noted that when TSi is reduced, the source/drain resistance may increase and have a negative impact on the current, as shown in Fig. 14. 4. Conclusions We have presented a detailed assessment of random discrete dopant fluctuation for junctionless double-gate transistors at the sub-22-nm technology node using numerical device simulation. As compared with conventional ultra-scaled devices, junctionless devices are more sensitive to channel thickness. However, our study suggested that when TSi is less than 4 nm, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement. When accounting for volume inversion in the thin silicon film, we proposed a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Acknowledgements Authors are grateful to the National Chip Implementation Center and National Center for High-Performance Computing for computational
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