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Charge-based compact analytical model for triple-gate junctionless nanowire transistors
Solid-State Electronics 122 (2016) 23–31
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Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Charge-based compact analytical model for triple-gate junctionless nanowire transistors F. Ávila-Herrera a,⇑, B.C. Paz b, A. Cerdeira a, M. Estrada a, M.A. Pavanello b a b
Sección de Electrónica de Estado Sólido, Depto. Ingeniería Eléctrica, CINVESTAV-IPN, Ciudad de México 07360, Mexico Department of Electrical Engineering, Centro Universitário da FEI, Av. Humberto de Alencar Castelo Branco n. 3972, 09850-901, São Bernardo do Campo, Brazil
a r t i c l e
i n f o
Article history: Received 7 March 2016 Received in revised form 20 April 2016 Accepted 25 April 2016 Available online 13 May 2016 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: 3-D compact model Triple-gate JLT Nanowire JLT SCE Fin height capacitance Threshold voltage
a b s t r a c t A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D continuous model has been developed, including the dependence of the fin height and the short channel effects. An expression for threshold voltage is presented. The model defines a one-dimensional semiconductor effective capacitance due to the width and the height of the fin, which in turn redefines the potentials and charges, without altering the general modeling procedure. Threshold voltage roll-off, subthreshold slope, DIBL and channel length modulation, as well as, the mobility degradation and the velocity saturation have been introduced into the model. The validation was done by 3-D numerical simulations for different fin heights and channel lengths, as well as, by experimental measurements in nanowire transistors with doping concentrations of 5 1018 and 1 1019 cm3. The developed model is suitable for describing the current–voltage characteristics in all operating regions from double-gate to nanowire transistor with only 8 adjusting parameters. Ó 2016 Elsevier Ltd. All rights reserved.
1. Introduction The search of MOSFETs structures that allow greater control of the electrical characteristics and thus reduce the undesired effects coming from the miniaturization has led to the appearance of the first tridimensional transistor in 1999, the FinFET [1]. This device was introduced into volume production by the electronics industry [2], presenting technological compatibility with the self-aligned process steps and planar technology. Currently, the studies are being focused on the multiple gate structures as double and triple gate. The efforts are not only invested on inversion mode (IM) MOSFETs, but also on new devices compatible with the same technology, an example of which is the Junctionless transistor (JLT) [3]. Advantages of the JLT over the inversion one have already been widely reported [4–6], such as better performance in short channel transistors, large Ion/Ioff ratio and improved analog properties. The main characteristic of this device is the absence of junctions and concentration gradients because of having a unique type of doping concentration in the channel and extensions of source and drain terminals. At the same time a high level of doping is required in
⇑ Corresponding author. E-mail address: [email protected] (F. Ávila-Herrera). http://dx.doi.org/10.1016/j.sse.2016.04.013 0038-1101/Ó 2016 Elsevier Ltd. All rights reserved.
order to improve the conductivity and achieve the suitable current levels. The deep depletion of the transistor is guaranteed by the difference in the work function between the gate material and appropriate semiconductor film cross section reduction (reduction of the fin height, width or both). The current is only provided by the diffusion mechanism. The fin cross section is supposed to be narrow and/or tiny enough, in order to turn the device off below the threshold voltage, VT. In contrast to the IM, JLT operating principle is based on working with majority carriers in two regions well defined by the applied voltages at gate (VG) and drain (VD): corresponding to partial depletion and accumulation. The transition between them is defined by the flat band voltage, VFB. In partial depletion, when a VG lower than VFB + VD is applied, the main current flows through the center of the semiconductor, where the device is neutral. For VG higher than VFB + VD, the device forms an accumulation layer at the surface, in which a second current starts to flow, in addition to the bulk one. Generally, models are developed before the commercial manufacturing of the device with the aim of describing the behavior in order to make possible circuit simulation. In the JLT case, this task is now in progress. Until now, the main JLT analytical models considering the effects introduced by reducing the channel length (L)
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F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
have been developed for double gate JLT devices (DGJLT), [7–10], models for triple gate JLT (TGJLT) are very scarce [11,12]. Besides, two models for describing the operation of both devices are commonly used. A short channel DGLJT for compact modeling was already presented in [13]. In this context, an extension of this model was developed for TGJLT, also considering the short channel effects [14,15], which due to its tridimensional physical description, can be used for modeling DG and TG structures and nanowire transistors without the need of switching models [12]. In this work, we present in detail, this generalized model. The influence of the fin height (HFin) and its width (WFin) are taken into account in the calculation of the capacitance included in the expression of the current and of the VT. Among main short channel effects (SCE), it considers velocity saturation, mobility degradation, threshold voltage roll-off, DIBL, subthreshold slope and channel length modulation. The model also includes the series resistance. The expression for current is continuous in all operation regimes, without using approximations for the transition between the two methods of conduction [11,12]. Although models for triple-gate transistors have been developed before, [11,12,16], most of them use approximations for carriers in the Poisson’s equation, adjustable transitions points and considering complete ionization by Boltzmann statistic even for high doping concentrations. Now in this paper it is developed a new physically based model to describe the influence of geometrical parameters considering for first time their dependences on the capacitances obtaining a complete analytical continuous model for all operation regimes, also including the incomplete ionization due to the Fermi statistic and valid from nanowires to double gate JLT and presenting an explicit expression for the threshold voltage. The validation of the model is supported by both 3-D numerical simulations and by experimental measurements of devices with different fin height, width, channel length and doping concentration. 2. Tridimensional core model description In order to introduce in the model the effects induced by the reduction of HFin in a tridimensional structure as the one presented in Fig. 1a, from now on we will use the subscript ‘‘L” to represent parameters already including such dependence. The studied device is shown in Fig. 1a, while its cross section is shown in Fig. 1b. As can be seen, in tridimensional devices the height of the transistor plays an important role in the semiconductor through another capacitance, CHFin, related to the height of the fin, in parallel with the 2-D capacitance caused by the silicon width, CS. The total equivalent silicon capacitance per unit length, CSL, is now obtained as:
C SL ¼ C S HFin þ C HFin W Fin ¼
eS
Lext L
(b)
Gate
Lext
tox
D
toxtop CS
z
S
HFin
y
x
tbox
z WFin
CHFin
x
Fig. 1. (a) TGJLNW structure under study, (b) x–z plane overview.
es HFin
W Fin ;
ð1Þ
where es is the semiconductor permittivity. We will analyze two possible cases due to the value of HFin: (a) when HFin is reduced sufficiently, the value of CHFin increases becoming comparable to CS, this is the case of the nanowire transistor; (b) on the contrary, if HFin increases, the total capacitance tends to the fixed value of the 2-D capacitance, which is the case of a DGJLT. Using the device symmetry, the analysis is done in one half of the structure, considering the effective channel width as Weff = HFin + WFin/2 for TGJLT or as Weff = HFin for DGJLT. The new effective gate capacitance per unit length including both, the lateral and top sides of the fin CoxL is now defined as:
C oxL ¼
eox tox
W eff ¼ C ox W eff ;
ð2Þ
where eox is the dielectric permittivity; tox is the equivalent oxide thickness, EOT, and Cox is the gate capacitance per unit area. 2.1. Model for the potentials After obtaining the total effective silicon capacitance CSL and considering the effective channel width Weff already defined, the same expressions for the potentials previously obtained for the DG device can be used [17]. The density of charges is equal to:
uV
q ¼ qND 1 e ut ;
ð3Þ
the expression for the surface electric field, ESL, is now rewritten as:
ESL ¼ ut
C oxL
eS
where bL ¼
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uSL V bL signðaL Þ e ut nL aL 1;
ð4Þ
qffiffiffiffiffiffiffiffiffiffiffi 2qbL C SL Fin H Fin and qbL ¼ qNDCW , nL ¼ 1 a1 , ut = kT/q is C oxL oxL u btL
t
the thermal potential; q is the electron charge; u is the potential at the channel and V is the potential drop across the channel, from source VS = 0 to drain VD; qbL is the total normalized fixed charge in the semiconductor; aL that is the normalized difference of potentials between the surface, uS, and the center, u0, respect to ut, calculated as:
uSL V ut
aL ¼ abtL þ LW abtL eabtL e
;
ð5Þ
where abtL is the value of the potential difference at deep subthreshold [17]. LW is the Lambert function implemented and used before in [18]. Applying the Gauss’s law the relation between uSL and the applied voltages is obtained by:
V G V FB ¼ uSL þ signðaL Þ ut bL
(a)
HFin þ
W Fin
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uSL V D e ut nL aL 1;
ð6Þ
This expression does not have an analytical solution, however, a third order precise solution based on the Newton–Raphson’s method was developed and implemented in [13]. 2.2. Continuous charge model The new total and the mobile charge, qtotL and qnL, can be expressed similarly as for the DG structure, only using the parameters that include the effects of the fin height, as follows:
qtotL ¼ signðaL Þ bL qnL ¼ qtotL
qbL : 2
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uSL V e ut n L a L 1;
ð7Þ ð8Þ
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As will be shown, the above expressions allow calculating the charge in all the operation regimes, continuously, which is something not always possible with most of the JLT triple gate models previously reported [11,12]. As we used in the case of the DG structures to obtain the current expression, it is necessary to decouple the charge in expression (7) for each operation regime. Following the same procedure as in [17]:
qdepL
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ bL enL aL nL aL 1 qbL =2
qaccL
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uSL V u V ¼ bL e ut SL 1 qbL =2
ð9Þ
ut
ð10Þ
It should be noted that the charge expressions in depletion (9) and in accumulation (10) only depend on one variable and are used for solving analytically the integral of the drain current. All the calculations are performed using the continuous expression for the charge in order to reduce the error.
The expression for the long channel VT of the triple gate structure, in which the effects of the HFin variation are included, is calculated also by the maximum of second derivative of the potential for DGJLT devices as in [19], but integrating now the new capacitances obtained for the triple gate structure. The new expression obtained is:
qbL 1 aTL ; aTL ln 1 4 2 abtL
ð11Þ
where the normalized difference of potentials at the threshold voltage is equal to:
"
a 1 aTL ¼ btL 1 abtL 1 2qbL 1 abtL
2 # :
ð12Þ
It is important to remark that the obtained expression (11) for the threshold voltage is valid for structures starting from DG (tall silicon height) down to TG nanowire transistors. 3. Short channel effects The main short channel effects are more relevant in the subthreshold regime, altering the threshold voltage, the subthreshold slope (S) and the drain induced barrier lowering (DIBL). These effects are incorporated in the model analyzing the behavior of the minimum of potential inside the channel. The channel length modulation is introduced in the model as indicated below. 3.1. Subthreshold characteristic: threshold voltage roll-off, DIBL and subthreshold slope In subthreshold regime, the 3-D Poisson’s equation can be approached as:
r2 uðx; y; zÞ ¼
d u 2
2
dx
d u 2
þ
due to the fin height,
tn;3D
dy
2
d u 2
þ
2
dz
¼
qN D
eS
ð13Þ
A solution of the 3-D potential can be obtained applying the superposition method, solving the Poisson’s equation for 2-D devices and adding the solution of the 3-D Laplace’s equation for 3-D devices. For calculating the minimum of the potential inside the channel, we use the approach for DGJLT presented in [13], where it was assumed a parabolic approximation of the potential (Young approximation) in a fully depleted device and it was found
d2 u , dz2
this dependence is expressed as [20]:
ffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi eS eox HFin HFin tox ; ¼ 1þ 4eox 2eS tox
ð14Þ
while the fin sides field penetration is:
tn;2D ¼
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi eS eox W Fin W Fin t ox : 1þ 2eox 4eS t ox
ð15Þ
An effective natural length can then be defined as the average of tn,2D and tn,3D as [21]:
1 tn;eff ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 1=t n;2D þ 1=ð2t n;3D Þ2
ð16Þ
The minimum of potential at the center is given by [13]:
u0min ¼
2.3. Threshold voltage
V TL ¼ V FB ut
a 2-D natural length, tn,2D. For TGJLT, the natural length is corrected considering the additional variation in the electrostatic potential
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðU 2S þ U 2D Þ þ 2U S U D coshðL=tn;eff Þ sinhðL=tn;eff Þ
þ u0pL ;
D 2 where US/D = VbiS/D u0pL, u0pL ¼ V G V FB þ qN eS t n;eff
ð17Þ is the sub-
threshold potential at the center for a long channel TGJLT device and VbiS/D is the built-in voltage at source/drain. As the channel length reduces enough, an additional effect of the source/drain regions has to be considered. In [8,13], this was done defining an effective built-in potential as:
V bieff ;S=D ¼ u0pL
qN Dext
eS
t 2n;eff 1
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! eS 2ðV biS þ V S=D u0pL Þ : 1þ qNDext t 2n;eff
ð18Þ
The SCE present mainly at subthreshold regime, such as threshold voltage roll-off, subthreshold slope and DIBL are included calculating an effective gate voltage through the increase of the minimum of potential, as follows:
V Geff ¼ V G þ u0min u0pL þ DpS
ð19Þ
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi where DpS ¼ abtL ut þ qN D t 2n;eff =es ut bL nL abtL 1 is the long channel deep subthreshold potential shift observed as HFin is reduced, obtained from the difference between the potential calculated by (6) and by the Young approximation [22]. 3.2. Channel length modulation The reduction of the channel length due to the applied drain voltage occurs as a result of the depletion region formed between the channel and the drain terminal, which decreases the channel length in a value of DL. This reduction just takes place when VD > VDsatL increasing the current by a rate of:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 es DL ¼ k ðV D V DeffL Þ; q ND
ð20Þ
where k is an adjusting parameter and VDeffL is the effective drain voltage. 4. Velocity saturation: drain saturation voltage A typical definition of the drain saturation voltage for long channel devices can be found in [19]. For short channel transistors, the drain saturation voltage is reached, when the electric field makes carriers move at maximum velocity.
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F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
In the TGJLT model presented, the drain saturation voltage for long channel devices is calculated as [19]:
6. Series resistance
V Dsat0L ¼ V G V TL :
In real fabricated transistors the channel is always in series with two resistances associated to the source and drain extensions, metal contacts, etc. Fig. 1 shows the drain/source extensions with length Lext, with a drop voltage defined by Ohm’s law. The total series resistances R must be take into account, because it reduces the drain current at high gate voltage. Its incorporation to the model is performed by introducing the following factor [13]:
ð21Þ
For short channel devices, the following semi-empirical equation is used to consider the effect introduced by the saturation velocity [13]:
V Dsat1 ¼ 0:08 þ gðLv sat Þ0:33 ðV G V TL Þ;
ð22Þ
where g is an adjusting parameter and vsat, is the velocity saturation.The drain saturation voltage is the smaller of the values obtained for VDsatL using (21) and (22). In order to provide a one piece expression without discontinuities, the effective drain voltage, VDeff, is calculated as follows:
V Deff ¼ V DsatL qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 þ V D V DsatL þ ut ðV D V DsatL þ ut Þ2 þ 4ut V DsatL : 2 ð23Þ Considering that in subthreshold regime the applied drain voltage, VD, plays the most important role, the final effective drain voltage, VDeffL, is equal to: 1 1 V DeffL ¼ V D ½1 tanh½15ðV G V TL Þ þ V Deff ð1 þ tanh ½15ðV G V TL ÞÞ : 2 2
KK L ¼
1
1 DLL
K L ut ; 1 þ K L RðV G V TL nV DeffL Þ 12 ½1 þ tanhð2ðV G V TL nV Deff ÞÞ ð27Þ
where K L ¼ 2 ox L eff leff ¼ 2 C oxL leff is the current factor and n is and L adjusting parameter. C W
7. Drain current model The expression for the drain current is found by solving the integral of the mobile charge:
Z
ð24Þ ID ¼ KK L
VD
ð28Þ
qnL dV VS
5. Mobility degradation JLT devices present two types of current depending on the device operation regime. When the device works in depletion regime, the carriers flow through the center of the silicon bar with low field bulk mobility, l0 [23], not affected by the perpendicular field. In the accumulation regime, an additional current is present at the Si/SiO2 interfaces due to the accumulated carriers. As the applied voltages increases, the surface collisions of the carriers also increase, causing a reduction of the mobility, limited by the surface roughness scattering. To consider these effects, the model includes the following expression for the surface mobility [24]:
lS ¼
l0 1 þ ½h1 ðV G V FB Þ þ h2 V DeffL 12 ½1 þ tanhð1:2ðV G V FB ÞÞ
;
where h1 and h2 are adjusting parameters for the accumulation current.
h
qbL 2
Integrating (28), a new subthreshold current is calculated by:
Idep bt ¼ KK L bL ut ½Su ðnL aLS Þ Su ðnL aLD Þ;
ð29Þ
where
" pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 x j 1 x0L j arctan
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi !# 1 x pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ; j 1 x0L j
lS leff ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi : lS V DeffL 2 Lv sat
where the value of
vsat, is considered an adjusting parameter.
ð26Þ
ð30Þ
evaluating for x = nLaLS/D. With x0L = nL abtL. In above threshold regime (partially depleted operation), the current is obtained as:
i ðV D V S Þ þ 0:01ð1:1 104 V D Þ þ u2t ðq2totLS q2totLD Þ þ unt LbL ½SaNðnL aLS Þ SaNðnL aLD Þ ut bL ½SbðV S Þ SbðV D Þ :
In short channel devices the longitudinal field is stronger, producing a reduction of the effective mobility, leff, due to majority carriers reaching the saturation velocity. This effect of mobility reduction is described as [25]:
1þ
7.1. Full and partial depletion current
Su ðxÞ ¼ 2 ð25Þ
Idep at ¼ KK L
The method consists of separating the integral for each operation regime to obtain the current in depletion, Idep, and in accumulation, Iacc. Because of paper length, details description of the procedure is found in [17].
ð31Þ
where aLS/D = aL (VG, VS/D) and qtotLS/D = qtot(VG,VS/D). Functions SaN and Sb are defined as in [17]. The current for the depletion regime is calculated through the following continuous expression: 1 1 Idep ¼ Idep bt ½1 tanh½25ðV G V TL Þ þ Idep at ð1 þ tanh½25ðV G V TL ÞÞ ; 2 2
ð32Þ
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F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
7.2. Accumulation current Integrating (28), the current in accumulation regime is obtained as: " qbL
# ut 2 2 ðV D h V S Þþ 2 ðqtotLS qtotLD Þ i : V G V FB V S þpS V G V FB V D þpS þut bL SaP þ qtotLS SaP þ qtotLD u u 2
t
10-5 Symbols: 3D simulation
ð33Þ
10
where function SaP is defined as in [17].
10-7
ID(L/Weff) [A]
The total current is as:
The total drain current in (34) used in this compact model for TGJLT considers the effective gate voltage, effective drain voltage, velocity saturation, mobility degradation and the main SCE previously defined. It is also important to remark that this 3-D current model for TGJLT reduces to the previously developed 2-D model for DGJLT devices, when considering a thick top oxide.
L= 50 nm
4 3
10-10
HFin [nm]
10-11
100 70 50 30 15 10
-12
10-13 10-14 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
2 1 0
1.2
VG [V] Fig. 2. Normalized transfer characteristic at VD = 50 mV for several fin heights.
8. Model validation
10-4 Symbols: 3D simulation 10-5 Lines: Model
50
10-6 VD= 1.5 V
40
10
ID(L/Weff) [A]
To validate the developed 3-D model, it was compared with 3-D numerical simulations and also with measurements from devices fabricated at CEA-LETI [26]. The model requires three parameters: l0, R and n corresponding to the core model parameters, necessary for long channel transistors. For short channel devices parameters h1, h2 and k must be added. The parameters g and vsat present an almost constant behavior and the extraction can be omitted. Parameters were extracted in the following sequence: l0 from the maximum linear gm [26], h1 and h2 from the accumulation current in the linear and saturation characteristics [13], R from the attenuation of the linear characteristic and n from the saturation characteristic [19] and k from the output characteristic at saturation [13]. g is obtained from the output characteristic [13] with a constant value equal to 0.13. vsat was fixed to 1.2 107 cm/s.
5
VD= 50 mV
10-9
10
ð34Þ
6
Lines: Model
10-8
7.3. Total drain current
1 Itot ¼ Idep ½1 tanh½20ðV G ðV FB þ V D ÞÞ 2 1 þ Iacc ½1 þ tanh½20ðV G ðV FB þ V D ÞÞ: 2
-6
ID(L/Weff) [µA]
t
-7
L= 50 nm
10-8
30
10-9 10-10
HFin [nm] 20
10-11
100 70 50 10 30 15 10 0
-12
10
10-13 10-14 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
ID(L/Weff) [µA]
Iacc ¼ KK L
With the purpose of reducing the paper length we present a summary of all obtained results. First of all, we start the analysis for transistors with several fin heights. Fig. 2 shows the behavior of the normalized simulated and modeled current for a channel of 50 nm in linear regime, at
1.2
VG [V] Fig. 3. Normalized transfer characteristic at VD = 1.5 V for several fin heights.
8.1. Simulations results and discussion
7
Symbols: 3D simulation Lines: Model
HFin [nm] 100 70 50 30 15 10
L= 50 nm
gm(L/Weff) [µS]
6 5
180 150 120
VD = 50 mV
4
90 3 60
gm(L/Weff) [µS]
8
The validation of the presented analytical compact model was done using 3-D ATLAS simulations [27]. The simulated structure is in Fig. 1. CVT mobility model was used, considering the bandgap narrowing variation with doping concentration dependence as the Slotboom model, as well as the affinity variation, impact ionization and carrier velocity saturation effect. Simulations were performed introducing the following parameters into the simulator: metal gate work-function of 5.2 eV; positive interface charge Nss = 5 1010 cm2; N-type doping concentration, ND = 5 1018 cm3; lateral and top oxide, tox = toxtop = 2 nm; buried oxide, tbox = 100 nm; silicon layer width, WFin = 15 nm; and extensions length, Lext = 30 nm. Many simulation series were done varying the fin height HFin from a large value down to nanowires, as 100, 70, 50, 30, 15 and 10 nm for several channel lengths from long to short channel, as 500, 300, 200, 100, 50 and 30 nm. The lineal transfer characteristic was simulated for VDS = 50 mV and the transfer one in saturation for VDS = 1.5 V. The output characteristic was obtained for VG = 1 V.
2 1
30
VD = 1.5 V
0
0 0.0
0.2
0.4
0.6
0.8
1.0
1.2
VG [V] Fig. 4. Comparison of modeled and simulated normalized transconductances at VD = 50 mV (left axis) and 1.5 V (right axis) for several fin heights.
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31 Table 1 Extracted model parameters for devices with different fin heights and with same channel length of 50 nm. HFin
Core model parameters
(nm)
l0
R (X)
n
h1 (V1)
h2 (V1)
k
(cm2 V1 s1) 108.97 103.4 96.559 88.752 81.2 86.043
830 1063 1271 1795 3462 7828
0.9 0.861 1.089 0.932 1.097 1.006
1.314 1.348 1.393 1.409 1.396 1.185
0.063 0.01 0.087 0.092 0.023 0.357
0.151 0.136 0.132 0.125 0.146 0.21
10-8 -9
10
10-10 10
Symbols: 3D simulation Lines: Model
WFin = 15 nm
10-13
HFin = 15 nm
-14
VD = 50 mV
1 -0.2
0.0
0.2
0
L = 50 nm
100 70 50 30 15 10
0 0.0
0.2
-40 0.6
0.8
1.0
0.4
0.6
0.8
1.0
1.2
1.4
VG [V] Fig. 6. Simulated and modeled transfer characteristics in linear and semilog scale at VD = 50 mV for several channel lengths.
10-5
180
Symbols: 3D simulation Lines: Model
150
10-6
L [nm] 500 100 50 30 Modeled
10-7 10-8 10-9 10-10 10-11
120 90 60
ND = 5x1018 cm-3 WFin = 15 nm
ID(L/W) [µA]
10-4
30
HFin = 15 nm VD = 1.5 V
0 0.2
0.4
0.6
0.8
1.0
1.2
1.4
VG [V]
-20
0.4
3
10-15
ID(L/Weff) [µA]
gD(L/Weff) [µS]
VG = 1 V
6
10-15
10-14
20
HFin [nm]
9
ND = 5x1018 cm-3
0.0
10
12
-11
10-12
10
15
L [nm] 500 100 50 30 Modeled
10-7
10-13
100
18
10-5 Symbols: 3D simulation Lines: Model 10-6
10-12
40
Short channel model parameters
ID(L/W) [µA]
100 70 50 30 15 10
ID(L/W) [A]
VD = 50 mV; one can see a very good agreement given by the model in the depletion and accumulation regime. Fig. 3 now presents the results for the saturation regime at VD = 1.5 V with a very good coincidence. Until now, one can observe that devices with HFin > 50 nm presents an almost identical behavior in all the voltage range, since there is no significant change in the charge due to the great height, approximating the device behavior to the DGJLT case. A reduction of the current starts when HFin/WFin 3 and is very drastically perceived when the device reaches a ratio of HFin/WFin = 2, which indicates that the top gate starts to play an important role in the electrostatic control of the device. Also an important change in the threshold voltage is observed. This behavior is expected from analyzing Eq. (11), as HFin is reduced to reach the nanowire case. Threshold voltage increases due to the reduction of the fixed charge in the channel. From Fig. 4 the normalized transconductance behavior is shown for linear and saturation cases, at VD = 50 mV and 1.5 V, respectively. At low drain voltage, the peak of the gm curve is governed mainly by the bulk mobility. The modeled results match very well with the simulated ones. In addition, the figure shows the transconductance for the saturation case. At the same time, in Fig. 5 the normalized output characteristic and its conductance are shown for VG = 1 V. From these figures, one can observe that there is a slow decay in the saturation current for the greater heights 100, 70 and 50 nm cases. Again, one can observe that nanowire devices exhibit a more marked difference respect to the other ones. Summarizing, the current reduction in transfer characteristics for the nanowire of 10 nm of height respect to the TGJLT of 100 nm is roughly 30% for linear and saturation operation, while for the output current characteristic the reduction is almost 50%. This means that the output characteristics decrease with a larger rate than transfer one. Although the threshold voltage depends on doping concentration and the fin width, in subthreshold operation the nanowire device presents the advantage of having a more positive VT respect to the DG or TGJLT, which makes easier to fabricate a normally-off device with a wider positive range for operating in sub-VT regime which leads to the nanowire device more useful for ultra-low power applications. The behavior of the model parameters for devices with the same channel length and different fin height is presented in Table 1. The value of physical parameters used in simulations such as vsat was retained in the model. Focusing in a critical device as a nanowire transistor with HFin = 15 nm, the drain current model was validated varying the
ID(L/W) [A]
28
1.2
VD [V] Fig. 5. Comparison of simulated and modeled output characteristics (right axis) and output conductance (left axis) at VG = 1 V for several fin heights.
Fig. 7. Simulated and modeled transfer characteristics in linear and semilog scale at VD = 1.5 V for several channel lengths.
channel length in a wide range from 500 nm to 30 nm. Fig. 6 shows the current behavior at VD = 50 mV, while Fig. 7 shows it at VD = 1.5 V. As can be seen, the simulated curves and the modeled ones match very well. Transconductance is displayed in the Fig. 8, where one can note a good agreement in linear and saturation operation. The output characteristic presented in Fig. 9 gives excellent results and also the output conductance follows very well the simulated curves. From all these plots, one can observe that the model can accurately reproduce the simulations results for several channel lengths with very small fin height, describing the short
29
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
500
ND = 5x1018 cm-3
gm(L/Weff) [µS]
12
400
HFin = 15 nm
L [nm] 500 100 50 30 Modeled
9 6 3
300 200
8.2. Experimental results and discussion
100
VD= 1.5 V
VD= 50 mV
gm(L/Weff) [µS]
WFin = 15 nm
0
-40
The proposed compact drain current model was also validated with measurements of experimental devices fabricated at CEALETI on SOI wafers with (1 0 0) orientation with 145 nm of buried oxide following the process described in [28] and reported in [11]. The one single fin devices are fabricated with PolySi/TiN as gate metal stack and 1.2 nm EOT HfSiON as gate dielectric material. The effective dimensions for the geometrical parameters HFin and WFin are 10 and 20 nm, respectively. Doping concentrations of 5 1018 and 1 1019 cm3 have being implanted in the single fin devices with channel length dimensions of 30, 40, 50, 70 and 90 nm. On the simulation case, one can work with Boltzmann statistics in order to make easier the analysis and time computing. Real devices, with heavy doping concentrations as the JLT case, present incomplete impurity ionization. In silicon as semiconductor with doping concentration above 3.6 1018 cm3, Boltzmann statistics overestimates the carrier concentration. For this reason, the Pseudo-Boltzmann model [29] was used to calculate the carrier concentration. This method allows obtaining carrier concentrations as when Fermi Dirac statistics is used, but using the following expressions:
-60
nPB ¼
0 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VG [V] Fig. 8. Simulated and modeled transconductances VD = 50 mV (left axis) and 1.5 V (right axis) for several channel lengths.
1000
40
Symbols: 3D simulation Lines: Model
20 VG = 1 V
0
ND = 5x1018 cm-3
10
WFin = 15 nm HFin = 15 nm
L [nm] 500 100 50 30 Modeled
1
0.1 -0.2
0.0
0.2
-20
ID(L/W) [µA]
gD(L/W) [µS]
100
0.4
0.6
0.8
1.0
1.2
1.4
VD [V] Fig. 9. Simulated and modeled output characteristics and output conductances at VG = 1 V for several channel lengths.
L [nm] 20
100
600
800 Symbols: 3D simulation Lines: Model
600
500 600
HFin= 10 nm HFin= 15 nm VTL Short Channel
500
400
300
400
L=500 nm VTL Long Channel
300 10
100
Threshold Voltage [mV]
Threshold Voltage [mV]
700
200 1000
HFin [nm] Fig. 10. Threshold voltage as a function of fin height and channel length.
NC ecC a NC ebcC
for cC < 2:03
for cC P 2:03
;
ð35Þ
EC where cC ¼ EFkT , In this case the values used for parameters a and b were: a = 0.765 and b = 0.8684. Since the above expressions have the same mathematical structure as Boltzmann one, they can be used for calculating the currents, without modifying the mathematical expressions of the model. Fig. 11 shows the normalized I–V characteristics at VD = 50 mV at linear and semilog scale, where the sub-VT behavior, the subthreshold slope degradation and the fall of the threshold voltage
10-5 Symbols: Measurements 10
-6
10-7 10-8
6 VD= 50 mV HFin= 10 nm
5
L [nm] 90 70 50 40 30
10-9 10-10 10
7
Lines: Model
4 3
-11
2
10-12 1
10-13 10-14 0.00
channel effects as VT roll-off, subthreshold slope and DIBL as well as the velocity saturation effect and the mobility degradation. Finally, in general aspects Fig. 10 presents the results obtained for the threshold voltage for long transistors modeled by (11),
ID(L/Weff) [µA]
15
which considers the change of the fin height, where it can be seen that the model predicts very well the behavior trend. On the other hand, the threshold voltage roll-off is also well reproduced. It was observed that there is a very small change in S as HFin is reduced while the DIBL varies within 10 mV/V. The extraction of VT was done by the second derivative method. As can be seen, the proposed model can predicts the changes of VT from DG to nanowire transistors for long and short channel devices.
600
Symbols: 3D simulation Lines: Model
ID(L/Weff) [A]
18
0.25
0.50
0.75
0 1.00
VG [V] Fig. 11. Experimental and modeled transfer characteristics in linear and semilog scale at VD = 50 mV for several channel lengths.
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
10-4 Symbols: Measurements 10-5 Lines: Model
20
ID(L/Weff) [A]
10-7 HFin= 10 nm
L [nm] 90 70 50 40 30
-8
10
10-9 10-10
40 30 20
10-11 10-12 10
10
-13
10-14 0.00
0.25
0.50
Fig. 12. Experimental and modeled transfer characteristics in linear and semilog scale at VD = 1 V for several channel lengths.
L [nm] 90 70 50 40 30
HFin= 10 nm
90
5
80
VD = 1 V
70
g m(L/Weff) [µS]
gm(L/W) [µS]
VD = 50 mV
60 50 40 30 20 10 0 0.00
0.25
0.50
0.75
1.00
VG [V]
0 -0.25
0.00
0.25
0.50
0.75
1.00
VG [V] Fig. 13. Experimental and modeled transconductances at VD = 50 mV and 1 V (insert figure) for several channel lengths.
106
15 12
HFin= 10 nm 9
104
6 103 L [nm] 90 70 50 40 30
2
101
3 0
ID(L/Weff) [µA]
gD(L/Weff) [µS]
60
5x1018 1x1019
45 30 15
70
0 65
-15 -30
40
50
60
70
80
90
L [nm] Fig. 15. Subthreshold slope and DIBL variation from experimental devices.
and also to observe how the current decremented as the channel length reduced. It can be seen that the longest transistor presents a high interface charge. Derivatives of the current at linear and saturation are very well described showing the results in Fig. 13 and in the insert one, respectively. The maximum mobility drops very drastically in the transconductance at 50 mV, as a result of the impact of the parallel electric field on the carrier acceleration. The output characteristic for current and conductance were also modeled, see Fig. 14. Even though the current decreases with scaling, the I–V plot makes possible to observe with much detail the powerful impact of the high series resistance on the device performance. In Fig. 15 are displayed the DIBL and subthreshold slope degradation for the two types of measured transistors with different doping concentration. The results show a better agreement for a lower ND, however, the tendency is very good reproduced. DIBL and S were extracted as in [13]. From all the results presented, the proposed model is able to describe suitably the static behavior of TGJLT as well as nanowires, with only 8 parameters. 9. Conclusion
Symbols: Measurements Lines: Model
105 VG = 0.7 V
10
80
ND [cm-3]
75
30
Symbols: Measurements Lines: Model
60
-45
VG [V]
10
40
Symbols: Measurements Lines: Model
60
0 1.00
0.75
Subthreshold Slope [mV/dec]
VD= 1 V
10
80
50
ID(L/Weff) [µA]
-6
L [nm]
60
DIBL [mV/V]
30
-3 -6
100 0.00
0.25
0.50
0.75
1.00
VD [V] Fig. 14. Experimental and modeled output characteristics (right axis) and output conductance (left axis) at VG = 1 V for several channel lengths.
are seen, due to the channel length scaling along with the small shift influence of the interface charges on the flat band voltage. On the other hand, a fairly well modeling for saturation at VD = 1 V is found in Fig. 12, allowing to study the DIBL phenomena
A new charge-based compact analytical model for triple gate JLT is presented, that includes the short channel effects and can be also used for double gate JLT. This model uses only 8 adjusting parameters and is included the influence of the fin height on the semiconductor capacitance. The main short channel effects: threshold voltage roll-off, subthreshold slope variation, DIBL and channel length modulation are also included, as well as, the mobility degradation, velocity saturation and series resistance. An expression for the threshold voltage expression is also presented. The model is supported by 3-D simulations and experimental measurements. Simulations results were validated for devices corresponding to DG case with 100 nm of height down to nanowire transistors with 10 nm height. Measured nanowire transistors had doping concentrations of 5 1018 and 1 1019 cm3. The channel length was scaled from long channel to short channel dimensions in both the simulations and fabricated devices. The validations confirm that the model is appropriate for JLT DC circuits’ analysis. Acknowledgements This work was supported at CINVESTAV in Mexico by CONACYT Project 236887. Marcelo A. Pavanello and Bruna C. Paz
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
acknowledge FAPESP and CNPq for the financial support. The authors acknowledge to the General Coordination of Information and Communications Technologies (CGSTIC) at CINVESTAV for providing HPC resources on the Hybrid Cluster Supercomputer ‘‘Xiuhcoatl”, that have contributed to the research results reported in this paper. The experimental junctionless devices were fabricated by CEA-LETI in the framework of the European project SQWIRE under Grant Agreement N° 257111, finished in September 2013. The authors are grateful to the staff of CEA-LETI for the fabrication and to Prof. Jean-Pierre Colinge and Dr. Isabelle Ferain for supplying of junctionless nanowire transistors. References [1] Huang X, Lee W-C, Kuo C, Hisamoto D, Chang L, Kedzierski J, et al. Sub 50-nm FinFET: PMOS. Int Electron Devices Meet (IEDM), 1999. p. 67–70. [2] Intel 2011. Intel 22 nm 3-D Tri-Gate Transistor Technology. [3] Colinge JP, Lee CW, Afzalian A, Dehdashti N, Yan R, Ferain I, et al. SOI gated resistor: CMOS without junctions. Proc IEEE Int SOI Conf, 2009. [4] Colinge JP, Kranti A, Yan R, Ferain I, Dehdashti Akhavan N, Razavi P, et al. A simulation comparison between junctionless and inversion-mode MuGFETs. ECS Trans 2011;35:63–72. [5] Holtij T, Graef M, Kloes A, Iñíguez B. Modeling and performance study of nanoscale double gate junctionless and inversion mode MOSFETs including carrier quantization effects. Solid-State Electron 2014;45:1220–5. [6] Colinge J-P et al. Nanowire transistors without junctions. Nat Nanotechnol 2010;5:225–9. [7] Paz BC, Ávila-Herrera F, Cerdeira A, Pavanello MA. Double-gate junctionless transistor model including short-channel effects. Semicond Sci Technol 2015;30(5):1–11. [8] Holtij T, Graef M, Hain FM, Kloes A, Iñiguez B. Compact model for short channel junctionless accumulation mode double-gate MOSFETs. IEEE Trans Electron Devices 2014;61(2):288–99. [9] Jazaeri F, Barbut L, Koukab A, Sallese J-M. Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime. SolidState Electron 2013;82:103–10. [10] Jin X, Liu X, Kwon H-I, Lee J-H, Lee J-H. A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid-State Electron 2013;82:77–81. [11] Trevisoli RD, Doria RT, De Souza M, Das S, Ferain I, Pavanello MA. Surfacepotential-based drain current analytical model for triple-gate junctionless nanowire transistors. IEEE Trans Electron Devices 2012;59(12):3510–8.
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[12] Holtij T, Kloes A, Iñíguez B. 3-D compact model for nanoscale junctionless triple-gate nanowire MOSFETs, including simple treatment of quantization effects. Solid-State Electron 2015;112:85–98. [13] Ávila-Herrera F, Cerdeira A, Paz BC, Estrada M, B Íñiguez B, Pavanello MA. Compact model for short-channel symmetric double-gate junctionless transistors. Solid-State Electron 2015;111:196–203. [14] Avila Herrera F, Cerdeira A, Cardoso Paz B, Estrada M, Pavanello MA. Analytical compact model for triple gate junctionless MOSFETs. SBMicro; 2015. p. 1–4. [15] Avila Herrera F, Cerdeira A, Estrada M, Cardoso Paz B, Pavanello MA. Proposal of compact analytical modeling for trigate junctionless nanowire transistors. ROPEC; 2015. [16] Fasarakis N, Tsormpatzoglou A, Tassis DH, Pappas I, Papathanasiou K, Bucher M, et al. Compact model of drain current in short-channel triple-gate FinFETs. IEEE Trans Electron Devices 2012;59(7):1891–8. [17] Cerdeira A, Ávila F, Íñiguez B, de Souza M, Pavanello MA, Estrada M. Compact core model for symmetric double-gate junctionless transistors. Solid-State Electron 2014;95:91–7. [18] Cerdeira Antonio, Iñiguez Benjamín, Estrada Magali. Compact model for short channel symmetric doped double-gate MOSFETs. Solid-State Electron 2008;52:1064–70. [19] Cerdeira A, Estrada M, Iñiguez B, Trevisoli RD, Doria RT, de Souza M, et al. Charge-based continuous model for long-channel symmetric double-gate junctionless transistors. Solid-State Electron 2013;85:59–63. [20] Colinge JP. FinFETs and others multi-gate transistors. New York: SpringerVerlag; 2008. [21] Pei G, Kedzierski J, Oldiges P, Ieong M, Kan EC-C. FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Trans Electron Devices 2002;49(8):1411–9. [22] Young KK. Short-channel effect in fully depleted MOSFETs. IEEE Trans Electron Devices 1989;36(2):399–402. [23] Jeon Dae-Young, Park So Jeong, Mouis Mireille, Joo Min-Kyu, Barraud Sylvain, Kim Gyu-Tae, et al. Separation of surface accumulation and bulk neutral channel in junctionless transistors. Appl Phys Lett 2014;104(26):263510. [24] Tsividis Yannis. 3rd ed. Oxford University Press; 2011. [25] Caughey DM, Thomas RE. Carrier mobilities in silicon empirically related to doping and field. Proc IEEE 1967;55:2192–3. [26] Jeon D-Y, Park SJ, Mouis M, Berthomé M, Barraud S, Kim G-T, et al. Revisited parameter extraction methodology for electrical characterization of junctionless transistors. Solid-State Electron 2013;90:86–93. [27] Silvaco Int. ATLAS; 2015. [28] Barraud S, Berthome M, Coquand R, Casse M, Ernst T, Samson M-P, et al. Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron Device Lett 2012;33:1225–7. [29] Avila-Herrera F, Cerdeira A, Roldan JB, Sánchez-Moreno P, Tienda-Luna IM, Iñiguez B. Pseudo-Boltzmann model for modeling the junctionless transistors. Solid-State Electron 2014;95:19–22.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Charge-based compact analytical model for triple-gate junctionless nanowire transistors F. Ávila-Herrera a,⇑, B.C. Paz b, A. Cerdeira a, M. Estrada a, M.A. Pavanello b a b
Sección de Electrónica de Estado Sólido, Depto. Ingeniería Eléctrica, CINVESTAV-IPN, Ciudad de México 07360, Mexico Department of Electrical Engineering, Centro Universitário da FEI, Av. Humberto de Alencar Castelo Branco n. 3972, 09850-901, São Bernardo do Campo, Brazil
a r t i c l e
i n f o
Article history: Received 7 March 2016 Received in revised form 20 April 2016 Accepted 25 April 2016 Available online 13 May 2016 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: 3-D compact model Triple-gate JLT Nanowire JLT SCE Fin height capacitance Threshold voltage
a b s t r a c t A new compact analytical model for short channel triple gate junctionless transistors is proposed. Based on a previous model for double-gate transistors which neglected the fin height effects, a new 3-D continuous model has been developed, including the dependence of the fin height and the short channel effects. An expression for threshold voltage is presented. The model defines a one-dimensional semiconductor effective capacitance due to the width and the height of the fin, which in turn redefines the potentials and charges, without altering the general modeling procedure. Threshold voltage roll-off, subthreshold slope, DIBL and channel length modulation, as well as, the mobility degradation and the velocity saturation have been introduced into the model. The validation was done by 3-D numerical simulations for different fin heights and channel lengths, as well as, by experimental measurements in nanowire transistors with doping concentrations of 5 1018 and 1 1019 cm3. The developed model is suitable for describing the current–voltage characteristics in all operating regions from double-gate to nanowire transistor with only 8 adjusting parameters. Ó 2016 Elsevier Ltd. All rights reserved.
1. Introduction The search of MOSFETs structures that allow greater control of the electrical characteristics and thus reduce the undesired effects coming from the miniaturization has led to the appearance of the first tridimensional transistor in 1999, the FinFET [1]. This device was introduced into volume production by the electronics industry [2], presenting technological compatibility with the self-aligned process steps and planar technology. Currently, the studies are being focused on the multiple gate structures as double and triple gate. The efforts are not only invested on inversion mode (IM) MOSFETs, but also on new devices compatible with the same technology, an example of which is the Junctionless transistor (JLT) [3]. Advantages of the JLT over the inversion one have already been widely reported [4–6], such as better performance in short channel transistors, large Ion/Ioff ratio and improved analog properties. The main characteristic of this device is the absence of junctions and concentration gradients because of having a unique type of doping concentration in the channel and extensions of source and drain terminals. At the same time a high level of doping is required in
⇑ Corresponding author. E-mail address: [email protected] (F. Ávila-Herrera). http://dx.doi.org/10.1016/j.sse.2016.04.013 0038-1101/Ó 2016 Elsevier Ltd. All rights reserved.
order to improve the conductivity and achieve the suitable current levels. The deep depletion of the transistor is guaranteed by the difference in the work function between the gate material and appropriate semiconductor film cross section reduction (reduction of the fin height, width or both). The current is only provided by the diffusion mechanism. The fin cross section is supposed to be narrow and/or tiny enough, in order to turn the device off below the threshold voltage, VT. In contrast to the IM, JLT operating principle is based on working with majority carriers in two regions well defined by the applied voltages at gate (VG) and drain (VD): corresponding to partial depletion and accumulation. The transition between them is defined by the flat band voltage, VFB. In partial depletion, when a VG lower than VFB + VD is applied, the main current flows through the center of the semiconductor, where the device is neutral. For VG higher than VFB + VD, the device forms an accumulation layer at the surface, in which a second current starts to flow, in addition to the bulk one. Generally, models are developed before the commercial manufacturing of the device with the aim of describing the behavior in order to make possible circuit simulation. In the JLT case, this task is now in progress. Until now, the main JLT analytical models considering the effects introduced by reducing the channel length (L)
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F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
have been developed for double gate JLT devices (DGJLT), [7–10], models for triple gate JLT (TGJLT) are very scarce [11,12]. Besides, two models for describing the operation of both devices are commonly used. A short channel DGLJT for compact modeling was already presented in [13]. In this context, an extension of this model was developed for TGJLT, also considering the short channel effects [14,15], which due to its tridimensional physical description, can be used for modeling DG and TG structures and nanowire transistors without the need of switching models [12]. In this work, we present in detail, this generalized model. The influence of the fin height (HFin) and its width (WFin) are taken into account in the calculation of the capacitance included in the expression of the current and of the VT. Among main short channel effects (SCE), it considers velocity saturation, mobility degradation, threshold voltage roll-off, DIBL, subthreshold slope and channel length modulation. The model also includes the series resistance. The expression for current is continuous in all operation regimes, without using approximations for the transition between the two methods of conduction [11,12]. Although models for triple-gate transistors have been developed before, [11,12,16], most of them use approximations for carriers in the Poisson’s equation, adjustable transitions points and considering complete ionization by Boltzmann statistic even for high doping concentrations. Now in this paper it is developed a new physically based model to describe the influence of geometrical parameters considering for first time their dependences on the capacitances obtaining a complete analytical continuous model for all operation regimes, also including the incomplete ionization due to the Fermi statistic and valid from nanowires to double gate JLT and presenting an explicit expression for the threshold voltage. The validation of the model is supported by both 3-D numerical simulations and by experimental measurements of devices with different fin height, width, channel length and doping concentration. 2. Tridimensional core model description In order to introduce in the model the effects induced by the reduction of HFin in a tridimensional structure as the one presented in Fig. 1a, from now on we will use the subscript ‘‘L” to represent parameters already including such dependence. The studied device is shown in Fig. 1a, while its cross section is shown in Fig. 1b. As can be seen, in tridimensional devices the height of the transistor plays an important role in the semiconductor through another capacitance, CHFin, related to the height of the fin, in parallel with the 2-D capacitance caused by the silicon width, CS. The total equivalent silicon capacitance per unit length, CSL, is now obtained as:
C SL ¼ C S HFin þ C HFin W Fin ¼
eS
Lext L
(b)
Gate
Lext
tox
D
toxtop CS
z
S
HFin
y
x
tbox
z WFin
CHFin
x
Fig. 1. (a) TGJLNW structure under study, (b) x–z plane overview.
es HFin
W Fin ;
ð1Þ
where es is the semiconductor permittivity. We will analyze two possible cases due to the value of HFin: (a) when HFin is reduced sufficiently, the value of CHFin increases becoming comparable to CS, this is the case of the nanowire transistor; (b) on the contrary, if HFin increases, the total capacitance tends to the fixed value of the 2-D capacitance, which is the case of a DGJLT. Using the device symmetry, the analysis is done in one half of the structure, considering the effective channel width as Weff = HFin + WFin/2 for TGJLT or as Weff = HFin for DGJLT. The new effective gate capacitance per unit length including both, the lateral and top sides of the fin CoxL is now defined as:
C oxL ¼
eox tox
W eff ¼ C ox W eff ;
ð2Þ
where eox is the dielectric permittivity; tox is the equivalent oxide thickness, EOT, and Cox is the gate capacitance per unit area. 2.1. Model for the potentials After obtaining the total effective silicon capacitance CSL and considering the effective channel width Weff already defined, the same expressions for the potentials previously obtained for the DG device can be used [17]. The density of charges is equal to:
uV
q ¼ qND 1 e ut ;
ð3Þ
the expression for the surface electric field, ESL, is now rewritten as:
ESL ¼ ut
C oxL
eS
where bL ¼
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uSL V bL signðaL Þ e ut nL aL 1;
ð4Þ
qffiffiffiffiffiffiffiffiffiffiffi 2qbL C SL Fin H Fin and qbL ¼ qNDCW , nL ¼ 1 a1 , ut = kT/q is C oxL oxL u btL
t
the thermal potential; q is the electron charge; u is the potential at the channel and V is the potential drop across the channel, from source VS = 0 to drain VD; qbL is the total normalized fixed charge in the semiconductor; aL that is the normalized difference of potentials between the surface, uS, and the center, u0, respect to ut, calculated as:
uSL V ut
aL ¼ abtL þ LW abtL eabtL e
;
ð5Þ
where abtL is the value of the potential difference at deep subthreshold [17]. LW is the Lambert function implemented and used before in [18]. Applying the Gauss’s law the relation between uSL and the applied voltages is obtained by:
V G V FB ¼ uSL þ signðaL Þ ut bL
(a)
HFin þ
W Fin
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uSL V D e ut nL aL 1;
ð6Þ
This expression does not have an analytical solution, however, a third order precise solution based on the Newton–Raphson’s method was developed and implemented in [13]. 2.2. Continuous charge model The new total and the mobile charge, qtotL and qnL, can be expressed similarly as for the DG structure, only using the parameters that include the effects of the fin height, as follows:
qtotL ¼ signðaL Þ bL qnL ¼ qtotL
qbL : 2
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uSL V e ut n L a L 1;
ð7Þ ð8Þ
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As will be shown, the above expressions allow calculating the charge in all the operation regimes, continuously, which is something not always possible with most of the JLT triple gate models previously reported [11,12]. As we used in the case of the DG structures to obtain the current expression, it is necessary to decouple the charge in expression (7) for each operation regime. Following the same procedure as in [17]:
qdepL
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ bL enL aL nL aL 1 qbL =2
qaccL
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi uSL V u V ¼ bL e ut SL 1 qbL =2
ð9Þ
ut
ð10Þ
It should be noted that the charge expressions in depletion (9) and in accumulation (10) only depend on one variable and are used for solving analytically the integral of the drain current. All the calculations are performed using the continuous expression for the charge in order to reduce the error.
The expression for the long channel VT of the triple gate structure, in which the effects of the HFin variation are included, is calculated also by the maximum of second derivative of the potential for DGJLT devices as in [19], but integrating now the new capacitances obtained for the triple gate structure. The new expression obtained is:
qbL 1 aTL ; aTL ln 1 4 2 abtL
ð11Þ
where the normalized difference of potentials at the threshold voltage is equal to:
"
a 1 aTL ¼ btL 1 abtL 1 2qbL 1 abtL
2 # :
ð12Þ
It is important to remark that the obtained expression (11) for the threshold voltage is valid for structures starting from DG (tall silicon height) down to TG nanowire transistors. 3. Short channel effects The main short channel effects are more relevant in the subthreshold regime, altering the threshold voltage, the subthreshold slope (S) and the drain induced barrier lowering (DIBL). These effects are incorporated in the model analyzing the behavior of the minimum of potential inside the channel. The channel length modulation is introduced in the model as indicated below. 3.1. Subthreshold characteristic: threshold voltage roll-off, DIBL and subthreshold slope In subthreshold regime, the 3-D Poisson’s equation can be approached as:
r2 uðx; y; zÞ ¼
d u 2
2
dx
d u 2
þ
due to the fin height,
tn;3D
dy
2
d u 2
þ
2
dz
¼
qN D
eS
ð13Þ
A solution of the 3-D potential can be obtained applying the superposition method, solving the Poisson’s equation for 2-D devices and adding the solution of the 3-D Laplace’s equation for 3-D devices. For calculating the minimum of the potential inside the channel, we use the approach for DGJLT presented in [13], where it was assumed a parabolic approximation of the potential (Young approximation) in a fully depleted device and it was found
d2 u , dz2
this dependence is expressed as [20]:
ffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi eS eox HFin HFin tox ; ¼ 1þ 4eox 2eS tox
ð14Þ
while the fin sides field penetration is:
tn;2D ¼
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi eS eox W Fin W Fin t ox : 1þ 2eox 4eS t ox
ð15Þ
An effective natural length can then be defined as the average of tn,2D and tn,3D as [21]:
1 tn;eff ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 1=t n;2D þ 1=ð2t n;3D Þ2
ð16Þ
The minimum of potential at the center is given by [13]:
u0min ¼
2.3. Threshold voltage
V TL ¼ V FB ut
a 2-D natural length, tn,2D. For TGJLT, the natural length is corrected considering the additional variation in the electrostatic potential
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðU 2S þ U 2D Þ þ 2U S U D coshðL=tn;eff Þ sinhðL=tn;eff Þ
þ u0pL ;
D 2 where US/D = VbiS/D u0pL, u0pL ¼ V G V FB þ qN eS t n;eff
ð17Þ is the sub-
threshold potential at the center for a long channel TGJLT device and VbiS/D is the built-in voltage at source/drain. As the channel length reduces enough, an additional effect of the source/drain regions has to be considered. In [8,13], this was done defining an effective built-in potential as:
V bieff ;S=D ¼ u0pL
qN Dext
eS
t 2n;eff 1
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! eS 2ðV biS þ V S=D u0pL Þ : 1þ qNDext t 2n;eff
ð18Þ
The SCE present mainly at subthreshold regime, such as threshold voltage roll-off, subthreshold slope and DIBL are included calculating an effective gate voltage through the increase of the minimum of potential, as follows:
V Geff ¼ V G þ u0min u0pL þ DpS
ð19Þ
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi where DpS ¼ abtL ut þ qN D t 2n;eff =es ut bL nL abtL 1 is the long channel deep subthreshold potential shift observed as HFin is reduced, obtained from the difference between the potential calculated by (6) and by the Young approximation [22]. 3.2. Channel length modulation The reduction of the channel length due to the applied drain voltage occurs as a result of the depletion region formed between the channel and the drain terminal, which decreases the channel length in a value of DL. This reduction just takes place when VD > VDsatL increasing the current by a rate of:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 es DL ¼ k ðV D V DeffL Þ; q ND
ð20Þ
where k is an adjusting parameter and VDeffL is the effective drain voltage. 4. Velocity saturation: drain saturation voltage A typical definition of the drain saturation voltage for long channel devices can be found in [19]. For short channel transistors, the drain saturation voltage is reached, when the electric field makes carriers move at maximum velocity.
26
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
In the TGJLT model presented, the drain saturation voltage for long channel devices is calculated as [19]:
6. Series resistance
V Dsat0L ¼ V G V TL :
In real fabricated transistors the channel is always in series with two resistances associated to the source and drain extensions, metal contacts, etc. Fig. 1 shows the drain/source extensions with length Lext, with a drop voltage defined by Ohm’s law. The total series resistances R must be take into account, because it reduces the drain current at high gate voltage. Its incorporation to the model is performed by introducing the following factor [13]:
ð21Þ
For short channel devices, the following semi-empirical equation is used to consider the effect introduced by the saturation velocity [13]:
V Dsat1 ¼ 0:08 þ gðLv sat Þ0:33 ðV G V TL Þ;
ð22Þ
where g is an adjusting parameter and vsat, is the velocity saturation.The drain saturation voltage is the smaller of the values obtained for VDsatL using (21) and (22). In order to provide a one piece expression without discontinuities, the effective drain voltage, VDeff, is calculated as follows:
V Deff ¼ V DsatL qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 þ V D V DsatL þ ut ðV D V DsatL þ ut Þ2 þ 4ut V DsatL : 2 ð23Þ Considering that in subthreshold regime the applied drain voltage, VD, plays the most important role, the final effective drain voltage, VDeffL, is equal to: 1 1 V DeffL ¼ V D ½1 tanh½15ðV G V TL Þ þ V Deff ð1 þ tanh ½15ðV G V TL ÞÞ : 2 2
KK L ¼
1
1 DLL
K L ut ; 1 þ K L RðV G V TL nV DeffL Þ 12 ½1 þ tanhð2ðV G V TL nV Deff ÞÞ ð27Þ
where K L ¼ 2 ox L eff leff ¼ 2 C oxL leff is the current factor and n is and L adjusting parameter. C W
7. Drain current model The expression for the drain current is found by solving the integral of the mobile charge:
Z
ð24Þ ID ¼ KK L
VD
ð28Þ
qnL dV VS
5. Mobility degradation JLT devices present two types of current depending on the device operation regime. When the device works in depletion regime, the carriers flow through the center of the silicon bar with low field bulk mobility, l0 [23], not affected by the perpendicular field. In the accumulation regime, an additional current is present at the Si/SiO2 interfaces due to the accumulated carriers. As the applied voltages increases, the surface collisions of the carriers also increase, causing a reduction of the mobility, limited by the surface roughness scattering. To consider these effects, the model includes the following expression for the surface mobility [24]:
lS ¼
l0 1 þ ½h1 ðV G V FB Þ þ h2 V DeffL 12 ½1 þ tanhð1:2ðV G V FB ÞÞ
;
where h1 and h2 are adjusting parameters for the accumulation current.
h
qbL 2
Integrating (28), a new subthreshold current is calculated by:
Idep bt ¼ KK L bL ut ½Su ðnL aLS Þ Su ðnL aLD Þ;
ð29Þ
where
" pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 x j 1 x0L j arctan
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi !# 1 x pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ; j 1 x0L j
lS leff ¼ rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi : lS V DeffL 2 Lv sat
where the value of
vsat, is considered an adjusting parameter.
ð26Þ
ð30Þ
evaluating for x = nLaLS/D. With x0L = nL abtL. In above threshold regime (partially depleted operation), the current is obtained as:
i ðV D V S Þ þ 0:01ð1:1 104 V D Þ þ u2t ðq2totLS q2totLD Þ þ unt LbL ½SaNðnL aLS Þ SaNðnL aLD Þ ut bL ½SbðV S Þ SbðV D Þ :
In short channel devices the longitudinal field is stronger, producing a reduction of the effective mobility, leff, due to majority carriers reaching the saturation velocity. This effect of mobility reduction is described as [25]:
1þ
7.1. Full and partial depletion current
Su ðxÞ ¼ 2 ð25Þ
Idep at ¼ KK L
The method consists of separating the integral for each operation regime to obtain the current in depletion, Idep, and in accumulation, Iacc. Because of paper length, details description of the procedure is found in [17].
ð31Þ
where aLS/D = aL (VG, VS/D) and qtotLS/D = qtot(VG,VS/D). Functions SaN and Sb are defined as in [17]. The current for the depletion regime is calculated through the following continuous expression: 1 1 Idep ¼ Idep bt ½1 tanh½25ðV G V TL Þ þ Idep at ð1 þ tanh½25ðV G V TL ÞÞ ; 2 2
ð32Þ
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F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
7.2. Accumulation current Integrating (28), the current in accumulation regime is obtained as: " qbL
# ut 2 2 ðV D h V S Þþ 2 ðqtotLS qtotLD Þ i : V G V FB V S þpS V G V FB V D þpS þut bL SaP þ qtotLS SaP þ qtotLD u u 2
t
10-5 Symbols: 3D simulation
ð33Þ
10
where function SaP is defined as in [17].
10-7
ID(L/Weff) [A]
The total current is as:
The total drain current in (34) used in this compact model for TGJLT considers the effective gate voltage, effective drain voltage, velocity saturation, mobility degradation and the main SCE previously defined. It is also important to remark that this 3-D current model for TGJLT reduces to the previously developed 2-D model for DGJLT devices, when considering a thick top oxide.
L= 50 nm
4 3
10-10
HFin [nm]
10-11
100 70 50 30 15 10
-12
10-13 10-14 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
2 1 0
1.2
VG [V] Fig. 2. Normalized transfer characteristic at VD = 50 mV for several fin heights.
8. Model validation
10-4 Symbols: 3D simulation 10-5 Lines: Model
50
10-6 VD= 1.5 V
40
10
ID(L/Weff) [A]
To validate the developed 3-D model, it was compared with 3-D numerical simulations and also with measurements from devices fabricated at CEA-LETI [26]. The model requires three parameters: l0, R and n corresponding to the core model parameters, necessary for long channel transistors. For short channel devices parameters h1, h2 and k must be added. The parameters g and vsat present an almost constant behavior and the extraction can be omitted. Parameters were extracted in the following sequence: l0 from the maximum linear gm [26], h1 and h2 from the accumulation current in the linear and saturation characteristics [13], R from the attenuation of the linear characteristic and n from the saturation characteristic [19] and k from the output characteristic at saturation [13]. g is obtained from the output characteristic [13] with a constant value equal to 0.13. vsat was fixed to 1.2 107 cm/s.
5
VD= 50 mV
10-9
10
ð34Þ
6
Lines: Model
10-8
7.3. Total drain current
1 Itot ¼ Idep ½1 tanh½20ðV G ðV FB þ V D ÞÞ 2 1 þ Iacc ½1 þ tanh½20ðV G ðV FB þ V D ÞÞ: 2
-6
ID(L/Weff) [µA]
t
-7
L= 50 nm
10-8
30
10-9 10-10
HFin [nm] 20
10-11
100 70 50 10 30 15 10 0
-12
10
10-13 10-14 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
ID(L/Weff) [µA]
Iacc ¼ KK L
With the purpose of reducing the paper length we present a summary of all obtained results. First of all, we start the analysis for transistors with several fin heights. Fig. 2 shows the behavior of the normalized simulated and modeled current for a channel of 50 nm in linear regime, at
1.2
VG [V] Fig. 3. Normalized transfer characteristic at VD = 1.5 V for several fin heights.
8.1. Simulations results and discussion
7
Symbols: 3D simulation Lines: Model
HFin [nm] 100 70 50 30 15 10
L= 50 nm
gm(L/Weff) [µS]
6 5
180 150 120
VD = 50 mV
4
90 3 60
gm(L/Weff) [µS]
8
The validation of the presented analytical compact model was done using 3-D ATLAS simulations [27]. The simulated structure is in Fig. 1. CVT mobility model was used, considering the bandgap narrowing variation with doping concentration dependence as the Slotboom model, as well as the affinity variation, impact ionization and carrier velocity saturation effect. Simulations were performed introducing the following parameters into the simulator: metal gate work-function of 5.2 eV; positive interface charge Nss = 5 1010 cm2; N-type doping concentration, ND = 5 1018 cm3; lateral and top oxide, tox = toxtop = 2 nm; buried oxide, tbox = 100 nm; silicon layer width, WFin = 15 nm; and extensions length, Lext = 30 nm. Many simulation series were done varying the fin height HFin from a large value down to nanowires, as 100, 70, 50, 30, 15 and 10 nm for several channel lengths from long to short channel, as 500, 300, 200, 100, 50 and 30 nm. The lineal transfer characteristic was simulated for VDS = 50 mV and the transfer one in saturation for VDS = 1.5 V. The output characteristic was obtained for VG = 1 V.
2 1
30
VD = 1.5 V
0
0 0.0
0.2
0.4
0.6
0.8
1.0
1.2
VG [V] Fig. 4. Comparison of modeled and simulated normalized transconductances at VD = 50 mV (left axis) and 1.5 V (right axis) for several fin heights.
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31 Table 1 Extracted model parameters for devices with different fin heights and with same channel length of 50 nm. HFin
Core model parameters
(nm)
l0
R (X)
n
h1 (V1)
h2 (V1)
k
(cm2 V1 s1) 108.97 103.4 96.559 88.752 81.2 86.043
830 1063 1271 1795 3462 7828
0.9 0.861 1.089 0.932 1.097 1.006
1.314 1.348 1.393 1.409 1.396 1.185
0.063 0.01 0.087 0.092 0.023 0.357
0.151 0.136 0.132 0.125 0.146 0.21
10-8 -9
10
10-10 10
Symbols: 3D simulation Lines: Model
WFin = 15 nm
10-13
HFin = 15 nm
-14
VD = 50 mV
1 -0.2
0.0
0.2
0
L = 50 nm
100 70 50 30 15 10
0 0.0
0.2
-40 0.6
0.8
1.0
0.4
0.6
0.8
1.0
1.2
1.4
VG [V] Fig. 6. Simulated and modeled transfer characteristics in linear and semilog scale at VD = 50 mV for several channel lengths.
10-5
180
Symbols: 3D simulation Lines: Model
150
10-6
L [nm] 500 100 50 30 Modeled
10-7 10-8 10-9 10-10 10-11
120 90 60
ND = 5x1018 cm-3 WFin = 15 nm
ID(L/W) [µA]
10-4
30
HFin = 15 nm VD = 1.5 V
0 0.2
0.4
0.6
0.8
1.0
1.2
1.4
VG [V]
-20
0.4
3
10-15
ID(L/Weff) [µA]
gD(L/Weff) [µS]
VG = 1 V
6
10-15
10-14
20
HFin [nm]
9
ND = 5x1018 cm-3
0.0
10
12
-11
10-12
10
15
L [nm] 500 100 50 30 Modeled
10-7
10-13
100
18
10-5 Symbols: 3D simulation Lines: Model 10-6
10-12
40
Short channel model parameters
ID(L/W) [µA]
100 70 50 30 15 10
ID(L/W) [A]
VD = 50 mV; one can see a very good agreement given by the model in the depletion and accumulation regime. Fig. 3 now presents the results for the saturation regime at VD = 1.5 V with a very good coincidence. Until now, one can observe that devices with HFin > 50 nm presents an almost identical behavior in all the voltage range, since there is no significant change in the charge due to the great height, approximating the device behavior to the DGJLT case. A reduction of the current starts when HFin/WFin 3 and is very drastically perceived when the device reaches a ratio of HFin/WFin = 2, which indicates that the top gate starts to play an important role in the electrostatic control of the device. Also an important change in the threshold voltage is observed. This behavior is expected from analyzing Eq. (11), as HFin is reduced to reach the nanowire case. Threshold voltage increases due to the reduction of the fixed charge in the channel. From Fig. 4 the normalized transconductance behavior is shown for linear and saturation cases, at VD = 50 mV and 1.5 V, respectively. At low drain voltage, the peak of the gm curve is governed mainly by the bulk mobility. The modeled results match very well with the simulated ones. In addition, the figure shows the transconductance for the saturation case. At the same time, in Fig. 5 the normalized output characteristic and its conductance are shown for VG = 1 V. From these figures, one can observe that there is a slow decay in the saturation current for the greater heights 100, 70 and 50 nm cases. Again, one can observe that nanowire devices exhibit a more marked difference respect to the other ones. Summarizing, the current reduction in transfer characteristics for the nanowire of 10 nm of height respect to the TGJLT of 100 nm is roughly 30% for linear and saturation operation, while for the output current characteristic the reduction is almost 50%. This means that the output characteristics decrease with a larger rate than transfer one. Although the threshold voltage depends on doping concentration and the fin width, in subthreshold operation the nanowire device presents the advantage of having a more positive VT respect to the DG or TGJLT, which makes easier to fabricate a normally-off device with a wider positive range for operating in sub-VT regime which leads to the nanowire device more useful for ultra-low power applications. The behavior of the model parameters for devices with the same channel length and different fin height is presented in Table 1. The value of physical parameters used in simulations such as vsat was retained in the model. Focusing in a critical device as a nanowire transistor with HFin = 15 nm, the drain current model was validated varying the
ID(L/W) [A]
28
1.2
VD [V] Fig. 5. Comparison of simulated and modeled output characteristics (right axis) and output conductance (left axis) at VG = 1 V for several fin heights.
Fig. 7. Simulated and modeled transfer characteristics in linear and semilog scale at VD = 1.5 V for several channel lengths.
channel length in a wide range from 500 nm to 30 nm. Fig. 6 shows the current behavior at VD = 50 mV, while Fig. 7 shows it at VD = 1.5 V. As can be seen, the simulated curves and the modeled ones match very well. Transconductance is displayed in the Fig. 8, where one can note a good agreement in linear and saturation operation. The output characteristic presented in Fig. 9 gives excellent results and also the output conductance follows very well the simulated curves. From all these plots, one can observe that the model can accurately reproduce the simulations results for several channel lengths with very small fin height, describing the short
29
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
500
ND = 5x1018 cm-3
gm(L/Weff) [µS]
12
400
HFin = 15 nm
L [nm] 500 100 50 30 Modeled
9 6 3
300 200
8.2. Experimental results and discussion
100
VD= 1.5 V
VD= 50 mV
gm(L/Weff) [µS]
WFin = 15 nm
0
-40
The proposed compact drain current model was also validated with measurements of experimental devices fabricated at CEALETI on SOI wafers with (1 0 0) orientation with 145 nm of buried oxide following the process described in [28] and reported in [11]. The one single fin devices are fabricated with PolySi/TiN as gate metal stack and 1.2 nm EOT HfSiON as gate dielectric material. The effective dimensions for the geometrical parameters HFin and WFin are 10 and 20 nm, respectively. Doping concentrations of 5 1018 and 1 1019 cm3 have being implanted in the single fin devices with channel length dimensions of 30, 40, 50, 70 and 90 nm. On the simulation case, one can work with Boltzmann statistics in order to make easier the analysis and time computing. Real devices, with heavy doping concentrations as the JLT case, present incomplete impurity ionization. In silicon as semiconductor with doping concentration above 3.6 1018 cm3, Boltzmann statistics overestimates the carrier concentration. For this reason, the Pseudo-Boltzmann model [29] was used to calculate the carrier concentration. This method allows obtaining carrier concentrations as when Fermi Dirac statistics is used, but using the following expressions:
-60
nPB ¼
0 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VG [V] Fig. 8. Simulated and modeled transconductances VD = 50 mV (left axis) and 1.5 V (right axis) for several channel lengths.
1000
40
Symbols: 3D simulation Lines: Model
20 VG = 1 V
0
ND = 5x1018 cm-3
10
WFin = 15 nm HFin = 15 nm
L [nm] 500 100 50 30 Modeled
1
0.1 -0.2
0.0
0.2
-20
ID(L/W) [µA]
gD(L/W) [µS]
100
0.4
0.6
0.8
1.0
1.2
1.4
VD [V] Fig. 9. Simulated and modeled output characteristics and output conductances at VG = 1 V for several channel lengths.
L [nm] 20
100
600
800 Symbols: 3D simulation Lines: Model
600
500 600
HFin= 10 nm HFin= 15 nm VTL Short Channel
500
400
300
400
L=500 nm VTL Long Channel
300 10
100
Threshold Voltage [mV]
Threshold Voltage [mV]
700
200 1000
HFin [nm] Fig. 10. Threshold voltage as a function of fin height and channel length.
NC ecC a NC ebcC
for cC < 2:03
for cC P 2:03
;
ð35Þ
EC where cC ¼ EFkT , In this case the values used for parameters a and b were: a = 0.765 and b = 0.8684. Since the above expressions have the same mathematical structure as Boltzmann one, they can be used for calculating the currents, without modifying the mathematical expressions of the model. Fig. 11 shows the normalized I–V characteristics at VD = 50 mV at linear and semilog scale, where the sub-VT behavior, the subthreshold slope degradation and the fall of the threshold voltage
10-5 Symbols: Measurements 10
-6
10-7 10-8
6 VD= 50 mV HFin= 10 nm
5
L [nm] 90 70 50 40 30
10-9 10-10 10
7
Lines: Model
4 3
-11
2
10-12 1
10-13 10-14 0.00
channel effects as VT roll-off, subthreshold slope and DIBL as well as the velocity saturation effect and the mobility degradation. Finally, in general aspects Fig. 10 presents the results obtained for the threshold voltage for long transistors modeled by (11),
ID(L/Weff) [µA]
15
which considers the change of the fin height, where it can be seen that the model predicts very well the behavior trend. On the other hand, the threshold voltage roll-off is also well reproduced. It was observed that there is a very small change in S as HFin is reduced while the DIBL varies within 10 mV/V. The extraction of VT was done by the second derivative method. As can be seen, the proposed model can predicts the changes of VT from DG to nanowire transistors for long and short channel devices.
600
Symbols: 3D simulation Lines: Model
ID(L/Weff) [A]
18
0.25
0.50
0.75
0 1.00
VG [V] Fig. 11. Experimental and modeled transfer characteristics in linear and semilog scale at VD = 50 mV for several channel lengths.
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
10-4 Symbols: Measurements 10-5 Lines: Model
20
ID(L/Weff) [A]
10-7 HFin= 10 nm
L [nm] 90 70 50 40 30
-8
10
10-9 10-10
40 30 20
10-11 10-12 10
10
-13
10-14 0.00
0.25
0.50
Fig. 12. Experimental and modeled transfer characteristics in linear and semilog scale at VD = 1 V for several channel lengths.
L [nm] 90 70 50 40 30
HFin= 10 nm
90
5
80
VD = 1 V
70
g m(L/Weff) [µS]
gm(L/W) [µS]
VD = 50 mV
60 50 40 30 20 10 0 0.00
0.25
0.50
0.75
1.00
VG [V]
0 -0.25
0.00
0.25
0.50
0.75
1.00
VG [V] Fig. 13. Experimental and modeled transconductances at VD = 50 mV and 1 V (insert figure) for several channel lengths.
106
15 12
HFin= 10 nm 9
104
6 103 L [nm] 90 70 50 40 30
2
101
3 0
ID(L/Weff) [µA]
gD(L/Weff) [µS]
60
5x1018 1x1019
45 30 15
70
0 65
-15 -30
40
50
60
70
80
90
L [nm] Fig. 15. Subthreshold slope and DIBL variation from experimental devices.
and also to observe how the current decremented as the channel length reduced. It can be seen that the longest transistor presents a high interface charge. Derivatives of the current at linear and saturation are very well described showing the results in Fig. 13 and in the insert one, respectively. The maximum mobility drops very drastically in the transconductance at 50 mV, as a result of the impact of the parallel electric field on the carrier acceleration. The output characteristic for current and conductance were also modeled, see Fig. 14. Even though the current decreases with scaling, the I–V plot makes possible to observe with much detail the powerful impact of the high series resistance on the device performance. In Fig. 15 are displayed the DIBL and subthreshold slope degradation for the two types of measured transistors with different doping concentration. The results show a better agreement for a lower ND, however, the tendency is very good reproduced. DIBL and S were extracted as in [13]. From all the results presented, the proposed model is able to describe suitably the static behavior of TGJLT as well as nanowires, with only 8 parameters. 9. Conclusion
Symbols: Measurements Lines: Model
105 VG = 0.7 V
10
80
ND [cm-3]
75
30
Symbols: Measurements Lines: Model
60
-45
VG [V]
10
40
Symbols: Measurements Lines: Model
60
0 1.00
0.75
Subthreshold Slope [mV/dec]
VD= 1 V
10
80
50
ID(L/Weff) [µA]
-6
L [nm]
60
DIBL [mV/V]
30
-3 -6
100 0.00
0.25
0.50
0.75
1.00
VD [V] Fig. 14. Experimental and modeled output characteristics (right axis) and output conductance (left axis) at VG = 1 V for several channel lengths.
are seen, due to the channel length scaling along with the small shift influence of the interface charges on the flat band voltage. On the other hand, a fairly well modeling for saturation at VD = 1 V is found in Fig. 12, allowing to study the DIBL phenomena
A new charge-based compact analytical model for triple gate JLT is presented, that includes the short channel effects and can be also used for double gate JLT. This model uses only 8 adjusting parameters and is included the influence of the fin height on the semiconductor capacitance. The main short channel effects: threshold voltage roll-off, subthreshold slope variation, DIBL and channel length modulation are also included, as well as, the mobility degradation, velocity saturation and series resistance. An expression for the threshold voltage expression is also presented. The model is supported by 3-D simulations and experimental measurements. Simulations results were validated for devices corresponding to DG case with 100 nm of height down to nanowire transistors with 10 nm height. Measured nanowire transistors had doping concentrations of 5 1018 and 1 1019 cm3. The channel length was scaled from long channel to short channel dimensions in both the simulations and fabricated devices. The validations confirm that the model is appropriate for JLT DC circuits’ analysis. Acknowledgements This work was supported at CINVESTAV in Mexico by CONACYT Project 236887. Marcelo A. Pavanello and Bruna C. Paz
F. Ávila-Herrera et al. / Solid-State Electronics 122 (2016) 23–31
acknowledge FAPESP and CNPq for the financial support. The authors acknowledge to the General Coordination of Information and Communications Technologies (CGSTIC) at CINVESTAV for providing HPC resources on the Hybrid Cluster Supercomputer ‘‘Xiuhcoatl”, that have contributed to the research results reported in this paper. The experimental junctionless devices were fabricated by CEA-LETI in the framework of the European project SQWIRE under Grant Agreement N° 257111, finished in September 2013. The authors are grateful to the staff of CEA-LETI for the fabrication and to Prof. Jean-Pierre Colinge and Dr. Isabelle Ferain for supplying of junctionless nanowire transistors. References [1] Huang X, Lee W-C, Kuo C, Hisamoto D, Chang L, Kedzierski J, et al. Sub 50-nm FinFET: PMOS. Int Electron Devices Meet (IEDM), 1999. p. 67–70. [2] Intel 2011. Intel 22 nm 3-D Tri-Gate Transistor Technology. [3] Colinge JP, Lee CW, Afzalian A, Dehdashti N, Yan R, Ferain I, et al. SOI gated resistor: CMOS without junctions. Proc IEEE Int SOI Conf, 2009. [4] Colinge JP, Kranti A, Yan R, Ferain I, Dehdashti Akhavan N, Razavi P, et al. A simulation comparison between junctionless and inversion-mode MuGFETs. ECS Trans 2011;35:63–72. [5] Holtij T, Graef M, Kloes A, Iñíguez B. Modeling and performance study of nanoscale double gate junctionless and inversion mode MOSFETs including carrier quantization effects. Solid-State Electron 2014;45:1220–5. [6] Colinge J-P et al. Nanowire transistors without junctions. Nat Nanotechnol 2010;5:225–9. [7] Paz BC, Ávila-Herrera F, Cerdeira A, Pavanello MA. Double-gate junctionless transistor model including short-channel effects. Semicond Sci Technol 2015;30(5):1–11. [8] Holtij T, Graef M, Hain FM, Kloes A, Iñiguez B. Compact model for short channel junctionless accumulation mode double-gate MOSFETs. IEEE Trans Electron Devices 2014;61(2):288–99. [9] Jazaeri F, Barbut L, Koukab A, Sallese J-M. Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime. SolidState Electron 2013;82:103–10. [10] Jin X, Liu X, Kwon H-I, Lee J-H, Lee J-H. A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid-State Electron 2013;82:77–81. [11] Trevisoli RD, Doria RT, De Souza M, Das S, Ferain I, Pavanello MA. Surfacepotential-based drain current analytical model for triple-gate junctionless nanowire transistors. IEEE Trans Electron Devices 2012;59(12):3510–8.
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