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Injection-locked frequency divider using single-injected dual-injection MOSFETs
Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Injection-locked frequency divider using single-injected dual-injection MOSFETs Sheng-Lyang Jang n, Wen-Cheng Liu Department of Electronic Engineering, National Taiwan University of Science and Technology, Taiwan ROC
art ic l e i nf o
a b s t r a c t
Article history: Received 3 November 2014 Received in revised form 26 May 2015 Accepted 6 June 2015
A wide locking range and operation range push–push divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 μm BiCMOS process. The divideby-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator for easy startup oscillation and single-ended injected dual-injection transistors. The common drain node of dual injection transistors is AC-tied to the output of a frequency doubler. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm the operation range of the divide-by-4 is 3.23 GHz, from the incident frequency 15.85 to 19.08 GHz, the percentage is 18.49%. The locking range of the divide-by-4 is 1.4 GHz, from the incident frequency from 17.08 GHz to 19.08 GHz, the percentage is 11.06%. The core power consumption is 6.53 mW. The die area is 0.83 0.597 mm2. & 2015 Elsevier Ltd. All rights reserved.
Keywords: Divide-by-4 injection-locked frequency divider Dual-injection MOSFETs Linear mixer Frequency doubler Locking range MOS
1. Introduction Frequency dividers (FDs) are widely used in frequency synthesizers and transceivers. LC-tank injection-locked frequency dividers (ILFDs) are a type of FDs and have potential of low power and high-frequency operation. The popular divide-by-2 ILFDs provide 2:1 frequency division because of easy design and implementation. The study of high modulo ILFDs is attractive because the design of a synthesizer can be simplified if a single-stage high modulo ILFD is used at the early IC design stage to reduce die area, consequently a cheaper circuit and system can be designed. However, a single-stage high division ratio ILFD has the property of narrow locking range. This paper studies the design of LC-tank divide-by-4 ILFD. A conventional CMOS single-stage LC-tank divide-by-4 ILFD as shown in Fig. 1(a) has been implemented using a single-injection MOSFET [1–4]. The block diagram of the conventional divide-by-4 ILFD is shown in Fig. 1(b), the ILFD [4] uses a nonlinear injection MOSFET M3 to generate the third harmonic at 3ωo. The drawback of this approach is narrow locking range. A large locking range is desirable for the ILFD robust to the variations of process, temperature and supply voltage. The second design method of divide-by-4 ILFD uses two divide-by-2 ILFDs cascaded together, this approach suffers from inevitable frequency misalignment between the two
n
Corresponding author. E-mail address: [email protected] (S.-L. Jang).
ILFDs, large die area and power consumption or increased voltage headroom. Recently, various techniques have been proposed to improve the locking range of divide-by-4 LC ILFD. Passive improvement techniques such as shunt peaking, series peaking and 4th-order LC tank [5] help improve injection efficiency at the cost of increase in die area due to the inclusion of more inductors. Active or mixed active-passive improvement techniques have been proposed in [6–8], where 4 or three active injection devices are used. The thought behind these is to utilize linear mixer instead of nonlinear mixer to enlarge the mixer conversion efficiency and hence extend the locking range. The linear mixer approach was originally invented by our research team in order to enhance the conversion efficiency [9] in a divide-by-3 ILFD. With this approach a differential injection signal is applied to the two injection MOSFETs across the LC resonator of cross-coupled oscillator [10]. The locking range is enhanced by feedback a second harmonic to the common node of two injection MOSFETs [11]. A divide-by-4 ILFD [12] was designed with the two-step mixing approach, the first step of mixing is to generate the frequency signal at (ωRF ωo) at the output of mixer, the output of first-mixer is applied to the second mixer of a divide-by-3 ILFD to provide a signal at (ωRF ωo) 2ωo at the output of ILFD. Here ωRF and ωo are, respectively, the frequencies of the injection and ILFD output signals. In this paper, we propose a single-ended injection divide-by-4 ILFD using two injection MOSFETs with an effort to make the injection circuit as simple as possible while the large locking range still remains. The ILFD uses two-step mixing approach. The block diagram of the proposed divide-by-four ILFD is shown in Fig. 2.
http://dx.doi.org/10.1016/j.mejo.2015.06.006 0026-2692/& 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: S.-L. Jang, W.-C. Liu, Injection-locked frequency divider using single-injected dual-injection MOSFETs, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.06.006i
S.-L. Jang, W.-C. Liu / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
2
VDD
VDD Vt
L1
Cv 1 Vo1
Cv 2 Vinj
R2
RFinput
Vo1
ωRF
M2
M1
C2
L2
Vo
R2
V inj
Cv2 B A
L2
R2
M4 L3
C1
R F input C 4 Vo2
M6 M2
LB
ωo
ωRF - 3ωo
3ωo
M3 M5
M6 C1
L1
Cv1
C4 Vo2
M3
M5 M1
Inj
Vt
Fig. 3. Schematic of the proposed ILFD. LB is the bonding wire inductor.
×3
Fig. 1. (a) Schematic of a conventional divide-by-4 ILFD. (b) Block diagram of the conventional divide-by-four ILFD.
Mixer1 Inj
ω RF - 2ωo
ω RF 2ωo
L2 ×2
Mixer2 ω In - ωo ω In
Filter1 C2
R2
ωo
Filter2 R1
×1
L1
ωo
CV
Vo
Vtune
Fig. 2. Simplified block diagram of the proposed divide-by-four ILFD.
The proposed ILFD consists of a feedback loop with two mixers, Mixer1 and Mixer2, and LC bandpass filters. As the input signal with angular frequency 4ωo(¼ωRF) mixes with the frequency doubler signal with angular frequency 2ωo, the angular frequency component of 2ωo(ωRF 2ωo) is produced at the output of Mixer1. The angular frequency component of 2ωo (ωRF 2ωo) mixing with the other input signal with angular frequency ωo generates a signal with angular frequency (ωRF 3ωo) at the output of Mixer2; this yields the divide-by-4 input-output frequency relation given by ωRF 3ωo ¼ωo. The RLC filters are used to filter out the undesired signals at other angular frequency. This paper is organized as follows. Section II discusses the design of the divide-by-4 LC ILFD and section III reports the experimental data of the ILFD implemented in 0.18 μm BiCMOS technology, and finally a conclusion is drawn in last section.
2. Circuit design Fig. 3 shows the schematic of the proposed divide-by-4 ILFD using a pair of cross-coupled nMOSFETs (M1, M2), which are used to generate the negative resistance to balance the resistive LC-tank loss. The parallel-tuned LC resonator consists of a center-tapped inductor L1, and accumulation-mode varactors (Cv1, Cv2). The voltage Vt is used to control the oscillation frequency of the ILFD. Two common-source amplifiers (M5, M6) with gates wired to the ILFD outputs are used as buffers for the measurement. The MOSFETs (M3, M4) are the injection MOSFETs, and the dc gate bias Vinj of MOSFETs (M3, M4) is used to optimize the locking range. An external injection signal at the frequency ωRF is ac-coupled to the common gate B of (M3, M4). Inductors (L2, L3) are series-peaking inductors used to enhance the locking range. The common node A of two injection MOSFETs (M3, M4) is wired to the output of the
bonding wire inductor LB via a dc blocking capacitor C1. The bonding wire inductor LB is used as the load of the 2nd harmonic at 2ωo, which results from the cross-coupled transistors (M1, M2) and buffers (M5, M6) operating between linear and saturation periodically. The dc blocking capacitor C1 is used to feedback the 2ωo signal to the common drain node of (M3, M4). The operation principle is discussed as follows. When no injection signal is impressed, the transistors (M3, M4) as a nonlinear common gate amplifier can generate current components at a fundamental signal at ωo and high-order harmonics; the common drain node of (M3, M4) serves as the virtual ground for the odd-harmonics and it also generates the voltage at the evenharmonics (2ωo, 4ωo). In Fig. 2, two filters are used, filter 2 represents the LC resonator in Fig. 3 and filter 1 models the C1, LB and capacitance due to (M3, M4)in Fig. 3. When injection signal at ωRF is impressed, M3 serves a Mixer1 in Fig. 2 and it generates a channel current signal IM3 at 2ωo (¼ωRF 2ωo); on the one hand, M4 serves a common gate switch Mixer2 in Fig. 2, part of IM3 goes to the source of M4 and is controlled by the source voltage of M4. The desired output current of M4 contains a frequency component at (ωRF 2ωo)–ωo which is equal to ωo. By circuit symmetry, M3 also serves as Mixer2 in Fig. 2, the source signal of M3 at (ωRF 2ωo) from capacitor C1 mixes with the gate signal of M3 to provide output signal at (ωRF 2ωo)–ωo, which is equal to ωo. The single-ended injection signal is applied to both the gates of (M3, M4) for symmetric outputs. Simulation shows that IM3 at 2ωo increases by using the feedback capacitor C1, which enhances the locking range. Simulation shows the locking range of the divide-by-4 ILFD mode under the bias condition of VDD ¼0.8 V, Vtune ¼ 0.5 V and Vinj ¼1.5 V is 2.8 GHz from 15.9 to 18.7 GHz at the injection power of 0 dBm. When the C1 is deleted, the divide-by-4 locking range is 2 GHz, from 17.0 GHz to 19.0 GHz. The 2ωo feedback increases the locking range. The injection MOSFETs switch between off and on-region periodically. For simplicity we assume that MOSFETs M3 operate in linear region, the drain current of M3 is simplified as I ds ¼ kð½V GS V TH V ds ½1 þ δV2ds =2Þ
ð1Þ
wherek ¼ μWC ox =L. W/L is channel width/length. μ is the mobility, Cox is the gate oxide capacitance. δis a coefficient accounting for the channel-length modulation effect. The primary ac voltages at source nodes of (M3 and M4) in Fig. 3 are vo sin ðωo tÞand vo sin ðωo tÞ, respectively. vs sin ðωi tÞis the injection signal. Since the output voltages of the ILFD are differential, only even harmonics vm sin ðωm tÞoccur at the common drain node A of M3 and M4. The ac drain current of injection MOSFET can be divided into
Please cite this article as: S.-L. Jang, W.-C. Liu, Injection-locked frequency divider using single-injected dual-injection MOSFETs, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.06.006i
S.-L. Jang, W.-C. Liu / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
different frequency components: ids ¼
fkv2o ½1 δ=2g
sin ðωo tÞ sin ðωo tÞ þkvs sin ðωi tÞvm sin ðωm tÞ þ kvo vm δ sin ðωo tÞ sin ðωm tÞ þ undesired terms
ð2Þ
The first term on the right-handed side is used to form the push– push signal at the common node of (M3, M4). Under injection locking condition ωm ¼2ωo, the second term is used for the mixing function of M3 (Mixer1) in Fig. 3. The third term is used for the mixing function of M4 (Mixer2) in Fig. 3.
3. Measurement results The divide-by-4 ILFD was designed and fabricated in the TSMC 0.18 μm 3P6M BiCMOS technology. As shown in Fig. 4, the proposed wide-band divide-by-4 ILFD occupies a die area of 0.83 0.597 mm2 including all test pads and dummy metal. The 3-turn inductor L1 is shown on the top side and 2-turn symmetric inductors (L2, L3) are shown on the right and left-hand sides. A standard FR4 material is used to build the test board for the ILFD measurement. To measure the locking range and phase noise performance of the divide-by-4 LC ILFD, an Agilent N5183A signal source has been used with the Agilent E4407B spectrum analyzer. The inductors were simulated using ADS momentum. The spectraRF is used to simulate the circuit performance. At VDD ¼0.8 V, Vtune ¼ 0 V, the current and power consumption of the ILFD without buffers are 8.16 mA and 6.53 mW, respectively. The freerunning frequency of the ILFD shown in Fig. 5 is tunable from 4.27 GHz to 4.565 GHz as a tuning voltage varies from 0.0 to 2 V and when dc bias voltage Vinj is 0 V. As Vt increases the capacitance of varactor decreases, and the oscillation frequency increases. Fig. 6 shows the measured locking range of the ILFD in the divide-by-4 mode under the condition of VDD ¼ 0.8 V, with a total locking range 3.23 GHz (18.49%) from 15.85 to 19.08 GHz at the injection power of 0 dBm. At the tuning voltage Vt of 0 V, the
3
divide-by-4 locking range is 1.33 GHz (8.03%), from 15.89 GHz to 17.22 GHz. At the tuning voltage Vt of 2 V, the divide-by-4 locking range is 2 GHz (11.06%), from 17.08 GHz to 19.08 GHz. Fig. 7(a) shows the measured output spectra of the frequency divider before and after the locked conditions in the C4 mode. The locked output spectrum shows a lower phase noise and the ILFD can track the low-phase-noise of injection source. Fig. 7(b) shows the measured phase noises of the injection-reference and the injectionlocked ILFD. When the signal is injected, at 1 MHz frequency offset the phase noise of the ILFD is 130.02 dBc/Hz, while the phase noise of the injection-reference is 122.11 dBc/Hz. At low offset frequency, the phase noise of the locked ILFD is smaller than the injection signal by about 12.5 dB. The phase noise of the divide-by-4 ILFD is due to the output phase noises of the free-running ILFD and the injection source. The measured phase noise of the ILFD is dominated by the noise of the injection signal. Table 1 is the performance comparison.
Fig. 6. Measured operation frequency vs input power. In the divide-by-4 mode. VDD ¼ 0.8 V, Vt ¼ 0, 2 V (from left to right).
Fig. 4. Chip micrograph for the divide-by-4 ILFD.
-80
Phase Noise(dBc/Hz)
Frequency (GHZ)
4.6
4.5
4.4
-90 -100 -110 -120 -130 Injection Power High Band
-140
4.3 -150 104
4.2 0.0
0.5
1.0
1.5
2.0
Vtune (V) Fig. 5. Measured tuning range by varying Vt of varactor. VDD ¼0.8 V and Vinj ¼ 0 V.
105
106
107
Offset Frequency(Hz) Fig. 7. (a) Measured spectra of the injection-reference and the locked divide-by-4 ILFD and (b) measured phase noises. VDD ¼ 0.8 V, Vt ¼2 V. Vinj ¼ 1.5 V. finj¼ 19 GHz and fo ¼4.75 GHz.
Please cite this article as: S.-L. Jang, W.-C. Liu, Injection-locked frequency divider using single-injected dual-injection MOSFETs, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.06.006i
S.-L. Jang, W.-C. Liu / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
4
Table 1 Performance Comparison of divide-by-4 LC-tank ILFDs.
[1] [2] [3] [13] [14] [8] [7] This
Mixer
Resonator
Process (um)
Pin (dBm)
Die area (mm2)
VDD (V)/Pdis (mW)
Oper. range (GHz)(%)
Lock. range (GHz)
Nonlinear Nonlinear Nonlinear Nonlinear Linear Linear Linear Linear
Passive LC Passive LC Passive LC Passive LC Active LC Active LC Passive LC Passive LC
0.18 0.09 0.18 0.18 0.18 0.18 0.09 0.18
0 0 0 40 0 0 0 0
1.04 1.01 0.11 0.13 0.76 0.562 0.175 0.465 0.317 0.503 0.36 0.86 0.75 0.83 0.597
1.2/3.12 0.5/2.75 0.67/1.87 1.2/7.56 1.5/1.5 4 1.7/7.6 4 0.6/2.58 0.8/6.53
6.86 8.02(15.6) 62.9–71.6(12.9) 15.3–17.3(12.3) 45.9–50.9(10.3) 14.5–16.8(14.7) 3.6–9.4(89.2) 21.1–26.4 (22.31) 15.85–19.08 (18.49)
7.55–7.65 64.5–65.2 15.2–16.25 48.6–48.9 14.6–16.3 6.8–8.6 21.1–22.5 (6.42%) 17.08–19.08 (11.06%)
The active LC ILFD [8] requires voltage headroom due to the active inductor and it utilizes three injection MOSFETs. It is a power consuming ILFD while tuning the control voltage to enhance the speed. The proposed LC divide-by-4 ILFD is potentially for high frequency, low voltage and low power operation.
4. Conclusion A wide locking range and operation range LC-tank push–push divide-by-4 injection locked frequency divider has been proposed and fabricated using MOSFETs. The proposed ILFD uses the LC-tank cross-coupled VCO as the core for easy start-up oscillation; and it also uses two injection MOSFETs and a frequency doubler circuit so that linear mixer can be used to extend the locking range. A wide locking range divide-by-4 ILFD has been successfully designed and verified by simulation and measurement. The measured divide-by-4 locking range is 2 GHz (11.06%), from 17.08 GHz to 19.08 GHz. The locking range percentage is larger than other published LC-tank data by other research groups. The singlestage LC-tank ILFD is useful for RF circuit application. To our knowledge, this is the first reported divide-by-4 ILFD using dualinjection MOSFETs.
Acknowledgment The authors would like to thank the Staff of the CIC for the chip fabrication and technical supports.
References [1] S.H. Lee, S.L. Jang, Y.H. Chung, A low voltage divide-by-4 injection locked frequency divider with quadrature outputs, IEEE Microw. Wirel. Compon. Lett. 17 (No. 5) (May 2007) 373–375. [2] K. Yamamoto and M. Fujishima, 70 GHz CMOS harmonic injection locked divider, in: Proceedings of IEEE International Solid-State Circuits Conference Digest, February 2006, pp. 600–601. [3] S.-L. Jang, C.-H. Liu, C.-W. Chang, M.-H. Juang, A low voltage, low power divideby-4 LC-tank injection-locked frequency divider, Int. J. Electron. 98 (4) (2011) 521–527. [4] S.-L. Jang, C.C. Liu, C.-W. Chung, A tail-injected divide-by-4 SiGe HBT injection locked frequency divider, IEEE Microw. Wirel. Compon. Lett. 19 (2009) 236–238. [5] L. Wu, H.C. Luong, Analysis and design of a 0.6 V 2.2 mW 58.5-to-72.9 GHz divide-by-4 injection-Llcked frequency divider with harmonic boosting Regular Papers, IEEE Trans. Circuits Syst. Part I 60 (No. 8) (Aug. 2013) 2001–2007. [6] S.-L. Jang, C.-C. Fu, Wide locking range divide-by-4 LC-tank injection-locked frequency divider using series-mixers, Analog Integr. Circuit Signal Process. (2014). [7] C.-W. Chang, S.-L. Jang, LC-Tank divide-by-4 injection-locked frequency divider using the 2nd harmonic feedback, Int. J. Electron. 101 (No. 2) (2014) 204–211. [8] C.-W. Chang, S.-L. Jang, M.-H. Juang, Divide-by-4 injection-locked frequency divider using two linear mixers, Microw. Opt. Technol. Lett. 54 (2012) 1359–1362. [9] S.-L. Jang, C.-W. Chang, A 90 nm CMOS LC-tank divide-by-3 Injection-locked frequency divider with record locking range, IEEE Microw. Wirel. Compon. Lett. 20 (2010) 229–231. [10] S.-L. Jang, C.-J. Huang, C.-C. Liu, A 0.35 mm CMOS divide-by-3 LC injectionlocked frequency divider, VLSI Des. Autom. Test (2009) 303–306. [11] C.-W. Chang, S.-L. Jang, C.-W. Hsieh, Wide-locking range C3 active-inductor injection-locked frequency divider using the push-push oscillator, Microw. Opt. Technol. Lett. 53 (2011) 2771–2773. [12] S.-L. Jang, C.-C. Fu, Wide locking range divide-by-4 LC-tank injection-locked frequency divider using series-mixers,, Analog Integr. Circuit Signal Process. 78 (2) (2014) 523–528. [13] M.-C. Chuang, J.-J. Kuo, C.-H Wang, H. Wang, A 50 GHz divide-by-4 injection lock frequency divider using matching method, IEEE Microw. Wirel. Compon. Lett. 18 (No. 5) (2008) 344–346. [14] C.-W. Chang, S.-L. Jang, A differential BiCMOS divide-by-4 injection-locked frequency divider,, Microw. Opt. Technol. Lett. 54 (2012) 2825–2828.
Please cite this article as: S.-L. Jang, W.-C. Liu, Injection-locked frequency divider using single-injected dual-injection MOSFETs, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.06.006i
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Injection-locked frequency divider using single-injected dual-injection MOSFETs Sheng-Lyang Jang n, Wen-Cheng Liu Department of Electronic Engineering, National Taiwan University of Science and Technology, Taiwan ROC
art ic l e i nf o
a b s t r a c t
Article history: Received 3 November 2014 Received in revised form 26 May 2015 Accepted 6 June 2015
A wide locking range and operation range push–push divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 μm BiCMOS process. The divideby-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator for easy startup oscillation and single-ended injected dual-injection transistors. The common drain node of dual injection transistors is AC-tied to the output of a frequency doubler. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm the operation range of the divide-by-4 is 3.23 GHz, from the incident frequency 15.85 to 19.08 GHz, the percentage is 18.49%. The locking range of the divide-by-4 is 1.4 GHz, from the incident frequency from 17.08 GHz to 19.08 GHz, the percentage is 11.06%. The core power consumption is 6.53 mW. The die area is 0.83 0.597 mm2. & 2015 Elsevier Ltd. All rights reserved.
Keywords: Divide-by-4 injection-locked frequency divider Dual-injection MOSFETs Linear mixer Frequency doubler Locking range MOS
1. Introduction Frequency dividers (FDs) are widely used in frequency synthesizers and transceivers. LC-tank injection-locked frequency dividers (ILFDs) are a type of FDs and have potential of low power and high-frequency operation. The popular divide-by-2 ILFDs provide 2:1 frequency division because of easy design and implementation. The study of high modulo ILFDs is attractive because the design of a synthesizer can be simplified if a single-stage high modulo ILFD is used at the early IC design stage to reduce die area, consequently a cheaper circuit and system can be designed. However, a single-stage high division ratio ILFD has the property of narrow locking range. This paper studies the design of LC-tank divide-by-4 ILFD. A conventional CMOS single-stage LC-tank divide-by-4 ILFD as shown in Fig. 1(a) has been implemented using a single-injection MOSFET [1–4]. The block diagram of the conventional divide-by-4 ILFD is shown in Fig. 1(b), the ILFD [4] uses a nonlinear injection MOSFET M3 to generate the third harmonic at 3ωo. The drawback of this approach is narrow locking range. A large locking range is desirable for the ILFD robust to the variations of process, temperature and supply voltage. The second design method of divide-by-4 ILFD uses two divide-by-2 ILFDs cascaded together, this approach suffers from inevitable frequency misalignment between the two
n
Corresponding author. E-mail address: [email protected] (S.-L. Jang).
ILFDs, large die area and power consumption or increased voltage headroom. Recently, various techniques have been proposed to improve the locking range of divide-by-4 LC ILFD. Passive improvement techniques such as shunt peaking, series peaking and 4th-order LC tank [5] help improve injection efficiency at the cost of increase in die area due to the inclusion of more inductors. Active or mixed active-passive improvement techniques have been proposed in [6–8], where 4 or three active injection devices are used. The thought behind these is to utilize linear mixer instead of nonlinear mixer to enlarge the mixer conversion efficiency and hence extend the locking range. The linear mixer approach was originally invented by our research team in order to enhance the conversion efficiency [9] in a divide-by-3 ILFD. With this approach a differential injection signal is applied to the two injection MOSFETs across the LC resonator of cross-coupled oscillator [10]. The locking range is enhanced by feedback a second harmonic to the common node of two injection MOSFETs [11]. A divide-by-4 ILFD [12] was designed with the two-step mixing approach, the first step of mixing is to generate the frequency signal at (ωRF ωo) at the output of mixer, the output of first-mixer is applied to the second mixer of a divide-by-3 ILFD to provide a signal at (ωRF ωo) 2ωo at the output of ILFD. Here ωRF and ωo are, respectively, the frequencies of the injection and ILFD output signals. In this paper, we propose a single-ended injection divide-by-4 ILFD using two injection MOSFETs with an effort to make the injection circuit as simple as possible while the large locking range still remains. The ILFD uses two-step mixing approach. The block diagram of the proposed divide-by-four ILFD is shown in Fig. 2.
http://dx.doi.org/10.1016/j.mejo.2015.06.006 0026-2692/& 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: S.-L. Jang, W.-C. Liu, Injection-locked frequency divider using single-injected dual-injection MOSFETs, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.06.006i
S.-L. Jang, W.-C. Liu / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
2
VDD
VDD Vt
L1
Cv 1 Vo1
Cv 2 Vinj
R2
RFinput
Vo1
ωRF
M2
M1
C2
L2
Vo
R2
V inj
Cv2 B A
L2
R2
M4 L3
C1
R F input C 4 Vo2
M6 M2
LB
ωo
ωRF - 3ωo
3ωo
M3 M5
M6 C1
L1
Cv1
C4 Vo2
M3
M5 M1
Inj
Vt
Fig. 3. Schematic of the proposed ILFD. LB is the bonding wire inductor.
×3
Fig. 1. (a) Schematic of a conventional divide-by-4 ILFD. (b) Block diagram of the conventional divide-by-four ILFD.
Mixer1 Inj
ω RF - 2ωo
ω RF 2ωo
L2 ×2
Mixer2 ω In - ωo ω In
Filter1 C2
R2
ωo
Filter2 R1
×1
L1
ωo
CV
Vo
Vtune
Fig. 2. Simplified block diagram of the proposed divide-by-four ILFD.
The proposed ILFD consists of a feedback loop with two mixers, Mixer1 and Mixer2, and LC bandpass filters. As the input signal with angular frequency 4ωo(¼ωRF) mixes with the frequency doubler signal with angular frequency 2ωo, the angular frequency component of 2ωo(ωRF 2ωo) is produced at the output of Mixer1. The angular frequency component of 2ωo (ωRF 2ωo) mixing with the other input signal with angular frequency ωo generates a signal with angular frequency (ωRF 3ωo) at the output of Mixer2; this yields the divide-by-4 input-output frequency relation given by ωRF 3ωo ¼ωo. The RLC filters are used to filter out the undesired signals at other angular frequency. This paper is organized as follows. Section II discusses the design of the divide-by-4 LC ILFD and section III reports the experimental data of the ILFD implemented in 0.18 μm BiCMOS technology, and finally a conclusion is drawn in last section.
2. Circuit design Fig. 3 shows the schematic of the proposed divide-by-4 ILFD using a pair of cross-coupled nMOSFETs (M1, M2), which are used to generate the negative resistance to balance the resistive LC-tank loss. The parallel-tuned LC resonator consists of a center-tapped inductor L1, and accumulation-mode varactors (Cv1, Cv2). The voltage Vt is used to control the oscillation frequency of the ILFD. Two common-source amplifiers (M5, M6) with gates wired to the ILFD outputs are used as buffers for the measurement. The MOSFETs (M3, M4) are the injection MOSFETs, and the dc gate bias Vinj of MOSFETs (M3, M4) is used to optimize the locking range. An external injection signal at the frequency ωRF is ac-coupled to the common gate B of (M3, M4). Inductors (L2, L3) are series-peaking inductors used to enhance the locking range. The common node A of two injection MOSFETs (M3, M4) is wired to the output of the
bonding wire inductor LB via a dc blocking capacitor C1. The bonding wire inductor LB is used as the load of the 2nd harmonic at 2ωo, which results from the cross-coupled transistors (M1, M2) and buffers (M5, M6) operating between linear and saturation periodically. The dc blocking capacitor C1 is used to feedback the 2ωo signal to the common drain node of (M3, M4). The operation principle is discussed as follows. When no injection signal is impressed, the transistors (M3, M4) as a nonlinear common gate amplifier can generate current components at a fundamental signal at ωo and high-order harmonics; the common drain node of (M3, M4) serves as the virtual ground for the odd-harmonics and it also generates the voltage at the evenharmonics (2ωo, 4ωo). In Fig. 2, two filters are used, filter 2 represents the LC resonator in Fig. 3 and filter 1 models the C1, LB and capacitance due to (M3, M4)in Fig. 3. When injection signal at ωRF is impressed, M3 serves a Mixer1 in Fig. 2 and it generates a channel current signal IM3 at 2ωo (¼ωRF 2ωo); on the one hand, M4 serves a common gate switch Mixer2 in Fig. 2, part of IM3 goes to the source of M4 and is controlled by the source voltage of M4. The desired output current of M4 contains a frequency component at (ωRF 2ωo)–ωo which is equal to ωo. By circuit symmetry, M3 also serves as Mixer2 in Fig. 2, the source signal of M3 at (ωRF 2ωo) from capacitor C1 mixes with the gate signal of M3 to provide output signal at (ωRF 2ωo)–ωo, which is equal to ωo. The single-ended injection signal is applied to both the gates of (M3, M4) for symmetric outputs. Simulation shows that IM3 at 2ωo increases by using the feedback capacitor C1, which enhances the locking range. Simulation shows the locking range of the divide-by-4 ILFD mode under the bias condition of VDD ¼0.8 V, Vtune ¼ 0.5 V and Vinj ¼1.5 V is 2.8 GHz from 15.9 to 18.7 GHz at the injection power of 0 dBm. When the C1 is deleted, the divide-by-4 locking range is 2 GHz, from 17.0 GHz to 19.0 GHz. The 2ωo feedback increases the locking range. The injection MOSFETs switch between off and on-region periodically. For simplicity we assume that MOSFETs M3 operate in linear region, the drain current of M3 is simplified as I ds ¼ kð½V GS V TH V ds ½1 þ δV2ds =2Þ
ð1Þ
wherek ¼ μWC ox =L. W/L is channel width/length. μ is the mobility, Cox is the gate oxide capacitance. δis a coefficient accounting for the channel-length modulation effect. The primary ac voltages at source nodes of (M3 and M4) in Fig. 3 are vo sin ðωo tÞand vo sin ðωo tÞ, respectively. vs sin ðωi tÞis the injection signal. Since the output voltages of the ILFD are differential, only even harmonics vm sin ðωm tÞoccur at the common drain node A of M3 and M4. The ac drain current of injection MOSFET can be divided into
Please cite this article as: S.-L. Jang, W.-C. Liu, Injection-locked frequency divider using single-injected dual-injection MOSFETs, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.06.006i
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different frequency components: ids ¼
fkv2o ½1 δ=2g
sin ðωo tÞ sin ðωo tÞ þkvs sin ðωi tÞvm sin ðωm tÞ þ kvo vm δ sin ðωo tÞ sin ðωm tÞ þ undesired terms
ð2Þ
The first term on the right-handed side is used to form the push– push signal at the common node of (M3, M4). Under injection locking condition ωm ¼2ωo, the second term is used for the mixing function of M3 (Mixer1) in Fig. 3. The third term is used for the mixing function of M4 (Mixer2) in Fig. 3.
3. Measurement results The divide-by-4 ILFD was designed and fabricated in the TSMC 0.18 μm 3P6M BiCMOS technology. As shown in Fig. 4, the proposed wide-band divide-by-4 ILFD occupies a die area of 0.83 0.597 mm2 including all test pads and dummy metal. The 3-turn inductor L1 is shown on the top side and 2-turn symmetric inductors (L2, L3) are shown on the right and left-hand sides. A standard FR4 material is used to build the test board for the ILFD measurement. To measure the locking range and phase noise performance of the divide-by-4 LC ILFD, an Agilent N5183A signal source has been used with the Agilent E4407B spectrum analyzer. The inductors were simulated using ADS momentum. The spectraRF is used to simulate the circuit performance. At VDD ¼0.8 V, Vtune ¼ 0 V, the current and power consumption of the ILFD without buffers are 8.16 mA and 6.53 mW, respectively. The freerunning frequency of the ILFD shown in Fig. 5 is tunable from 4.27 GHz to 4.565 GHz as a tuning voltage varies from 0.0 to 2 V and when dc bias voltage Vinj is 0 V. As Vt increases the capacitance of varactor decreases, and the oscillation frequency increases. Fig. 6 shows the measured locking range of the ILFD in the divide-by-4 mode under the condition of VDD ¼ 0.8 V, with a total locking range 3.23 GHz (18.49%) from 15.85 to 19.08 GHz at the injection power of 0 dBm. At the tuning voltage Vt of 0 V, the
3
divide-by-4 locking range is 1.33 GHz (8.03%), from 15.89 GHz to 17.22 GHz. At the tuning voltage Vt of 2 V, the divide-by-4 locking range is 2 GHz (11.06%), from 17.08 GHz to 19.08 GHz. Fig. 7(a) shows the measured output spectra of the frequency divider before and after the locked conditions in the C4 mode. The locked output spectrum shows a lower phase noise and the ILFD can track the low-phase-noise of injection source. Fig. 7(b) shows the measured phase noises of the injection-reference and the injectionlocked ILFD. When the signal is injected, at 1 MHz frequency offset the phase noise of the ILFD is 130.02 dBc/Hz, while the phase noise of the injection-reference is 122.11 dBc/Hz. At low offset frequency, the phase noise of the locked ILFD is smaller than the injection signal by about 12.5 dB. The phase noise of the divide-by-4 ILFD is due to the output phase noises of the free-running ILFD and the injection source. The measured phase noise of the ILFD is dominated by the noise of the injection signal. Table 1 is the performance comparison.
Fig. 6. Measured operation frequency vs input power. In the divide-by-4 mode. VDD ¼ 0.8 V, Vt ¼ 0, 2 V (from left to right).
Fig. 4. Chip micrograph for the divide-by-4 ILFD.
-80
Phase Noise(dBc/Hz)
Frequency (GHZ)
4.6
4.5
4.4
-90 -100 -110 -120 -130 Injection Power High Band
-140
4.3 -150 104
4.2 0.0
0.5
1.0
1.5
2.0
Vtune (V) Fig. 5. Measured tuning range by varying Vt of varactor. VDD ¼0.8 V and Vinj ¼ 0 V.
105
106
107
Offset Frequency(Hz) Fig. 7. (a) Measured spectra of the injection-reference and the locked divide-by-4 ILFD and (b) measured phase noises. VDD ¼ 0.8 V, Vt ¼2 V. Vinj ¼ 1.5 V. finj¼ 19 GHz and fo ¼4.75 GHz.
Please cite this article as: S.-L. Jang, W.-C. Liu, Injection-locked frequency divider using single-injected dual-injection MOSFETs, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.06.006i
S.-L. Jang, W.-C. Liu / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎
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Table 1 Performance Comparison of divide-by-4 LC-tank ILFDs.
[1] [2] [3] [13] [14] [8] [7] This
Mixer
Resonator
Process (um)
Pin (dBm)
Die area (mm2)
VDD (V)/Pdis (mW)
Oper. range (GHz)(%)
Lock. range (GHz)
Nonlinear Nonlinear Nonlinear Nonlinear Linear Linear Linear Linear
Passive LC Passive LC Passive LC Passive LC Active LC Active LC Passive LC Passive LC
0.18 0.09 0.18 0.18 0.18 0.18 0.09 0.18
0 0 0 40 0 0 0 0
1.04 1.01 0.11 0.13 0.76 0.562 0.175 0.465 0.317 0.503 0.36 0.86 0.75 0.83 0.597
1.2/3.12 0.5/2.75 0.67/1.87 1.2/7.56 1.5/1.5 4 1.7/7.6 4 0.6/2.58 0.8/6.53
6.86 8.02(15.6) 62.9–71.6(12.9) 15.3–17.3(12.3) 45.9–50.9(10.3) 14.5–16.8(14.7) 3.6–9.4(89.2) 21.1–26.4 (22.31) 15.85–19.08 (18.49)
7.55–7.65 64.5–65.2 15.2–16.25 48.6–48.9 14.6–16.3 6.8–8.6 21.1–22.5 (6.42%) 17.08–19.08 (11.06%)
The active LC ILFD [8] requires voltage headroom due to the active inductor and it utilizes three injection MOSFETs. It is a power consuming ILFD while tuning the control voltage to enhance the speed. The proposed LC divide-by-4 ILFD is potentially for high frequency, low voltage and low power operation.
4. Conclusion A wide locking range and operation range LC-tank push–push divide-by-4 injection locked frequency divider has been proposed and fabricated using MOSFETs. The proposed ILFD uses the LC-tank cross-coupled VCO as the core for easy start-up oscillation; and it also uses two injection MOSFETs and a frequency doubler circuit so that linear mixer can be used to extend the locking range. A wide locking range divide-by-4 ILFD has been successfully designed and verified by simulation and measurement. The measured divide-by-4 locking range is 2 GHz (11.06%), from 17.08 GHz to 19.08 GHz. The locking range percentage is larger than other published LC-tank data by other research groups. The singlestage LC-tank ILFD is useful for RF circuit application. To our knowledge, this is the first reported divide-by-4 ILFD using dualinjection MOSFETs.
Acknowledgment The authors would like to thank the Staff of the CIC for the chip fabrication and technical supports.
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Please cite this article as: S.-L. Jang, W.-C. Liu, Injection-locked frequency divider using single-injected dual-injection MOSFETs, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.06.006i