- Email: [email protected]
Innovative packaging technique for backside optical testing of wire-bonded chips
Microelectronics Reliability 45 (2005) 1493–1498 www.elsevier.com/locate/microrel
Innovative packaging technique for backside optical testing of wire-bonded chips A. Tosia,*, F. Stellarib, F. Zappaa a
Politecnico di Milano, Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32, 20133 Milano (Italy) b IBM T.J. Watson Research Center – Yorktown Heights – NY 10598 (USA)
Abstract This paper describes an innovative packaging technique for versatile backside optically testing chips that require wire bonding. Since both electrical connections to the device under test and optical access through the silicon substrate are required, the sample preparation for testing the chip becomes a key issue. In fact, the thinned die is very fragile and a specific holder is necessary. The proposed package fulfils all these requirements and can be used for PICA measurements, EMMI investigations, LVP, TLS, PLS and other failure analysis methods that require optical access to the transistor level through the silicon backside. Ó 2005 Elsevier Ltd. All rights reserved.
1. Introduction Testability of ultra-scaled chips is an important issue of modern semiconductor companies. Optical testing techniques, especially Picosecond Imaging Circuit Analysis (PICA) [1], EMission MIcroscopy (EMMI) [2], Laser Voltage Probe (LVP) [3], Thermal Laser Stimulation (TLS) [4], Photoelectric Laser Stimulation (PLS) [5], allow testing internal signals, provided that an optical access to the transistor level of the chip does exist. Nowadays, the high number of metal layers prevents optical testing from the front side of integrated circuits, and imposes the testing from only the backside of the chip, where optical access to MOS transistors is possible [6]. Since the silicon absorption is high, especially for wavelengths shorter than 1.1 µm and for highly-doped substrates [7], it is
necessary to thin the substrate of the chip in order to lower the silicon absorption [8]. After the thinning, the die is fragile and has to be packaged for electrical and optical testing. During the optical testing phase, the chips designed for Flip-Chip Ball Grid Array (BGA) packages are mounted into Temporally Chip Attach (TCA) packages. The TCA package allows the thinning of the chip and can be used directly during optical testing. However, when a chip either cannot be put into a TCA package or does not come inside a package with free optical access to the substrate, there are no means of easily optically testing it from the backside. Unfortunately, all available packages are mostly designed for electrical testing and they do not take into account the requirements of optical testing from the backside. At the same time, the optical testing from the
* Corresponding author. [email protected] Tel: +39-02-2399.6174; Fax: +39-02-2399.3699 0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.044
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A. Tosi et al. / Microelectronics Reliability 45 (2005) 1493–1498
2. Glass Attached Chip
(a)
(b) Fig. 1 Schematic diagram of a conventional wire-bond package (a) and of conventional flip-chip package (b).
front side of the chip is in general impeded by the dense Back End Of Line (BEOL) structures. In fact, the high number of metal layers shields the transistors when the chip is accessed from the front side, thus preventing either the collection of photons emitted from the MOSFET or the focusing of a laser beam. A package that can fulfil all the requirements of optical testing from the backside and from the front side of the chips is very desirable.
(a) Photons
pin (b)
(c)
glass
CHIP bonding
Photons
Laser
Fig. 2 Schematic diagram depicting the cross-section (a) and 3D views (b and c) of the Glass Attached Chip.
In this paper, we present our newly invented packaging method, called “Glass Attached Chip” (GAC), specifically designed to hold a thinned chip for optical testing from the backside. The specifications of such versatile package are herein reported. It provides electrical connections for bonding/wiring on-chip front side pads to external pins; it provides optical access to the backside and possibly the front side of the integrated circuit; it has a transparent medium (glass or other material) to hold the thinned fragile chip and to allow light transmission; it can take advantage of matching index materials for improving detection efficiency (coating and matching materials for the supporting transparent medium and the chip attachment to the medium are a very important and intrinsic part of these packages); all package dimensions are scalable to fit chips of different sizes, as well as Device Under Test (DUT) board requirements; it is compatible with the use of diamond windows [9] or spray cooling for chip cooling [10]; it is compatible with Solid Immersion Lens (SIL) [11] and liquid immersion lens. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, relatively low cost, and the fact that it is designed for optical testing and not just for electrical testing. 3. Package description Commercial packages do not provide both electrical connections and optical access to the backside of the chip at the same time. Only flip-chip packages can be easily used for optical testing from the backside. In flip-chip packages, like BGA (Ball Grid Array), the die has pads across the entire front surface. Solder balls connect the chip to the package with the die mounted face-down in the package. However, a lot of chips are not designed for flip-chip packages and they usually fit only wire-bond packages with no optical access to the backside. These packages are connected to the pads placed along the die perimeter through wires. The die is mounted face-up in the package and the probe can see the top layers of metals. Fig. 1 shows a schematic of wire-bond (a) and of flip-chip (b) packages. The sample preparation for optical testing requires a substrate thinning down to less than 100 µm. There are both global and local techniques for thinning chips. Global techniques, such as the mechanical grinding,
A. Tosi et al. / Microelectronics Reliability 45 (2005) 1493–1498
D
(a)
OBJECTIVE
n0
LF
air
WD
\
ng
H
glass
T
air
W
silicon
[ G
n0 nsi
I A
(b)
OBJECTIVE
n0
D LF
air
WD ng
\
H
glass
T
match
W
silicon
[ nM nsi
I A
Fig. 3 Detection efficiency analysis of the Glass Attached Chip structure without (a) and with (b) a matching index material between glass and silicon.
the lapping and the chemical etchings, thin the whole die. On the contrary, local techniques, such as the Computer Numerically Controlled Milling, the Focused Ion Beam (FIB) and the Laser Activated Etching, usually thin small areas. Both global and local techniques can be used for thinning chip that will be housed in the proposed GAC package. Furthermore, the thinned chip is much more fragile than a standard non-thinned one. In order to handle it and to provide the electrical connections together with the optical access we propose the package shown in Fig. 2. The proposed GAC package allows the use of PICA tools (such as the Emiscope series from Credence [12]), backside infrared emission
1495
microscopes (such as the Phemos series from Hamamatsu [13]), LVP tools and other optical techniques on virtually every chip. In the following, we will refer mainly to emission-based systems (Fig. 2 (a)) but the same considerations apply to laser-based techniques (Fig. 2 (b)). The Device Under Test (DUT), i.e. the chip, is laid on a thin layer of glass. The glass is the holder and must be chosen in order to allow a high transmission in the wavelength range of interest (e.g. 0.8 µm - 1.7 µm for measuring hot-carrier luminescence emitted by MOSFET in CMOS technologies). Instead of glass, a high transmittance material for the range of interest can be used (e.g. quartz materials, plastics, diamond). The chip is glued to the glass with glue droplets only on the corners of the chip or along the sides. Optionally, a matching index material can be placed between the die and the glass in order to improve the collection efficiency of the photons emitted from the backside of the die. Using a matching index material, with a refractive index value between that of the refractive index of silicon and that of the glass, the transmittance through the Glass Attached Chip structure toward the collection lenses improves. Analyzing the structure objective-air-glass“space”-silicon, there may be two cases: one with the air (refractive index n0) between the glass and the silicon (see Fig. 3(a)), and the other one with a matching index material (refractive index nM > n0) between the glass and the silicon (see Fig. 3(b)). In Fig. 3, “A” indicates the point where photons are emitted, “D” is the diameter of the collecting objective lens and “WD” is the working distance of the objective in air. Fig. 3(b) reports the case with nM=nSi. If thickness of the glass (H), silicon (W) and “space” (between the chip and the glass) are the same in the two cases, from Fig. 3 one can note that the angle is wider when a matching index material is used (Fig. 3(a)). In fact, by using basic formulas of optics, the distance LF between the objective lens and the glass is lower and the collecting angle can reach higher values. Moreover, the transmission of light from “A” to the objective is higher due to the matching of refractive indexes. For normal incidence, the transmitting coefficient T from medium 1 to medium 2 can be written as
T
4 n1 n2
n1 n2
2
.
(1)
The maximum T can be achieved with an appropriate matching index material (nM).
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The thickness of the glass should be chosen to adequately hold the die (especially during the wire bonding phase) and to transmit the highest amount of light. The glass and the body of the package must be sufficiently sturdy to provide a solid package that can be easily used also in commercial sockets. The glass, with the attached chip, is then mounted on the body of the package. The body of the package provides the electrical connections. There are pads for wiring the chip to the GAC package and pins to connect the GAC package to the electronic board for testing (see Fig. 2). The package can be designed with the most suitable shape in order to fulfil the requirements of the electronic testing board. Moreover, it is possible to add electronic components very close to the DUT, directly on the package, in order to avoid the parasitic effects of the electrical connections towards the outer electronic board. For example, it is possible to place decoupling capacitors on power lines or to design signal paths with EMI shielding or impedance matching. The body of the GAC has a hole in the centre (see Fig. 2). The glass with the die must be aligned with the hole and fastened to the body. Once the chip has been
fixed to the Glass Attached Chip, wire bondings can be placed from the chip to the pads of the package for the electrical connections. Since the bonding wires should not touch the body of the GAC, the latter should be very thin around the hole. Hence, the front side and package pads are almost on the same level. It must be noted that during the bonding phase care must be taken in order to prevent glass from cracking. To this purpose, the whole structure (glass plus body package) has to be laid temporary on a plain surface. The resulting GAC package is shown in Fig. 4, where the bottom figure is a zoom of the bonded chip showing how the chip is connected to the body package.
(a)
(b)
Fig. 4
Pictures of a sample of Glass Attached Chip.
Fig. 5 Photos of the mounting of the Glass Attached Chip package inside a Hamamatsu Phemos (a) and PICA tool by NPTest [14] (b) used for measurements on a recent technologies.
A. Tosi et al. / Microelectronics Reliability 45 (2005) 1493–1498
4. Applications and measurements The proposed GAC package has been successfully used for optically measure test chips in advanced CMOS technologies [16]. Here we report two examples. During the first case study, we characterized single MOS transistors with channel length of 100 nm. The die was housed in a GAC package, set in a Hamamatsu Phemos 1000 [13] and connected to a parameter analyzer (see Fig. 5(a)). Fig. 6(a) shows a LSM (Laser Scanning Microscope) image of a MOS transistor mounted in a GAC package. The image is obtained focusing the laser (Ȝ=1.064 µm) through the glass substrate and the backside of the chip. The contrast and the overall image quality are very good. We did not observe any decrease in the image quality when acquiring through the glass substrate compared to images acquired with no glass layer. The photon emission from the MOSFET has been measured (by means of HgCdTe detector [13]) and is reported in Fig. 6(b). Again, the collection efficiency is very good and no drawbacks have been observed. As a second case study, we measured the photon emission from an CMOS ring oscillator (supply voltage VDD=1.2V, channel length L=100 nm). The chip, mounted in a GAC package, has been inserted in a test board inside the PICA tool (see Fig. 5(b)). By means of a Superconducting Single-Photon Detector (SSPD) detector [15] and a TCSCP technique [17], we reconstructed the optical waveforms emitted through the substrate of the chip (see Fig. 7). The quality of the acquired measurements is very good and the high SNR obtained allows measuring also the faint luminescence from p-FET. Also the timing characteristics of the
1497
optical waveforms (e.g. FWHM of the peaks, peak position accuracy, etc) are in agreement with what measured on chips mounted in packages other than GAC package. The proposed package is also compatible with the diamond windows or spray (air, nitrogen or specific cooling sprays) used for cooling the chip. It is also compatible with Solid Immersion Lens (SIL) [11] that can be used for increasing the Numeric Aperture of the optical system that collects the photon from the backside of the chip. SIL lenses can be used directly on the outer side of the glass with respect to the DUT. 5. Conclusions In this paper, we presented an innovative packaging technique for backside optically testing chips that require wire bonding. The proposed solution provides both electrical connections to the device under test and optical access through the silicon substrate and it can be used for PICA-like techniques, EMMI investigations, LVP, TLS, PLS and other failure analysis methods that require optical access to the transistor level through the silicon backside. Applications and measurements proved that the GAC package is a valid tool for backside testing of wirebond chips. 6. Acknowledgements The authors wish to thank Luciano Pallaro, Sergio Masci, Peilin Song, Richard A. John, Christian W. Baks, James R. Salimeno and John D. Sylvestri for their help in preparing the samples, manufacturing and mounting the prototype packages and testing the chips.
(a)
(b)
10µm
Photon Counts (a.u.)
40
n-FET
35 30 25
p-FET
20 15 10 5 0
3
4
5
6
7
8
9
10
Time [ns] Fig. 6 LSM image of a single MOSFET (a) and corresponding emission (b). The circuit is from a chip mounted in a GAC package (backside access).
Fig. 7 Time-resolved measurement of a ring oscillator. The circuit is from a chip mounted in a GAC package (backside access).
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References [1] J.C. Tsang and J.A. Kash, “Picosecond hot electron light emission from submicron complementary metaloxide-semiconductor circuits”, Appl. Phys. Lett., vol. 70, no. 7, 1997, pp. 889-891. [2] J. Kolzer et al., “Quantitative emission microscopy”, J. Appl. Phys., vol. 71, no. 11, 1992, pp. 23-41. [3] T.M. Eiles, D.L. Woods, V. R. Rao “Optical Probing of Flip-Chip-Packaged Microprocessors”, Proc. of International Solid-State Circuits Conference, 2000, pp. 220-221. [4] E.I. Cole Jr., P. Tangyunyong, D.L. Barton “Backside Localization of Open and Shorted IC Interconnections”, Proc. Of International Reliability Physics Symposium, 1998, pp. 129-136. [5] A. Firiti, D. Lewis, F. Beaudoin, P. Perdu, G. Haller, Y. Danto, “Implementing Thermal Laser and Photoelectric Laser Stimulation in a failure analysis laboratory”, Proc. of IPFA 2003, 7-11 July 2003, pp. 210 – 212. [6] A. Tosi, F. Stellari, F. Zappa, and S. Cova, “Backside Flip-Chip testing by means of high-bandwidth luminescence detection”, Microelectronics Reliability, vol. 43, issue 9-11, 1169-1674, 2003. [7] P.E. Schmid, “Optical absorption in heavily doped silicon”, Phys. Rev. B, vol. 23, 10, 1981, pp. 55315536. [8] P. Perdu, R. Desplats, F. Beaudoin, “A review of sample backside preparation techniques for VLSI”, Microelectronics Reliability, vol. 40, 2000, pp. 14311436. [9] T.M. Eiles, D. Hunt, and David Chi, "Transparent heat spreader for backside optical analysis of high power microprocessor", Proc. of ISTFA 2000, 15-19 November 2000, Bellevue, Washington, pp. 547-551. [10] R.R. Goruganthu, D. Bethke, Shawn McBride, T. Crawford, J. Frank, D. Cotton, and T. Cader, "Spray Cooling for Time Resolved Emission Measurements of ICs", Proc. of International Symposium for Testing and Failure Analysis, November 14-18, 2004, Worcester, Massachusetts, pp. 18-23. [11] S. B. Ippolito, B. B. Goldberg, and M. S. Unlu, “High spatial resolution subsurface microscopy”, Appl. Phys. Lett., vol. 78, no. 26, 2001, pp. 4071-4073. [12] Emiscope II description, www.credence.com [13] Phemos description, www.hamamatsu.com [14] OptiCA description, www.nptest.com [15] Gol'tsman, G. N., Okunev, O., Chulkova, G., Lipatov, A., Dzardanov, A., Smirnov, K., Semenov, A., Voronov, B., Williams, C., and Sobolewski, R., “Fabrication and properties of an ultrafast NbN hotelectron single-photon detector”, Applied Superconductivity, IEEE Transactions on, 11, pp. 574577, 2001. [16] F. Stellari, A. Tosi, F. Zappa, and S. Cova, “CMOS Circuit Testing via Time-Resolved Luminescence Measurements and Simulations”, IEEE Trans. on
Instrumentation and Measurements, vol. 53, 163-169, 2004. [17] D.V. O’Connor, D. Phillips, Time-correlated Single Photon Counting, The Royal Institution, Academic Press, London (1984).
Innovative packaging technique for backside optical testing of wire-bonded chips A. Tosia,*, F. Stellarib, F. Zappaa a
Politecnico di Milano, Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32, 20133 Milano (Italy) b IBM T.J. Watson Research Center – Yorktown Heights – NY 10598 (USA)
Abstract This paper describes an innovative packaging technique for versatile backside optically testing chips that require wire bonding. Since both electrical connections to the device under test and optical access through the silicon substrate are required, the sample preparation for testing the chip becomes a key issue. In fact, the thinned die is very fragile and a specific holder is necessary. The proposed package fulfils all these requirements and can be used for PICA measurements, EMMI investigations, LVP, TLS, PLS and other failure analysis methods that require optical access to the transistor level through the silicon backside. Ó 2005 Elsevier Ltd. All rights reserved.
1. Introduction Testability of ultra-scaled chips is an important issue of modern semiconductor companies. Optical testing techniques, especially Picosecond Imaging Circuit Analysis (PICA) [1], EMission MIcroscopy (EMMI) [2], Laser Voltage Probe (LVP) [3], Thermal Laser Stimulation (TLS) [4], Photoelectric Laser Stimulation (PLS) [5], allow testing internal signals, provided that an optical access to the transistor level of the chip does exist. Nowadays, the high number of metal layers prevents optical testing from the front side of integrated circuits, and imposes the testing from only the backside of the chip, where optical access to MOS transistors is possible [6]. Since the silicon absorption is high, especially for wavelengths shorter than 1.1 µm and for highly-doped substrates [7], it is
necessary to thin the substrate of the chip in order to lower the silicon absorption [8]. After the thinning, the die is fragile and has to be packaged for electrical and optical testing. During the optical testing phase, the chips designed for Flip-Chip Ball Grid Array (BGA) packages are mounted into Temporally Chip Attach (TCA) packages. The TCA package allows the thinning of the chip and can be used directly during optical testing. However, when a chip either cannot be put into a TCA package or does not come inside a package with free optical access to the substrate, there are no means of easily optically testing it from the backside. Unfortunately, all available packages are mostly designed for electrical testing and they do not take into account the requirements of optical testing from the backside. At the same time, the optical testing from the
* Corresponding author. [email protected] Tel: +39-02-2399.6174; Fax: +39-02-2399.3699 0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.044
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A. Tosi et al. / Microelectronics Reliability 45 (2005) 1493–1498
2. Glass Attached Chip
(a)
(b) Fig. 1 Schematic diagram of a conventional wire-bond package (a) and of conventional flip-chip package (b).
front side of the chip is in general impeded by the dense Back End Of Line (BEOL) structures. In fact, the high number of metal layers shields the transistors when the chip is accessed from the front side, thus preventing either the collection of photons emitted from the MOSFET or the focusing of a laser beam. A package that can fulfil all the requirements of optical testing from the backside and from the front side of the chips is very desirable.
(a) Photons
pin (b)
(c)
glass
CHIP bonding
Photons
Laser
Fig. 2 Schematic diagram depicting the cross-section (a) and 3D views (b and c) of the Glass Attached Chip.
In this paper, we present our newly invented packaging method, called “Glass Attached Chip” (GAC), specifically designed to hold a thinned chip for optical testing from the backside. The specifications of such versatile package are herein reported. It provides electrical connections for bonding/wiring on-chip front side pads to external pins; it provides optical access to the backside and possibly the front side of the integrated circuit; it has a transparent medium (glass or other material) to hold the thinned fragile chip and to allow light transmission; it can take advantage of matching index materials for improving detection efficiency (coating and matching materials for the supporting transparent medium and the chip attachment to the medium are a very important and intrinsic part of these packages); all package dimensions are scalable to fit chips of different sizes, as well as Device Under Test (DUT) board requirements; it is compatible with the use of diamond windows [9] or spray cooling for chip cooling [10]; it is compatible with Solid Immersion Lens (SIL) [11] and liquid immersion lens. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, relatively low cost, and the fact that it is designed for optical testing and not just for electrical testing. 3. Package description Commercial packages do not provide both electrical connections and optical access to the backside of the chip at the same time. Only flip-chip packages can be easily used for optical testing from the backside. In flip-chip packages, like BGA (Ball Grid Array), the die has pads across the entire front surface. Solder balls connect the chip to the package with the die mounted face-down in the package. However, a lot of chips are not designed for flip-chip packages and they usually fit only wire-bond packages with no optical access to the backside. These packages are connected to the pads placed along the die perimeter through wires. The die is mounted face-up in the package and the probe can see the top layers of metals. Fig. 1 shows a schematic of wire-bond (a) and of flip-chip (b) packages. The sample preparation for optical testing requires a substrate thinning down to less than 100 µm. There are both global and local techniques for thinning chips. Global techniques, such as the mechanical grinding,
A. Tosi et al. / Microelectronics Reliability 45 (2005) 1493–1498
D
(a)
OBJECTIVE
n0
LF
air
WD
\
ng
H
glass
T
air
W
silicon
[ G
n0 nsi
I A
(b)
OBJECTIVE
n0
D LF
air
WD ng
\
H
glass
T
match
W
silicon
[ nM nsi
I A
Fig. 3 Detection efficiency analysis of the Glass Attached Chip structure without (a) and with (b) a matching index material between glass and silicon.
the lapping and the chemical etchings, thin the whole die. On the contrary, local techniques, such as the Computer Numerically Controlled Milling, the Focused Ion Beam (FIB) and the Laser Activated Etching, usually thin small areas. Both global and local techniques can be used for thinning chip that will be housed in the proposed GAC package. Furthermore, the thinned chip is much more fragile than a standard non-thinned one. In order to handle it and to provide the electrical connections together with the optical access we propose the package shown in Fig. 2. The proposed GAC package allows the use of PICA tools (such as the Emiscope series from Credence [12]), backside infrared emission
1495
microscopes (such as the Phemos series from Hamamatsu [13]), LVP tools and other optical techniques on virtually every chip. In the following, we will refer mainly to emission-based systems (Fig. 2 (a)) but the same considerations apply to laser-based techniques (Fig. 2 (b)). The Device Under Test (DUT), i.e. the chip, is laid on a thin layer of glass. The glass is the holder and must be chosen in order to allow a high transmission in the wavelength range of interest (e.g. 0.8 µm - 1.7 µm for measuring hot-carrier luminescence emitted by MOSFET in CMOS technologies). Instead of glass, a high transmittance material for the range of interest can be used (e.g. quartz materials, plastics, diamond). The chip is glued to the glass with glue droplets only on the corners of the chip or along the sides. Optionally, a matching index material can be placed between the die and the glass in order to improve the collection efficiency of the photons emitted from the backside of the die. Using a matching index material, with a refractive index value between that of the refractive index of silicon and that of the glass, the transmittance through the Glass Attached Chip structure toward the collection lenses improves. Analyzing the structure objective-air-glass“space”-silicon, there may be two cases: one with the air (refractive index n0) between the glass and the silicon (see Fig. 3(a)), and the other one with a matching index material (refractive index nM > n0) between the glass and the silicon (see Fig. 3(b)). In Fig. 3, “A” indicates the point where photons are emitted, “D” is the diameter of the collecting objective lens and “WD” is the working distance of the objective in air. Fig. 3(b) reports the case with nM=nSi. If thickness of the glass (H), silicon (W) and “space” (between the chip and the glass) are the same in the two cases, from Fig. 3 one can note that the angle is wider when a matching index material is used (Fig. 3(a)). In fact, by using basic formulas of optics, the distance LF between the objective lens and the glass is lower and the collecting angle can reach higher values. Moreover, the transmission of light from “A” to the objective is higher due to the matching of refractive indexes. For normal incidence, the transmitting coefficient T from medium 1 to medium 2 can be written as
T
4 n1 n2
n1 n2
2
.
(1)
The maximum T can be achieved with an appropriate matching index material (nM).
1496
A. Tosi et al. / Microelectronics Reliability 45 (2005) 1493–1498
The thickness of the glass should be chosen to adequately hold the die (especially during the wire bonding phase) and to transmit the highest amount of light. The glass and the body of the package must be sufficiently sturdy to provide a solid package that can be easily used also in commercial sockets. The glass, with the attached chip, is then mounted on the body of the package. The body of the package provides the electrical connections. There are pads for wiring the chip to the GAC package and pins to connect the GAC package to the electronic board for testing (see Fig. 2). The package can be designed with the most suitable shape in order to fulfil the requirements of the electronic testing board. Moreover, it is possible to add electronic components very close to the DUT, directly on the package, in order to avoid the parasitic effects of the electrical connections towards the outer electronic board. For example, it is possible to place decoupling capacitors on power lines or to design signal paths with EMI shielding or impedance matching. The body of the GAC has a hole in the centre (see Fig. 2). The glass with the die must be aligned with the hole and fastened to the body. Once the chip has been
fixed to the Glass Attached Chip, wire bondings can be placed from the chip to the pads of the package for the electrical connections. Since the bonding wires should not touch the body of the GAC, the latter should be very thin around the hole. Hence, the front side and package pads are almost on the same level. It must be noted that during the bonding phase care must be taken in order to prevent glass from cracking. To this purpose, the whole structure (glass plus body package) has to be laid temporary on a plain surface. The resulting GAC package is shown in Fig. 4, where the bottom figure is a zoom of the bonded chip showing how the chip is connected to the body package.
(a)
(b)
Fig. 4
Pictures of a sample of Glass Attached Chip.
Fig. 5 Photos of the mounting of the Glass Attached Chip package inside a Hamamatsu Phemos (a) and PICA tool by NPTest [14] (b) used for measurements on a recent technologies.
A. Tosi et al. / Microelectronics Reliability 45 (2005) 1493–1498
4. Applications and measurements The proposed GAC package has been successfully used for optically measure test chips in advanced CMOS technologies [16]. Here we report two examples. During the first case study, we characterized single MOS transistors with channel length of 100 nm. The die was housed in a GAC package, set in a Hamamatsu Phemos 1000 [13] and connected to a parameter analyzer (see Fig. 5(a)). Fig. 6(a) shows a LSM (Laser Scanning Microscope) image of a MOS transistor mounted in a GAC package. The image is obtained focusing the laser (Ȝ=1.064 µm) through the glass substrate and the backside of the chip. The contrast and the overall image quality are very good. We did not observe any decrease in the image quality when acquiring through the glass substrate compared to images acquired with no glass layer. The photon emission from the MOSFET has been measured (by means of HgCdTe detector [13]) and is reported in Fig. 6(b). Again, the collection efficiency is very good and no drawbacks have been observed. As a second case study, we measured the photon emission from an CMOS ring oscillator (supply voltage VDD=1.2V, channel length L=100 nm). The chip, mounted in a GAC package, has been inserted in a test board inside the PICA tool (see Fig. 5(b)). By means of a Superconducting Single-Photon Detector (SSPD) detector [15] and a TCSCP technique [17], we reconstructed the optical waveforms emitted through the substrate of the chip (see Fig. 7). The quality of the acquired measurements is very good and the high SNR obtained allows measuring also the faint luminescence from p-FET. Also the timing characteristics of the
1497
optical waveforms (e.g. FWHM of the peaks, peak position accuracy, etc) are in agreement with what measured on chips mounted in packages other than GAC package. The proposed package is also compatible with the diamond windows or spray (air, nitrogen or specific cooling sprays) used for cooling the chip. It is also compatible with Solid Immersion Lens (SIL) [11] that can be used for increasing the Numeric Aperture of the optical system that collects the photon from the backside of the chip. SIL lenses can be used directly on the outer side of the glass with respect to the DUT. 5. Conclusions In this paper, we presented an innovative packaging technique for backside optically testing chips that require wire bonding. The proposed solution provides both electrical connections to the device under test and optical access through the silicon substrate and it can be used for PICA-like techniques, EMMI investigations, LVP, TLS, PLS and other failure analysis methods that require optical access to the transistor level through the silicon backside. Applications and measurements proved that the GAC package is a valid tool for backside testing of wirebond chips. 6. Acknowledgements The authors wish to thank Luciano Pallaro, Sergio Masci, Peilin Song, Richard A. John, Christian W. Baks, James R. Salimeno and John D. Sylvestri for their help in preparing the samples, manufacturing and mounting the prototype packages and testing the chips.
(a)
(b)
10µm
Photon Counts (a.u.)
40
n-FET
35 30 25
p-FET
20 15 10 5 0
3
4
5
6
7
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Time [ns] Fig. 6 LSM image of a single MOSFET (a) and corresponding emission (b). The circuit is from a chip mounted in a GAC package (backside access).
Fig. 7 Time-resolved measurement of a ring oscillator. The circuit is from a chip mounted in a GAC package (backside access).
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