- Email: [email protected]
output microprogramming: an overview
Q Euromicro, 1976 North-Holland Publishing Co., Amsterdam
INPUT/OUTPUT
MICROPROGRAMMING:
Helmut
Berndt
Guest
Editor
Abstract An i n t r o d u c t i o n to t h e d e v e l o p m e n t of inp u t / o u t p u t h a n d l i n g in d a t a p r o c e s s i n g s y s t e m s is b e i n g p r o v i d e d . The d i f f e r e n t o r g a n i z a t i o n a l forms are d i s c u s s e d in rel a t i o n to m i c r o p r o g r a m c o n t r o l l e d i m p l e mentations. f h e r e e x i s t s e v e r a l - m i c r o p r o g r a m supp o r t e d - c o n t r o l s t r a t e g i e s today. P e r t i n e n t e x a m p l e s of such r e a l i z a t i o n s are b e i n g r e p o r t e d in this special issue of the EUROMICRO Newsletter. T h i s s u r v e y is m e a n t to p r o v i d e t h e n e c e s s a r y b a c k g r o u n d and p e r s p e c t i v e . 1. I N T R O D U C T I O N E f f i c i e n t input as w e l l as o u t p u t h a n d l i n g s t i l l c o n s t i t u t e s one of the m o s t p r e s s i n g p r o b l e m s e n c o u n t e r e d in contemporary data processing system design and d e v e l o p m e n t . T h e e m p h a s i s , h o w e v e r , has s h i f t e d c o n s i d e r a b l y f r o m the o n c e p r e v a i l i n g c o m p l a i n t a b o u t slow p e r i p h e rals to the c o n c e r n of h o w to a c c o m m o d a t e the just e m e r g i n g g e n e r a t i o n of high-speed d e v i c e s , like d i s k d r i v e s , tape s t a t i o n s , and n o n i m p a c t p r i n t e r s . In a d d i t i o n , the i n c r e a s e d use of d a t a c o m m u n i c a t i o n - f a c i l i t i e s p o s e s even n e w p r o b l e m s w i t h r e g a r d to r e a l - t i m e beh a v i o r and the d i s t r i b u t i o n of i n t e l l i gence.
The g e n e r a l n e g l e c t of i n p u t and o u t p u t h a n d l i n g - to be o b s e r v e d in p r a c t i c a l l y all a c c e s s i b l e p u b l i c a t i o n s - m u s t h a v e c o n t r i b u t e d to that r a t h e r u n f o r t u n a t e s i t u a t i o n . This first " s p e c i a l " of the EUROMICRO Newsletter t h r i v e s to p r o v i d e at l e a s t - some r e m e d y . R e p r e s e n t a t i v e e x a m p l e s of m o r e recent, E u r o p e a n c o n t r i b u t i o n s to input/output microprogramming, control, and r e l a t e d system organization are p u b l i s h e d in this i s s u e [i] - [5]. The list of p o t e n t i a l c o n t r i b u t o r s is n e c e s s a r i l y i n c o m p l e t e . Y e t all i m p o r t a n t i n p u t / o u t p u t o r g a n i z a t i o n s are b e i n g covered. -
This i n t r o d u c t o r y s u r v e y s h o u l d p r o v i d e the n e c e s s a r y background i n f o r m a t i o n in o r d e r to a l l o w p r o p e r a s s e s s m e n t s of the contributed papers. 2.
INPUT/OUTPUT
ORGANIZATION
The t r a n s f e r of d a t a (as w e l l as p r o grams) b e t w e e n p e r i p h e r a l devices and a c e n t r a l o r main memory c o n s t i t u t e s o n e of the m a j o r a c t i v i t i e s e n c o u n t e r e d in
IMAINMEMORYI
F o r t u n a t e l y , t h o s e g r o w i n g n e e d s are being m e t by p r o f o u n d a d v a n c e s in p r o c e s s o r o r g a n i z a t i o n and t e c h n o l o g y . The u s e of m i c r o p r o g r a m m i n g has f o u n d its w a y into the i n p u t / o u t p u t a r e a a i d e d by the a v a i l a b i l i t y of s u f f i c i e n t l y "fast" c o n t r o l stores. But p r o p e r r e c o g n i t i o n of the n e c e s s i t y for an i t e r a t i v e d e s i g n p r o cess - i n c l u d i n g s t e p w i s e r e f i n e m e n t c o n t r i b u t e d just as h e a v i l y t o w a r d s the s u c c e s s f u l d e p l o y m e n t of t h i s c o n t r o l t e c h n i q u e . Today, input~output microprogrammzng o f f e r s a g r e a t p o t e n t i a l in m e e t i n g the d e m a n d s of the future.
0101i01 Fig.
But d e s p i t e of such p e r s p e c t i v e s , v i r t u a l l y n o t h i n g m a y b e f o u n d in the app r o p r i a t e l i t e r a t u r e to s u p p o r t this view.
AN OVERVIEW
l: G e n e r a l v i e w of i n p u t / o u t p u t as d a t a e x c h a n g e b e t w e e n p e r i p h e r a l d e v i c e s (D) and m a i n memory
4
HELMUT BERNDT
'aJ
MAINMEMORY I I
(b]
I MAINMEMORYI
\
CPU
° (C)
I
I ol
lololol (d)
MAINMEMORY
I MAINMEMORYI
/
\
CPU IOC
Fig.
2: I n p u t / o u t p u t as d a t a e x c h a n g e b e t w e e n m a i n m e m o r y and p e r i p h e r a l d e v i c e s (D) v i a a c e n t r a l p r o c e s s i n g u n i t (CPU) a n d / o r an i n p u t / o u t p u t c o n t r o l l e r (IOC). The d i f f e r e n t forms of o r g a n i z a t i o n are being shown
any d a t a p r o c e s s i n g s y s t e m [6]. We comm o n l y r e f e r to it as input o r output (in s h o r t input~output). F i g u r e 1 p r o v i d e s a r a t h e r g e n e r a l v i e w of this a c t i v i t y . Data are b e i n g e x c h a n g e d b e t w e e n i n d i v i d u a l d e v i c e s (D), or d e v i c e c l u s t e r s (several D's), and m a i n m e m o r y , A n y i n p u t / o u t p u t o p e r a t i o n to be e x e c u t e d in such an e n v i r o n m e n t has to f u l l f i l all of the f o l l o w i n g o b j e c t i v e s :
o
device addressing which
amounts
to the s e l e c t i o n
of the
requested o
input/output
device;
device status handling w h i c h a m o u n t s to an i n t e r r o g a t i o n the a p p r o p r i a t e d e v i c e status;
o
command transmission w h i c h a m o u n t s to the d e t e r m i n a t i o n the d e s i r e d o p e r a t i o n ;
o
of
medium addressin E w h i c h a m o u n t s to the d e f i n i t i o n of the r e q u e s t e d i n p u t / o u t p u t a r e a on the d a t a carrier;
of
INPUT/OUTPUT MICROPROGRAMMING: AN OVERVIEW o
o o
2.1 Central Processor Control
memory addressing which amounts the r e q u e s t e d main memory;
to t h e d e f i n i t i o n of i n p u t / o u t p u t a r e a in
data transfers; termination w h i c h a m o u n t s to s i g n a l i n g a T e r m i n a t i o n I n t e r r u p t (or the like) to the c e n t r a l p r o c e s s i n g unit.
This s e q u e n t i a l l i s t i n g of p e r t i n e n t control a c t i v i t i e s e x c l u d e s all t i m i n g cons t r a i n t s , as d i c t a t e d b y c e r t a i n r e a l i z a t i o n s of p a r t i c u l a r i n p u t / o u t p u t interfaces. A l l of the l i s t e d f u n c t i o n s have to be p e r f o r m e d for any i n p u t / o u t p u t oper a t i o n [6].
F i g u r e 2 d e m o n s t r a t e s four c o n c e p t i o n a l p o s s i b i l i t i e s for m e e t i n g t h e s e o b j e c tives. T h e y r e l y u p o n d i f f e r i n g forms of input/output organizations.
The f i r s t case, d e p i c t e d in F i g 2 (a) , a u g m e n t s the g e n e r a l c o n c e p t of i n p u t / o u t p u t h a n d l i n g (see Fig. i) by the nec e s s a r y p r o c e s s i n g p o w e r in o r d e r to ass e m b l e a d a t a p r o c e s s i n g system. But in reality, actual development commenced a r o u n d the c e n t r a l p r o c e s s i n g unit (CPU). It h a n d l e d all i n p u t / o u t p u t n e e d s in m o s t e a r l i e r d a t a p r o c e s s i n g s y s t e m s as w e l l as in c u r r e n t micro c o m p u t e r s . T h i s case is s h o w n as Fig. 2 (b). S i m i l a r i l y , further e n h a n c e m e n t s of the i n p u t / o u t p u t org a n i z a t i o n o c c u r r e d in r e l a t i o n to the CPU. T h e channel c o n c e p t e v o l v e d f r o m the IBM 709-7090-7094 c o m p u t e r " f a m i l y " [7]. F i g u r e 2 (c) d e m o n s t r a t e s this s i t u a t i o n . A n i n p u t / o u t p u t c o n t r o l l e r (IOC) r e a l i z e s the c h a n n e l f u n c t i o n s [8]. T h i s f o r m for an i n p u t / o u t p u t o r g a n i z a t i o n of general purpose c o m p u t e r s y s t e m s d e v e l o p e d into an i n d u s t r y s t a n d a r d for third g e n e r a t i o n e q u i p m e n t . But the e v e r i n c r e a s i n g d a t a t r a n s f e r r a t e s of m o d e r n p e r i p h e r a l s dem a n d m u c h h i g h e r s e r v i c i n g rates. I n p u t / o u t p u t c o n t r o l l e r s or e v e n processors h a n d l i n g the r e q u i r e d d a t a t r a n s f e r s w i t h o u t any i n t e r v e n t i o n of t h e c e n t r a l p r o c e s s i n g unit, m a y m e e t this i n c r e a s e d r e q u i r e m e n t s . F i g u r e 2 (d) s h o w s t h e app r o p r i a t e i n p u t / o u t p u t o r g a n i z a t i o n . Curr e n t l y , it is p r e d o m i n a n t l y u s e d at the l o w p e r f o r m a n c e e n d [3], w h e r e the central p r o c e s s i n g p o w e r p r o v e s i n a d e q u a t e to h a n d l e i n p u t / o u t p u t . C o n s e q u e n t l y , o n l y three i n p u t / o u t p u t g a n i z a t i o n s n e e d to be e v a l u a t e d .
5
or-
S i n c e the e a r l y days of d a t a p r o c e s s i n g , c o m p u t e r s h a v e b e e n in e x i s t e n c e w h i c h h a n d l e i n p u t / o u t p u t o p e r a t i o n s like "normal" c o m p u t a t i o n a l i n s t r u c t i o n s . This case c o r r e s p o n d s to Fig. 2 (b) . R e a d or W r i t e c o m m a n d s , m e a n t to a c c o m p l i s h d a t a t r a n s f e r s b e t w e e n p e r i p h e r a l d e v i c e s and m a i n m e m o r y are b e i n g i n s e r t e d into the n o r m a l i n s t r u c t i o n s t r e a m of the c e n t r a l p r o c e s s i n g unit. This m o d e of o p e r a t i o n is still v e r y p o p u l a r w i t h c u r r e n t m i c r o processor designs.
2.2 Simultaneous Input~Output I n p u t / o u t p u t o p e r a t i o n s m a y also be exec u t e d in p a r a l l e l to CPU a c t i o n s , if an i n p u t / o u t p u t c o n t r o l l e r is b e i n g p r o v i d e d (see Fig. 2 (c)) . In such a system, i n p u t / o u t p u t o p e r a t i o n s are o n l y i n i t i a t e d by the c e n t r a l p r o c e s sing unit, c e r t a i n c o n t r o l a c t i o n s o c c u r in p a r a l l e l and all d a t a t r a n s f e r s are e x e c u t e d s i m u l t a n e o u s l y to i n t e r n a l p r o c e s s i n g . O n l y the t e r m i n a t i o n of the inp u t / o u t p u t a c t i v i t y or a b n o r m a l situation~ require once again central processing unit attention. This type of o p e r a t i o n w a s c o n c e i v e d the 1950's. O n e of the m o s t a d v a n c e d l i t t l e k n o w n c o m p u t e r f e a t u r i n g such i n p u t / o u t p u t s y s t e m w a s the Siemens [9].
in but an
3003
2.3 Independent Input~Output The d e s i r e to m a k e l e t t e r use of the m u l t i t u d e of p e r i p h e r a l d e v i c e s and in o r d e r to e m p l o y p r o c e s s i n g p o w e r m o r e e f f e c t i v e ly, e v e n m o r e i n d e p e n d e n c e b e t w e e n i n t e r nal and e x t e r n a l p r o c e s s e s w a s a c h i e v e d in the t h i r d c o m p u t e r g e n e r a t i o n . S u c h d e v e l o p m e n t s , h o w e v e r , r e q u i r e d basic c h a n g e s in the a c c u s t o m e d c o m p u t e r architecture. Third generation systems f e a t u r e channel p r o g r a m s [2] - [5] to execute input/output tasks within rather autonomous i n p u t / o u t p u t channels [4], [5] or e v e n processors [3]. The c e n t r a l proc e s s o r o n l y i n i t i a t e s such p r o g r a m s and r e c e i v e s status i n f o r m a t i o n b e f o r e an int e r r u p t s i g n a l s the t e r m i n a t i o n of the d e s i r e d task. F i g u r e s 2 (c) and 2 (d) show the u n d e r l y i n g o r g a n i z a t i o n a l concept. I n p u t / o u t p u t p r o c e s s i n g by c h a n n e l s or i n p u t / o u t p u t p r o c e s s o r s , w h e r e m o s t of the c o m m a n d s are e x e c u t e d w i t h i n the per i p h e r a l c o n t r o l l e r , m a y e v e n be v i e w e d as c o n s t i t u t i n g o n l y an i n t e r m e d i a t e step t o w a r d s i n p u t / o u t p u t subsystems
6
HELMUT BERNDT
CPU
CPU
11
1
TIME
Fig.
=~
IOC
IOC
PC
-!
3: Input/output control principles: (a) control by the central processing unit (CPU), (b) simultaneous operation to CPU actions, (c) independent operation from CPU actions. Besides CPU, IOC designates the input/output controller or channel, and PC stands for peripheral controller.
where the entire channel program is being executed in the controller. However, this seemingly superfluous advance proved quite useful. It p r o v i d e d the functional basic for the implementation of a standardized interface between the controllers of all peripherals and the central system. Thus, all types of input/output units may be connected in an identical fashion to the central system via their controllers. 3. INPUT/OUTPUT
REALIZATION
The or g a n i z a t i o n a l forms of input/output handling are oonceptual in nature and constitute only architectural parameters during the implementation phase. Microp r o g r a m m i n g plays an important role in the necessary transformation to arrive at real systems. Its varying use in the input/output area determines the actual realization principles. These may be cathegorized as o o o
CPU
resource sharing, integrated channels, and independent processors.
Figure 3 attempts an illustration of the three organizations showing actions to be p e r f o r m e d as a function of time. Black
indicates the running task demanding an input or output action which is shaded. White indicates that the central processing unit (CPU) or the input/output controller (IOC) or the peripheral controller (PC) are available to handle other tasks. The three organizational forms, Figs. 3 (a), 3 (b), and 3 (c), may be mapped directly into equivalent realization schemes, where - as a function of time all three input/output principles could be executed on either one of the three input/output system realizations. This fact means, e.g., that an input/output system realized according to Fig. 3 (a) may emulate all three input/output control principles shown in Figs. 3 (a), 3 (b), and 3 (c). Regarding single tasks, the same applies for all other alternatives. Thus, resource sharing in an input/output system realization, e.g., is equivalent to the concept of input/output control by the central processing unit, but may still accommodate the other control principles. The same applies for the other schemes. Having established the organizational forms of input/output control and their
INPUT/OUTPUT MICROPROGRAMMING: AN OVERVIEW possible realization principles, the mic r o p r o g r a m m i n g a s p e c t s of t h e d i f f e r e n t s c h e m e s w i l l be c o n s i d e r e d .
3.1 R e s o u r c e
Sharing
Under the label resource sharing we may u n d e r s t a n d a m i c r o p r o g r a m c o n t r o l l e d system, w h e r e the c e n t r a l p r o c e s s o r h a n d l e s n o t o n l y the u s u a l i n p u t / o u t p u t task init i a t i o n , but a s s u m e s d i r e c t p e r i p h e r a l c o n t r o l d o w n to the d a t a t r a n s f e r l e v e l [i]. U s u a l l y d e v i c e a d a p t e r s aid the central s y s t e m in the i n t e r f a c i n g e f f o r t [2]. O t h e r w i s e , all c o n t r o l a s w e l l as p r o c e s s i n g a c t i o n s are c o o r d i n a t e d by an i n t e grated microprogram package. A "micro"e x e c u t i v e or at l e a s t m o n i t o r - h a n d l e s the i n t e r n a l and e x t e r n a l p r o c e s s i n g n e e d s on a t i m e - s h a r i n g basis.
t r a n s f e r s m a y or m a y n o t be h a n d l e d by m i c r o i n s t r u c t i o n s d e p e n d i n g on the i n t e r nal to e x t e r n a l s p e e d r a t i o d e s i r e d . In fast i n p u t / o u t p u t c h a n n e l s ; they m a y req u i r e h a r d w a r e c o n t r o l but w i t h i n a low s p e e d c h a n n e l on the same s y s t e m m i c r o p r o g r a m c o n t r o l m a y be s u f f i c i e n t . I n t e g r a t e d i n p u t / o u t p u t c o n t r o l is poss i b l e w i t h all t h r e e c o n t r o l p r i n c i p l e s . It is w e l l a d a p t e d to cope w i t h the m o r e independent control schemes where microp r o g r a m m i n g m a y also be u s e d e f f i c i e n t l y provided that a microprogram interrupt f a c i l i t y or s t a c k is i m p l e m e n t e d . As an e x a m p l e for this t e c h n i q u e , m o d e l 7.755 of S i e m e n s S y s t e m 7 . 0 0 0 is b e i n g d i s c u s s e d in [5].
3.3 I n d e p e n d e n t M i c r o p r o g r a m c o n t r o l e n a b l e s s u c h a sys t e m to a c c o m m o d a t e all t h r e e i n p u t / o u t p u t c o n t r o l p r i n c i p l e s in an e c o n o m i c fashion. T e c h n i c a l l i m i t a t i o n s e x i s t o n l y in r e g a r d to s e r v i c i n g "fast" p e r i p h e r a l s . F o r the t i m e being, u n i t s w i t h d a t a t r a n s f e r r a t e s of 1 M B / s and a b o v e p o s e a p r o b l e m b e c a u s e of m i c r o i n s t r u c t i o n e x e c u t i o n times. F a s t e n o u g h c o n t r o l m e m o ries p r o v e t o o c o s t l y . Hence, r e s o u r c e s h a r i n g is c u r r e n t l y l i m i t e d to the l o w e r e n d of f u l l s c a l e d a t a p r o c e s s i n g s y s t e m s . The Unidata 7.720 p r o v i d e s a g o o d e x a m p l e [2] for a r e a l i z a t i o n of this t e c h n i q u e . It f e a t u r e s d e v i c e a d a p t e r s , in p a r t i c u lar for f a s t e r p e r i p h e r a l s , and is cont r o l l e d by a m i c r o p r o g r a m p a c k a g e h a n d l i n g i n p u t / o u t p u t as w e l l as i n t e r n a l p r o c e s s i n g t a s k s in a t i m e - s h a r i n g fashion.
3.2 I n t e g r a t e d
Channels
M o s t c o m m o n in m e d i u m - t o - l a r g e s c a l e d a t a p r o c e s s i n g s y s t e m s is the p r i n c i p l e of i n t e g r a t e d i n p u t / o u t p u t c h a n n e l s [4]~ C e n t r a l p r o c e s s o r s in this p e r f o r m a n c e r e g i o n are u s u a l l y "fast" e n o u g h to outp e r f o r m the i n p u t / o u t p u t system. Hence, it is d e s i r a b l e to m a k e e c o n o m i c use of the i n t e r n a l p r o c e s s i n g p o w e r s in o r d e r to s p e e d - u p i n p u t / o u t p u t h a n d l i n g [5], [lO]. And certain input/output control tasks are a c t u a l l y h a n d l e d w i t h i n the c e n t r a l p r o c e s s o r e v e n if they are l o g i c a l l y ind e p e n d e n t . T h e r e f o r e , t h e s e a c t i o n s are p e r f o r m e d t o t a l l y u n d e r m i c r o p r o g r a m control in a m i c r o p r o g r a m m e d system. H a r d w a r e c o n t r o l m a y e v e n be l i m i t e d to int e r f a c i n g t h e p e r i p h e r a l . As a r u l e it p r o v e s a d v a n t a g e o u s to p e r f o r m r e a l - t i m e t a s k s r e q u i r i n g fast a t t e n t i o n u n d e r h a r d w a r e c o n t r o l d e l e g a t i n g the low s p e e d a c t i o n s to a m i c r o p r o g r a m . But e v e n d a t a
7
Processors
In m o r e r e c e n t y e a r s i n d e p e n d e n t i n p u t / o u t p u t p r o c e s s o r s h a v e b e c o m e m o r e common. F i r s t of all, t h e y are w e l l s u i t e d to s y s t e m a r c h i t e c t u r e s w i t h a p r o n o u n c e d d e c o u p l i n g of i n p u t / o u t p u t h a n d l i n g from i n t e r n a l p r o c e s s i n g such that, e.g., channel p r o g r a m s m a y be e x e c u t e d e n t i r e l y in s u c h p r o c e s s o r s . F u r t h e r m o r e , the d e c l i n e in h a r d w a r e cost m a d e such u n i t s f e a s i b l e and m i c r o p r o g r a m c o n t r o l a d d e d the r e q u i r e d f l e x i b i l i t y to u s e the same p r o c e s s o r for d i f f e r e n t i n p u t / o u t p u t tasks. We find the i n p u t / o u t p u t p r o c e s s o r of this t y p e in a v a r i e t y of uses. It m a y be d e d i c a t e d by a p p r o p r i a t e m i c r o p r o g r a m s to c o n t r o l o n l y a c e r t a i n t y p e of p e r i p h e r a l like in IBM S y s t e m ~ 3 7 0 Model 115 and Model 125 [3]. Or it m a y be u s e d p r i m a r i l y for t h r o u g h p u t r e a s o n s at the l o w e r end of a p r o d u c t line, w h e r e the i n t e r n a l p r o c e s sing p o w e r p r o v e s i n s u f f i c i e n t to g u a r a n tee the h i g h d a t a r a t e s r e q u i r e d by m o dern peripherals. 4. C O N C L U S I O N S This b r i e f s u r v e y o f the r e l e v a n t f o r m s of i n p u t / o u t p u t o r g a n i z a t i o n and p o s s i b l e r e a l i z a t i o n s is m e a n t to p r o v i d e the nec e s s a r y b a c k g r o u n d i n f o r m a t i o n in o r d e r to f u l l y a p p r e c i a t e the o t h e r c o n t r i b u t i o n s in this special issue of the EUROM I C R O N e w s l e t t e r . N e c e s s a r i l y , the emp h a s i s had to be m o r e on the u n d e r l y i n g p r i n c i p l e s w h i c h are o n l y r e f l e c t e d in a c t u a l i n p u t / o u t p u t m i c r o p r o g r a m m i n g . But it is h o p e d that this i n t r o d u c t i o n m a y also c o n t r i b u t e t o w a r d s m o r e a w a r e n e s s of i n p u t / o u t p u t . It is there.
8
HELr.TUT BERNDT
REFERENCES Ill
[2]
[3]
A. Recoque, "Mitra 15 - An example of handling peripheral units by specific microprogramming," EUROMICRO Newsletter, 2 (1976) no. 3, pp. 9-14. Ph. Nyssens, "Input/output microprogram handling within the Unidata 7.720," EUROMICRO Newsletter, 2 (1976) no. 3, pp. 15-23. R. Assmuth, F. Irro, L. Reichl, and H. Schaal, "Input/output control of IBM System /370 Model 125 through dedicated input/output processors," EUROMICRO Newsletter, 2 (1976) no. 3, pp. 24-40.
[4]
H. Spreen, "Partially integrated input/output channels," EUROMICRO Newsletter, 2 (1976) no. 3, pp. 41-46.
[5]
H. Sebbel, "Input/output microprogramming for the 7.755 central pro-
cessing unit of Siemens System 7.000," EUROMICRO Newsletter, 2 (1976) no. 3, pp. 47-53. [6]
H. Berndt, "Microprogram Controlled Input/Output," in: Microarchitecture of Computer Systems, R.W. Hartenstein and R. Zaks, Eds. Amsterdam: North-Holland, 1975, pp. 177-180.
[7]
C.G. Bell and A. Newell, Computer Structures: Reading and Examples. New York: Mc Graw-Hill, 1971.
[8]
H. Hellerman, Digital Computer System Principles. New York: McGraw-Hill, 1968.
[9]
K. Leipold and W. Rekowski, "A method for the simultaneous processing of several programs," Information Processing, Proc. IFIP Congress 65, Washington, DC: Spartan Books, 1965, vol. 2, pp. 320-321.
[iO] S. S. Husson, Microprogramming - Principles and Practices. Englewood Cliffs NJ: Prentice-Hall, 1970.
INPUT/OUTPUT
MICROPROGRAMMING:
Helmut
Berndt
Guest
Editor
Abstract An i n t r o d u c t i o n to t h e d e v e l o p m e n t of inp u t / o u t p u t h a n d l i n g in d a t a p r o c e s s i n g s y s t e m s is b e i n g p r o v i d e d . The d i f f e r e n t o r g a n i z a t i o n a l forms are d i s c u s s e d in rel a t i o n to m i c r o p r o g r a m c o n t r o l l e d i m p l e mentations. f h e r e e x i s t s e v e r a l - m i c r o p r o g r a m supp o r t e d - c o n t r o l s t r a t e g i e s today. P e r t i n e n t e x a m p l e s of such r e a l i z a t i o n s are b e i n g r e p o r t e d in this special issue of the EUROMICRO Newsletter. T h i s s u r v e y is m e a n t to p r o v i d e t h e n e c e s s a r y b a c k g r o u n d and p e r s p e c t i v e . 1. I N T R O D U C T I O N E f f i c i e n t input as w e l l as o u t p u t h a n d l i n g s t i l l c o n s t i t u t e s one of the m o s t p r e s s i n g p r o b l e m s e n c o u n t e r e d in contemporary data processing system design and d e v e l o p m e n t . T h e e m p h a s i s , h o w e v e r , has s h i f t e d c o n s i d e r a b l y f r o m the o n c e p r e v a i l i n g c o m p l a i n t a b o u t slow p e r i p h e rals to the c o n c e r n of h o w to a c c o m m o d a t e the just e m e r g i n g g e n e r a t i o n of high-speed d e v i c e s , like d i s k d r i v e s , tape s t a t i o n s , and n o n i m p a c t p r i n t e r s . In a d d i t i o n , the i n c r e a s e d use of d a t a c o m m u n i c a t i o n - f a c i l i t i e s p o s e s even n e w p r o b l e m s w i t h r e g a r d to r e a l - t i m e beh a v i o r and the d i s t r i b u t i o n of i n t e l l i gence.
The g e n e r a l n e g l e c t of i n p u t and o u t p u t h a n d l i n g - to be o b s e r v e d in p r a c t i c a l l y all a c c e s s i b l e p u b l i c a t i o n s - m u s t h a v e c o n t r i b u t e d to that r a t h e r u n f o r t u n a t e s i t u a t i o n . This first " s p e c i a l " of the EUROMICRO Newsletter t h r i v e s to p r o v i d e at l e a s t - some r e m e d y . R e p r e s e n t a t i v e e x a m p l e s of m o r e recent, E u r o p e a n c o n t r i b u t i o n s to input/output microprogramming, control, and r e l a t e d system organization are p u b l i s h e d in this i s s u e [i] - [5]. The list of p o t e n t i a l c o n t r i b u t o r s is n e c e s s a r i l y i n c o m p l e t e . Y e t all i m p o r t a n t i n p u t / o u t p u t o r g a n i z a t i o n s are b e i n g covered. -
This i n t r o d u c t o r y s u r v e y s h o u l d p r o v i d e the n e c e s s a r y background i n f o r m a t i o n in o r d e r to a l l o w p r o p e r a s s e s s m e n t s of the contributed papers. 2.
INPUT/OUTPUT
ORGANIZATION
The t r a n s f e r of d a t a (as w e l l as p r o grams) b e t w e e n p e r i p h e r a l devices and a c e n t r a l o r main memory c o n s t i t u t e s o n e of the m a j o r a c t i v i t i e s e n c o u n t e r e d in
IMAINMEMORYI
F o r t u n a t e l y , t h o s e g r o w i n g n e e d s are being m e t by p r o f o u n d a d v a n c e s in p r o c e s s o r o r g a n i z a t i o n and t e c h n o l o g y . The u s e of m i c r o p r o g r a m m i n g has f o u n d its w a y into the i n p u t / o u t p u t a r e a a i d e d by the a v a i l a b i l i t y of s u f f i c i e n t l y "fast" c o n t r o l stores. But p r o p e r r e c o g n i t i o n of the n e c e s s i t y for an i t e r a t i v e d e s i g n p r o cess - i n c l u d i n g s t e p w i s e r e f i n e m e n t c o n t r i b u t e d just as h e a v i l y t o w a r d s the s u c c e s s f u l d e p l o y m e n t of t h i s c o n t r o l t e c h n i q u e . Today, input~output microprogrammzng o f f e r s a g r e a t p o t e n t i a l in m e e t i n g the d e m a n d s of the future.
0101i01 Fig.
But d e s p i t e of such p e r s p e c t i v e s , v i r t u a l l y n o t h i n g m a y b e f o u n d in the app r o p r i a t e l i t e r a t u r e to s u p p o r t this view.
AN OVERVIEW
l: G e n e r a l v i e w of i n p u t / o u t p u t as d a t a e x c h a n g e b e t w e e n p e r i p h e r a l d e v i c e s (D) and m a i n memory
4
HELMUT BERNDT
'aJ
MAINMEMORY I I
(b]
I MAINMEMORYI
\
CPU
° (C)
I
I ol
lololol (d)
MAINMEMORY
I MAINMEMORYI
/
\
CPU IOC
Fig.
2: I n p u t / o u t p u t as d a t a e x c h a n g e b e t w e e n m a i n m e m o r y and p e r i p h e r a l d e v i c e s (D) v i a a c e n t r a l p r o c e s s i n g u n i t (CPU) a n d / o r an i n p u t / o u t p u t c o n t r o l l e r (IOC). The d i f f e r e n t forms of o r g a n i z a t i o n are being shown
any d a t a p r o c e s s i n g s y s t e m [6]. We comm o n l y r e f e r to it as input o r output (in s h o r t input~output). F i g u r e 1 p r o v i d e s a r a t h e r g e n e r a l v i e w of this a c t i v i t y . Data are b e i n g e x c h a n g e d b e t w e e n i n d i v i d u a l d e v i c e s (D), or d e v i c e c l u s t e r s (several D's), and m a i n m e m o r y , A n y i n p u t / o u t p u t o p e r a t i o n to be e x e c u t e d in such an e n v i r o n m e n t has to f u l l f i l all of the f o l l o w i n g o b j e c t i v e s :
o
device addressing which
amounts
to the s e l e c t i o n
of the
requested o
input/output
device;
device status handling w h i c h a m o u n t s to an i n t e r r o g a t i o n the a p p r o p r i a t e d e v i c e status;
o
command transmission w h i c h a m o u n t s to the d e t e r m i n a t i o n the d e s i r e d o p e r a t i o n ;
o
of
medium addressin E w h i c h a m o u n t s to the d e f i n i t i o n of the r e q u e s t e d i n p u t / o u t p u t a r e a on the d a t a carrier;
of
INPUT/OUTPUT MICROPROGRAMMING: AN OVERVIEW o
o o
2.1 Central Processor Control
memory addressing which amounts the r e q u e s t e d main memory;
to t h e d e f i n i t i o n of i n p u t / o u t p u t a r e a in
data transfers; termination w h i c h a m o u n t s to s i g n a l i n g a T e r m i n a t i o n I n t e r r u p t (or the like) to the c e n t r a l p r o c e s s i n g unit.
This s e q u e n t i a l l i s t i n g of p e r t i n e n t control a c t i v i t i e s e x c l u d e s all t i m i n g cons t r a i n t s , as d i c t a t e d b y c e r t a i n r e a l i z a t i o n s of p a r t i c u l a r i n p u t / o u t p u t interfaces. A l l of the l i s t e d f u n c t i o n s have to be p e r f o r m e d for any i n p u t / o u t p u t oper a t i o n [6].
F i g u r e 2 d e m o n s t r a t e s four c o n c e p t i o n a l p o s s i b i l i t i e s for m e e t i n g t h e s e o b j e c tives. T h e y r e l y u p o n d i f f e r i n g forms of input/output organizations.
The f i r s t case, d e p i c t e d in F i g 2 (a) , a u g m e n t s the g e n e r a l c o n c e p t of i n p u t / o u t p u t h a n d l i n g (see Fig. i) by the nec e s s a r y p r o c e s s i n g p o w e r in o r d e r to ass e m b l e a d a t a p r o c e s s i n g system. But in reality, actual development commenced a r o u n d the c e n t r a l p r o c e s s i n g unit (CPU). It h a n d l e d all i n p u t / o u t p u t n e e d s in m o s t e a r l i e r d a t a p r o c e s s i n g s y s t e m s as w e l l as in c u r r e n t micro c o m p u t e r s . T h i s case is s h o w n as Fig. 2 (b). S i m i l a r i l y , further e n h a n c e m e n t s of the i n p u t / o u t p u t org a n i z a t i o n o c c u r r e d in r e l a t i o n to the CPU. T h e channel c o n c e p t e v o l v e d f r o m the IBM 709-7090-7094 c o m p u t e r " f a m i l y " [7]. F i g u r e 2 (c) d e m o n s t r a t e s this s i t u a t i o n . A n i n p u t / o u t p u t c o n t r o l l e r (IOC) r e a l i z e s the c h a n n e l f u n c t i o n s [8]. T h i s f o r m for an i n p u t / o u t p u t o r g a n i z a t i o n of general purpose c o m p u t e r s y s t e m s d e v e l o p e d into an i n d u s t r y s t a n d a r d for third g e n e r a t i o n e q u i p m e n t . But the e v e r i n c r e a s i n g d a t a t r a n s f e r r a t e s of m o d e r n p e r i p h e r a l s dem a n d m u c h h i g h e r s e r v i c i n g rates. I n p u t / o u t p u t c o n t r o l l e r s or e v e n processors h a n d l i n g the r e q u i r e d d a t a t r a n s f e r s w i t h o u t any i n t e r v e n t i o n of t h e c e n t r a l p r o c e s s i n g unit, m a y m e e t this i n c r e a s e d r e q u i r e m e n t s . F i g u r e 2 (d) s h o w s t h e app r o p r i a t e i n p u t / o u t p u t o r g a n i z a t i o n . Curr e n t l y , it is p r e d o m i n a n t l y u s e d at the l o w p e r f o r m a n c e e n d [3], w h e r e the central p r o c e s s i n g p o w e r p r o v e s i n a d e q u a t e to h a n d l e i n p u t / o u t p u t . C o n s e q u e n t l y , o n l y three i n p u t / o u t p u t g a n i z a t i o n s n e e d to be e v a l u a t e d .
5
or-
S i n c e the e a r l y days of d a t a p r o c e s s i n g , c o m p u t e r s h a v e b e e n in e x i s t e n c e w h i c h h a n d l e i n p u t / o u t p u t o p e r a t i o n s like "normal" c o m p u t a t i o n a l i n s t r u c t i o n s . This case c o r r e s p o n d s to Fig. 2 (b) . R e a d or W r i t e c o m m a n d s , m e a n t to a c c o m p l i s h d a t a t r a n s f e r s b e t w e e n p e r i p h e r a l d e v i c e s and m a i n m e m o r y are b e i n g i n s e r t e d into the n o r m a l i n s t r u c t i o n s t r e a m of the c e n t r a l p r o c e s s i n g unit. This m o d e of o p e r a t i o n is still v e r y p o p u l a r w i t h c u r r e n t m i c r o processor designs.
2.2 Simultaneous Input~Output I n p u t / o u t p u t o p e r a t i o n s m a y also be exec u t e d in p a r a l l e l to CPU a c t i o n s , if an i n p u t / o u t p u t c o n t r o l l e r is b e i n g p r o v i d e d (see Fig. 2 (c)) . In such a system, i n p u t / o u t p u t o p e r a t i o n s are o n l y i n i t i a t e d by the c e n t r a l p r o c e s sing unit, c e r t a i n c o n t r o l a c t i o n s o c c u r in p a r a l l e l and all d a t a t r a n s f e r s are e x e c u t e d s i m u l t a n e o u s l y to i n t e r n a l p r o c e s s i n g . O n l y the t e r m i n a t i o n of the inp u t / o u t p u t a c t i v i t y or a b n o r m a l situation~ require once again central processing unit attention. This type of o p e r a t i o n w a s c o n c e i v e d the 1950's. O n e of the m o s t a d v a n c e d l i t t l e k n o w n c o m p u t e r f e a t u r i n g such i n p u t / o u t p u t s y s t e m w a s the Siemens [9].
in but an
3003
2.3 Independent Input~Output The d e s i r e to m a k e l e t t e r use of the m u l t i t u d e of p e r i p h e r a l d e v i c e s and in o r d e r to e m p l o y p r o c e s s i n g p o w e r m o r e e f f e c t i v e ly, e v e n m o r e i n d e p e n d e n c e b e t w e e n i n t e r nal and e x t e r n a l p r o c e s s e s w a s a c h i e v e d in the t h i r d c o m p u t e r g e n e r a t i o n . S u c h d e v e l o p m e n t s , h o w e v e r , r e q u i r e d basic c h a n g e s in the a c c u s t o m e d c o m p u t e r architecture. Third generation systems f e a t u r e channel p r o g r a m s [2] - [5] to execute input/output tasks within rather autonomous i n p u t / o u t p u t channels [4], [5] or e v e n processors [3]. The c e n t r a l proc e s s o r o n l y i n i t i a t e s such p r o g r a m s and r e c e i v e s status i n f o r m a t i o n b e f o r e an int e r r u p t s i g n a l s the t e r m i n a t i o n of the d e s i r e d task. F i g u r e s 2 (c) and 2 (d) show the u n d e r l y i n g o r g a n i z a t i o n a l concept. I n p u t / o u t p u t p r o c e s s i n g by c h a n n e l s or i n p u t / o u t p u t p r o c e s s o r s , w h e r e m o s t of the c o m m a n d s are e x e c u t e d w i t h i n the per i p h e r a l c o n t r o l l e r , m a y e v e n be v i e w e d as c o n s t i t u t i n g o n l y an i n t e r m e d i a t e step t o w a r d s i n p u t / o u t p u t subsystems
6
HELMUT BERNDT
CPU
CPU
11
1
TIME
Fig.
=~
IOC
IOC
PC
-!
3: Input/output control principles: (a) control by the central processing unit (CPU), (b) simultaneous operation to CPU actions, (c) independent operation from CPU actions. Besides CPU, IOC designates the input/output controller or channel, and PC stands for peripheral controller.
where the entire channel program is being executed in the controller. However, this seemingly superfluous advance proved quite useful. It p r o v i d e d the functional basic for the implementation of a standardized interface between the controllers of all peripherals and the central system. Thus, all types of input/output units may be connected in an identical fashion to the central system via their controllers. 3. INPUT/OUTPUT
REALIZATION
The or g a n i z a t i o n a l forms of input/output handling are oonceptual in nature and constitute only architectural parameters during the implementation phase. Microp r o g r a m m i n g plays an important role in the necessary transformation to arrive at real systems. Its varying use in the input/output area determines the actual realization principles. These may be cathegorized as o o o
CPU
resource sharing, integrated channels, and independent processors.
Figure 3 attempts an illustration of the three organizations showing actions to be p e r f o r m e d as a function of time. Black
indicates the running task demanding an input or output action which is shaded. White indicates that the central processing unit (CPU) or the input/output controller (IOC) or the peripheral controller (PC) are available to handle other tasks. The three organizational forms, Figs. 3 (a), 3 (b), and 3 (c), may be mapped directly into equivalent realization schemes, where - as a function of time all three input/output principles could be executed on either one of the three input/output system realizations. This fact means, e.g., that an input/output system realized according to Fig. 3 (a) may emulate all three input/output control principles shown in Figs. 3 (a), 3 (b), and 3 (c). Regarding single tasks, the same applies for all other alternatives. Thus, resource sharing in an input/output system realization, e.g., is equivalent to the concept of input/output control by the central processing unit, but may still accommodate the other control principles. The same applies for the other schemes. Having established the organizational forms of input/output control and their
INPUT/OUTPUT MICROPROGRAMMING: AN OVERVIEW possible realization principles, the mic r o p r o g r a m m i n g a s p e c t s of t h e d i f f e r e n t s c h e m e s w i l l be c o n s i d e r e d .
3.1 R e s o u r c e
Sharing
Under the label resource sharing we may u n d e r s t a n d a m i c r o p r o g r a m c o n t r o l l e d system, w h e r e the c e n t r a l p r o c e s s o r h a n d l e s n o t o n l y the u s u a l i n p u t / o u t p u t task init i a t i o n , but a s s u m e s d i r e c t p e r i p h e r a l c o n t r o l d o w n to the d a t a t r a n s f e r l e v e l [i]. U s u a l l y d e v i c e a d a p t e r s aid the central s y s t e m in the i n t e r f a c i n g e f f o r t [2]. O t h e r w i s e , all c o n t r o l a s w e l l as p r o c e s s i n g a c t i o n s are c o o r d i n a t e d by an i n t e grated microprogram package. A "micro"e x e c u t i v e or at l e a s t m o n i t o r - h a n d l e s the i n t e r n a l and e x t e r n a l p r o c e s s i n g n e e d s on a t i m e - s h a r i n g basis.
t r a n s f e r s m a y or m a y n o t be h a n d l e d by m i c r o i n s t r u c t i o n s d e p e n d i n g on the i n t e r nal to e x t e r n a l s p e e d r a t i o d e s i r e d . In fast i n p u t / o u t p u t c h a n n e l s ; they m a y req u i r e h a r d w a r e c o n t r o l but w i t h i n a low s p e e d c h a n n e l on the same s y s t e m m i c r o p r o g r a m c o n t r o l m a y be s u f f i c i e n t . I n t e g r a t e d i n p u t / o u t p u t c o n t r o l is poss i b l e w i t h all t h r e e c o n t r o l p r i n c i p l e s . It is w e l l a d a p t e d to cope w i t h the m o r e independent control schemes where microp r o g r a m m i n g m a y also be u s e d e f f i c i e n t l y provided that a microprogram interrupt f a c i l i t y or s t a c k is i m p l e m e n t e d . As an e x a m p l e for this t e c h n i q u e , m o d e l 7.755 of S i e m e n s S y s t e m 7 . 0 0 0 is b e i n g d i s c u s s e d in [5].
3.3 I n d e p e n d e n t M i c r o p r o g r a m c o n t r o l e n a b l e s s u c h a sys t e m to a c c o m m o d a t e all t h r e e i n p u t / o u t p u t c o n t r o l p r i n c i p l e s in an e c o n o m i c fashion. T e c h n i c a l l i m i t a t i o n s e x i s t o n l y in r e g a r d to s e r v i c i n g "fast" p e r i p h e r a l s . F o r the t i m e being, u n i t s w i t h d a t a t r a n s f e r r a t e s of 1 M B / s and a b o v e p o s e a p r o b l e m b e c a u s e of m i c r o i n s t r u c t i o n e x e c u t i o n times. F a s t e n o u g h c o n t r o l m e m o ries p r o v e t o o c o s t l y . Hence, r e s o u r c e s h a r i n g is c u r r e n t l y l i m i t e d to the l o w e r e n d of f u l l s c a l e d a t a p r o c e s s i n g s y s t e m s . The Unidata 7.720 p r o v i d e s a g o o d e x a m p l e [2] for a r e a l i z a t i o n of this t e c h n i q u e . It f e a t u r e s d e v i c e a d a p t e r s , in p a r t i c u lar for f a s t e r p e r i p h e r a l s , and is cont r o l l e d by a m i c r o p r o g r a m p a c k a g e h a n d l i n g i n p u t / o u t p u t as w e l l as i n t e r n a l p r o c e s s i n g t a s k s in a t i m e - s h a r i n g fashion.
3.2 I n t e g r a t e d
Channels
M o s t c o m m o n in m e d i u m - t o - l a r g e s c a l e d a t a p r o c e s s i n g s y s t e m s is the p r i n c i p l e of i n t e g r a t e d i n p u t / o u t p u t c h a n n e l s [4]~ C e n t r a l p r o c e s s o r s in this p e r f o r m a n c e r e g i o n are u s u a l l y "fast" e n o u g h to outp e r f o r m the i n p u t / o u t p u t system. Hence, it is d e s i r a b l e to m a k e e c o n o m i c use of the i n t e r n a l p r o c e s s i n g p o w e r s in o r d e r to s p e e d - u p i n p u t / o u t p u t h a n d l i n g [5], [lO]. And certain input/output control tasks are a c t u a l l y h a n d l e d w i t h i n the c e n t r a l p r o c e s s o r e v e n if they are l o g i c a l l y ind e p e n d e n t . T h e r e f o r e , t h e s e a c t i o n s are p e r f o r m e d t o t a l l y u n d e r m i c r o p r o g r a m control in a m i c r o p r o g r a m m e d system. H a r d w a r e c o n t r o l m a y e v e n be l i m i t e d to int e r f a c i n g t h e p e r i p h e r a l . As a r u l e it p r o v e s a d v a n t a g e o u s to p e r f o r m r e a l - t i m e t a s k s r e q u i r i n g fast a t t e n t i o n u n d e r h a r d w a r e c o n t r o l d e l e g a t i n g the low s p e e d a c t i o n s to a m i c r o p r o g r a m . But e v e n d a t a
7
Processors
In m o r e r e c e n t y e a r s i n d e p e n d e n t i n p u t / o u t p u t p r o c e s s o r s h a v e b e c o m e m o r e common. F i r s t of all, t h e y are w e l l s u i t e d to s y s t e m a r c h i t e c t u r e s w i t h a p r o n o u n c e d d e c o u p l i n g of i n p u t / o u t p u t h a n d l i n g from i n t e r n a l p r o c e s s i n g such that, e.g., channel p r o g r a m s m a y be e x e c u t e d e n t i r e l y in s u c h p r o c e s s o r s . F u r t h e r m o r e , the d e c l i n e in h a r d w a r e cost m a d e such u n i t s f e a s i b l e and m i c r o p r o g r a m c o n t r o l a d d e d the r e q u i r e d f l e x i b i l i t y to u s e the same p r o c e s s o r for d i f f e r e n t i n p u t / o u t p u t tasks. We find the i n p u t / o u t p u t p r o c e s s o r of this t y p e in a v a r i e t y of uses. It m a y be d e d i c a t e d by a p p r o p r i a t e m i c r o p r o g r a m s to c o n t r o l o n l y a c e r t a i n t y p e of p e r i p h e r a l like in IBM S y s t e m ~ 3 7 0 Model 115 and Model 125 [3]. Or it m a y be u s e d p r i m a r i l y for t h r o u g h p u t r e a s o n s at the l o w e r end of a p r o d u c t line, w h e r e the i n t e r n a l p r o c e s sing p o w e r p r o v e s i n s u f f i c i e n t to g u a r a n tee the h i g h d a t a r a t e s r e q u i r e d by m o dern peripherals. 4. C O N C L U S I O N S This b r i e f s u r v e y o f the r e l e v a n t f o r m s of i n p u t / o u t p u t o r g a n i z a t i o n and p o s s i b l e r e a l i z a t i o n s is m e a n t to p r o v i d e the nec e s s a r y b a c k g r o u n d i n f o r m a t i o n in o r d e r to f u l l y a p p r e c i a t e the o t h e r c o n t r i b u t i o n s in this special issue of the EUROM I C R O N e w s l e t t e r . N e c e s s a r i l y , the emp h a s i s had to be m o r e on the u n d e r l y i n g p r i n c i p l e s w h i c h are o n l y r e f l e c t e d in a c t u a l i n p u t / o u t p u t m i c r o p r o g r a m m i n g . But it is h o p e d that this i n t r o d u c t i o n m a y also c o n t r i b u t e t o w a r d s m o r e a w a r e n e s s of i n p u t / o u t p u t . It is there.
8
HELr.TUT BERNDT
REFERENCES Ill
[2]
[3]
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