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Integrating CAM and process simulation to enhance online analysis and control of IC fabrication
208
World Abstracts on Microelectronics and Reliability
dation of the DSS is another key segment of this paper. The paper also addresses how the DSS is being used to help make design recommendations for large-scale (factory-wide) fab automation projects as well as automation at the area, cell, and equipment levels. Analysis of printed wiring board assembly system. MORRISR. DRIELSand JOHN S. KLEGKA. IEEE Trans. Compon. Hybrids mfg Technol. 13(1), 109 (1990). A model for predicting the cost of manufacturing printed wiring boards is presented. The model represents manufacturing systems currently in use in the industry. The model concentrates on surfacemount technology, using a mixture of automatic, programmable assembly and manual assembly techniques. The model includes elements to account for inventory, assembly, and test and rework costs. The model also considers the effect of introducing a new component type on total manufacturing cost. Results of a simulation using typical data found in-batch manufacturing of printed wiring assemblies are presented. Silicon-on-insulator: materials aspects and technological applications. G. BOMCHIL. Vacuum 41(4) 781 (1990). Materials and techniques to obtain silicon-on-insulator structures are presented including a brief discussion on the physical principles of each technique. The advantages and limitations of the various silicon-on-insulator materials for technological applications in the development of future electron devices and Very Large Scale Integrated circuits are discussed. Thermal stress analysis of tape automated bonding packages and interconnections. JOHN H. LAU, DONALD W. RICE and C. GIRVIN HARKINS. IEEE Trans. Compon. Hybrids mfg Technol, 13(1), 182 (1990). The stresses and strains in tape automated bonding (TAB) assemblies have been studied using a nonlinear three-dimensional finite element method. Emphasis is placed on the thermomechanical behavior of TAB assembly beam leads, polyimide rings, gold bumps, silicon chips, and solder joints. Unlike conventional surface mount technology (SMT) packages, the TAB beam leads are more likely to fail than the solder joints. Furthermore, the analytical results agree with the observed failure mechanisms of the beam leads. The results presented should be useful in understanding and designing more reliable advanced surface-mount assemblies. Direct chip interconnect using polymer bonding. KEN GILLEO. IEEE Trans. Compon. Hybrids mfg Technol. 13(1), 229 (1990). High-density, fine-pitch interconnection is now possible with novel polymer bonding systems. This discussion focuses on new polymer bonding methods for the direct interconnection of integrated circuit (IC) components. Emerging concepts, using polymer materials engineered for direct mechanical and electrical connection of ICs, will be covered. Polymer Thick Film (PTF) technology, the earliest approach to printed circuits, has only recently moved from the simple membrane switch arena to the more complex and demanding realm of circuity. Today, millions of circuits for the commercial electronics market are made with PTF. Once aimed only at cost reduction, PTF technology now offers new alternatives to relieve the high-density interconnect bottleneck. Innovation, combining advanced polymeric materials and techniques with traditional processes, has made PTF a leading edge interconnect technology. We will explore several new polymer bonding methods for directly interconnecting ICs to the circuit. Anisotropic conducive adhesive technology will be the focus, both for tape automated bonding (TAB) and flip-chip bonding strategies. However, we will also examine emerging concepts
using isotropically conductive and nonconductive polymer bonding agents for direct mechanical and electrical connection of bare die to circuit boards. Although some of these technologies remain experimental, anisotropic conductive adhesive bonding of electronic components has reached high volume production status. Etch diagnostics for new III-V and other semiconductors. D. FIELD, Y. P. SONG, D. F. KLEMPERER and A. P. DAY. Vacuum 40(4) 357 (1990). The device industry is entering a period characterized by the introduction of a number of new materials associated with multilayer structures. These structures are themselves being developed for use in sub-micron VLSI. A variety of new compounds and alloys such as Ti/W, nitrides and silicides are being introduced as barrier layers to overcome problems of elcctromigration, hillock formation and interfacial diffusion. The range of III-V compounds involving Ga, As, In, Sb, AI, P, etc. is also being extended and these are the materials of choice in optoelectronic devices (lasers, waveguides, etc.) as well as having important applications in high-speed VLSI technology. Layered structures of new materials are also to be found in quantum well and superlattice systems, in strained-layer growth of unipolar and bipolar heterostructure devices (e.g. Si~Ge alloys) and in superconducting films. These advanced materials bring with them the necessity for developing new etching techniques and processes. Increasingly the emphasis must be upon process control during etching and accurately controllable etch characteristics. This paper will centre on this theme with special reference to end-point detection using both optical emission spectroscopy and massspectrometry. The latter is carried out with a probe technique which we have developed in our laboratories at Bristol. Examples will be taken from silicon based and III V based materials (e.g. InP, GaAs), S i ~ e alloys in layered structures and superconducting films on all of which topics we have work currently in progress. Qualifying of chip bonding operations in the process of fabrication of bipolar transistors by means of noise measurements in the low-frequency range. BOGUSLAWGRZYaOWSKI, ALICJA KONCZAKOWSKAand LUDW1K SPIRALSKI. Electron Technol. 20(3/4), 17 (1987). The paper presents connections between the narrow-band noise factor of bipolar transistors, which is measured in the very low-frequency range, and the quality of operations of assembling those transistors. We have described some advantages of the method of quality estimation which consists of measuring the standard noise parameters of the transitors. Integrating CAM and process simulation to enhance online analysis and control of IC fabrication. ANGUS J. MACDONALD, ANTHONY J. WALTON, J. M. ROBERTSON and ROBERT J. HOLWILL. IEEE Trans. Semicond. Mfg 3(2), 72
(1990). How a process simulator has been integrated with a commercial computer-aided manufacturing (CAM) system to provide a set of powerful tools for process analysis, diagnosis, and control, is described. The CAM system acts as the interface to the simulator and maintains the simulation control data as part of the process specification. Making process simulation available in a manufacturing environment allows engineers to investigate the process intuitively, thus aiding their understanding of the interrelation of process steps; it is believed that this is the first time such a system has been implemented. A misprocessing scenario in an ASIC facility is used to demonstrate how the system can be used to analyse options for corrective processing. Other applications exist in its use for documenting processes, to simplify process transfer and implementation, and investigating the effect of corrective processing on device reliability.
World Abstracts on Microelectronics and Reliability
dation of the DSS is another key segment of this paper. The paper also addresses how the DSS is being used to help make design recommendations for large-scale (factory-wide) fab automation projects as well as automation at the area, cell, and equipment levels. Analysis of printed wiring board assembly system. MORRISR. DRIELSand JOHN S. KLEGKA. IEEE Trans. Compon. Hybrids mfg Technol. 13(1), 109 (1990). A model for predicting the cost of manufacturing printed wiring boards is presented. The model represents manufacturing systems currently in use in the industry. The model concentrates on surfacemount technology, using a mixture of automatic, programmable assembly and manual assembly techniques. The model includes elements to account for inventory, assembly, and test and rework costs. The model also considers the effect of introducing a new component type on total manufacturing cost. Results of a simulation using typical data found in-batch manufacturing of printed wiring assemblies are presented. Silicon-on-insulator: materials aspects and technological applications. G. BOMCHIL. Vacuum 41(4) 781 (1990). Materials and techniques to obtain silicon-on-insulator structures are presented including a brief discussion on the physical principles of each technique. The advantages and limitations of the various silicon-on-insulator materials for technological applications in the development of future electron devices and Very Large Scale Integrated circuits are discussed. Thermal stress analysis of tape automated bonding packages and interconnections. JOHN H. LAU, DONALD W. RICE and C. GIRVIN HARKINS. IEEE Trans. Compon. Hybrids mfg Technol, 13(1), 182 (1990). The stresses and strains in tape automated bonding (TAB) assemblies have been studied using a nonlinear three-dimensional finite element method. Emphasis is placed on the thermomechanical behavior of TAB assembly beam leads, polyimide rings, gold bumps, silicon chips, and solder joints. Unlike conventional surface mount technology (SMT) packages, the TAB beam leads are more likely to fail than the solder joints. Furthermore, the analytical results agree with the observed failure mechanisms of the beam leads. The results presented should be useful in understanding and designing more reliable advanced surface-mount assemblies. Direct chip interconnect using polymer bonding. KEN GILLEO. IEEE Trans. Compon. Hybrids mfg Technol. 13(1), 229 (1990). High-density, fine-pitch interconnection is now possible with novel polymer bonding systems. This discussion focuses on new polymer bonding methods for the direct interconnection of integrated circuit (IC) components. Emerging concepts, using polymer materials engineered for direct mechanical and electrical connection of ICs, will be covered. Polymer Thick Film (PTF) technology, the earliest approach to printed circuits, has only recently moved from the simple membrane switch arena to the more complex and demanding realm of circuity. Today, millions of circuits for the commercial electronics market are made with PTF. Once aimed only at cost reduction, PTF technology now offers new alternatives to relieve the high-density interconnect bottleneck. Innovation, combining advanced polymeric materials and techniques with traditional processes, has made PTF a leading edge interconnect technology. We will explore several new polymer bonding methods for directly interconnecting ICs to the circuit. Anisotropic conducive adhesive technology will be the focus, both for tape automated bonding (TAB) and flip-chip bonding strategies. However, we will also examine emerging concepts
using isotropically conductive and nonconductive polymer bonding agents for direct mechanical and electrical connection of bare die to circuit boards. Although some of these technologies remain experimental, anisotropic conductive adhesive bonding of electronic components has reached high volume production status. Etch diagnostics for new III-V and other semiconductors. D. FIELD, Y. P. SONG, D. F. KLEMPERER and A. P. DAY. Vacuum 40(4) 357 (1990). The device industry is entering a period characterized by the introduction of a number of new materials associated with multilayer structures. These structures are themselves being developed for use in sub-micron VLSI. A variety of new compounds and alloys such as Ti/W, nitrides and silicides are being introduced as barrier layers to overcome problems of elcctromigration, hillock formation and interfacial diffusion. The range of III-V compounds involving Ga, As, In, Sb, AI, P, etc. is also being extended and these are the materials of choice in optoelectronic devices (lasers, waveguides, etc.) as well as having important applications in high-speed VLSI technology. Layered structures of new materials are also to be found in quantum well and superlattice systems, in strained-layer growth of unipolar and bipolar heterostructure devices (e.g. Si~Ge alloys) and in superconducting films. These advanced materials bring with them the necessity for developing new etching techniques and processes. Increasingly the emphasis must be upon process control during etching and accurately controllable etch characteristics. This paper will centre on this theme with special reference to end-point detection using both optical emission spectroscopy and massspectrometry. The latter is carried out with a probe technique which we have developed in our laboratories at Bristol. Examples will be taken from silicon based and III V based materials (e.g. InP, GaAs), S i ~ e alloys in layered structures and superconducting films on all of which topics we have work currently in progress. Qualifying of chip bonding operations in the process of fabrication of bipolar transistors by means of noise measurements in the low-frequency range. BOGUSLAWGRZYaOWSKI, ALICJA KONCZAKOWSKAand LUDW1K SPIRALSKI. Electron Technol. 20(3/4), 17 (1987). The paper presents connections between the narrow-band noise factor of bipolar transistors, which is measured in the very low-frequency range, and the quality of operations of assembling those transistors. We have described some advantages of the method of quality estimation which consists of measuring the standard noise parameters of the transitors. Integrating CAM and process simulation to enhance online analysis and control of IC fabrication. ANGUS J. MACDONALD, ANTHONY J. WALTON, J. M. ROBERTSON and ROBERT J. HOLWILL. IEEE Trans. Semicond. Mfg 3(2), 72
(1990). How a process simulator has been integrated with a commercial computer-aided manufacturing (CAM) system to provide a set of powerful tools for process analysis, diagnosis, and control, is described. The CAM system acts as the interface to the simulator and maintains the simulation control data as part of the process specification. Making process simulation available in a manufacturing environment allows engineers to investigate the process intuitively, thus aiding their understanding of the interrelation of process steps; it is believed that this is the first time such a system has been implemented. A misprocessing scenario in an ASIC facility is used to demonstrate how the system can be used to analyse options for corrective processing. Other applications exist in its use for documenting processes, to simplify process transfer and implementation, and investigating the effect of corrective processing on device reliability.