- Email: [email protected]
Inversion-channel enhancement-mode GaAs MOSFETs with regrown source and drain contacts
ARTICLE IN PRESS Journal of Crystal Growth 311 (2009) 1958–1961
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Inversion-channel enhancement-mode GaAs MOSFETs with regrown source and drain contacts Chichih Liao a,, Donald Cheng a, Chienchia Cheng a, K.Y. Cheng a, Milton Feng a, T.H. Chiang b, J. Kwo b, M. Hong b a b
Electrical and Computer Engineering Department, University of Illinois, 208 North Wright Street, Urbana, IL 61801, USA Department Materials Science and Engineering, Department of Physics, National Tsing Hua University, Hsinchu, Taiwan 30012
a r t i c l e in f o
a b s t r a c t
Available online 24 November 2008
The use of compound semiconductors as the channel material has recently drawn great attention because of its potential to solve the upcoming Si metal–oxide–semiconductor field effect transistor (MOSFET) scaling problem for device beyond 22 nm node. In this work, a method of fabricating inversion-channel enhancement-mode GaAs n-MOSFET by incorporating molecular beam epitaxy regrown source and drain regions is demonstrated. By using regrown contact layers to avoid hightemperature processes and, thus, preserve the integrity of the oxide–semiconductor interface, the structure allows the fabrication of self-aligned III–V-based MOSFET. The fabricated n-channel enhancement-mode GaAs MOSFET with a 4 mm gate length shows a record high transconductance of 75 mS/mm. & 2008 Elsevier B.V. All rights reserved.
Keywords: A3. Molecular beam epitaxy B1. Oxides B2. Semiconducting gallium arsenide B3. Field effect transistors
1. Introduction For more than 30 years, silicon-based metal–oxide–semiconductor field effect transistor (MOSFET) technologies have been advancing at a dramatic pace due to the progressive and aggressive scaling-down of MOSFET structures to smaller dimensions, resulting in improved performance. However, recent developments indicate that scaling MOSFET beyond 22 nm node will confront some obstacles intrinsic to the Si material system [1]. In order to keep the development pace, the introduction of new material system or novel designs of device structure have been investigated. Among several emerging nano-scale devices with the potential to integrate with current silicon technology, MOSFETs based on III–V compound semiconductors are among the most attractive due to their high electron motility [2]. In addition, III–V materials can be patterned and shaped using ‘‘top–down’’ lithographic and etching methods, which are almost completely compatible with today’s integrated circuit (IC) fabrication equipment and facilities. Considering these advantages, III–V-based MOSFET could be the most competitive candidate for the next-generation high-speed integrated circuits. Although III–V compound semiconductors have these advantages, there are still many obstacles need to be overcome. One of the most challenging tasks of III–V MOSFET is the lack of a high
Corresponding author.
E-mail address: [email protected] (C. Liao). 0022-0248/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2008.11.064
quality and thermodynamically stable native oxide which possesses low interface states. After decades of research by many groups, Ga2O3(Gd2O3) [GaGdO] [3] and HfO2 [4] have been identified as the suitable gate dielectrics for III–V semiconductor. However, the device characteristics of III–V MOSFET using these materials as the gate dielectrics are still inferior in comparison with silicon-based MOSFET. For example, the interface-state density (Dit) is still close to the order of 1012/cm2 eV and Ion/Ioff is only 103, which cannot fulfill the requirement of current applications [4]. Therefore, developing a stable and reliable gate dielectric structure is extremely important for adopting III–V MOSFET in the future ICs. Besides the gate dielectric issue, minimizing the resistance of source and drain regions is another crucial one. In long channel III–V MOSFETs, the source and drain contact resistance are small enough compared to the intrinsic channel resistance. As the gate length is scaled down, the channel resistance is significantly lowered and becomes very small in comparison to the external resistances. These large extrinsic resistances become a key limiting factor of device performance. In silicon MOSFET technology, ion-implantation followed by an activation annealing is used to form shallow, diffusionless, and highly doped source and drain in both n- and p-MOSFETs. However, III–V compound semiconductors are not tolerant of high-temperature processes. In the case of III–V MOSFET, the non-native oxide/channel interface would easily degrade after undergoing high-temperature processes such as post-ion-implantation annealing. For example, a rapid thermal annealing at 780 1C for 6 s would severely damage the interface
ARTICLE IN PRESS C. Liao et al. / Journal of Crystal Growth 311 (2009) 1958–1961
between Ga2O3 and GaAs, [5] while the gate leakage current of HfO2/GaAs structure would increase noticeably after annealing at 750 1C. [6] It was shown that the thermal stability of GaGdO on GaAs at temperatures at or above 750 1C can be improved by either annealing in ultra-high vacuum or using a two-step annealing process. [7] However, the high performance GaGdO/ GaAs enhancement-mode MOSFET is yet to be demonstrated using this approach. Therefore, the formation of source and drain regions using an alternative lower-temperature process is needed in order to avoid the possible interface degradation and to achieve high device performance. In this work, we propose a new approach of making III–V compound semiconductor-based MOS structures, combining a high-quality GaGdO/GaAs system, self-aligned source/drain formation and heavily doped regrown source and drain region. The GaGdO/GaAs system represents the state-of-the-art in creating a gate-channel interface to mitigate interface states, while the regrown source and drain allow highly doped and low-resistance contacts with no high-temperature processing. The highest temperature the sample encountered is the surface oxide desorption temperature of GaAs, which is only 580 1C and much lower than the post-ion-implantation annealing temperature. The experimental results suggested that this fabrication approach is suitable for the fabrication of high-quality III–V MOSFET, which has demonstrated outstanding performance even though the processing methods are not optimized.
1959
3. Results and discussion For the regrowth of source/drain contacts, a thorough cleaning of wet-etched sample before the growth is extremely important. After the cleaning, the patterned sample was loaded into the MBE system for the regrowth. The regrowth starts with surface oxide desorption and a H+ treatment. When the sample is well cleaned, a (2 4) streaky reflection high-energy electron diffraction (RHEED) pattern could be observed. In this work, the acetone/ methanol/IPA rinsing followed by oxygen plasma etch was determined to keep the sample surface free from contaminations. Fig. 1 shows the regrown surfaces of dummy samples patterned with Ti to simulate the sacrificial gate. Fig. 1(a) is the sample with acetone/methanol/IPA rinsing only, which shows extremely rough surfaces on both metal-masked and source/drain regions. On the contrary, for a well-cleaned sample, smooth and defectfree regrown source/contact regions could be achieved, as it could be seen in Fig. 1(b). In Fig. 1(b), the metal-masked region is fairly rough after the regrowth because of the formation of polycrystalline GaAs on the metal. Since the Si-doped polycrystalline GaAs is conductive, removal of the overgrown material is important to avoid the possible leakage paths. Although a smooth and defect-free regrowth of source and drain areas is achieved, some issues remain to be solved. Improving the growth selectivity to get rid of undesired polycrystalline grown over the metal gate is one of them. If the
2. Experimental procedures The device process flow started with molecular beam epitaxial (MBE) growth of beryllium-doped p-type GaAs grown on SI-GaAs substrate followed by an in-situ deposition of 20-nm-thick GaGdO as the gate dielectric in an interconnected ultra-high vacuum oxide deposition chamber [8]. After removed from the growth chamber, titanium is deposited and patterned on the sample as a sacrificial gate, which will help to lift-off the overgrown III–V material after the regrowth process. After the sacrificial gate is patterned, the sample is wet-etched with H2SO4/H2O2/H2O (1:8:1000) to form the source and drain trench. The sample is then cleaned and loaded into the MBE system for the regrowth of source and drain regions. After the regrowth, the sacrificial gate is removed to lift-off the overgrown material, and then gold is deposited as the gate metal. Finally, AuGe/Ni/Au (70/10/300 nm) is deposited on source/drain region to form the contact. The drain current–voltage (I–V) characteristics of MOSFETs with a gate dimension of 4 mm 64 mm are measured with a HP-4145 semiconductor analyzer.
Fig. 2. SEM micrograph of selective growth of GaAs over a dielectric (SiN) covered Ti metal.
Fig. 1. Scanning electron microscope (SEM) micrographs of regrown GaAs on Ti patterned GaAs surface (a) without proper cleaning, and (b) cleaned with the procedures mentioned in the text.
ARTICLE IN PRESS 1960
C. Liao et al. / Journal of Crystal Growth 311 (2009) 1958–1961
Fig. 3. SEM micrographs of the regrown MOSFET gate area by utilizing (a) MBE and (b) MEE growth mode.
growth selectivity could be increased and the overgrown material on the sacrificial gate is reduced, it will be easier to completely remove the overgrown material. It has been shown that the selective growth can be achieved by utilizing dielectric masks [9]. Therefore, in Fig. 2, a SiN/Ti double-layer mask was substituted for the Ti mask used in the gate region. As shown in Fig. 2, on the regrown sample, the source/contact regions remain smooth, while the density of polycrystalline on top of the masked region is greatly reduced, as compared with Fig. 1. This improvement suggests that better growth selectivity and perhaps less complicated process flow is possible. A careful design of the sacrificial gate and the following lift-off process is necessary, and the process compatibility with the gate dielectric has to be considered. Another issue is the trench or gap formation between the regrown source/drain region and the conduction channel region, which can be seen in Fig. 3(a). It is caused by the limited migration of adatoms under the shadow of the gate metal during MBE growth. This phenomenon would increase the resistance between source/drain contacts and the channel. In order to alleviate this problem, migration enhancement epitaxy (MEE) was adopted. MEE has demonstrated advantages of enhancing the migration length of adatoms and lowering surface defects while growing at low temperature [10]. The sample shown in Fig. 3(b) is grown with the first 50 ML GaAs by MEE and the remaining (100 nm) using SSMBE. It can be seen easily that the gap between regrown source/drain and the gate/ channel region is effectively reduced without introducing any defects. To further reduce the gap, the undercut caused by etching has to be carefully designed and the growth conditions need adjustments to further enhance the migration ability of adatoms. Finally, n-type enhancement-mode GaAs MOSFETs with a gate dimension of 4 mm 64 mm were fabricated using optimized cleaning procedures and Ti sacrificial gate. However, MEE was not utilized since the growth conditions were not optimized. Its drain I–V characteristics are shown in Fig. 4. The gate voltage is scanned from 0 to 5 V at a step of 0.2 V, and drain-source current decreases as the gate voltage decreases when Vds is fixed. This indicates that the device can be effectively controlled by the gate biases. The threshold gate voltage of the device is estimated to be about 3.2 V. The device showed a high transconductance of 75 mS/ mm at the gate voltage of 5 V and drain-source voltage of 8 V. Compared with other GaAs inversion-channel enhancementmode MOSFETs [11], the regrown device showed an excellent performance. Because the transconductance is inversely proportional to the gate length, our device is calculated to have an expected transconductance over 120 mS/mm if the gate length is shrunk down to 1 mm. Another advantage of the regrown device is that it completely mimics conventional Si MOSFET structure,
Fig. 4. The Ids–Vds characteristics of a 4 mm 64 mm n-channel enhancement mode GaAs MOSFET measured at different gate voltages between 0 and 5 V with steps of 0.2 V. A drain saturation current of over 70 mA/mm is achieved for Vg=5 V. High transconductance gm of 75 mS/mm is achieved at a gate voltage of 5 V.
while others with higher transconductance are HEMT-like devices. Furthermore, the device performance is expected to improve since the device dimension is large and the process has not yet been optimized. However, some of the I–V characteristics do not cross the zeropoint, which indicates that a leakage current exists at zero bias. The leakage could come from the remaining of the regrown material on top or sidewall of the gate dielectric which is highly conductive. Some poly-crystal might remain around the sidewall of the gate dielectric and led to a leakage path from the source through gate metal to the drain.
4. Summary In summary, we proposed a method of fabricating n-channel enhancement-mode GaAs MOSFET using MBE regrown source and drain regions. By utilizing the regrowth technique, we can avoid the possible issues originated from high-temperature processes. The regrowth selectivity between the metal gate area and source/ drain regions can be improved by covering the metal sacrificial gate with SiN and utilizing MEE growth method. The MEE can effectively reduce the gap between source/drain region and the
ARTICLE IN PRESS C. Liao et al. / Journal of Crystal Growth 311 (2009) 1958–1961
channel. The n-channel enhancement-mode GaAs MOSFET with a 4 mm gate length shows a record high transconductance of 75 mS/mm. Although the process has not yet been optimized, the results suggested that the regrown source/drain region approach is an excellent method for the fabrication of enhancement-mode III–V MOSFET.
Acknowledgements The work is supported in part by the MARCO MSD Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program. The authors also wish to thank Department of Natural Sciences at National Science Council under Grants of NSC-97-2120-M-007-008 and NSC-96-2628-M-007-003-MY3, Taiwan, Republic of China for supporting this work performed at National Tsing Hua University.
1961
References [1] Thomas Skotnicki, James A. Hutchby, Tsu-Jae King, H.-S. Philip Wong, Frederic Boeuf, IEEE Circuits Devices Mag. 21 (2005) 16. [2] Robert Chau, Brian Doyle, Suman Datta, Jack Kavalieros, Kevin Zhang, Nat. Mater. 6 (2007) 810. [3] M. Hong, M. Passlack, J.P. Mannaerts, J. Kwo, S.N.G. Chu, N. Moriya, S.Y. Hou, V.J. Fratello, J. Vac. Sci. Technol. B 14 (1996) 2297. [4] S.J. Koester, W. Kiewra, Yanning Sun, D.A. Neumayer, J.A. Ott, M. Copel, D.K. Sadana, Appl. Phys. Lett. 89 (2006) 042104. [5] M. Passlack, J.K. Abrokwah, Z. Yu, R. Droopad, C. Overgaard, H. Kawayoshi, Appl. Phys. Lett. 82 (2003) 1691. [6] S. Oktyabrsky, V. Tokranov, M. Yakimov, R. Moore, S. Koveshnikov, W. Tsai, F. Zhu, J.C. Lee, Mater. Sci. Eng. B 135 (2006) 272. [7] C.P. Chen, Y.J. Lee, Y.C. Chang, Z.K. Yang, M. Hong, J. Kwo, H.Y. Lee, T.S. Lay, J. Appl. Phys. 100 (2006) 104502. [8] P.J. Tsai, L.K. Chu, Y.W. Chen, Y.N. Chiu, H.P. Yang, P. Chang, J. Kwo, J. Chi, M. Hong, J. Crystal Growth 301–302 (2007) 1013. [9] Christian Heinlein, Jostein K. Grepstad, Bjørn-Ove Fimland, Torunn Berge, J. Crystal Growth 201/202 (1999) 586. [10] Y. Horikoshi, Minoru Kawashima, Hiroshi Yamaguchi, Jpn. J. Appl. Phys. 27 (1988) 169. [11] K. Rajagopalan, Jonathan Abrokwah, Ravi Droopad, Matthias Passlack, IEEE Electron. Devices Lett. 27 (2006) 959.
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Inversion-channel enhancement-mode GaAs MOSFETs with regrown source and drain contacts Chichih Liao a,, Donald Cheng a, Chienchia Cheng a, K.Y. Cheng a, Milton Feng a, T.H. Chiang b, J. Kwo b, M. Hong b a b
Electrical and Computer Engineering Department, University of Illinois, 208 North Wright Street, Urbana, IL 61801, USA Department Materials Science and Engineering, Department of Physics, National Tsing Hua University, Hsinchu, Taiwan 30012
a r t i c l e in f o
a b s t r a c t
Available online 24 November 2008
The use of compound semiconductors as the channel material has recently drawn great attention because of its potential to solve the upcoming Si metal–oxide–semiconductor field effect transistor (MOSFET) scaling problem for device beyond 22 nm node. In this work, a method of fabricating inversion-channel enhancement-mode GaAs n-MOSFET by incorporating molecular beam epitaxy regrown source and drain regions is demonstrated. By using regrown contact layers to avoid hightemperature processes and, thus, preserve the integrity of the oxide–semiconductor interface, the structure allows the fabrication of self-aligned III–V-based MOSFET. The fabricated n-channel enhancement-mode GaAs MOSFET with a 4 mm gate length shows a record high transconductance of 75 mS/mm. & 2008 Elsevier B.V. All rights reserved.
Keywords: A3. Molecular beam epitaxy B1. Oxides B2. Semiconducting gallium arsenide B3. Field effect transistors
1. Introduction For more than 30 years, silicon-based metal–oxide–semiconductor field effect transistor (MOSFET) technologies have been advancing at a dramatic pace due to the progressive and aggressive scaling-down of MOSFET structures to smaller dimensions, resulting in improved performance. However, recent developments indicate that scaling MOSFET beyond 22 nm node will confront some obstacles intrinsic to the Si material system [1]. In order to keep the development pace, the introduction of new material system or novel designs of device structure have been investigated. Among several emerging nano-scale devices with the potential to integrate with current silicon technology, MOSFETs based on III–V compound semiconductors are among the most attractive due to their high electron motility [2]. In addition, III–V materials can be patterned and shaped using ‘‘top–down’’ lithographic and etching methods, which are almost completely compatible with today’s integrated circuit (IC) fabrication equipment and facilities. Considering these advantages, III–V-based MOSFET could be the most competitive candidate for the next-generation high-speed integrated circuits. Although III–V compound semiconductors have these advantages, there are still many obstacles need to be overcome. One of the most challenging tasks of III–V MOSFET is the lack of a high
Corresponding author.
E-mail address: [email protected] (C. Liao). 0022-0248/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2008.11.064
quality and thermodynamically stable native oxide which possesses low interface states. After decades of research by many groups, Ga2O3(Gd2O3) [GaGdO] [3] and HfO2 [4] have been identified as the suitable gate dielectrics for III–V semiconductor. However, the device characteristics of III–V MOSFET using these materials as the gate dielectrics are still inferior in comparison with silicon-based MOSFET. For example, the interface-state density (Dit) is still close to the order of 1012/cm2 eV and Ion/Ioff is only 103, which cannot fulfill the requirement of current applications [4]. Therefore, developing a stable and reliable gate dielectric structure is extremely important for adopting III–V MOSFET in the future ICs. Besides the gate dielectric issue, minimizing the resistance of source and drain regions is another crucial one. In long channel III–V MOSFETs, the source and drain contact resistance are small enough compared to the intrinsic channel resistance. As the gate length is scaled down, the channel resistance is significantly lowered and becomes very small in comparison to the external resistances. These large extrinsic resistances become a key limiting factor of device performance. In silicon MOSFET technology, ion-implantation followed by an activation annealing is used to form shallow, diffusionless, and highly doped source and drain in both n- and p-MOSFETs. However, III–V compound semiconductors are not tolerant of high-temperature processes. In the case of III–V MOSFET, the non-native oxide/channel interface would easily degrade after undergoing high-temperature processes such as post-ion-implantation annealing. For example, a rapid thermal annealing at 780 1C for 6 s would severely damage the interface
ARTICLE IN PRESS C. Liao et al. / Journal of Crystal Growth 311 (2009) 1958–1961
between Ga2O3 and GaAs, [5] while the gate leakage current of HfO2/GaAs structure would increase noticeably after annealing at 750 1C. [6] It was shown that the thermal stability of GaGdO on GaAs at temperatures at or above 750 1C can be improved by either annealing in ultra-high vacuum or using a two-step annealing process. [7] However, the high performance GaGdO/ GaAs enhancement-mode MOSFET is yet to be demonstrated using this approach. Therefore, the formation of source and drain regions using an alternative lower-temperature process is needed in order to avoid the possible interface degradation and to achieve high device performance. In this work, we propose a new approach of making III–V compound semiconductor-based MOS structures, combining a high-quality GaGdO/GaAs system, self-aligned source/drain formation and heavily doped regrown source and drain region. The GaGdO/GaAs system represents the state-of-the-art in creating a gate-channel interface to mitigate interface states, while the regrown source and drain allow highly doped and low-resistance contacts with no high-temperature processing. The highest temperature the sample encountered is the surface oxide desorption temperature of GaAs, which is only 580 1C and much lower than the post-ion-implantation annealing temperature. The experimental results suggested that this fabrication approach is suitable for the fabrication of high-quality III–V MOSFET, which has demonstrated outstanding performance even though the processing methods are not optimized.
1959
3. Results and discussion For the regrowth of source/drain contacts, a thorough cleaning of wet-etched sample before the growth is extremely important. After the cleaning, the patterned sample was loaded into the MBE system for the regrowth. The regrowth starts with surface oxide desorption and a H+ treatment. When the sample is well cleaned, a (2 4) streaky reflection high-energy electron diffraction (RHEED) pattern could be observed. In this work, the acetone/ methanol/IPA rinsing followed by oxygen plasma etch was determined to keep the sample surface free from contaminations. Fig. 1 shows the regrown surfaces of dummy samples patterned with Ti to simulate the sacrificial gate. Fig. 1(a) is the sample with acetone/methanol/IPA rinsing only, which shows extremely rough surfaces on both metal-masked and source/drain regions. On the contrary, for a well-cleaned sample, smooth and defectfree regrown source/contact regions could be achieved, as it could be seen in Fig. 1(b). In Fig. 1(b), the metal-masked region is fairly rough after the regrowth because of the formation of polycrystalline GaAs on the metal. Since the Si-doped polycrystalline GaAs is conductive, removal of the overgrown material is important to avoid the possible leakage paths. Although a smooth and defect-free regrowth of source and drain areas is achieved, some issues remain to be solved. Improving the growth selectivity to get rid of undesired polycrystalline grown over the metal gate is one of them. If the
2. Experimental procedures The device process flow started with molecular beam epitaxial (MBE) growth of beryllium-doped p-type GaAs grown on SI-GaAs substrate followed by an in-situ deposition of 20-nm-thick GaGdO as the gate dielectric in an interconnected ultra-high vacuum oxide deposition chamber [8]. After removed from the growth chamber, titanium is deposited and patterned on the sample as a sacrificial gate, which will help to lift-off the overgrown III–V material after the regrowth process. After the sacrificial gate is patterned, the sample is wet-etched with H2SO4/H2O2/H2O (1:8:1000) to form the source and drain trench. The sample is then cleaned and loaded into the MBE system for the regrowth of source and drain regions. After the regrowth, the sacrificial gate is removed to lift-off the overgrown material, and then gold is deposited as the gate metal. Finally, AuGe/Ni/Au (70/10/300 nm) is deposited on source/drain region to form the contact. The drain current–voltage (I–V) characteristics of MOSFETs with a gate dimension of 4 mm 64 mm are measured with a HP-4145 semiconductor analyzer.
Fig. 2. SEM micrograph of selective growth of GaAs over a dielectric (SiN) covered Ti metal.
Fig. 1. Scanning electron microscope (SEM) micrographs of regrown GaAs on Ti patterned GaAs surface (a) without proper cleaning, and (b) cleaned with the procedures mentioned in the text.
ARTICLE IN PRESS 1960
C. Liao et al. / Journal of Crystal Growth 311 (2009) 1958–1961
Fig. 3. SEM micrographs of the regrown MOSFET gate area by utilizing (a) MBE and (b) MEE growth mode.
growth selectivity could be increased and the overgrown material on the sacrificial gate is reduced, it will be easier to completely remove the overgrown material. It has been shown that the selective growth can be achieved by utilizing dielectric masks [9]. Therefore, in Fig. 2, a SiN/Ti double-layer mask was substituted for the Ti mask used in the gate region. As shown in Fig. 2, on the regrown sample, the source/contact regions remain smooth, while the density of polycrystalline on top of the masked region is greatly reduced, as compared with Fig. 1. This improvement suggests that better growth selectivity and perhaps less complicated process flow is possible. A careful design of the sacrificial gate and the following lift-off process is necessary, and the process compatibility with the gate dielectric has to be considered. Another issue is the trench or gap formation between the regrown source/drain region and the conduction channel region, which can be seen in Fig. 3(a). It is caused by the limited migration of adatoms under the shadow of the gate metal during MBE growth. This phenomenon would increase the resistance between source/drain contacts and the channel. In order to alleviate this problem, migration enhancement epitaxy (MEE) was adopted. MEE has demonstrated advantages of enhancing the migration length of adatoms and lowering surface defects while growing at low temperature [10]. The sample shown in Fig. 3(b) is grown with the first 50 ML GaAs by MEE and the remaining (100 nm) using SSMBE. It can be seen easily that the gap between regrown source/drain and the gate/ channel region is effectively reduced without introducing any defects. To further reduce the gap, the undercut caused by etching has to be carefully designed and the growth conditions need adjustments to further enhance the migration ability of adatoms. Finally, n-type enhancement-mode GaAs MOSFETs with a gate dimension of 4 mm 64 mm were fabricated using optimized cleaning procedures and Ti sacrificial gate. However, MEE was not utilized since the growth conditions were not optimized. Its drain I–V characteristics are shown in Fig. 4. The gate voltage is scanned from 0 to 5 V at a step of 0.2 V, and drain-source current decreases as the gate voltage decreases when Vds is fixed. This indicates that the device can be effectively controlled by the gate biases. The threshold gate voltage of the device is estimated to be about 3.2 V. The device showed a high transconductance of 75 mS/ mm at the gate voltage of 5 V and drain-source voltage of 8 V. Compared with other GaAs inversion-channel enhancementmode MOSFETs [11], the regrown device showed an excellent performance. Because the transconductance is inversely proportional to the gate length, our device is calculated to have an expected transconductance over 120 mS/mm if the gate length is shrunk down to 1 mm. Another advantage of the regrown device is that it completely mimics conventional Si MOSFET structure,
Fig. 4. The Ids–Vds characteristics of a 4 mm 64 mm n-channel enhancement mode GaAs MOSFET measured at different gate voltages between 0 and 5 V with steps of 0.2 V. A drain saturation current of over 70 mA/mm is achieved for Vg=5 V. High transconductance gm of 75 mS/mm is achieved at a gate voltage of 5 V.
while others with higher transconductance are HEMT-like devices. Furthermore, the device performance is expected to improve since the device dimension is large and the process has not yet been optimized. However, some of the I–V characteristics do not cross the zeropoint, which indicates that a leakage current exists at zero bias. The leakage could come from the remaining of the regrown material on top or sidewall of the gate dielectric which is highly conductive. Some poly-crystal might remain around the sidewall of the gate dielectric and led to a leakage path from the source through gate metal to the drain.
4. Summary In summary, we proposed a method of fabricating n-channel enhancement-mode GaAs MOSFET using MBE regrown source and drain regions. By utilizing the regrowth technique, we can avoid the possible issues originated from high-temperature processes. The regrowth selectivity between the metal gate area and source/ drain regions can be improved by covering the metal sacrificial gate with SiN and utilizing MEE growth method. The MEE can effectively reduce the gap between source/drain region and the
ARTICLE IN PRESS C. Liao et al. / Journal of Crystal Growth 311 (2009) 1958–1961
channel. The n-channel enhancement-mode GaAs MOSFET with a 4 mm gate length shows a record high transconductance of 75 mS/mm. Although the process has not yet been optimized, the results suggested that the regrown source/drain region approach is an excellent method for the fabrication of enhancement-mode III–V MOSFET.
Acknowledgements The work is supported in part by the MARCO MSD Focus Center, one of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program. The authors also wish to thank Department of Natural Sciences at National Science Council under Grants of NSC-97-2120-M-007-008 and NSC-96-2628-M-007-003-MY3, Taiwan, Republic of China for supporting this work performed at National Tsing Hua University.
1961
References [1] Thomas Skotnicki, James A. Hutchby, Tsu-Jae King, H.-S. Philip Wong, Frederic Boeuf, IEEE Circuits Devices Mag. 21 (2005) 16. [2] Robert Chau, Brian Doyle, Suman Datta, Jack Kavalieros, Kevin Zhang, Nat. Mater. 6 (2007) 810. [3] M. Hong, M. Passlack, J.P. Mannaerts, J. Kwo, S.N.G. Chu, N. Moriya, S.Y. Hou, V.J. Fratello, J. Vac. Sci. Technol. B 14 (1996) 2297. [4] S.J. Koester, W. Kiewra, Yanning Sun, D.A. Neumayer, J.A. Ott, M. Copel, D.K. Sadana, Appl. Phys. Lett. 89 (2006) 042104. [5] M. Passlack, J.K. Abrokwah, Z. Yu, R. Droopad, C. Overgaard, H. Kawayoshi, Appl. Phys. Lett. 82 (2003) 1691. [6] S. Oktyabrsky, V. Tokranov, M. Yakimov, R. Moore, S. Koveshnikov, W. Tsai, F. Zhu, J.C. Lee, Mater. Sci. Eng. B 135 (2006) 272. [7] C.P. Chen, Y.J. Lee, Y.C. Chang, Z.K. Yang, M. Hong, J. Kwo, H.Y. Lee, T.S. Lay, J. Appl. Phys. 100 (2006) 104502. [8] P.J. Tsai, L.K. Chu, Y.W. Chen, Y.N. Chiu, H.P. Yang, P. Chang, J. Kwo, J. Chi, M. Hong, J. Crystal Growth 301–302 (2007) 1013. [9] Christian Heinlein, Jostein K. Grepstad, Bjørn-Ove Fimland, Torunn Berge, J. Crystal Growth 201/202 (1999) 586. [10] Y. Horikoshi, Minoru Kawashima, Hiroshi Yamaguchi, Jpn. J. Appl. Phys. 27 (1988) 169. [11] K. Rajagopalan, Jonathan Abrokwah, Ravi Droopad, Matthias Passlack, IEEE Electron. Devices Lett. 27 (2006) 959.