drain MOSFETs

Microelectronics Journal 42 (2011) 1164–1168

Contents lists available at ScienceDirect

Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Electric potential and threshold voltage models for double-gate Schottky-barrier source/drain MOSFETs Peicheng Li, Guangxi Hu n, Ran Liu, Tingao Tang State Key Laboratory of ASIC and System, School of Information Science and Technology, Fudan University, Shanghai 200433, PR China

a r t i c l e i n f o

a b s t r a c t

Article history: Received 9 April 2011 Received in revised form 8 June 2011 Accepted 14 June 2011 Available online 2 July 2011

The threshold voltage, Vth of a double-gate (DG) Schottky-barrier (SB) source/drain (S/D) metal-oxidesemiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential is obtained by using Gauss’s law and solving Poisson’s equation, the results of which are compared with simulations, and good agreement is observed. Based on the potential model, a new definition for Vth is developed, and an analytic expression for Vth is obtained, including quantum mechanical effects and SB lowering effect. We find that Vth is very sensitive to the silicon body thickness, tsi. For a device with a small tsi ( o 3 nm), Vth increases dramatically with the reduction of tsi. Vth decreases with the increase of the back-gate oxide thickness, and with the increasing of the drain bias. All the results can be of great help to the ultra-large scale integrated-circuit (ULSI) designers. & 2011 Elsevier Ltd. All rights reserved.

Keywords: Double-gate MOSFET Threshold voltage Schottky-barrier

1. Introduction To minimize the short channel effects (SCEs) and reduce the source/drain (S/D) series resistance, many new structures of metal-oxide-semiconductor field-effect transistor (MOSFET) have been proposed and investigated to some extent. Of all, a MOSFET with a double-gate Schottky-barrier (DGSB) S/D seems to be the most favorable candidate to replace the traditional planar one gate doped S/D device [1–5]. As discussed in [6,7], the DG MOSFETs can suppress the SCEs, decrease the gate leakage current, and improve the subthreshold slope. As we know that, the resistivity of the traditional doped S/D is two orders of magnitude larger than that of the metal S/D [5,8]. As the complementary MOS scaling continues, the series resistance of the S/D will degrade the performance of the device. In 2004, a p-type channel SB MOSFET with an excellent performance was reported, whose on/off ratio of current can be as high as 107– 108 [9]. Moreover, simple fabrication processes can manufacture the SB device [8], therefore, an SB S/D device becomes the most potential substitute for doped S/D MOSFET. As the threshold voltage, Vth is one of the most important parameters in MOSFET, we study the characteristics of Vth of the DGSB MOSFET. In [2], the authors studied the Vth behaviors of the doped symmetric DGSB device, but the channel length of the device was rather large and quantum mechanical (QM) effects were excluded. In [3], the authors investigated the Vth of the undoped symmetric DGSB device. As the devices scale to nanometer regime, only a few dopants will result in a doping density

n

Corresponding author. Fax: þ86 21 51355287. E-mail address: [email protected] (G. Hu).

0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2011.06.002

to as high as 1018 cm  3 [10], and unintentional impurities can be inevitable in the fabrication process. Therefore, we think it is worthwhile to study the doped DGSB MOSFET in nanoscale and give a reasonable definition of Vth for the new device. In this work, we develop an analytic model to obtain the Vth for doped DGSB S/D device. An analytic model for surface potential in the channel is developed and the results are verified via simulations, and good agreement is observed. Based on the surface potential model, a definition for Vth is presented by taking into account of QM effects and SB lowering (SBL) effect.

2. Electric potential model The schematic diagram of a DGSB MOSFET is shown in Fig. 1. Similar to the method used in [11], by using Gauss0 s law to a rectangular Gaussian box with a height of tsi in the silicon channel, and neglecting the mobile charges, one can obtain the following equation:

esi tsi dESF ðyÞ dy Z

þCfox ½VGSF VFBF VSF ðyÞ

þ Cbox ½VGSB VFBB VSB ðyÞ ¼ qNA tsi

ð1Þ

where ESF is the front surface lateral electric field, VSF/VSB the front/back surface potential at the Si–SiO2 interface, VFBF/VFBB the front/back-gate flat-band voltage, NA the doping concentration of the silicon body, Cfox/Cbox the front/back oxide capacitance per unit area , and Z a fitting parameter, the physical meaning of which was given in [11]. The other symbols have their usual

P. Li et al. / Microelectronics Journal 42 (2011) 1164–1168

1165

VGSF L

Front Gate Gaussian Box SiO2 (tfox)

Source (Metal)

y Drain

tsi

Si

VDS

(Metal)

SiO2 (tbox) Back Gate Fig. 2. Energy band diagram for electron tunneling through an SB. qFMS is the SB height. Solid line corresponds to a smaller gate bias while dashed line corresponds to a larger gate bias.

VGSB

x

Fig. 1. Diagram of a DGSB MOSFET.

meanings. The back surface potential can be expressed as VSB ðyÞ ¼ VSF ðyÞENOR ðyÞtsi þ

qNA tsi2 2esi

ð2Þ

here ENOR(y) is the longitudinal electric field in the silicon channel. By applying the boundary condition that the normal component of electric displacement is continuous at the front Si–SiO2 interface, esiENOR(y)¼ eoxEfox ¼(eox/tfox)(tfoxEfox) ¼CfoxVfox, Efox and Vfox are the normal component of electric field and voltage drop in the front oxide, respectively. Then one obtains ENOR ðyÞ ¼

Cfox ½VGSF VFBF VSF ðyÞ

esi

ð3Þ

Substituting (2) and (3) into (1), one obtains dESF ðyÞ VSF ðyÞ þ VSL ¼ 0 ð4Þ dy pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi where l  esi tsi =ZCox , is the characteristic length, Cox  Cfox 2 ð1þ rÞ þrCfox =Csi , r ¼Cbox/Cfox, Csi is the capacitance per unit area of the silicon film, Csi ¼ esi/tsi, and VSL represents the long channel front surface potential and is expressed as

l2

VSL ¼

1 þrCfox =CSi r ðVGSF VFBF Þ þ ðVGSB VFBB Þ 1þ r þ rCfox =CSi 1 þr þ rCfox =CSi 1 þrCfox =2Csi  qNA tsi 2 =C Cfox ð1 þ rÞ þ rCfox Si

ð5Þ

By considering the boundary conditions at the source end and the drain end, VSF ð0Þ ¼ FMS and VSF ðLÞ ¼ FMS þ VDS

ð6Þ

one can obtain the front surface potential analytically [9] sinhðy=lÞ VSF ðyÞ ¼ VSL þ ðFMS VSL þVDS Þ sinhðL=lÞ   sinh ðLyÞ=l þ ðFMS VSL Þ sinhðL=lÞ

the front surface potential will be large, and the thickness of the SB will be small. Similar to the definition of Vth described in [5], we define Vth as the voltage applied to the front-gate which makes the minimum of silicon conduction band bend to the Fermi-level of the source. Based on the said definition, the equivalent condition for Vth is: VSFm ¼2FBeff, VSFm being the maximum front surface potential, and FBeff the effective SB height. We model here FBeff as

FBeff ¼ FMS þ ðD1 D2 Þ=q 2 2

ð8Þ

where D1 ¼ p _ =ð2mn tsi Þ, mn being the effective mass of an electron and is set to be 0.22m0, with m0 being the free electron mass [13]. D1 arises from the QM effects. When the thickness of the silicon body is as small as several nanometers, space confinement will be significant, the silicon channel can be regarded as a quantum well, and the carrier energies are now quantized in the x direction. At the subthreshold region, the carriers in the channel are mainly electrons and they will have the minimum kinetic energy owing to the confinement in the silicon film. D2 is the SBL effect due to image force [14], sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi q9E9 D2 ¼ q ð9Þ 4peo esi n 2

n

where E is the electric field near the interface of metal S/D and semiconductor. D2 results mainly from the lateral electric field, E, near the interface of metal S/D and silicon, as shown in [9]. The extremum front surface potential, VSFm and its location, ym, can be obtained by solving:  dVSF  ¼0 ð10Þ dy y ¼ ym and ym is approximated as   L l VDS ym   ln 1þ 2 2 FMS VSL

ð7Þ

where L is the channel length, VDS is the voltage applied to the drain, FMS is the SB height for the S/D, FMS ¼(WM  w)/q, with WM being the work function of the metal used in S/D, and w ¼4.05 eV, is the electron affinity of silicon.

ð11Þ

For the DGSB device, by equating VSFm to 2FBeff, one obtains Vth Vth ¼ VFBF þ  

1þ r þ rCfox =Csi 1 þ rCfox =Csi

1 þrCfox =2Csi qNA tsi rðVGSB VFBB Þ  þG 1 þ r þrCfox =Csi 1þ r þ rCfox =Csi Cfox

ð12Þ

where G is given by 3. Threshold voltage model For an SB device, in the subthreshold region, especially when the gate bias is small, thermionic current dominates. However, as the gate bias increases and the device is near its on state, tunneling current will dominate, and the magnitude of the current can be significantly large when the SB thickness is small as is demonstrated in Fig. 2 [5,12]. When the gate bias increases,

G

1 sinhðL=lÞsinhðym =lÞsinh½ðLym Þ=l   

y  ðLym Þ m  2FBeff sinhðL=lÞðFBeff þ VDS Þ sinh FBeff sinh

l

l

ð13Þ The location of the extremum surface potential can be approximated as ym EL/2 for a small drain bias, VDS. For the

1166

P. Li et al. / Microelectronics Journal 42 (2011) 1164–1168

asymmetric DGSB device, where VGSF ¼ VGSB, VFBF ¼VFBB, but r a1, the threshold voltage is ð14Þ

For the symmetric DGSB device, where VGSF ¼VGSB, VFBF ¼VFBB, and r ¼1, the threshold voltage is simplified as 1 þ Cfox =2CSi qNA tSi 2 =C 2Cfox þ Cfox Si

ð15Þ

When the voltage applied to the drain is low enough to justify VDS 5 FMS  VSL, the location of the extremum surface potential can be approximated from (11) as ym EL/2, and G is simplified to the following expression:

DIBL  DVth ¼ Vth ðVDS ¼ 0:05VÞVth ðVDS ¼ 1VÞ

Figs. 3 and 4 show the front surface potential versus channel position under drain biases of 0.05 and 1 V, respectively. Solid lines are the analytic results, while symbols are simulation results, which are obtained with a device simulator, Medici [15]. It is noted that the analytic results are in good accordance with simulation results. NA ¼1018 cm  3, and Z ¼0.5412 are assumed. L¼20 nm, tsi ¼6 nm, tfox ¼tbox ¼1 nm, and FMS ¼ 0.2 V. For simulation parameters, the gate work function is set to be 4.58 eV, and the electron affinity of silicon is set to be 4.05 eV. With Eq. (12), numerical results for threshold voltage can be obtained easily. Fig. 5 presents the Vth characteristics of the device with or without QM effects, including or excluding SBL effect. NA ¼1018 cm  3 is assumed. In Fig. 5, one can notice that while tsi is small ( o3 nm), Vth will shift severely due to the QM effects, which is consistent with the results obtained in the literature 0.5

Front Surface Potential (V)

0.5 V 0.4 V 0.3 V

0.1

V GSF =VGSB =0.2 V

0.0

0.1 V 0V

-0.1 -0.2

Solid line---Analytical Symbol---Simulation

-0.3 0

5 10 15 Position Along the Channel, y (nm)

0.6

VGSF = VGSB = 0.5 V

0.4 0.3 V

0.2

0.1 V -0.1 V 0

20

Fig. 3. Front surface potential along the channel under a small drain bias. L¼ 20 nm, tsi ¼ 6 nm, tfox ¼ tbox ¼1 nm, VDS ¼0.05 V, and FMS ¼0.2 V.

5

10

15

20

Position Along the Channel, y (nm) Fig. 4. Front surface potential along the channel under a large drain bias: L¼20 nm, tsi ¼ 6 nm, tfox ¼tbox ¼ 1 nm, VDS ¼1 V, and FMS ¼ 0.2 V.

Ignore SBL only With Both QM and SBL Ignore QM and SBL Ignore QM only

1.4

ð17Þ

4. Results and discussion

0.2

0.8

ð16Þ

From Eq. (12), we observe that the threshold voltage of an SB device is a function of drain bias, VDS, silicon body thickness, tsi, and channel length, L. When the channel length approaches to the scaling limit, saying 10 nm, Vth will be strongly influenced by VDS, this is the so called drain induced barrier lowering (DIBL) effect. We define DIBL effect as

0.3

Symbol---Simulation 1.0

-0.2

2FBeff coshðL=2lÞðFBeff þ VDS =2Þ coshðL=2lÞ1

0.4

Solid line---Analytical

0.0

Threshold Voltage, Vth (V)

G

Front Surface Potential (V)

1.2

1þ rCfox =2CSi qNA tSi Vth ¼ VFBF þG þ 2 =C Cfox ð1 þ rÞ þ rCfox Si

Vth ¼ VFBF þG þ

1.4

1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0

2.5

3.0 3.5 4.0 4.5 5.0 Silicon Body Thickness, tsi (nm)

5.5

6.0

Fig. 5. Threshold voltages of the SBDG MOSFETs including different effects: L¼20 nm, tfox ¼tbox ¼ 1 nm, VDS ¼ 0.05 V, and FMS ¼ 0.2 V.

[16,17]. Solid line with open circles are results for ignoring SBL, solid line with open/solid squares are results for including/ ignoring both QM and SBL effects, solid line with solid triangles are results for ignoring QM effects. Fig. 5 shows that threshold voltage is lowered by SBL effect and is raised by QM effects. When ignoring QM effects, threshold voltage is almost independent of silicon body thickness. Fig. 6 shows the characteristics of Vth versus the ratio of the capacitance of the back-gate oxide over that of the front-gate oxide, Cbox/Cfox, r. It is noted that, Vth decreases with the reduction of r, the reason is that, while keeping Cfox fixed, Cbox will decrease along with r, hence the thickness of the back-gate oxide will increase, then voltage will drop less near the back-gate, and the front surface potential will rise. Therefore a smaller gate voltage is now needed to switch on the device with a smaller r. Fig. 7 demonstrates the drain induced barrier lowering (DIBL) effect, which is DVth defined in Eq. (17). We find that DIBL effect is not too severe for a DGSB S/D MOSFET, since the shift of the threshold voltage is only about 10 mV. It is noted that a device with a smaller silicon body thickness will have a smaller DIBL effect. Fig. 8 reveals the dependence of threshold voltage, Vth on the doping density, NA. It is noted that Vth increases with NA, which is the same with the traditional planar one gate MOSFET. As NA

P. Li et al. / Microelectronics Journal 42 (2011) 1164–1168

0.50

1167

1.6

0.48

Threshold Voltage, Vth (V)

Threshold Voltage, Vth (V)

ΦMS = 0.4 V

VDS = 0.05 V 0.46 0.44 VDS = 1 V 0.42

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Ratio Parameter, r = Cbox/Cfox Fig. 6. Threshold voltage versus ratio parameter, r: L¼ 20 nm, tsi ¼6 nm, tfox ¼ 1 nm, FMS ¼ 0.2 V.

ΦMS = 0.1 V

0.8

tsi = 6 nm 12

8

12 16 Channel Length, L (nm)

20

Fig. 9. Threshold voltage versus channel length for different FMS: tsi ¼L/2, tfox ¼ tbox ¼1 nm, VDS ¼0.05 V, and VGSB ¼0 V.

SB more difficult, then a larger gate bias is needed to turn on the device, therefore the Vth increases. However, the variation of Vth is only about 10 mV for a wide range of doping density, from NA ¼1015 to 1018 cm  3, and the variation of Vth is only 2%. Fig. 9 illustrates how threshold voltage is affected by SB height. As we know that a higher SB will result in less tunneling, and the threshold voltage will increase with the SB height. One point should be noted here is that in Fig. 9, the ratio of silicon body thickness over channel length is set to be 0.5, which means when L is small, so is tsi. The threshold voltage increases when both L and tsi, decrease simultaneously, the results are consistent with those obtained with quantum simulations in [18].

14 tsi = 3 nm

10 ΔVth (mV)

ΦMS = 0.2 V

1.2

0.4

0.40 1.0

ΦMS = 0.3 V

8 6 4 2

5. Conclusions 0 20

30

40 Channel Length, L (nm)

50

60

Fig. 7. DIBL effect versus device channel length: tfox ¼ tbox ¼1 nm, and FMS ¼ 0.2 V.

Threshold Voltage, Vth (V)

0.412

0.408 L = 20 nm, tsi = 6 nm

0.404

0.400 1E15

1E16

1E17

1E18

So far we have presented and developed a potential model and a threshold voltage model for the DGSB S/D MOSFET, the validity of which has been verified with simulations. For the threshold voltage model, we have taken quantum mechanical effects and Schottky-barrier lowering effect into account. As the semiconductor technology continues to progress, the DGSB S/D MOSFET will be used in the near future. The following design rules are obtained and they will be useful for integrated circuit designers: (i) A device with a very small silicon body thickness, tsi ( o3 nm) should be avoided, since the threshold voltage of the device will be very sensitive to tsi, and the stability of the performance of the device is limited. (ii) To obtain a smaller threshold voltage, a device with a thicker back-gate oxide, and/or a device with a smaller SB height can be employed. (iii) A device with a thin silicon body thickness will have a small DIBL effect. (iv) In the scaling process, the threshold voltage will increase with the reductions of both channel length and silicon body thickness.

Doping Concentration, NA (cm-3) Fig. 8. Threshold voltage versus doping concentration: tfox ¼ tbox ¼1 nm, VDS ¼ 0.05 V, and FMS ¼ 0.2 V.

increases, the Fermi energy level in the channel will be lowered and the effective SB thickness will be larger, or the effective SB height will be higher, making the carriers’ tunneling through the

Acknowledgement The authors would like to acknowledge the support of Shanghai Science Foundation (Project Grant no. 09ZR1402900). The project is supported in part by the Special Funds for Major State Basic Research (973, Project Grant no. 2006CB302703).

1168

P. Li et al. / Microelectronics Journal 42 (2011) 1164–1168

References [1] J. Guo, M.S. Lundstrom, A computational study of thin-body, double-gate, Schottky barrier MOSFETs, IEEE Transactions on Electron Devices 49 (11) (2002) 1897–1902. [2] R. Tanabe, K. Suzuki, Analytical threshold voltage model for double-gate Schottky source/drain silicon-on-insulator metal semiconductor field effect transistor, Japanese Journal of Applied Physics 47 (11) (2008) 8311–8316. [3] B.J. Xu, Z.L. Xia, X.Y. Liu, R.Q. Han, An analytical potential model of doublegate MOSFETs with Schottky source/drain, in: Proceedings of the ICSICT, Beijing, China, 2006, pp. 1296–1298. [4] G.J. Zhu, X. Zhou, T.S. Lee, L.K. Ang, G.H. See, S.H. Lin, A compact model for undoped silicon-nanowire MOSFETs with Schottky-Barrier source/drain, IEEE Transactions on Electron Devices 56 (5) (2009) 1100–1109. [5] S. Xiong, T.-J. King, J. Bokor, A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain, IEEE Transactions on Electron Devices 52 (8) (2005) 1859–1867. [6] A. Tsormpatzoglou, C.A. Dimitriadis, R. Clerc, Q. Rafhay, G. Pananakakis, G. Ghibaudo, Semi-analytical modeling of short channel effects in Si and Ge symmetrical double-Gate MOSFETs, IEEE Transactions on Electron devices 54 (8) (2007) 1943–1952. [7] F. Djeffal, M. Meguellati, A. Benhaya, A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs, Physica E 41 (2009) 1872–1877. [8] J.M. Larson, J.P. Snyder, Overview and status of metal S/D Schottky-Barrier MOSFET technology, IEEE Transactions on Electron Devices 53 (5) (2006) 1048–1058.

[9] S. Zhu, H.Y. Yu, S.J. Whang, J.H. Chen, C. Shen, C. Zhu, S.J. Lee, M.F. Li, D.S.H. Chan, W.J. Yoo, A. Du, C.H. Tung, J. Singh, A. Chin, D.L. Kwong, Schottkybarrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode, IEEE Transactions on Electron Devices 25 (5) (2004) 268–270. [10] Z. Ding, G. Hu, J. Gu, R. Liu, L. Wang, T. Tang, An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric doublegate MOSFETs, Microelectronics Journal 42 (2011) 515–519. [11] Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, Y.C. Cheng, Threshold voltage model for deep-submicrometer MOSFETs, IEEE Transactions on Electron Devices 40 (1) (1993) 86–95. [12] J. Knoch, M. Zhang, S. Mantl, J. Appenzeller, On the performance of singlegated ultrathin-body SOI Schottky-barrier MOSFETs, IEEE Transactions on Electron Devices 53 (7) (2006) 1669–1674. [13] G.X. Hu, L.L. Wang, R. Liu, T.A. Tang, Z.J. Qiu, Quantum-mechanical study on surrounding-gate metal-oxide-semiconductor field-effect transistors, Communications of Theoretical Physics 54 (4) (2010) 736–767. [14] S.M. Sze, K.K. Ng, Physics of Semiconductor Devices, third ed, Wiley-Interscience, New York, 2007. [15] Taurus Medici, Medici User Guide, Version A-2008.09, Synopsys Inc., 2008. [16] V.P. Trivedi, J.G. Fossum, Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs, IEEE Electron Device Letters 26 (8) (2005) 579–582. [17] G.X. Hu, R. Liu, Z.J. Qiu, L.L. Wang, T.A. Tang, Quantum mechanical effects on the threshold voltage of double-gate metal-oxide-semiconductor field-effect transistors, Japanese Journal of Applied Physics 49 (3) (2010) 034001. [18] C. Ahn, M. Shin, Ballistic quantum transport in nanoscale Schottky-barrier tunnel transistors, IEEE Transaction on Nanotechnology 5 (3) (2006) 278–283.