Inverting voltage buffer based lossless grounded inductor simulators

Int. J. Electron. Commun. (AEÜ) 83 (2018) 131–137

Contents lists available at ScienceDirect

International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue

Regular paper

Inverting voltage buffer based lossless grounded inductor simulators Abdullah Yesil a,⇑, Erkan Yuce b, Shahram Minaei c a

Department of Naval Architecture and Marine Engineering, Bandirma Onyedi Eylul University, Balikesir 10200, Turkey Department of Electrical and Electronics Engineering, Pamukkale University, Kinikli, 20160 Denizli, Turkey c Department of Electronics and Communications Engineering, Dogus University, Acibadem, Kadikoy, 34722 Istanbul, Turkey b

a r t i c l e

i n f o

Article history: Received 15 May 2017 Accepted 20 August 2017

Keywords: Grounded inductor simulator Current conveyor CCII+ Inverting voltage buffer

a b s t r a c t In this study, two new lossless grounded inductor simulators (GISs) made up of a single plus-type secondgeneration current conveyor, two inverting voltage buffers and a minimum number of passive components are proposed. There is no requirement of matching conditions and cancellation constraints among passive elements of the proposed GISs. Nevertheless, both of the proposed GISs have a floating capacitor which can be easily realized in nowadays integrated circuit fabrication. A second-order voltage-mode band-pass filter application is given for the proposed lossless GISs. A number of simulations based on SPICE program are given so as to verify the theory. Ó 2017 Elsevier GmbH. All rights reserved.

1. Introduction Physical spiral inductors have been widely used for a number of years. Nevertheless, they are usually unwanted components in integrated circuits (ICs) because of the fact that they have magnetic properties, low quality factors, small and non-tunable inductor values, low self-resonance frequencies and the requirements of large silicon areas. Thus, simulated inductors [1–46] have been employed instead of physical spiral inductors in IC technology. In the open literature, a number of floating inductor simulators [1–23,45,46] and grounded inductor simulators (GISs) [24–46] based on different active elements have been presented. However, previously presented GISs [24,27–33] employ two or three number of second-generation current conveyors (CCIIs). Some GISs are composed of inverting and non-inverting type CCIIs [24,27]. Some of the GISs consist of four or more passive elements [25,26,28,30,31,33,34]. Several GISs are made up of a complex internal structure [31,33,35,40,41,45]. Some of them require passive components matching conditions [25,26,30,31,33,35–38,45]. Several GISs [39,41,42] are lossy. Some GISs [43,44,46] use operational transconductance amplifier (OTA) in their internal structure; thus, their high frequency operation is limited [47]. Apart from these, Yuce and Minaei proposed a GIS employing three currentfeedback operational amplifiers (CFOAs) and four passive components [34]. The GIS reported by Soliman uses a single plus-type

⇑ Corresponding author. E-mail addresses: [email protected] (A. Yesil), [email protected] (E. Yuce), [email protected] (S. Minaei). http://dx.doi.org/10.1016/j.aeue.2017.08.026 1434-8411/Ó 2017 Elsevier GmbH. All rights reserved.

CCII (CCII+) and five passive elements [25]. Also, it needs two critical passive element matching conditions and cancellation constraints. The main features of the presented grounded inductor simulators in [24–46] and the proposed ones are summarized in Table 1. In this paper, we propose two new lossless GISs employing a single CCII+, two inverting voltage buffers (IVBs), two resistors and a capacitor. Both of the proposed GISs do not require any critical passive component matching conditions and cancellation constraints. The IVB can be easily constructed by using only two MOS transistors operated in the saturation region. A self-biasing MOS transistor based CCII+ with very low parasitic resistor at X terminal is selected to increase low frequency performance of the second proposed GIS. Hence, the second proposed GIS can be operated roughly between 200 Hz and 10 MHz. A voltage-mode (VM) band-pass (BP) filter given as an application of the proposed lossless GISs can be operated in a wide frequency range. Thanks to self-biasing technique on the CCII+, any biasing voltages and/or biasing currents except two DC symmetrical supply voltages are not used. Implementation of the lossless GISs is composed of twenty MOS transistors. This work is organized as follows: After the introduction is given in Section 1, both of the proposed GISs are treated in Section 2. After parasitic resistor effects on the performance of both of the lossless GISs are investigated in Section 3, an application example such as second-order VM BP filter is given in Section 4. After a number of simulations are achieved in Section 5, this study is concluded in Section 6.

132

A. Yesil et al. / Int. J. Electron. Commun. (AEÜ) 83 (2018) 131–137

Table 1 Comparison of the previously presented grounded inductance simulators [24–46] and the proposed ones. a,b

References

# of active elements

# of floating/grounded passive elements

# of transistors

Area

[24] [25] [26] [27] [28] [29] [30] in Fig. 1 [31] in Fig. 4 [32] in Fig. 1 [33] in Fig. 7 [34] [35] in Fig. 2b [36] in Fig. 3b [37] in Fig. 2a [38] [39] [40] [41] [42] [43] in Fig. 2a [44] [45] in Fig. 5 [46] The first GIS The second GIS

1 1 1 1 3 3 2 3 2 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0/3 3/2 4/2 0/3 0/4 0/3 1/3 1/3 0/3 1/3 1/3 2/1 1/2 2/1 1/2 2/1 0/1 2/0 3/0 0/2 2/0 1/2 1/1 2/1 2/1

NA NA NA AD844 AD844 AD844 AD844 30 NA 30 AD844 48c 29c 28 27 (BJT) AD844 31 14 20 22 2 OPA860 18 22 20 20

NA NA NA NA NA NA NA 191.1 mm2 NA 219 mm2 NA 276.6 mm2 155.8 mm2 142.2 mm2 NA NA 563 mm2 2075 mm2 NA 132.3 mm2 NA 267.3 mm2 144.5 mm2 155.2 mm2 155.2 mm2

CCII-, 1 CCII+ CCII+ CCII+ CCII-, 1 CCII+ CCII+ CCII+ CCII+ CCII+ CCII+ CCII+ CFOA DXCCII DXCCII DXCCII DCCII CDBA ZC-CCCITA OTRA OTRA VDCC VDBA MDO-DDCC VD-DIBA CCII+, 2 IVF CCII+, 2 IVF

Matching condition

Operating frequency ranges

Biasing voltage/ current source

Electronic Tunability

No Yes Yes No No No Yes Yes No Yes No Yes Yes Yes Yes No No No No No No Yes No No No

NA NA NA NA NA NA NA 30 kHz to 200 MHz NA 1 Hz to3 MHz NA NA 30 kHz to 30 MHz 100 Hz to 10 MHz NA NA 14 kHz to 21 MHz NA NA 30 kHz to 20 MHz 10 kHz to 10 MHz 5 kHz to 700 kHz NA 200 kHz to 20 MHz 200 Hz to 10 MHz

NA NA NA No No No No Yes NA Yes No Yes Yes Yes Yes No Yes Yes Yes Yes No Yes Yes No No

No No No No No No No No No No No No No No No No Yes No No Yes Yes No Yes No No

NA: not available. a Sum of products of the lengths and widths of each transistor in the CMOS structures. b Ideal current source assumed. c Z terminals must be copied according to the CMOS realization.

2. The proposed grounded inductor simulators Electrical symbols of the CCII+ and IVB are respectively shown in Figs. 1and 2. The CCII+ and IVB are respectively described by the following matrix equations:

2

3 2 b RX Vx 6 7 6 4 Iy 5 ¼ 4 0 0 0 a Izþ 

Vx Iy



 ¼

c RB 0 0

32

3 Vy 76 7 54 I x 5 1=RZþ V zþ 0 0



Vy Ix

ð1aÞ

 ð1bÞ

where b and c are non-ideal voltage gains of the CCII+ and IVB, respectively. Further, a is a current gain of the CCII+. Non-ideal voltage gains can be defined as b = 1 + eb and c = 1 + ec in which voltage tracking errors are identified as |eb|  1 and |ec|  1. In a similar way, the non-ideal current gain can be defined as a = 1 + ea where current tracking error is defined as |ea|  1. b, a and c are ideally

equal to unity and their signs are positive. RX and RB in series are respectively X terminal parasitic resistors of the CCII+ and IVB, which are ideally equal to zero. Also, RZ+ in parallel is the Z+ terminal parasitic resistor, which is ideally equal to infinity. The first proposed lossless GIS consists of two IVBs and one CCII + as active components and two resistors and a single capacitor as passive elements. Further, the electrical equivalent circuit of the proposed lossless GIS in Fig. 3 is given in Fig. 4 where Leq = CR1R2. The input impedance of the first proposed lossless GIS in Fig. 3 is ideally obtained by using the port relation of active elements as in the following:

Z in ¼

V in ¼ sCR1 R2 Iin

Fig. 1. Electrical symbol of the CCII+.

Fig. 2. Electrical symbol of the IVF.

Fig. 3. The first proposed lossless grounded inductor simulator.

ð2Þ

A. Yesil et al. / Int. J. Electron. Commun. (AEÜ) 83 (2018) 131–137

133

Fig. 4. The electrical equivalent circuit of the proposed lossless GIS in Fig. 3.

Considering only non-ideal gains of the IVB and CCII+, input admittance of the first proposed lossless GIS in Fig. 3 is computed as

abc2

1  c1 c2 1 1 Y in ¼ þ ¼ þ sLeq Req sCR1 R2 R1

ð3Þ

It is seen from Eq. (3) that input impedance of the first proposed GIS behaves like a parallel connected resistor and an ideal inductor. Also, Leq = CR1R2/abc2 and Req = R1/(1  c1c2). The inductance value of the proposed GIS changes slightly due to non-ideal gains but the value of the parallel resistor determined by non-ideal voltage gains of the IVB varies considerably. Note that the value of Req is negative with the condition 1  c1c2 < 0. The designer should pay attention by selecting the values of c in MOS transistor based realization of the IVBs. Otherwise, the first proposed lossless GIS may have stability problem [30]. On the other hand, the value of R1 can be selected high in order to decrease the non-ideal gain effects on the first proposed lossless GIS. The second proposed lossless GIS is shown in Fig. 5. It includes two IVBs and one CCII+ as active components and two resistors and a single capacitor as passive elements. The input impedance of the second proposed lossless GIS in Fig. 5 is the same as given in Eq. (2). Moreover, the second proposed lossless GIS has the same equivalent circuit which the first one does. Considering only non-ideal gains of the IVB and CCII+, input admittance of the second proposed lossless GIS in Fig. 5 is found as

Y in ¼

1 1  bc1 c2 1 1 þ ¼ þ sCR1 R2 abc2 sLeq Req R1 abc2

ð4Þ

It is observed from Eq. (4) that the second proposed GIS behaves like a parallel connected resistor and an ideal inductor. Further,

Fig. 6. Inverting voltage buffer employing only two NMOS transistors.

Leq = abc2CR1R2 and Req = abc2R1/(1  bc1c2). The inductance value of the second proposed lossless GIS changes slightly due to nonideal gains but the value of the parallel resistor determined by non-ideal voltage gains of the CCII+ and IVB varies considerably. Note that the value of Req is negative with the condition1  bc1c2 < 0. The designer should pay attention by selecting the values of b and c in MOS transistor based realization of the CCII+ and IVBs. Otherwise, the proposed GIS may have stability problem [30]. Also, the value of R1 can be selected high so as to decrease the non-ideal gain effects on the proposed GIS. Apart from these, IVB can be realized by using two NMOS transistors as given in Fig. 6 [48]. If VSS = VDD, kn1 = kn2 = kn and VTN1 = VTN2 = VTN are chosen, the IVB in Fig. 6 can provide the following output voltage:

V out ¼ V in

ð5Þ

For proper operation of the IVB in Fig. 6, the following constraints must be satisfied:

V SS þ V TN < V in <

V TN 2

ð6Þ

3. Parasitic resistor effects If only parasitic resistors of the active elements are considered, input impedance of the first proposed lossless GIS is obtained as

Z inp1 ¼

sCRT1 RT2 ðRB1 þ RZþ Þ þ RT1 RT2 sCRB1 ðRT2 þ RZþ Þ þ RT2 þ RZþ

ð7Þ

Here, RT1 = R1 + RB2 and RT2 = R2 + RX. If only parasitic resistors of the active components are taken into account, the input impedance of the second proposed lossless GIS is found as follows:

Z inp2 ¼

Fig. 5. The second proposed lossless grounded inductor simulator.

sCðR2 RZþ RT1 þ RT2 RX ðRZþ þ RT1 ÞÞ þ ðRZþ þ RT1 ÞRX sCðRB2 RZþ þ RT2 RT1 Þ þ RZþ þ RT1

ð8Þ

Here, RT1 = R1+RB1 and RT2 = R2+RB2. It is observed that parasitic resistance at Z+ terminal of the CCII+ should be chosen as high as possible to enhance low frequency performance of the first proposed lossless GIS. Also, in order to increase low frequency performance of the second proposed lossless GIS, it is necessary to choose the value of RX as small as possible; thus, MOS transistor based realization of the CCII+ should be selected properly. High frequency performance of both of the proposed lossless GIS is restricted by RZ+ whose effects can be reduced by using cascode current mirrors. Also, to enhance high frequency performance of both of the proposed lossless GIS, it is necessary to select small parasitic resistor value for the IVB, which can be achieved by choosing large MOS transistors. On the other hand, the effects of parasitic capacitors of the CCII+ and IVB are ignored for simplicity. It is important to note that frequency dependent non-ideal gains also affect high frequency performance of both of the pro-

134

A. Yesil et al. / Int. J. Electron. Commun. (AEÜ) 83 (2018) 131–137

posed GISs. The methods given in [49] can be used for the proposed lossless GISs to improve their low and high frequency performances. 4. Application example As an application example for the proposed lossless GISs, a VM BP filter in Fig. 7 is given. Transfer function of the VM BP filter in Fig. 7 is computed as

HðsÞ ¼

1 s RC V BP ¼ 2 1 V in s þ s RC þ Leq1 C

ð9Þ

Here, angular resonance frequency (xo) and quality factor (Q) are respectively found as

1 Leq C

xo ¼ pffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffi C Q ¼R Leq

ð10Þ

ð11Þ

5. Simulation results Both of the proposed GISs as well as their band-pass filter application are simulated by LTSPICE using TSMC 0.18 mm process model parameters [50]. To enhance the performance of the proposed GIS, a self-biasing CCII+ with a very small parasitic resistor at the X terminal [51] is preferred as given in Fig. 8. Also, IVB in Fig. 6 with (W/L)2 = (W/L)1 = 15 mm/0.36 mm is chosen. Neither bias voltage nor bias current except two supply voltagesVDD = VSS = 1.25 V is used. Aspect ratios of the MOS transistors of the CCII+ in Fig. 8 are given in Table 2. All the bulks of the MOS transistors are connected to related sources to prevent body effect. Parasitic resistors of the CCII+ and IVB are obtained as: RX = 0.2 O in series at X terminal, RZ+ = 30 kO in parallel at Z+ terminal and RB = 204 O in series at the output terminal. b and a of the CCII+ are found to be 0.97 and 0.99 in SPICE simulations, respectively. Further, c of the IVB is evaluated as 0.96. Magnitudes of impedances of the proposed lossless GISs with respect to frequency are given in Fig. 9. Passive elements values in both of the proposed GISs are selected as C = 25 pF and R1 = R2 = 2.5 kO resulting in Leq ffi 156 mH. However, measured values of the first and second proposed lossless GISs are respectively found as Leq = 174 mH and Leq = 142 mH according to simulation results. It is clearly seen from Fig. 9 that the first proposed lossless GISs can be operated roughly between 200 kHz and 20 MHz. Also, the second one can be operated roughly between 200 Hz and 10 MHz. In other words, the first and second proposed lossless GISs can be operated properly through two and four decades, respectively. Regarding passive element mismatching and DC power supply voltage variations, the sensitivity of frequency response of the impedance of the proposed lossless GISs is evaluated by using

Fig. 7. Passive component realization of the voltage-mode band-pass filter.

Fig. 8. MOS transistor based implementation of the CCII+ [51].

Table 2 Aspect ratios of the CCII+ in Fig. 8. MOS transistors

W (mm)

L (mm)

M1, M2, M3 M4, M5 M6, M7 M8, M9 M10, M11 M12, M13, M14 M15 M16

9 45 10 30 15 3 30 120

0.36 0.36 0.36 0.36 0.36 0.36 0.18 0.18

Fig. 9. Ideal and simulated magnitudes of the impedances of the first and second proposed lossless GISs with respect to frequency.

Monte Carlo (MC) analysis, which is performed by one hundred times. Simulation results of MC analysis for 5% Gaussian distribution change in all the passive element values and supply voltages are also obtained. Changes of the values of the first and second proposed lossless GISs reveal standard deviations of 2% and 2.1% at 1 MHz as given in Figs. 10 and 11, respectively. It is clearly observed from Figs. 12 and 13 that the deviation of the passive ele-

A. Yesil et al. / Int. J. Electron. Commun. (AEÜ) 83 (2018) 131–137

135

Fig. 13. Frequency domain Monte Carlo simulation results for the second proposed lossless grounded inductor simulator.

Fig. 10. Monte Carlo simulation results for the first proposed lossless grounded inductor simulator.

Fig. 14. Ideal and simulated frequency responses of voltage-mode band-pass filters.

Fig. 11. Monte Carlo simulation results for the second proposed lossless grounded inductor simulator.

Fig. 12. Frequency domain Monte Carlo simulation results for the first proposed lossless grounded inductor simulator.

Fig. 15. Dependence of IM3 of voltage-mode band-pass filter on input voltage amplitude.

136

A. Yesil et al. / Int. J. Electron. Commun. (AEÜ) 83 (2018) 131–137

as telecommunication, signal processing, control engineering, instrumentation and measurement. References

Fig. 16. The spectrum of the voltage-mode band-pass filter in given Fig. 7 with two input tones.

ment mismatching and power supply voltage variations influence performances of the low frequency performance of both of the proposed lossless GISs. All the passive elements are chosen as C = 40 pF, R = 2 kO and Leq = 156 mH which yield a center frequency of 2 MHz. To observe the performance of both of the proposed lossless GISs in Figs. 3 and 5, VM BP filter shown in Fig. 7 is used. Gain characteristics of the VM BP filter are shown in Fig. 14. Gain responses of the BP filters against frequency are in good agreement with ideal filter one. The linear performance of the VM BP filter given in Fig. 7 by using the proposed inductance simulator of Fig. 5 instead of the ideal inductor has been investigated by performing a two-tone test where intermodulation distortion is obtained. To survey dependence of 3rd order intermodulation distortion (IM3) of the VM filter on input voltage, two closely spaced tones, 2 MHz and 2.01 MHz, have been applied to the input terminal of the VM BP filter, simultaneously. Fig. 15 depicts IM3 changing over input voltage. Considering 1% (40 dB) level of IM3 in Fig. 15, the obtained spectrum plot by applied 185 mV (peak) to the input terminal is shown in Fig. 16 and correspond to an input power (PIN) of 4.66 dBm (referred to 50 O). Therefore, 3rd order input intercept point (IIP3) is 15.34 dBm, where IIP3 can be calculated by the formula IIP3 = PIN + IM3/2 [52,53]. 6. Conclusion In this paper, two new lossless GISs employing a minimum number of passive components are proposed. Also, the proposed lossless GISs are composed of two IVBs in addition to one CCII+ as active components. There is no requirement of matching conditions and cancellation constraints among passive elements of the proposed GISs. Nevertheless, both of the proposed GISs use a floating capacitor. We prefer to use self-biasing MOS transistor based CCII+ with very low parasitic resistance at X terminal. The MOS transistor based realizations of both of the proposed GISs use no additional bias voltages or bias currents except DC power supply voltages. Furthermore, on account of having very low parasitic resistor at X terminal, the second proposed GIS can be operated properly throughout four decades. Ideal and simulation results verify the claimed theory well as expected. Nonetheless, the slight difference between them arises from frequency dependent nonideal gains and parasitic impedances. It is expected that both of the proposed GISs will be beneficial in a number of areas such

[1] Pal K. Novel floating inductance using current conveyors. Electron Lett 1981;17:638. [2] Li Y. A series of new circuits based on CFTAs. AEU – Int J Electron Commun 2012;66:587–92. http://dx.doi.org/10.1016/j.aeue.2011.11.011. [3] Kiranon W, Pawarangkoon P. Floating inductance simulation based on current conveyors. Electron Lett 1997;33:1748. [4] Yuce E. Floating inductance, FDNR and capacitance simulation circuit employing only grounded passive elements. Int J Electron 2006;93:679–88. [5] Psychalinos C, Pal K, Vlassis S. A floating generalized impedance converter with current feedback operational amplifiers. AEU – Int J Electron Commun 2008;62:81–5. http://dx.doi.org/10.1016/j.aeue.2007.03.002. [6] Yuce E. On the realization of the floating simulators using only grounded passive components. Analog Integr Circ Signal Process 2006;49:161–6. [7] Li Y. NAM expansion method for systematic synthesis of OTA-based floating gyrators. AEU – Int J Electron Commun 2013;67:289–94. http://dx.doi.org/ 10.1016/j.aeue.2012.08.012. [8] Yuce E, Cicekoglu O, Minaei S. CCII-based grounded to floating immittance converter and a floating inductance simulator. Analog Integr Circ Signal Process 2006;46:287–91. [9] Jaikla W, Siripruchyanan M. Floating positive and negative inductance simulators based on OTAs. In: International symposium on communications and information technologies. p. 344–7. [10] Minaei S, Yuce E. Realization of tunable active floating inductance simulators. Int J Electron 2008;95:27–37. [11] Sagbas M, Ayten UE, Sedef H, Koksal M. Electronically tunable floating inductance simulator. AEU – Int J Electron Commun 2009;63:423–7. [12] Koomgaew C, Petchmaneelumka W, Riewruja V. ‘‘OTA-based floating inductance simulator”, in ICCAS-SICE, 2009. ICCAS-SICE, 2009, Fukuoka, vol. 1. p. 857–60. [13] Prasad D, Bhaskar DR, Singh AK. New grounded and floating simulated inductance circuits using current differencing transconductance amplifiers. Radioengineering 2010;19:194–8. [14] Yuce E. On the implementation of the floating simulators employing a single active device. AEU – Int J Electron Commun 2007;61:453–8. http://dx.doi.org/ 10.1016/j.aeue.2006.08.001. [15] Lahiri A. DO-CCII based generalised impedance convertor simulates floating inductance, capacitance multiplier and FDNR. Aust J Electr Electron Eng 2010;7:15–20. [16] Prasad D, Bhaskar DR, Pushkar KL. Realization of new electronically controllable grounded and floating simulated inductance circuits using voltage differencing differential input buffered amplifiers. Act Passiv Electron Compon 2011;2011:1–8. [17] Sagbas M. Component reduced floating ±L, ±C and ±R simulators with grounded passive components. AEU – Int J Electron Commun 2011;65:794–8. http://dx.doi.org/10.1016/j.aeue.2011.01.006. [18] Manhas PS, Pal K. A low voltage active circuit for realizing floating inductance, capacitance, frequency dependent negative resistances and admittance converter. Arab J Sci Eng 2011;36(7):1313–9. [19] Ayten UE, Sagbas M, Herencsar N, Koton J. Novel floating FDNR, inductor and capacitor simulator using CBTA. In: 2011 34th international conference on telecommunications and signal processing (TSP); 2011. p. 312–6. [20] Bhaskar DR, Senani R. Simulation of a floating inductance: a new two-CFOAbased configuration. In: in 2013 fifth international conference on computational intelligence, modelling and simulation; 2013. p. 381–3. [21] Channumsin O, Pimpol J, Thongsopa C, Tangsrirat W. VDBA-based floating inductance simulator with a grounded capacitor. In: 2015 7th international conference on information technology and electrical engineering (ICITEE), no. 1; 2015. p. 114–7. [22] Yuce E, Cicekoglu O, Minaei S. Novel floating inductance and FDNR simulator employing CCII+s. J Circ Syst Comp 2006;15:75–81. [23] Metin B, Cicekoglu O. A novel floating lossy inductance realization topology with NICs using current conveyors. IEEE Trans Circ Syst II Express Briefs 2006;53:483–6. http://dx.doi.org/10.1109/TCSII.2006.873826. [24] Sedra A, Smith K. A second-generation current conveyor and its applications. IEEE Trans Circ Theory 1970;17:132–4. [25] Soliman AM. New active-gyrator circuit using a single current conveyor. Proc IEEE 1978;66:1580–1. [26] Chang C-M, Wang H-Y, Chien C-C. Realization of series impedance functions using one CCII+. Int J Electron 1994;76:83–5. [27] Cicekoglu O. New current conveyor based active-gyrator implementation. Microelectronics J 1998;29:525–8. [28] Cicekoglu MO. Active simulation of grounded inductors with CCII+s and grounded passive elements. Int J Electron 1998;85:455–62. [29] Cicekoglu O, Toker A, Kuntman H. Universal immittance function simulators using current conveyors. Comput Electr Eng 2001;27:227–38. [30] Yuce E, Cicekoglu O. The effects of non-idealities and current limitations on the simulated inductances employing current conveyors. Analog Integr Circ Signal Process 2006;46:103–10. [31] Yuce E. Grounded inductor simulators with improved low-frequency performances. IEEE Trans Instrum Meas 2008;57:1079–84.

A. Yesil et al. / Int. J. Electron. Commun. (AEÜ) 83 (2018) 131–137 [32] Ferri G, Guerrini NC, Romanato R, Scotti G, Trifiletti A. CCII-based high-valued inductance simulators with minimum number of active elements. In: Eur. conf. circuit theory des. 2007, ECCTD; 2008. p. 440–3. [33] Alpaslan H, Yuce E. Bandwidth expansion methods of inductance simulator circuits and voltage-mode biquads. J Circ Syst Comput 2011;20:557–72. [34] Yuce E, Minaei S. On the realization of simulated inductors with reduced parasitic impedance effects. Circ Syst Signal Process 2009;28:451–65. [35] Kacar F, Yesil A. Novel grounded parallel inductance simulators realization using a minimum number of active and passive components. Microelectronics J 2010;41:632–8. [36] Myderrizi I, Minaei S, Yuce E. DXCCII-based grounded inductance simulators and filter applications. Microelectronics J 2011;42:1074–81. [37] Metin B. Supplementary inductance simulator topologies employing single DXCCII. Radioengineering 2011;20:614–8. [38] Metin B. Canonical inductor simulators with grounded capacitors using DCCII. Int J Electron 2012;99:1027–35. http://dx.doi.org/10.1080/ 00207217.2011.639274. [39] Pathak JK, Singh AK, Senani R. New canonic lossy inductor using a single CDBA and its application. Int J Electron 2016;103:1–13. http://dx.doi.org/10.1080/ 00207217.2015.1020884. [40] Herencsar N, Lahiri A, Koton J, Vrba K, Metin B. Realization of resistorless lossless positive and negative grounded inductor simulators using single ZCCCCITA. Radioengineering 2012;21:264–72. [41] Senani R, Singh AK, Gupta A, Bhaskar DR. Simple simulated inductor, low-pass/ band-pass filter and sinusoidal oscillator using OTRA. Circ Syst 2016;7:83–99. http://dx.doi.org/10.4236/cs.2016.73009. [42] Cam U, Kacar F, Cicekoglu O, Kuntman H, Kuntman A. Novel grounded parallel immittance simulator topologies employing single OTRA. AEU – Int J Electron Commun 2003;57:287–90. http://dx.doi.org/10.1078/1434-8411-54100173.

137

[43] Kacar F, Yesil A, Minaei S, Kuntman H. Positive/negative lossy/lossless grounded inductance simulators employing single VDCC and only two passive elements. AEU – Int J Electron Commun 2014;68:73–8. [44] Yesil A, Kacar F, Gurkan K. Lossless grounded inductance simulator employing single VDBA and its experimental band-pass filter application. AEÜ – Int J Electron Commun 2014;68:143–50. [45] Ibrahim MA, Minaei S, Yuce E. Lossy/lossless floating/grounded inductance simulation using one DDCC. Radioengineering 2012;21:3–10. [46] Bhaskar DR, Prasad D, Pushkar KL. Electronically-controllable groundedcapacitor-based grounded and floating inductance simulated circuits using VD-DIBAs. Circ Syst 2013;4:422–30. [47] Fabre A, Saaid O, Wiest F, Boucheron C. ‘‘High frequency applications based on a new current controlled conveyor”. IEEE Trans Circ Syst I: Fundam Theor Appl 1996;43:82–91. [48] Minaei S, Yuce E. High input impedance NMOS-based phase shifter with minimum number of passive elements. Circ Syst Signal Process 2012;31:51–60. [49] Minaei S, Yuce E. A simple CMOS-based inductor simulator and frequency performance improvement techniques. AEÜ – Int J Electron Commun 2012;66:884–91. [50] Minaei S, Yuce E. Novel voltage-mode all-pass filter based on using DVCCs. Circ Syst Signal Process 2010;29:391–402. [51] Arslan E, Morgul A. Self-biasing current conveyor for high frequency applications. J Circ Syst Comput 2012;21:1250039. [52] Razavi B. RF microelectronics. 2nd ed. Prentice Hall; 2011. [53] Laoudias C, Psychalinos C. Integrated filters for short range wireless and biomedical applications. Springer Science & Business Media; 2011.