Accepted Manuscript Regular paper Minimum Passive Components Based Lossy and Lossless Inductor Simulators Employing a New Active Block Faseehuddin Mohammad, Jahariah Sampe, Sadia Shireen, Shawal Hamid Md Ali PII: DOI: Reference:
S1434-8411(17)31222-0 http://dx.doi.org/10.1016/j.aeue.2017.08.046 AEUE 52042
To appear in:
International Journal of Electronics and Communications
Received Date: Revised Date: Accepted Date:
18 May 2017 25 August 2017 26 August 2017
Please cite this article as: F. Mohammad, J. Sampe, S. Shireen, S. Hamid Md Ali, Minimum Passive Components Based Lossy and Lossless Inductor Simulators Employing a New Active Block, International Journal of Electronics and Communications (2017), doi: http://dx.doi.org/10.1016/j.aeue.2017.08.046
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Title: Minimum Passive Components Based Lossy and Lossless Inductor Simulators Employing a New Active Block Faseehuddin Mohammad (M.Tech)a, Jahariah Sampe (PhD)b, Sadia Shireen (M.Tech)cI, Shawal Hamid Md Ali (PhD)d a
Institute of Microengineering and Nanoelectronics (IMEN), University Kebangsaan
Malaysia (UKM), Level 4 MINES Lab UKM 43600 Bangi, Selangor, Malaysia. Email :
[email protected]. b
Institute of Microengineering and Nanoelectronics (IMEN), University Kebangsaan
Malaysia (UKM), Level 4 MINES Lab UKM 43600 Bangi, Selangor, Malaysia. Email :
[email protected]. c
Institute of Microengineering and Nanoelectronics (IMEN), University Kebangsaan
Malaysia (UKM), Level 4 MINES Lab UKM 43600 Bangi, Selangor, Malaysia. Email:
[email protected] d
Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan
Malaysia (UKM), Faculty of Engineering & Built Environment, UKM, 43600 Bangi, Selangor, Malaysia. Email:
[email protected]. Corresponding Author: Mohammad Faseehuddin I
Department of Electronics and Communication, Indus Institute of Technology and Management, Bilhaur
Kanpur, India. Pin Code : 209202. (Permanent address of Sadia Shireen)
Abstract In this paper a new active element namely Dual X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing eight topologies of lossy and lossless grounded inductor simulators and two topologies of floating inductor simulators. All the designed grounded simulators require only two passive elements and a single active block. The two floating inductor simulators require a single active block and one or three grounded passive elements. In addition, all the designs make use of only grounded capacitors for implementation which is advantageous for fabrication. All the proposed active inductors, except two, did not require any component matching conditions for realization and all the inductor simulators are perfectly tunable. The effect of non-idealities on the proposed grounded simulator structures is also studied. To demonstrate the workability of the inductor simulators they are used in design of second order low pass filter, parallel RLC resonance circuit, third order Butterworth high pass filter, parallel RLC current mode multifunction filter and a voltage mode band pass filter. The DXCCDITA is implemented in 0.35µm TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient number of simulations are provided to establish the functionality of the active inductor structures. Keywords: Active inductor, Current conveyor, Current mode, Operational transconductance amplifier, Tunability 1. INTRODUCTION Inductor is an indispensable component in analog circuits. The tuned circuits designed using inductors, capacitors and resistors are used in communication systems for filtering applications. The inductor finds applications in LC oscillators, for parasitic cancellation,
impedance matching and phase shifters etc. [1-3]. The major limitation curtailing the use of the passive spiral inductors is their bulky nature. Moreover, the current fabrication technology supports monolithic inductors of around 1nH and limited quality factors [2]. Furthermore, inductors consume most of the chip area and also suffer from process variability’s and resistive losses [1]. Last few decades have seen the increased use of Current mode active elements in analog design and impedance simulation [4-7]. The most utilized current mode active blocks in inductance simulation are the second generation current conveyor (CCII) [6], third generation current conveyor (CCIII) [7], current feedback operational amplifier (CFOA) [8], current differencing buffered amplifier (CDBA) [9], differential current conveyor (DCCII) [10], differential voltage current conveyor (DVCCII) [13], dual x current conveyor (DXCCII) [14] etc. The inductor simulators can be categorized based on number of active blocks used, number of passive elements employed and whether they emulate lossy or loss less inductance. The simulators presented in [11, 12, 17, 19] use more than one active elements and excessive passive elements. The circuits in [8, 9, 10, 14, 15, 16, 18, 20, 21, 22, 23, 24, 25, 26, 27, 29] require a single active block and three or more passive elements for implementation. The work described in [8, 9, 10, 12, 14, 15, 16, 18, 20, 21, 22, 23, 26, 27, 28, 29, 30] require one or more floating passive elements for implementing inductance. The simulator circuits in [10, 12, 14, 16, 18, 20, 22, 23, 26, 29] requires components matching for inductance realization. The design in [25] utilized a grounded capacitor and a floating resistor implemented using MOS transistor to realize lossy inductor simulators. In comparison to [25] the proposed DXCCDITA based inductor simulators can realize both pure and lossy inductance while requiring a grounded capacitor and a single resistor. In addition, if resistors in the proposed inductor simulators are realized using MOS transistors they become resistorless implementation employing only single passive element similar to [25] with options for realizing both grounded and floating
inductance which is an advantage. A comparison of some exemplary grounded inductor simulators with the proposed inductor simulators is given in Table 1. The literature survey points out that most of the designs suffer from one or more of the following limitations. (i) the use of excessive active and passive elements (ii) use of floating capacitors (iii) no provision for on chip tunability (iv) requirement of components matching condition. In this research eight simulator topologies for simulating lossy and lossless grounded inductance are presented. The proposed circuits employ only two passive elements with capacitor grounded in each design. The simulators are developed based on a new active block Dual X current conveyor differential input transconductance amplifier (DXCCDITA). All the designed simulators, except one, enjoy tunability and require no passive elements matching condition. Additionally, to emphasize the versatility of DXCCDITA two perfectively tunable structures of floating inductor simulators are also developed. To establish the performance of the designed active inductors they are used in designing a second order low pass filter, parallel RLC resonant circuit, third order Butterworth high pass filter, parallel RLC current mode multifunction filter and a voltage mode band pass filter. Simulations are performed using TSMC 0.35μm parameters to prove theoretical analysis. Table 1: Comparison of grounded inductor simulators with the proposed simulators using DXCCDITA Reference
Active Element
No. of Active Devices Used
[1] [8] [9] [10] [11] [12] [14] [15] [16] [17] [18] [20] [21] [23]
MDO-DDCC CFOA CDBA DCCII CDTA OTRA DXCCII PFTN CCI CCII CCII GVCCIII CFOA DXCCII
1 1 1 1 2 2 1 1 1 3 1 1 1 1
No. of Passive Elements 3 3 3 3 1 5 ¾ 5 5 4 5 3 3 3
Capacitor Floating
Matching Condition
Inbuilt Tunability
No Yes No No No Yes Yes Yes Yes No Yes Yes Yes Yes
Yes No No Yes No Yes Yes Yes Yes No Yes Yes No Yes
No No No No Yes No No No No No No No No No
[24] [25] [26] [27] [28] [29] [30] GIS-1 GIS-(2-8)
MCFOA VDIBA MICCII DCCII VDBA DVCCII LT1228 DXCCDITA DXCCDITA
1 1 1 1 1 1 1 1 1
3 1 3 3 2 3 2 2 or 1** 2 or 1**
No No Yes Yes Yes No Yes No No
No No Yes No No Yes No Yes No
No Yes No No Yes No Yes Yes Yes
* CCII-second generation current conveyor, CCI-first generation current conveyor, CDBA-current differencing buffered amplifier, CDTA-current differencing current conveyor, CFOA-current feedback operational amplifier, DCCII-differential current conveyor, DXCCII- dual X current conveyor, GVCCIII-gain variable third generation current conveyor, LT1228- integrated circuit from linear technology, MCFOA-modified current feedback operational amplifier, MCICCII-modified inverting current conveyor, MDO-DDCCModified dual output differential difference current conveyor, OTRA-operational transresistance amplifier, PFTN- positive four terminal floating nullor, VDIBA-voltage differencing inverting buffered amplifier, VDBA-voltage differencing buffered amplifier
** If passive resistors in the proposed active inductors are realized using MOS transistors then only one passive element (grounded capacitor) will be required.
2. DXCCDITA A NEW ACTIVE BLOCK The proposed Dual X current conveyor differential Input transconductance amplifier (DXCCDITA) is functionally a connection of DXCCII [31] and operational transconductance amplifier (OTA). The new block carries features of inverting current conveyor (ICCII) [32], CCII, and tunable trans-conductor in one single architecture which is also simple to implement and develop in to integrated circuit. The Voltage current characteristics of the developed DXCCDITA are given in matrix Equation 1 and the block diagram is presented in Fig. 1. 0 1
−1 = 0 0 0
0 0
0 0 0 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 −
0 0 0 0 0 0 0 0
0 0 0
0 0 0 0
0
(1)
Figure.1:Block diagram of DXCCDITA
The CMOS implementation of DXCCDITA is presented in Fig. 2. It is a nine terminal active element. The first stage consists of DXCCII, transistors (M1-M20). The voltage at Y appears at and in inverted format at . The current input at node is transferred to nodes . In the same way the current from node is transferred to . If required the and
nodes can be easily added. The Y and Z nodes are high impedance while the XP and XN node are low impedance. The second stage is composed of OTA. The transconductance is realized using transistors (M21-M32). The output current of the transconductor depends on the voltage difference between voltages at terminals and . Assuming saturation region operation for all transistors and equal W/L ratio for transistors M21 and M22 the output current of the OTA is given by Equation 2. = − ! = "#2%&'( )* − ! 2!
Where, the transconductance parameter Ki =µCox W+2L (i=21, 22), W is the effective channel width, L is the effective length of the channel, Cox is the gate oxide capacitance per unit area and μ is the carrier mobility. It is evident from (2) that the transconductance can be tuned by the bias current thus imparting tunability to the structure. The proposed active block appears to be complex with large number of transistors but authors wants to stress that the active block is very versatile as it provides higher degree of freedom to the designers owning to the availability of opposite voltages at the two independent X nodes together with inbuilt tunability. Additionally, the independent and
terminals are connected to the two inputs of OTA giving it a differential input advantage which can be helpful in floating impedance simulation and minimum component filters and oscillators realization. This active block can also simulate many popular active elements as special cases, by connecting to ground the unused nodes, like the current conveyor transconductance amplifier (CCTA), Z-copy current conveyor transconductance amplifier (ZC-CCTA), inverting current conveyor transconductance amplifier (ICCTA), current follower transconductance amplifier (CFTA) and current follower differential input transconductance amplifier (CFDITA) etc. Given the flexibility of DXCCDITA slightly increased transistor count should not be considered a disadvantage. A thorough comparison of the proposed DXCCDITA with other popular active elements in terms of input and output voltage and current signals available at each terminal and also different active elements that can be realized as special is given in Table 2. Table 2: Comparison of the features of the proposed DXCCDITA with other popular active elements Active Element
No. of Independent Voltage input terminals
No. of Independent current input terminals
DXCCDITA (proposed)
One
Two ( & )
CCTA
One
One
CFTA
DXCCII
No voltage input terminal One
CBTA
Availability of opposite voltage at two independent current input terminals simultaneously Yes
No. of Independent current output terminals
Utilization of transconductance stage for tunability
Realization of other active elements as special cases
Two ( & )
Yes
No
One
Yes
One
No
One
Yes
CCTA, ICCTA, CFTA, CFDITA, DXCCII, ICCII, CCII CCII, CFTA -
Two
Yes
Two
No
One
One
No
One
Yes
DVCCII
Two
One
No
One
No
DCCII
One
Two
No
One(provide
No
ICCII, CCII CCII, CCTA, CFTA, CFDITA ICCII, CCII CCII
DDCC
Three
One
No
difference of input current) One
CCCCTA
One
One
No
One
No
Yes
DVCCII, ICCII, CCII CCCII, CFTA
*CBTA- current backward transconductance amplifier, CCCCTA- current controlled current conveyor transconductance amplifier, CCTAcurrent conveyor transconductance amplifier, CFTA- current follower transconductance amplifier, DCCII- differential current conveyor, DDCC- differential difference current conveyor, DVCCII- differential voltage current conveyor, DXCCII- dual X current conveyor
Figure 2. CMOS Implementation of DXCCDITA
3. Proposed Minimum Passive Components based Grounded and Floating Inductor Simulators The proposed Grounded Inductance simulators (GIS) using the newly developed active block the DXCCDITA are presented in Fig. 3(a-h). It is worth mentioning that in all the eight proposed structures only grounded capacitors are employed which are considered ideal for fabrication. Moreover, the use of grounded capacitor is advantageous in mitigating noise and parasitic effects [19]. The first proposed GIS-1 Fig. 3(a) can simulate positive inductance in series with a resistance. The simulator requires a simple matching condition for realization. The GSI-2 Fig. 3(b) simulates a positive inductance in parallel with the resistance. The circuits from GIS-3 Fig. 3(c) to GIS-8 Fig. 3(h) all realize lossless positive inductance.
The authors also like to point out some important attributes of the designed simulators. First, in simulators (GIS-1, GIS-3, GIS-4), for simplicity the resistance R1 is shown connected between X. and X/ , in actual implementation the resistor will be replaced by a MOS transistor working in triode region, as voltage controlled resistor (VCR), making the three simulators a resistorless implementation. Moreover, as was discussed in [31] due to the availability of inverted voltages between and nodes, when a MOS transistor is connected between them the voltage between the source and drain of the triode MOS transistor becomes differential which cancels out the even order non linearities leading to increased linearity in the realized resistance. In addition, these simulators (except GIS-1) will enjoy dual tunability property i.e. they can be tuned either by bias current of OTA or control voltage of the triode region MOSFET. Second, the grounded capacitors connected at the Z terminals of the simulators will absorb the parasitic capacitance 01 this will improve frequency performance and enable realization of high frequency filters and oscillators using the presented active inductors [9]. Third, the grounded resistors at the X node will absorb the parasitic impedance further reducing parasitic effects. Fourth, by interchanging the OTA output terminals (O+ & O-) in (GIS-3 to GIS-8) the negative inductance can also be realized. All the presented GIS except one (GIS-1) are tunable via bias current of the OTA and does not require any matching conditions for realization. The transfer functions along with other features are summarized in Table 3.
(b) GIS-2 (a) GIS-1
(c) GIS-3
(e) GIS-5
(d) GIS-4
(f) GIS-6
(g) GIS-7 (h) GIS-8 Fig. 3: The proposed Lossy and Lossless Grounded Inductor Simulators
Simulator GIS-1
Impedance Realized Leq + Req
GIS-3
1 1 + Leq Req Leq
GIS-4
Leq
GIS-5
Leq
GIS-6
Leq
GIS-7
Leq
GIS-8
Leq
GIS-2
Table 3: Transfer Functions of the Active Inductors Leq Req Type
20 3 2 20 3 20 3 2 20 3 2 20 3 20 3 20 3 20 3
Matching Condition Yes
Tunability
No
Yes
No
Yes
1 2 1 -
L in series with R L in parallel with R Pure L
-
Pure L
No
Yes
-
Pure L
No
Yes
-
Pure L
No
Yes
-
Pure L
No
Yes
-
Pure L
No
Yes
No
To further emphasize the versatility of the proposed DXCCDITA two topologies of floating inductance simulators (FIS) are also developed as shown in Fig. 4. The FIS-1 is a resistorless implementation requiring only a single grounded capacitor while FIS-2 requires two matched grounded resistors and a grounded capacitor for implementation. The analysis of the circuits gives the short-circuit admittance matrix as presented in Equations 3-4. It can be seen that the proposed FIS requires less number of active and passive components compared to [1-3, 11, 13, 33].
(a) FIS-1
(b) FIS-2
Fig. 4: The proposed Lossless Floating Inductor Simulators
< 9: ; = 2 = ? 1 (>= −1
ABC =
2D +2 E
−1 @ 1
(3)
Where E = 1+3 , is the resistance of the voltage controlled resistor. The FIS-1 has dual F
tunability capability. It can be tuned either by bias current of OTA or the control voltage > of the triode MOS transistor. < 9:; = = ? 1 −1@ (>= −1 1
ABC =
(4)
2D + E
Where E = 1+3 (i=1, 2), the resistance of the two grounded resistors. The implementation &
requires a simple resistive matching of (3 = 3 ). 4. Non-Ideal Analysis
In this section the non-idealities of the DXCCDITA are considered and their influence on the proposed inductance simulator circuits is analyzed [28]. A simplified non-ideal model of DXCCDITA is presented in Fig. 5 for analysis. The most important aspects contributing to the deviations in frequency performance are the non-ideal frequency dependent current and voltage transfer gains G , ! 2! and I , ! 2!, where G , ! 2! = G , ! / 1 + 2⁄KL and I , ! 2! = I , ! / 1 + 2⁄KN KN
, !
, ! !.
Ideally, G , ! = I , ! = 1 and KL
, ! !
, !
=
= ∞. Considering only the effect of the non-ideal gains the impedance function of
the active inductor simulators will be modified as presented in Table 4. It can be said that the active inductors must be made to function only in the frequency range where the transfer gains are constant and close to unity. Another important performance parameter is the associated parasitics at the X nodes which can be quantified as = = 3
, !
+ 2A
, ! .
The parasitic resistance
associated with the Z and Y nodes are 3 , 3 and 3 respectively. While the associated
capacitances are 0 , 0 and 0 respectively. There ideal values being equal to zero. The γ represents the transconductance transfer inaccuracy of the OTA, while 3 , 3P and 0 , 0P are parasitics at the OTA output. The modified voltage current relation of DXCCDITA including the parasitic are given in Equation 5. For moderate frequency operation the inductance at the X nodes can be ignored. Taking into account the effect of parasitic elements present in DXCCDITA, the modified impedance relations for the simulators are summarized in Table 5.
Figure 5: Non-Ideal model of DXCCDITA
20 + QR ! I 2! −I 2! 0 = 0 0
0 0
0
0
G 2! G 2!
0
0
0 0
0
G 2!
0
G 2!
0
0
0
0 0
20 + 0
0 0
W
0
QST=
!
0
0 0
0
20 + 0
0
0 0
QSTU
0 !
0
0
0 20 + 0
0 0 0 0 0 0 0 0 0
20
+ Q ! 0 SVU 0 0 0 0
QSV=
−W
!
Table 4: The impedance of the active inductor simulators including effect of non-ideal transfer gains Simulator GIS-1 GIS-2 GIS-3 GIS-4
Impedance Realized 1 G
20 3 3 X + Y − G G I + I ! G I + I ! 1 G I
X + Y G 20 3 20 3 G I + I ! 20 3 G I + I !
Matching Condition G
3 = 2G G I + I ! No No No
(5)
20 3 G G I
GIS-5
No
20 3 G I
GIS-6
No
20 3 G I 20 3 G I
GIS-7 GIS-8
No No
Table 5: The impedance of the active inductor simulators including effect of parasitic impedance Simulator GIS-1
GIS-2
GIS-3
GIS-4 GIS-5
GIS-6 GIS-7
GIS-8
Non Ideal
Assumed Values
20 \ = 20 + 20^ + 20P
Z[ Q= + 201_ 3 3 \ =3^ //3P //31_ // +2 31_ 20 \ = 20 + 201_ + − 20 \ − 3 \ \ 20 \ = 20^ + 20 + 201 3 20 31_ + 1! 3 \ =3^ //3 //31 3 20 \ 31_ + 1! 20 \ = 20 + 201_ \ \ \ \ \ 2 31_ + 20 3 20 31_ + 1! + 3 20 31_ + 1!3 20 = 20^ + 20P \ 3 =3^ //3P \ \ 20 3 + 3 3 ! 20 \ = 20^ + 20P + 20 3 \ =3^ //3P 2 \ 3 20 31_ + 1! 20 \ = 20 + 201_ \ \ \ \ \ \ 3 31_ − 20 3 3 20 31_ + 1! − 3 20 31_ + 1! 20 = 20^ + 20P + 201 \ 3 =3^ //3 //31 20 \ 3 \ + 1! 20 \ = 20^ + 20P + 20 \ 3 \ =3^ //3P 3 3 \ 3 20 31 + 1! 20 \ = 20 + 201 20 \ = 20^ + 20P 31 + 20 \ 3 "20 \ 31 + 1* + 3 "20 \ 31 + 1*3 \ 3 \ =3^ //3P \ 3 20 31_ + 1! 20 \ = 20 + 201_ \ \ \ \ 20 \ = 20^ + 20 31_ + 20 3 20 31_ + 1! + 3 20 31_ + 1!3 3 \ =3^ //3 Q=
[20 \ - +
]]
The frequency performance of the inductor simulators can be further improved by cancelling the parasitic impedances and adopting techniques suggested in [6, 20]. 5. Simulation Results In order to establish the workability of the proposed DXCCDITA, it is designed in 0.35µm parameters from TSMC. The circuit was simulated in Tanner EDA to measure the important design metrics. The aspect ratios of the transistors are given in Table 6. The supply voltages
are kept at `` = −aa = 1.5V. The bias voltage was fixed at d&'( =0.55V. The bias current of OTA was set at 50µA which resulted in a transconductance of = 0.1mS. The proposed active element is characterized using the method stated in [34]. The important performance parameters of DXCCDITA are summarized in Table 7. Table 6: Aspect ratios of the transistors Transistor Width (W µm) Length(L µm) M1- M2 1.4 0.7 M3- M5 2.8 0.7 M6- M7 2.4 0.7 M8- M10 4.8 0.7 M11-M20 9.6 0.7 M21-M32 2 1
Table 7: Performance parameters of the proposed DXCCDITA Voltage Gain ( / ) 0.98 Voltage Gain ( / ) 0.95 Current Gain ( / ) 1.05 Current Gain ( / ) 1.05 DC Voltage transfer range ±400mV DC Current Transfer range ( ) ±60μA DC Current Transfer range ( ) ±60μA Voltage Transfer B.W. ( / ) 632MHz Voltage Transfer B.W. ( / ) 728MHz Current Transfer B.W. ( / ) 932MHz Current Transfer B.W. ( / ) 1.32GHz Parasitic Resistance at node 3 71.1Ω Parasitic Resistance at node 3
38.2 Ω Resistance at node 3
305K Ω Resistance at node 3 305 K Ω Resistance at O node 1.05M Ω
Now the proposed inductor simulators are tested to ascertain their applicability. First, the GIS-1 is simulated. The values of passive elements are selected as C =50pF, R =10kΩ resulting in the inductance of Lhi =2.5mH in series with a resistance R hi =5kΩ for Ibias=50uA. The simulated magnitude and phase curves of the inductor are given in Fig. 6.
Figure 6: The magnitude and Phase of the GIS-1
Next, the GIS-2 is simulated. The parallel R-L simulator circuit is designed by selecting Ibias=50uA, C =50pF, R =1kΩ giving the value of inductance equal to Lhi =500µH in parallel with R hi =10kΩ. The associated magnitude and phase curves are presented in Fig. 7.
Figure 7: The magnitude and Phase of the GIS-2
The pure inductor simulator GIS-4 is examined. The passive components values are selected as C =50pF, R =10kΩ. The inductance was calculated as Lhi = 2.5mH for Ibias=50uA. The obtained gain and phase plots are presented in Fig. 8. Transient analysis is performed to measure the phase difference between current and voltage for GIS-4 as given in Fig. 9. The phase difference is found to be 91.5 degrees. The deviation can be attributed to the non-idealities present in the DXCCDITA. Time domain analysis is also performed by giving a triangular wave as input for obtaining square wave output as given in Fig. 10. To test the tunability of the GIS-4 the inductance is plotted for different values of bias current
ranging from (10μA to 150μA). The resulting magnitude curves are shown in Fig. 11. It can be seen that the simulator is tunable over a wide range of bias currents. The total harmonic distortion of GIS-4 is also measured for different amplitudes of input current. It can be deduced from Fig. 12 that the THD is within acceptable limit. Finally, Monte Carlo analysis for 10% deviation in capacitor value is done for 100 runs to study the effect of process variability on the response of the simulator as presented in Fig. 13. Any deviation in inductance can be nullified by adjusting the bias current.
Figure 8: The magnitude and Phase of the GIS-4
Figure 9: The transient analysis output of the GIS-4
Figure 10: The response of GIS-4 to a triangular wave input
Figure 11: The magnitude plot of the GIS-4 for different bias currents
Figure 12: THD of GIS-4 for different signal amplitudes
Figure 13: Monte Carlo analysis results of GIS-4 for 10% deviation in capacitor value
Finally, to demonstrate the resistor-less inductor implementation the resistor in GIS-4 is replaced by a triode region MOSFET transistor with W=L=1.5µm as shown in Fig. 14. The control voltage of the MOSFET is varied from 0.6V to 1V and the obtained magnitude and phase curves are presented below in Fig. 15. The value of the resistance can be calculated P
using jQ = kl_ 0m n+A > − o_ !p
for different values of control voltage.
Figure 14: Resistor less implementation of GIS-4
Figure 15: Phase and Magnitude of resistorless inductance simulator for different control voltages
To illustrate the practical use of the proposed inductor simulators few application are designed using them. An RLC resonance circuit structure as shown in Fig. 16 is designed using parallel R-L GIS-2. The component values selected are Lhi =1mH, R hi =10kΩ and C =100pF. The GIS-2 passive elements are selected as R =10kΩ C =100pF at Ibias=50μA to get Lhi =1mH. The ideal and simulated plots of the filter are given in Fig. 17 for different values of bias current Ibias=50μA, 100μA, 150μA (different values of Lhi ). The ideal and simulated resonance frequencies are found to be 0.501MHz and 0.498MHz at Ibias=50μA using the relation given below. K =
1
#ArC 0
Figure 16: RLC parallel resonance circuit
Figure 17: The Impedance –frequency plot of parallel R-L circuit for various bias currents
A low pass second order filter is used to verify the functionality of simulator GIS-1. The values of passive elements of the filter are selected as Lhi = 2.5mH,
R hi = 5kΩ and
Cv. = 50pF.The series R and L in the filter structure Fig. 18 are replaced by the series RL
simulator GIS-1. The passive components values of the simulator are set to Ibias=50uA, R = 10kΩ and C = 50pF to achieve Lhi = 2.5mH and R hi = 5kΩ. The ideal and simulated gain plots of the filter are given in Fig. 19 which shows that the inductor functions well. The transient analysis is also performed to test the filter as shown in Fig. 20. The THD plot is also given in Fig. 21 which reveals that the filter can work up to 55μA signal amplitude with acceptable performance. Moreover, the THD can be further reduced by increasing the bias current of the DXCCII part of the DXCCDITA at the expense of the increased power dissipation. K =
1
#ArC 0|
Figure 18: The structure of the current mode low pass filter
Figure 19: The gain plot of the low pass filter
Figure 20: The transient analysis result of the low pass filter
Figure 21: The %THD of the low pass filter for different current amplitudes
The pure inductor GIS-4 is employed to design a Butterworth third order high pass filter as given in Fig. 22. The components values are selected as R = R =10kΩ, C = C = 50pF and L = 2.5mH. The passive elements values of the GIS-4 are set at R = 10kΩ and C = 50pF to realize Lhi = 2.5mH. The ideal and simulated gain plots of the filter are given in Fig. 23 which proves excellent correlation between simulated and ideal values.
Figure 22: The structure of the Butterworth third order high pass filter
Figure 23: The gain plot of the Butterworth third order high pass filter
In another example GIS-4 is used in the design of a current mode parallel RLC filter structure as shown in Fig. 24. The values of the components of the parallel resonant circuit were as follows L=1mH, C=10pF, R=10kΩ which resulted in a pole frequency of 1.59MHz. To achieve ArC =1mH for GIS-4, the values of elements are selected as R =10kΩ and C =20pF. The simulated and ideal low pass (LP), high pass (HP) and band pass (BP) responses are presented in Fig. 25 as can be seen the simulated and ideal plots bear close resemblance.
Figure 24: Parallel RLC current mode filter
Figure 25: Parallel RLC current mode filter circuit responses
To validate the resistorless floating inductor simulator a second order band pass filter is used for the test . The structure of the band pass filter is shown in Fig. 26. The inductor in the structure is replaced by its equivalent active FIS-1 simulator. The component values for FIS-1 are RM = 1/G1 = 92.97kΩ, 0 = 10pF resulting in Leq =4.648mH and pole frequency of 0.233MHz for Ceq =100pF and 3| = 10kΩ at IBias =50u. The ideal and simulated gain and phase response of the filter are given in Figure 27.
=
#| >
Figure 26. The structure of the band pass filter
Figure 27. The gain and Phase of the band pass filter
6. Conclusion
In this research, a new active block Dual X current conveyor differential input transconductance amplifier (DXCCDITA) is presented. The versatility of the new active block is illustrated by designing eight topologies of minimum component grounded inductor simulators and two structures of floating inductor simulators. The designed simulators require only one active element. The presented simulators can realize lossy and lossless inductors. All the proposed inductors employ only grounded capacitors which is beneficial for noise cancellation and fabrication. In four simulator structures namely, GIS-1, GIS-3, GIS-4 and FIS-1 the MOS transistors working in triode region can be used in place of resistors thus making them a resistor-less implementation. The influence of non ideal and parasitic effects on the inductor simulators is also discussed. The designed inductor simulators are also employed in design of second order low pass filter, parallel RLC resonance circuit, third order Butterworth high pass filter, parallel RLC current mode multifunction filter and a band pass filter to further ascertain their applicability and feasibility. Enough number of simulation results are provided to validate the theory. The simulation are performed using the 0.35µm parameters using Tanner EDA. The results are in good agreement with the proposed theoretical analysis. ACKNOWLEDGEMENT The authors gratefully acknowledge the support provided by UKM internal grant [GUP2015-021] and grant from ministry of education [FRGS/2/2014/TK03/UKM/02/1] for this study. REFERENCES 1. Ibrahim MA, Minaei S, Yuce E, Herencsar N, Koton J. Lossy/Lossless Floating/Grounded Inductance Simulation Using One DDCC. Radioengineering 2012;21(1):3-10.
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Authors Biography Mohammad Faseehuddin: He received M. Tech in Electronics Engineering in 2014. He is currently working towards his PhD at Institute of Microengineering and Nanoelectronics, University Kebangsaan Malaysia (UKM). His Research Interests includes current mode circuits, Low voltage circuit design, analog filters and oscillators. Jahariah Sampe: She is Research Fellow / Senior Lecturer at Institute of Microengineering and Nanoelectronics, University Kebangsaan Malaysia (UKM). Her field of research includes Very Large Scale Integration (VLSI) design, Wireless and Data Communication, Energy Harvesting etc. She has authored and co-authored numerous journals of repute and international conferences. Sadia Shireen: She is a Lecturer at Indus Institute of Technology and Management, Kanpur, India. She received M. Tech in Electronics Engineering in 2014. Her research interests include includes current mode circuits, Low voltage circuit design, analog filters and oscillators.
Sawal Hamid Md Ali: He is the Associate Professor in the Department of Electrical, Electronic & Systems Engineering, University Kebangsaan Malaysia (UKM). His field of research includes VLSI design, Energy Harvesting, Digital Electronics etc. He has authored and co-authored numerous journal papers and international conferences.