LAPLACE: Another second generation PLA design tool

North-Holland Microprocessing and Microprogramming 16 (1985) 61-66

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LAPLACE: Another Second Generation PLA Design Tool Alessandro Cagnola, Marco Corti, Giorgio Vignati

SGS Microelettronica, Central R&D Agrate Brianza, Italy In the field of VLSI the extended usage of regular structures is a way to cope with the problem of complexity connected to the increasing circuits size. L A P L A C E is a new interactive program which refine and support the design of a PLA. Callecting information in its data base, it gives a worst case delay time of the PLA which accurately fits the actual one and compile the PLA layout.

Keywords: PLA, layout generation, critical delay extimation.

1

Introduction

LAPLACE is a new tool for supporting a part of the design cycle of CMOS PLAs. Usually, the design cycle of a PLA starts with the translation of equations into a symbolic form, then it continues with logical and, possibly, topologic minimization [2]. At present, LAPLACE supports the last stages of the cycle, i.e. electrical simulation and generation of layout, while the preliminary ones are left to other tools of the same package. The program is completely menu driven and the user interface has been specifically designed never to make the circuit designer feel alone. A variety of tools is nowaday available to generate PLAs layout (TPLA, PLAID, PANDA from UC Berkeley, HpLA from MIT and many others) [3][4]. Some of them are tile-based, some others have a more complex data base which allows a sophisticated approach resulting in a more compact layout, but, as a matter of fact, most of them simply translate a symbolic form into its corresponding layout, disregarding any electrical consideration about the performance of the circuit. After a period of experience with those packages, it was evident that designers would appreciate a tool including also an evaluation of electrical properties of the PLA; this is particularly true when PLAs are part of more complex systems, like microprocessors or microcontrollers, with tight timing constraints: in these cases the automatic generation of a file for electrical simulation is a must! The evolution of PLA tools is in this direction: some of them include now evaluation of the timing behaviour of the PLA. This point may be chosen as a reference point to distinguish among the first generation layout tools and the second generation. Few of second

generation tools have been described in the literature althought some companies use them. The design of a PLA follows some steps and implies some refinement loops as indicated in fig. 1. Interactive design requires a fast simulation, as to allow the user to modify the dimensions of transistors and to check, in the same work session, the new re-

LO61E MINIMIZATION

TOPOLOGIC MINIMIZATION

1

$ TRANSISTORS DIMENSIONING

SATI S/ACTORY

7 LAYOUT GENERATION

FIG, 1

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A. Cagnolaet aL / LAPLACE

sponse time of the PLA. We want to point out that this kind of problem is neither a simple circuit extraction from the layout nor a parallel description of the same objetc on two planes. In fact both these approaches lead to the simulation of the whole PLA, irreparably slowing the program down. When dealing with PLAs the problem of extimating its timing behaviour is twofold: on one side the program should identify the slowest path through the PLA and simulate only this path; on the other side, once this path has been identified, it should be simulated with the most accurate model. We are now briefly discussing three topics: in section 2 problems related to critical path search and its algorithm are presented, in section 3 is presented the model used to extract a subnetwork of the PLA to be simulated and, eventually, in section 4 we shall discuss the layout generation.

PRODUCT TERM

2

Critical p a t h search

Initially, the program preprocesses the symbolic form of the PLA, collecting the information contelned in the personality matrix in a data base together with other information such as the current dimensions of all transistors, the architecture used for PLA implementation and the process used. The algorithm works on the symbolic representation of the PLA; this reduces the computing time since it does not require generation of layout. In general, a computation is performed, based both on the resistive coefficients of wires and on capacitive effects of wires and transistors, to sort all paths of the PLA according to their extimated propagation delay. Let us define a path as a triple (i,p,o) where i is an input column, p is a product term and o is an output colum (fig 2). For a path to exist there must be two transistors respectively at the intersection of i and p and of p and o: the name of these transistors is pivot transistors. The electrical characterization of a path is expressed by four RC constants, each one related to a

P

.......

o

....

i---I--

P P

i ............. I-I ...........

1 . . . . . . . . .

~~~I ~~I

~

I ~~~ ~~~I

I I ! Fig.

FIG,

2

SCHEMATIC OF THE CRITICAL PATH

3

A PLA c r i t i c a l

path

part of the path, specifically the polysillcon input line, the product term, the output llne and the external capacitances. The program scans the personality matrix and for each existing path it computes the values of the RC constants; the evaluation of the timing of a path is then performed considering both a trailing edge and a falling edge applied to the input buffer, thus obtaining two figures for each path. All paths are eventually sorted by the extimated delay and this llst is led by the slowest path, also named c r l t i c a l p a t h . Fig. 3 shows the critical path of a generic PLA. Each path may be simulated independentely but the simulation of the slowest path gives a precise extimation of the delay time of the whole PLA as a black box.

A. Cagnola et al. / LAPLACE

3

Simulation

As a second step the program accurately describes the slowest path [5][6][7][8]. This is the most critical step: while it is fairly easy to identify the slowest path in the PLA, the quality of the simulation results, and their credibility, depend on how accurate the description of the circuit is. Experience teaches that some effects are easily neglected during the construction of the network to be simulated mostly when the description is hand drafted by designers: it's a common opinion among designers that the simulated time should be doubled in order to get a reliable extlmatlon of the circuit timing, but if the description is automatically compiled by a program, considering the double of elements a designer would consider, then we could get a very precise results. We have tuned a model to give a realistic description of the slowest path, ready to be simulated by SPICE. The program describes the whole path, from input buffer to output inverter, as a sequence of elements, describing very precisely each effect encountered through tha path. Globally the network used to simulate the critical path is composed of ten transistors and many resistences and capacitances as in fig. 4. In a path some parts depend on the particular PLA per-

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sonality and others do not depend on them, as for input buffers, output inverters and pullups: these subcircults have been characterized once and forever as their SPICE description is concerned, while the remaining part has to be computed each time. Each gate belonging to the input column and to the output column is substituted by its capacitive effect considered at a constant voltage. Besides the usual poly and diffusion ones, the capacitive effects of metal wires on different layers is considered, as well as the capacitive effects of contacts. Results are highly reliable and they forecast, within a narrow error margin, the actual delay of the PLA, with that specified process and with that specified transistors dimensions. A typical output of the grafic post- processor of SPICE is shown in fig. 5. At the beginning this model has been proposed and studied using an NMOS process. Then, to verify our conclusions and, possibly, to refine and tune the model, a test vehicle chip has been integrated with different sized PLAs. Some measures have been performed to check threshold voltages and current through depletion load transistors, to correctly characterise the process. The delay time of each PLA was then directly measured and compared with the simulated time. The first model was slightly modified and the simulation of the new circuit model gave results fitting the measured values

4

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I FiG, Lt

TFE O~ITIFJ~ PATH DESCRIPTION

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A. Cagnola et aL / LAPLACE

References PLR

SIMULATION

[1] C.Mead, L.Conway, "Introduction to VLSI systems," Addison-Wesley, Reading (MA), (1980). [2] L. Glasser, P. Penfield Jr., "An interactive PLA Generator as an Archetype for a New VLSI Design Methodology," MIT Vlsi Memo 80-25, July 1980. [3] M. Meyer, "A VLSI FSM Design System," 21st Design Automation Conference, (1984). a_

rifle

Fig.

5

( SEC )

Input

and o u t p u t

*,|t-7 waveforms

as shown in the table. Later on, the same algorithms and model have been moved to CMOS processes.

4

Layout generation

LAPLACE eventually compile the layout of the PLA in CIF format. The layout generation is design rules independendt and uses a technology file containing all design rules of a process. Layout is performed as a hierarchy of cells and the program operates in two steps: firstly it accesses its data base and performes some computations and evaluation on its leaf cells, slightly modifying the topology of their layout, respecting the dimensions of transistors, in order to obtain a better compaction. In the second step the actual layout is drawn using CIF primitives. As an example we inlude the layout of a generic PLA in a static CMOS tipical architecture.

5

Conclusion

In conclusion, LAPLACE is an integrated environment to refine and conclude the design of PLAs, which allows the designers to change dimensions interactively and to simulate the PLA. A graphic postprocessor and a graphic editor are used to display, respectively, input output waveforms and the layout. In the future LAPLACE is going to grow in some directions. It will include the generation of PLAs in NMOS processes and, at the same time, it will manage a wider set of dynamic architectures for PLAs. In the far future it will include even logic and topologic minimization.

[4] M. Stebnisky et al. , "APSS: an automatic PLA synthesis system," 20th Design Automation Conference, (1983). [5] J. Rubinstein, P. Penfield Jr., "Signal Delay in RC Tree Networks," Caltech Conference on VLSI (Jan. 1981). [6] E. Tamura, k. Ogawa, T. Nakano, " Path delay analysis for hierarchical building block layout system," Proc. of 20th Design Automation Conference (1983).

[7]

T.M. Lin, C. Mead, " Signal delay in general RC networks," IEEE Trans. on CAD, No. 4, October 1984.

[8] M. Horowitz,

"Timing models for MOS circuits," Stanford University - Dept. of Electrical Engineering, Technical Report No. SEL83-003, Dec. 1983

A. Cagnola et aL / LAPLACE

Fig, 6

Layout example of a generic static CMOS

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PLA.