Large format two-color CMOS ROIC for SLS detectors

Infrared Physics & Technology 59 (2013) 78–83

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Large format two-color CMOS ROIC for SLS detectors Brian Simolon ⇑, Naseem Aziz, Steve Barskey, Randy Hansen, Eric Kurth, John Long, Susan Petronio FLIR Systems, Inc., 70 Castilian Dr., Goleta, CA 93117, United States

a r t i c l e

i n f o

Article history: Available online 11 January 2013 Keywords: Strained-layer superlattice CMOS Readout integrated circuits Multiplexing Two-color

a b s t r a c t The ISC0905 is a 640  512, large format, two-color CMOS readout integrated circuit (ROIC) designed for strained-layer superlattice (SLS) detectors. The detector interface is supported through one input pad in each 30 lm pixel. One bit in the serial control word programs the chip to automatically adjust all biases and timing to allow for the integration of either electrons or holes. This feature allows users to easily operate this ROIC with a wide variety of p-on-n or n-on-p detectors. The ROIC has been specifically designed to allow for both polarities of detectors to be placed back-to-back and to connect to the ROIC through a single input pad to obtain a two-color image. The two-color image is achieved by switching the ROIC mode between the two colors on a per frame basis. This paper will describe the interface, design and features of the ISC0905 ROIC as well as a summary of the characterization test results. Ó 2013 Elsevier B.V. All rights reserved.

1. Introduction The advancement of technology from the early days of infrared in the 1950s until today has brought about significant improvements to the capabilities of infrared systems. With every major step in infrared technology that resulted in significant changes to the performance of infrared imaging systems, a new generation of systems has been defined. The first generation infrared systems that were in production in the 1970s were based on scanning mirrors that would focus an image onto a single-element or linear array to obtain a full image over time. The first step toward second generation systems began in the 1980s as linear arrays were expanded to include multiple rows instead of just one to take advantage of the time-delay and integration (TDI) technique to improve image quality [1]. The advent of staring arrays in the 1990s fully ushered in the second generation of infrared systems. Staring arrays have detector pixels in two dimensions and the information from those pixels is multiplexed out electronically. By removing the mechanical scanning mirror in second generation systems, significant reduction in size, weight and power was achieved over first generation systems. In addition, all detector pixels could now collect information from the scene for nearly the entire frame time, rather than sharing time looking at the scene through the scanning mirror, allowing more signal to be collected on every pixel in a given frame time [2]. With this increase in signal, second generation infrared systems also gained improvement in signal to noise ratio allowing for earlier detection and identification of targets, doubling the range of first generation systems [3]. ⇑ Corresponding author. Tel.: +1 805 690 6739; fax: +1 805 685 2711. E-mail address: brian.simolon@flir.com (B. Simolon). 1350-4495/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.infrared.2012.12.018

The goal of third generation infrared systems is to make the next major steps in reducing the size, weight and power of the systems while allowing for better detection and identification of targets. Characteristics of third generation infrared systems include cooled imagers with high performance, high-resolution, and multiple spectral bands as well as uncooled imagers with medium to high performance and very low cost [4]. All cooled third generation systems share the requirements of operation at higher temperatures, fast frame rates, and on-chip processing with a user friendly detector interface. Cooled third generation systems can then be categorized as single-color large-format, multi-color, or 3-D active imaging [3]. SLS detectors hold the potential to meet the requirements of these cooled third generation systems and thus, there has been a recent focus on development of SLS detectors [5]. SLS detectors enable third generation characteristics of multi-spectral infrared focal plane arrays (IRFPAs) with two-color infrared detectors in a compact stacked configuration [6] and allow for imaging at higher operating temperatures [7]. As SLS detectors are developed for these third generation applications, many SLS developers have fabricated p-on-n polarity detectors to be compatible with the commercially available p-on-n ROICs and their supporting electronics [8] while other developers have developed SLS detectors with the opposite, n-on-p, polarity [9]. Furthermore, advanced SLS developers are now concentrating on developing for multispectral IRFPAs with detector designs that include both p-on-n and n-on-p polarities to allow for two detectors to be stacked back to back in one pixel [10]. The objective of the new two-color ISC0905 is to provide the SLS community an ROIC to interface with SLS detectors of either polarity or both polarity detectors to support third generation systems. The format of the ISC0905 is a 640  512 array with a 30 lm pixel

B. Simolon et al. / Infrared Physics & Technology 59 (2013) 78–83

pitch. The details of this large format, two-color ROIC including detector interface, analog design, digital design, fabrication, and test results with sample images will be presented in detail throughout this paper.

2. Readout integrated circuit design The ISC0905 is a large format two-color CMOS ROIC designed for use with one detector of either polarity or with both polarities of detectors placed back-to-back to obtain a two-color focal plane array (FPA). The ROIC has been designed for maximum charge capacity to support testing of developmental SLS detectors that tend to have low resistance at zero bias, and thus large amounts of dark current. The ISC0905 can be operated with only one positive bias supply and one ground supply. One reference output is available to provide a pseudo-differential output. A 240 Hz frame rate is supported for full-frame readout in eight-output mode with an input clock rate of 9 MHz. In addition to the 9 MHz input clock, three other digital clocks are required, one to control the frame and integration timing (FSYNC), one to control the line timing (LSYNC), and another to set the modes on the chip through a serial interface (DATA). The standard operating temperature range is 60–77 K, but the device can also be operated at up to 300 K. 2.1. Detector interface The detector interface of the ISC0905 is a scaled up version of the 320  256 two-color SLS ROIC named the ISC0903 [11]. The interface to the detector is composed of an array of 652  524 pixels. The active part of the array is the center 640  512 pixels. Each 30 lm pixel contains only one 6 lm by 6 lm pad opening that is located at the center of the pixel. By having an ROIC to detector interface for a two-color FPA through only one pad per pixel instead of two pads per pixel, the hybridization of the ROIC to the detector becomes easier due to fewer connections that need to be made and larger spacing between connections. The disadvantage of this one pad per pixel ROIC design is that the FPA is limited to only integrating one detector at a time, so true simultaneous integration of two detectors is not supported. The ROIC is designed to support either p-on-n or n-on-p detector configurations as shown in Fig. 1a and b. To create a two-color FPA, the detectors must be configured so that the two detectors are placed back-toback with one detector connected to VDETCOM and the other connected to the input pad of the ROIC pixel as displayed in Fig. 1c or d. Based on this configuration and with appropriate biasing, one of

VDETCOM

N

P Indium Bumps

VDETCOM

VDETCOM

VDETCOM

P

N

N

P

P

N

P

N Indium Bumps

Indium Bumps

Indium Bumps

ROIC Input / Bias

ROIC Input / Bias

ROIC Input / Bias

ROIC Input / Bias

(a)

(b)

(c)

(d)

Fig. 1. Detector configurations compatible with the ISC0905 include (a) p-on-n configuration; (b) n-on-p configuration; (c) two-color p-n-p configuration; (d) twocolor n-p-n configuration.

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the detectors will be forward biased to act as a short while the other detector will be reverse biased to act as photodiode. Surrounding the 640  512 active array is a guard ring that is six pixels wide with all detector pad openings tied to the detector common bias (VDETCOM). For detector testing, four of the pixels in this guard ring have the VDETCOM connection replaced with a connection directly to four corresponding probe pads to allow access to the test detectors located on these pixels. 2.2. Analog design The analog signal path for the ISC0905 ROIC begins in the unit cell at the detector interface. The interface between the analog signal path and the detectors is used to both bias the detectors and to allow charge generated by the detectors to flow into the unit cell for collection. A direct injection (DI) input circuit is used in the unit cell to bias the detector or detectors. Each detector polarity has its own DI input circuit to bias the interface node at the detector and ROIC interface either low (p-on-n) or high (n-on-p). In a given frame only one DI input circuit in every unit cell is biased at a time and the polarity which is not being integrated has its DI input circuit turned off. The bias for each polarity can be adjusted either through the serial control word bits or through the pads VDET_ADJP for p-on-n polarity detectors and VDET_ADJN for n-on-p polarity detectors. The detector bias is determined by the difference between the bias generated on each pixel’s DI circuit and the voltage of VDETCOM on other side of the detector (or detectors). The ISC0905 is designed to supply up to 800 mV of reverse bias across either polarity detector. By default, the ROIC controls the voltage on the VDETCOM signal based on the detector polarity that is being integrated during that frame. However, by changing a bit in the serial control word the VDETCOM voltage can also be driven from off-chip. Based on the biases supplied by the ROIC and the photon flux at the detector, a current is generated by the detector and enters the ROIC through a DI circuit in the unit cell. The DI input circuit allows for high density charge storage capability with low power. An anti-blooming circuit is included in the unit cell for each polarity to prevent high detector current from de-biasing the detector and thus blooming detector current to neighboring pixels. The anti-blooming can be disabled through the serial control interface to allow for increased detector bias or increased charge capacity. Since only one DI circuit is turned on at a time, only one detector is in reverse bias and able to generate charge from input photons, and thus only one integration capacitor is required. The need for only one integration capacitor for a twocolor ROIC allows the integration capacitor to be much larger than if two separate integration capacitors had to share the same unit cell real estate. The integration capacitor is large enough to allow for a charge capacity of greater than 22 million carriers. The unit cell circuitry is designed in such a way to support snap-shot integration in integrate-then-read (ITR) or integrate-while-read (IWR) modes. Each unit cell signal is read out to the column by a voltage mode column buffer during the line time. The value of every column is then multiplexed down to four or eight analog output drivers. The number of output drivers that are used for each frame is set through the serial control register and each output driver can support a data rate of up to 18 MHz. An optional reference output can be turned on through the serial control register. During the line times, the output of the reference pad can be set to either the VOUTREF bias or from a polarity dependent bias generated on chip. The reference output allows common mode noise introduced through the ROIC column and output multiplexing circuitry to be subtracted off at the system level. The trade for removing this common-mode noise through the output reference is increased ROIC power and noise. Fig. 2 shows a block diagram of the analog signal chain as described in this section.

B. Simolon et al. / Infrared Physics & Technology 59 (2013) 78–83

VDET_ADJP

80

VDETCOM

Programmed Detector Bias PN

FSYNC LSYNC DATA CLK

Unit Cell (640 x 512)

Detector AntiBlooming

Digital Logic Control

VDET_ADJN

DAC S/H Integrator

Programmed Detector Bias NP

+1

x 640 Columns

Internal Reference Temp Sensor

IMSTR_ADJ

TEMP

OUT A OUT B

+1 +1

Power Control

+1

OUT H REFOUT

VOUTREF

Fig. 2. Analog signal path block diagram.

The analog signal path can be optimized and tested through the use of serial control bits and external pads. The master current of the chip, for example, can be adjusted through the IMSTR_ADJ pad or through the serial control register. Furthermore, bits are available to independently adjust the power setting of each block of the analog signal path. Power adjustments are typically not necessary, but they can be useful during testing and they allow the advanced user to optimize both performance and power of the analog signal path. 2.3. Digital design To control the operating modes of the chip, the ISC0905 utilizes a simple serial control interface. A high bit on the DATA signal is called a ‘‘start bit’’ and begins data being clocked into the chip. Data is clocked in once per frame and the settings are applied at the start of the next frame. If a ‘‘start bit’’ is not received during a frame, then the settings remain unchanged. After a power up or an applied reset the command word is set to predefined default values. The 120-bit data word controls which polarity detector is integrated during each frame, the detector bias for each polarity, anti-blooming control, power adjustments, reference output

enable, row and column windowing, row and column scan directions, output driver mode, on-chip timing adjustments, programmable test, and a master reset. The detector polarity that is integrated is controlled through the digital serial interface. Based on setting one serial control bit, the chip is placed in a mode to integrate either p-on-n or n-on-p detectors. The serial bit in the control word to control the integration polarity can be changed on a per-frame basis, so for a two-color detector the polarity being integrated can alternate every frame. For a single detector, the control bit can be set to the appropriate detector polarity and be kept constant to have the ROIC act as either a single-color hole collector or a single-color electron collector. When the bit is applied for the p-on-n polarity at the start of the frame, the biases and clocks are set to correctly bias the detector and integrate the photo generated holes on the ROIC. The DI input circuit for the p-on-n detector is set to the correct bias while the DI input circuit for the n-on-p circuit is turned off and the VDETCOM signal is driven to the appropriate level. If the bit is then changed to the n-on-p polarity, then the biases and timing are changed at the start of the next frame so that the photo generated electrons are integrated on the ROIC from the n-on-p detector. Even though

FSYNC

LSYNC

DATA

N-P

P-N

N-P

(Serial Data Word)

Integration Biases / Timing

OUT[A-H]

P - on - N

N - on - P

N - on - P

P - on - N

P - on - N

N - on - P

(Data Readout)

Fig. 3. Integration and read cycles when toggling detector polarity every frame.

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B. Simolon et al. / Infrared Physics & Technology 59 (2013) 78–83

the biases and timing are set by the serial control bit to integrate a given polarity during a frame, the data from that integration is not read out until the following frame as shown in Fig. 3. As discussed in Section 2.2, the chip has been designed to operate in either ITR or IWR integration modes. ITR allows for the best performance with reduced frame rate as the integration and readout stages are separated in time. IWR mode allows integration of one frame and the readout of the previous frame to occur simultaneously, allowing for an increased frame rate at the expense of slightly decreased image performance. In both of these modes the start of integration is controlled by the falling edge of the FSYNC input clock, and the rising edge of the FSYNC triggers the global stop and hold of the integrated signal in all unit cells. Many other features controlled by the digital design can be accessed through the serial control register. For instance, the ROIC can be programmed to readout only a select number of pixels at a given location in the array down to a minimum window of 64 columns by 8 rows in eight output mode. Reading out windows smaller than the full frame allows for higher frame rates. Digital controls also allow rows to be read out in reverse order to invert the image and allow columns to be read out in reverse order to revert the image. The digital design and serial interface also allow for extra features to help in the testing and characterization, including moving timing edges and accessing data from a test row. The typical user should never have to adjust these logic test features, but the added flexibility allows for a robust testing of the ROIC. 2.4. Physical design The ISC0905 is fabricated on 200 mm (8-inch) wafers using a standard CMOS transistor process with multiple metal layers. The die size is 22.77 mm by 20.73 mm as measured to edge of scribe lane, resulting in 48 die per 8-inch wafer with 180 lm scribe lanes in the X and Y directions. Fig. 4 shows a block diagram of the chip layout.

Table 1 Characterization of two-color performance. Test

Measurement p-on-n

Measurement n-on-p

Full scale swing @ 77 K Full scale swing @ 300 K (CP & CL bits at reduced settings) Noise @ 77 K

>2.75 V >2.5 V

>2.75 V >2.5 V

117 lV (1143 e ) 183 lV (1787 e ) 980 mV/ 7.8 mV <±1% <±2%

107 lV (1045 e ) 150 lV (1465 e ) 1024 mV/ 8.1 mV <±1% <±2%

Noise @ 300 K Detector bias range/resolution @77 K Linearity @ 77 K (15–85% of signal swing) Linearity @ 300 K (15–85% of signal swing)

Table 2 Characterization independent to detector polarity. Test

Measurement

Power: 4 outputs (77 K PT = 00 and 300 K PT = 11) Power: 8 outputs (77 K PT = 00 and 300 K PT = 11) Offset uniformity @ 77 K Power adjustments Temperature sensor Multiplex outputs Invert/revert Windowing

<142 mW <129 mW (reference on) (reference off) <183 mW <171 mW (reference on) (reference off) 91 mV peak to peak Functional @ 77 K and 300 K Functional @ 77 K and 300 K Functional @ 77 K and 300 K Functional @ 77 K and 300 K Functional @ 77 K and 300 K

The unit cell of each pixel has been designed in such a way that, with a few mask changes, the charge capacity of the ROIC can be reduced in future versions. As SLS detectors evolve and have reduced dark currents, a smaller charge capacity may be desired. By reducing the charge capacity of the ROIC, the front-end gain

22.77 mm BOND PADS

ROW SELECT

20.73 mm

(0,511)

(639,511)

INPUT CELL ARRAY (640x512) (19.2 mm x 15.36 mm)

(639,0) COLUMN & MUX BUFFER AMPS COLUMN SELECT CONTROL LOGIC BOND PADS Fig. 4. ISC0905 layout block diagram (not to scale).

BIAS GEN

(0,0)

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B. Simolon et al. / Infrared Physics & Technology 59 (2013) 78–83

Fig. 5. ISC0905 SLS two-color FPA images.

of the ROIC is increased, thus reducing the noise from all downstream ROIC circuitry and external electronics. 3. Performance 3.1. Characterization The characterization of the ISC0905 was done at 77 K and 300 K on an ROIC without any detectors. The tests were completed for both p-on-n and n-on-p modes where appropriate. The measurements from the characterization of a single die are included in Tables 1 and 2. The ROIC specifications are all based on operation at 77 K, and all 77 K measurements met specifications. 3.2. Sample image Northwestern University has fabricated two-color SLS FPAs with the large format ISC0905. Fig. 5 shows pictures of Center for Quantum Devices graduate student Edward Huang holding a lighter and a narrow-band filter centered at 11.3 lm. The filter blocks the flame from detectors with detection wavelength up to 9.5 lm (left) but can be seen when imaged with detectors sensitive up to 13 lm (right). [12]. 4. Conclusion The ISC0905 targets the development of multi-spectral SLS detectors for third generation systems by providing an interface and multiplexing for these detectors. The ISC0905 ROIC also supports the three key characteristics of all cooled third generation systems which are higher operating temperature, higher frame rates and simple user interface. With the extra information provided by two different wavelength bands on the same FPA, the characteristics of objects become more distinct. This extra distinction allows for the fast detection of objects with minimal error and minimal computing power [13]. The extra image information available by comparing and contrasting the two colors can provide valuable data in military, medical, geological and astronomical applications, as well as the ability to easily identify everyday objects for commercial applications [14]. While extra complexity is involved in detecting two different detectors with opposite polarity biases, the ISC0905 masks this complexity to the end user. In order for a user to choose a detector polarity to integrate for a given frame, the user is only required to set a bit in the control word and the ROIC automatically adjusts all the appropriate timing and biases. This simple interface allows users to operate the ROIC even if they are not well skilled in the details of ROIC design.

To take advantage of the information from two colors, computer algorithms can be applied to the image to further improve sensitivity [15]. These computer algorithms can also take advantage of over sampling of images provided by higher frame rates. The ISC0905 provides frame rates of up to 240 Hz for a full 640  512 frame and up to 3.8 kHz frame rate for windowed frames to allow for computer interpretation of the data and even better detection and identification. Finally, the ISC0905 ROIC supports SLS detectors that can achieve higher operating temperatures and the ROIC itself can be operated at higher operating temperatures with a slight degradation in performance. Providing a two-color ROIC with high frame rates will allow systems to better detect and identify a target while operating with detectors at higher operating temperatures and a simple user interface will allow for systems with reductions in size, weight and power. Overall, this ISC0905 ROIC has the characteristics to help enable SLS detectors for third generation infrared systems.

Acknowledgements The authors would like to acknowledge the work of Peter Solodkin, Clay Stanford and James Woolaway on the testing, design and development of this ISC0905 ROIC. The authors would like to acknowledge Professor M. Razeghi at the Center for Quantum Devices at Northwestern University for the contribution of the images from an SLS FPA using the ISC0905 ROIC.

References [1] P. Norton, Third-generation sensors for night vision, Opto-Electron. Rev. 14 (1) (2003) 3498–3516. [2] A. Rogalski, Third-generation infrared photon detectors, Opt. Eng. 42 (12) (2006) 1–10. [3] P. Tribolet, G. Destefanis, Third generation and mutli-color IRFPA developments: a unique approached based on DEFIR, Proc. SPIE. 5783 (2005) 350–365. [4] P. Norton, J. Campbell III, et al., Third-generation infrared imagers, Proc. SPIE. 4130 (2000) 226–236. [5] A. Rogalski, P. Martyniuk, InAs/GaInSb superlattices as a promising material system for third generation infrared detectors, Infrared Phys. Technol. 48 (1) (2006) 39–52. [6] E. Plis, S.S. Krishna, et al., Voltage controllable dual-band response from InAs/ GaSb strained layer superlattice detectors with nBn design, Electron. Lett. 47 (2) (2011) 133–134. [7] S.A. Pour, E.K. Huang, et al., High operating temperature midwave infrared photodiodes and focal plane arrays based on type-II InAs/GaSb superlattices, Appl. Phys. Lett. 98 (14) (2011) 143501. [8] P. Delaunay, B.M. Nguyen, et al., High-performance focal plane array based on InAs–GaSb superlattices with a 10-lm cutoff wavelength, IEEE J. Quantum Electron. 44 (5) (2008) 462–467. [9] A.D. Hood, A.J. Evans, et al., LWIR strained-layer superlattice materials and devices at teledyne imaging sensors, J. Electron. Mater. 39 (7) (2010) 1001– 1006.

B. Simolon et al. / Infrared Physics & Technology 59 (2013) 78–83 [10] E. Huang, A. Haddadi, et al., Type-II superlattice dual-band LWIR imager with M-barrier and Fabry–Perot resonance, Opt. Lett. 36 (13) (2011) 2560–2562. [11] B. Simolon, N. Aziz, et al., Standard format two-color CMOS ROIC for SLS detectors, Infrared Phys. Technol. 54 (3) (2011) 306–309. [12] E.K. Huang, M. Razeghi, World’s first demonstration of type-II superlattice dual-band 640  512 LWIR focal plane array, Proc. SPIE 8268 (2012). 82680Z1.

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[13] M. Münzberg, R. Breiter, et al., Dual color IR detection modules, trends and applications, Proc. SPIE. 6542 (2007) 654207. [14] S. Gunapala, S.V. Bandara, et al., Development of megapixel dual-band QWIP focal plane array, Proc. SPIE. 6540 (2008) 65402T. [15] A. Rogalski, J. Antoszewski, et al., Third-generation infrared photodetector arrays, J. Appl. Phys. 105 (2009) 091101.