Standard format two-color CMOS ROIC for SLS detectors

Infrared Physics & Technology 54 (2011) 306–309

Contents lists available at ScienceDirect

Infrared Physics & Technology journal homepage: www.elsevier.com/locate/infrared

Standard format two-color CMOS ROIC for SLS detectors Brian Simolon ⇑, Naseem Aziz, Randy Hansen, Eric Kurth, Simon Lam, Susan Petronio, James Woolaway FLIR Systems, Inc., 70 Castilian Dr., Goleta, CA 93117, United States

a r t i c l e

i n f o

Article history: Available online 28 December 2010 Keywords: Strained-layer superlattice CMOS Readout integrated circuits Multiplexing Two-color

a b s t r a c t The ISC0903 is a 320  256, standard format, two-color CMOS readout integrated circuit (ROIC) designed for strained-layer superlattice (SLS) detectors. The detector interface is supported through one input pad in each 30 micron pixel. One bit in the serial control word programs the chip to automatically adjust all biases and timing to allow for the integration of either electrons or holes. This feature allows users to easily operate this ROIC with a wide variety of p-on-n or n-on-p detectors. The ROIC has been specifically designed to allow for both polarities of detectors to be placed back-to-back and to connect to the ROIC through the one input pad to obtain a two-color image. The two-color image is achieved by switching the ROIC mode between the two colors on a per-frame basis. This paper will describe the interface, design, and features of the ISC0903 ROIC. Ó 2010 Elsevier B.V. All rights reserved.

1. Introduction FLIR Systems, Inc. has been a leader in providing commercial ROICs to all users in the infrared community. The history of FLIR’s ROICs can be traced back to the Indigo Systems Corporation’s general functionality and easy to operate suite of ROICs. Indigo’s most widely used standard ROIC product is a 320  256 standard format array with a 30 micron pixel pitch named the ISC9705 [1]. The ISC9705 ROIC has been, and continues to be, widely used by those in the infrared community to support a broad range of detectors including, indium antimonide (InSb), indium gallium arsenide (InGaAs), mercury cadmium telluride (MCT), and quantum well infrared photodetectors (QWIPs) [2–4]. More than 10 years after its initial development, the ISC9705 continues to be a dominant ROIC in the industry. With the recent focus on development of SLS detectors, many detector developers have chosen to use the ISC9705 ROIC to develop their SLS technology due to the ISC9705’s low cost, commercial availability, and supported electronics [5]. While many SLS developers have fabricated p-on-n polarity detectors to be compatible with the ISC9705 ROIC, other developers fabricate SLS detectors with the opposite, n-on-p, polarity [6]. Most commercially available ROICs, including the ISC9705, are designed for p-on-n detectors which only accept holes. This mismatch between the polarity for some SLS detector designs and available ROICs has left many in the SLS community in need of a new ROIC, optimized for their detector type. The objective of the new two-color ISC0903 is to provide the same functionality as the ISC9705 while adding the ability to also ⇑ Corresponding author. Tel.: +1 805 690 6739; fax: +1 805 685 2711. E-mail address: brian.simolon@flir.com (B. Simolon). 1350-4495/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.infrared.2010.12.035

interface with n-on-p polarity detectors. The format of the ISC0903 is a 320  256 array with a 30 micron pixel pitch. The details of the standard format, two-color ISC0903 ROIC including detector interface, analog design, digital design, and fabrication will be presented in detail throughout this paper. 2. Readout integrated circuit design The ISC0903 is a standard format two-color CMOS ROIC designed for use with one detector of either polarity or with both polarities of detectors placed back-to-back to obtain a two-color focal plane array (FPA). The ROIC has been designed for maximum charge capacity to support testing of developmental SLS detectors that tend to have low resistance at zero bias, and thus large amounts of dark current. The ISC0903 can be operated with only one positive bias supply and one ground supply, similar to the ISC9705. One reference output is available to provide a pseudo-differential output. A 240 Hz frame rate is supported for full-frame readout in four-output mode with an input clock rate of 6.25 MHz. In addition to the 6.25 MHz input clock, three other digital clocks are required, one to control the frame and integration timing (FSYNC), one to control the line timing (LSYNC), and another to set the modes on the chip through a serial interface (DATA). The standard operating temperature range is 60–77 K, but the device can also be operated at up to 300 K. 2.1. Detector interface The detector interface of the ISC0903 is identical to that of the ISC9705. By keeping the detector interface the same, current

307

B. Simolon et al. / Infrared Physics & Technology 54 (2011) 306–309 VDETCOM

P

N

N

P

this guard ring have the VDETCOM connection replaced with a connection directly to four corresponding probe pads to allow access to the test detectors located on these pixels. These test detectors are located in the same place as the ISC9705 test detectors to keep the same ROIC to detector interface.

P

N

2.2. Analog design

Indium Bumps

Indium Bumps

VDETCOM

N

VDETCOM

VDETCOM

P

N

P Indium Bumps

Indium Bumps

ROIC Input / Bias

ROIC Input / Bias

ROIC Input / Bias

ROIC Input / Bias

(a)

(b)

(c)

(d)

Fig. 1. Detector configurations compatible with the ISC0903 include (a) p-on-n configuration; (b) n-on-p configuration; (c) two-color p-n-p configuration; (d) twocolor n-p-n configuration.

VDET_ADJP

detector vendors who use the ISC9705 will be able to use many of the same mask sets when designing an opposite polarity detector for the ISC0903. The interface to the detector is composed of an array of 332  268 pixels. The active part of the array is the center 320  256 pixels. Each 30 micron pixel contains only one 6 micron by 6 micron pad opening that is located at the center of the pixel. By having an ROIC to detector interface for a two-color FPA through only one pad per pixel instead of two pads per pixel, the hybridization of the ROIC to the detector becomes easier due to fewer connections that need to be made and larger spacing between connections. The disadvantage of this one pad per pixel ROIC design is that the FPA is limited to only integrating one detector at a time, so true simultaneous integration of two detectors is not supported. The ROIC is designed to support either p-on-n or n-on-p detector configurations as shown in Fig. 1a and b. To create a two-color FPA, the detectors must be configured so that the two detectors are placed back-to-back with one detector connected to VDETCOM and the other connected to the input pad of the ROIC pixel as displayed in Fig. 1c or d. Based on this configuration and with appropriate biasing, one of the detectors will be forward biased to act as a short while the other detector will be reverse biased to act as photodiode. Surrounding the 320  256 active array is a guard ring that is six pixels wide with all detector pad openings tied to the detector common bias (VDETCOM). For detector testing, four of the pixels in

The analog signal path for the ISC0903 ROIC begins in the unit cell at the detector interface. The interface between the analog signal path and the detectors is used to both bias the detectors and to allow charge generated by the detectors to flow into the unit cell for collection. A direct injection (DI) input circuit is used in the unit cell to bias the detector or detectors. Each detector polarity has its own DI input circuit to bias the interface node at the detector and ROIC interface either low (p-on-n) or high (n-on-p). Only one DI input circuit is biased at a time and the polarity which is not being integrated has its DI input circuit turned off. The bias for each polarity can be adjusted either through the serial control word bits or through the pads VDET_ADJP for p-on-n polarity detectors and VDET_ADJN for n-on-p polarity detectors. The detector bias is determined by the difference between the bias generated on each pixel’s DI circuit and the voltage of VDETCOM on other side of the detector (or detectors). The ISC0903 is designed to supply up to 800 mV of reverse bias across either polarity detector. By default, the ROIC controls the voltage on the VDETCOM signal based on the detector polarity that is being integrated during that frame. However, by changing a bit in the serial control word the VDETCOM voltage can also be driven from off-chip. Based on the biases supplied by the ROIC and the photon flux at the detector, a current is generated by the detector and enters the ROIC through a DI circuit in the unit cell. The DI input circuit allows for high density charge storage capability with low power. An anti-blooming circuit is included in the unit cell for each polarity to prevent high detector current from de-biasing the detector and thus blooming detector current to neighboring pixels. The anti-blooming can be disabled through the serial control interface to allow for increased detector bias or increased charge capacity. Since only one DI circuit is turned on at a time, only one detector is in reverse bias and able to generate charge from input photons, and thus only one integration capacitor is required. The need for only one integration capacitor for a twocolor ROIC allows the integration capacitor to be much larger than

VDETCOM

Programmed Detector Bias PN

Unit Cell (320 x 256)

Detector AntiBlooming

FSYNC LSYNC DATA CLK

Digital Logic Control

VDET_ADJN

DAC Programmed Detector Bias NP

+1

S/H Integrator

Internal Reference Temp Sensor

IMSTR_ADJ

x 320 Columns

TEMP Power Control

OUT A OUT B

+1 +1

• •

+1 VOUTREF

Fig. 2. Analog signal path block diagram.

OUT D REFOUT

308

B. Simolon et al. / Infrared Physics & Technology 54 (2011) 306–309

if two separate integration capacitors had to share the same unit cell real estate. The integration capacitor is large enough to allow for a charge capacity of greater than 22 million carriers. The unit cell circuitry is designed in such a way to support snap-shot integration in integrate-then-read (ITR) or integrate-while-read (IWR) modes. Each unit cell signal is read out to the column by a voltage mode column buffer during the line time. The value of every column is then multiplexed down to one, two, or four analog output drivers. The number of output drivers that are used for each frame is set through the serial control register and each output driver can support a data rate of up to 12.5 MHz. An optional reference output can be turned on through the serial control register. During the line times, the output of the reference pad can be set to either the VOUTREF bias or from a polarity dependent bias generated on chip. The reference output allows common-mode noise introduced through the ROIC column and output multiplexing circuitry to be subtracted off at the system level. The trade for removing this common-mode noise through the output reference is increased ROIC power and noise. Fig. 2 shows a block diagram of the analog signal chain as described in this section. The analog signal path can be optimized and tested through the use of serial control bits and external pads. The master current of the chip, for example, can be adjusted through the IMSTR_ADJ pad or through the serial control register. Furthermore, bits are available to independently adjust the power setting of each block of the analog signal path. Power adjustments are typically not necessary, but they can be useful during testing and they allow the advanced user to optimize both performance and power of the analog signal path. 2.3. Digital design To control the operating modes of the chip, the ISC0903 utilizes a simple serial control interface. A high bit on the DATA signal is called a ‘‘start bit’’ and begins data being clocked into the chip. Data is clocked in once per frame and the settings are applied at the start of the next frame. If a ‘‘start bit’’ is not received during a frame, then the settings remain unchanged. After a power up or an applied reset the command word is set to predefined default values. The 120-bit data word controls which polarity detector is integrated during each frame, the detector bias for each polarity, anti-blooming control, power adjustments, reference output enable, row and column windowing, row and column scan directions, output driver mode, on-chip timing adjustments, programmable test, and a master reset. The detector polarity that is integrated is controlled through the digital serial interface. Based on setting one serial control bit, the chip is placed in a mode to integrate either p-on-n or n-on-p

detectors. The serial bit in the control word to control the integration polarity can be changed on a per-frame basis, so for a twocolor detector the polarity being integrated can alternate every frame. For a single detector, the control bit can be set to the appropriate detector polarity and be kept constant to have the ROIC act as either a single-color hole collector, similar to the ISC9705, or a single-color electron collector of the opposite polarity. When the bit is applied for the p-on-n polarity at the start of the frame, the biases and clocks are set to correctly bias the detector and integrate the photo generated holes on the ROIC. The DI input circuit for the p-on-n detector is set to the correct bias while the DI input circuit for the n-on-p circuit is turned off and the VDETCOM signal is driven to the appropriate level. If the bit is then changed to the n-on-p polarity, then the biases and timing are changed at the start of the next frame so that the photo generated electrons are integrated on the ROIC from the n-on-p detector. Even though the biases and timing are set by the serial control bit to integrate a given polarity during a frame, the data from that integration is not read out until the following frame as shown in Fig. 3. As discussed in the analog design section, the chip has been designed to operate in either ITR or IWR integration modes. ITR allows for the best performance with reduced frame rate as the integration and readout stages are separated in time. IWR mode allows integration of one frame and the readout of the previous frame to occur simultaneously, allowing for an increased frame rate at the expense of slightly decreased image performance. In both of these modes the start of integration is controlled by the falling edge of the FSYNC input clock, and the rising edge of the FSYNC triggers the global stop and hold of the integrated signal in all unit cells. Many other features controlled by the digital design can be accessed through the serial control register. For instance, the ROIC can be programmed to readout only a select number of pixels at a given location in the array down to a minimum window of 16 columns by 4 rows in four-output mode. Reading out windows smaller than the full frame allows for higher frame rates. Digital controls also allow rows to be read out in reverse order to invert the image and allow columns to be read out in reverse order to revert the image. The digital design and serial interface also allow for extra features to help in the testing and characterization, including moving timing edges and accessing data from a test row. The typical user should never have to adjust these logic test features, but the added flexibility allows for a robust testing of the ROIC. 2.4. Physical design The ISC0903 is fabricated on 200 mm (8-inch) wafers using a standard CMOS transistor process with multiple metal layers. The die size is 12.5 mm by 12.5 mm as measured to edge of scribe lane,

Fig. 3. Integration and read cycles when toggling detector polarity every frame.

B. Simolon et al. / Infrared Physics & Technology 54 (2011) 306–309

12.5 mm BOND PADS

ROW SELECT

12.5 mm

(0,255)

(319,255)

INPUT CELL ARRAY (320 x 256) (9.6mm x 7.68mm)

COLUMN & MUX BUFFER AMPS

BIAS GEN

(319,0)

(0,0)

COLUMN SELECT CONTROL LOGIC BOND PADS

Fig. 4. ISC0903 layout block diagram (not to scale).

resulting in approximately 154 die per 8-inch wafer with 90 micron scribe lanes in the X and Y directions. Fig. 4 shows a block diagram of the chip layout. The unit cell of each pixel has been designed in such a way that, with a few mask changes, the charge capacity of the ROIC can be reduced. As SLS detectors evolve and have reduced dark currents, a smaller charge capacity may be desired. By reducing the charge capacity of the ROIC, the front-end gain of the ROIC is increased, thus reducing the noise from all downstream ROIC circuitry and external electronics. Due to the fact that the ISC0903 and the ISC9705 have slightly different die sizes and functionality, the physical interface of the ISC0903 could not exactly match that of ISC9705. The pad locations of the ISC0903 have been matched as close as possible to the pads of the ISC9705. The pads for the power supplies, input clocks, and output drivers are in the same relative locations as the ISC9705. An additional pad has been added to support the adjustment of two detector biases instead of one through the pads. VDET_ADJN adjusts the bias for n-on-p detectors and VDET_ADJP adjusts the bias for p-on-n detectors. Pads to control column gain and offset functions on the ISC9705 have been removed since those features have been removed from the ISC0903. 3. Conclusion The goal of the ISC0903 is to build on the success of the ISC9705 ROIC while providing extra functionality and flexibility for modern detector developers. The high performance, versatility and the ease of operating the ISC9705 led to its wide use in the infrared commu-

309

nity. This popularity in turn lowered the price for all users. Additionally, the large number of users with many different applications allowed the ISC9705 to be tested in a wide variety of conditions. Feedback from this large and diverse user base helped FLIR better understand the capabilities of the ROIC and, in turn, help new users. With an ROIC design so thoroughly tested through large volume use, users can eliminate the ROIC as a source of errors or problems in the system once it has been properly integrated. By leveraging from FLIR’s experience with the ISC9705 and adding the n-on-p and two-color capability, the ISC0903 opens a large window of opportunities. With the extra information provided by two possibly different wavelength bands on the same FPA, the characteristics of objects become more distinct. This extra distinction allows for the fast detection of objects with minimal error and minimal computing power [7]. The extra image information available by comparing and contrasting the two colors can provide valuable data in military, medical, geological and astronomy applications, as well as the ability to easily identify everyday objects for commercial applications [8]. For current users of the ISC9705, the detector interface is identical and the electrical interface and timing are very similar. In order for a user to choose a detector polarity to integrate for a given frame, the user is only required to set a bit in the control word and the ROIC automatically adjusts all the appropriate timing and biases. This simple interface to the ROIC allows users to operate the ROIC even if they are not well skilled in the details of ROIC design. The ISC0903 will include the user base of the ISC9705 as well as an additional user base of all detectors that require an n-on-p readout, including the SLS community. Thus, the ISC0903 should share the same benefits due to volume that the ISC9705 has enjoyed and the ISC0903 may become a new industry standard. References [1] N.Y. Aziz et al., Standardized high-performance 320 by 256 readout integrated circuit for infrared applications, Proc. SPIE 3360 (1998) 80–90. [2] T.R. Hoelter et al., Flexible high-performance IR camera systems, Proc. SPIE 3698 (1999) 837–846. [3] M. Chu et al., HgCdTe focal plane arrays formed by heterojunction epitaxy and boron implantation, Proc. SPIE 4721 (2002) 234–241. [4] J.R. Andrews et al., Comparison of long-wave infrared quantum-dots-in-a-well and quantum-well focal plane arrays, IEEE Trans. Electron Devices 56 (2009) 512–516. [5] P. Delaunay et al., High-performance focal plane array based on InAs–GaSb superlattices with a 10-lm cutoff wavelength, IEEE J. Quant. Electron. 44 (2008) 462–467. [6] A.D. Hood et al., LWIR strained-layer superlattice materials and devices at teledyne imaging sensors, J. Electron. Mater. 39 (2010) 1001–1006. [7] M. Münzberg et al., Dual color IR detection modules, trends and applications, Proc. SPIE 6523 (2007) 654207. [8] S. Gunapala et al., Development of megapixel dual-band QWIP focal plane array, Proc. SPIE 6540 (2008) 65402T.