Large-Signal analysis of silicon BARITT diodes

World Abstracts on Microelectronics and Reliability plants. This concept is being used to serve the muitinati0n technical community by reserving specific ratings in an element bank independent of nationalistic packaging. By

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making package commitment at the last moment, faster delivery at the required ratings are made and an inventory reduction on the part of the user can be realized.

5. MICROELECTRONICS DESIGN AND CONSTRUCTION Cma'mt-steering chip upgrades performance of d-a converter. E. MADDOX. Electronics 125 (4 Apr. 1974). Steered bitswitching currents produced by a dielectrically isolated monolithic IC provide increased speed and accuracy by avoiding thermal tails, the lag in time involved in stabilizing switching transistors. DIP inserter aims at low-volume users. G. FARRELL.Electronics 155 (4 Apr. 1974). Semiautomatic machine can handle 3600 dual in-line packages per hr; technique is aimed at manufacturers of calculators and minicomputers. Error analysis of high-frequency MOS capacitance calcolatio~t. J. R. BREWS. Solid St. Electron. 17, 447 (1974). An error analysis of the Lindner and Grove et al. methods of

computing the high-frequency capacitance of metal-oxidesemiconductor (MOS) capacitors is presented. The analysis is based upon a differential equation for the capacitance introduced by Sah, Pierret and Tole (the "SPT capacitance"). This equation does not employ the minority-carrierdepletion approximation of Lindner, nor the depletionwidth approximation of Grove et al., nor does it require matching different solutions in different bias regions. Consequently, all these approximations can be tested. Our results show that the approximations in the Lindner capacitance introduce only 1-2-5 per cent deviation from the SPT capacitance in the doping range from 1017/cm3 to 1013/cm3, respectively. The simple Grove capacitance based upon the majority carrier depletion approximation differs by 10 per cent from the SlaT capacitance at a band bending 5 kT/q on the depletion side of flatbands, and differs by 6-11 per cent in strong inversion for the same doping range. Finally, it is shown that by resorting to a numerical integration the Lindner capacitance can be made to agree with the SPT capacitance to 10- lo CFB at 1017/cm3 and 10 -5 CFB at 1013/cm3 (CFB = flatband capacitance). These results indicate that the SPT calculation is rather well approximated by the Lindner capacitance, and that for most purposes some form of the Lindner capacitance would be adequate. Our results also indicate the level of accuracy,that is meaningful in any numerical evaluation of the various calculations. Finally, it should be noted that errors due to overidealizations in the SPT formulation itself have not been evaluated. However, whatever this error may be, the net error in any of the other methods is the sum of the SPT error and the error computed here. Consequently, any future error analysis need not repeat what has been done here, but may confine itself to the error in the SPT calculation. Two new IC toelmologies improve LSI Mmufacturing processes. JEI Japan 21, (3) Series No. 235, 62 (Mar. 1974).

Fujitsu has developed two new IC technologies which it says will improve the LSI manufacturing process and LSI reliability and multi-layering. One of the technologies is the buried wiring technique accomplished through electrolytic etching to facilitate LSI multi-layering. The other is a doped oxide diffusion technique enabling all diffusion processes on bipolar ICs to be carried out in the same way.

Surface desorptien of gases from photoresist. V. VINIKMAN, A. SAMUELand D. S C I ~ D ~ . Vacuum 24, 77 (1974). This work describes the analysis of gases desorbed in vacuum from photoresists manufactured by Shipley and Kodak, as a function of temperature. Test samples were prepared by spin coating of a special heating element prepared by photolithographic techniques on a nichrome, gold-coated alumina substrate, the degassing of this type of heating element is relatively low by comparison to that of the photoresist. The analysis of gases desorbed was performed at a pressure of 10-6 torr utilizing a monopole mass spectrometer. The type of photoresist and temperature were the determining factors in the quantity and species of gases desorbed. In this manner the breakdown temperature of each type of photoresist was determined. The results of this work aid in choosing a photoresist compatible with microelectronic vacuum technology. Current steering simldifles and shirks lk hilmlSr RAM. J. E. GERSBACH.Electronics 110 (2 May 1974). Steering a current through the decoder matrixes simplifies circuitry and eliminates the many resistors needed by voltage-mode TTL devices; moreover, a single circuit can perform an entire logic function. MOS-CV test system for IC process control and Monitoring. C. R. VISWANATHAN,R. HowEs and V. O. HINKLE.Solid St. Technol. 43 (1974). An MOS-CV system capable of monitoring and evaluating various processing steps and quality of material used in IC technology is described. This system has been found very useful in identifying processing steps giving rise to mobile ion contamination. It permits measurements of various parameters such as the minority carrier lifetime, surface-state density, mobile ion contamination level, and impurity concentration profile. Film-carrier technique automates the packalliag of IC chips. S. E. GROSSMAN.Electronics 89 (16 May 1974). With wages rising and offshore assembly losing some of its appeal, automation is replacing traditional labour-intensive wirebonding--slashing production costs and boosting assembly rates tenfold. Al~Ucation of the graphic COM recorder to creation of LSI mask pattern drawings for checking. M. SmyroH, Y. MITAand N. SUGIYAMA.NEC Res. & Develop. (32) 79 (1974). A COM recorder, which has hardware line generators and records a graphic pattern at a rate of 200 x 103 incremental steps per sec in on-line operation, was developed. An application of the graphic COM recorder to creation of a check drawing of LSI mask pattern is described. It is mentioned that the mask pattern checking system using the graphic COM recorder has advantages over the conventional system using a mechanical plotter. Large-SIpal analysis of silicon BARITT diodes. M. MATSUMURA.NEC Res. & Develop. (32) 1 (1974). Since previous large-signal analyses on BARITT diode were based on

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World Abstracts on Microelectronics and Reliability

relatively crude approximations, correct estimation of diode capability was difficult. In order to estimate the ultimate capability of BARITT diode in a more realistic manner, a large-signal computer simulation has been made using a realistic silicon diode model. By this simulation, details of carrier dynamics in large-signal operation has been clarified; large-signal admittance characteristics have been obtained; and upper limits for output power and efficiency have been derived. The computed results show that,

although formation of a spiky carrier density waveform agrees with previous theories, the phase angle at which the carrier-injection takes place advances considerably as compared with the one previously expected, due to a carrier space-charge effect on the injection process. Because of the advanced injection-phase-angle, maximum output power density is as low as 1 kW/cm 2, and negative Q of the diode in high output power density operation becomes as high as about 100.

6. MICROELECTRONICS--COMPONENTS, SYSTEMS AND EQUIPMENTS A line regulator with capacitor -MOSFET-memory for level control on widebaad carrier systems over coaxial cables. V. H. KAGELMANN and K. SCHWARZnAUER. Frequenz 28, (4) 108 (1974). (In German). A new electronic line regulator, which operates with a capacitor-MOSFET-memory, has been developed for wideband coaxial-cable systems. By suitable selection of a delay network with dampening properties (proportional-plus-rate controller), the stability of the line regulator can be so influenced that 100 of them can be connected in series without the CCITT-Recommendations for a sudden 2 dB-deviation being exceeded. In the event of a pilot failure, the level drop amounts 0-1 dB per regulator per day. The regulator has both a high degree of reliability, as it comprises only a small number of semiconductors and other components and a high degree of noise immunity, as it is a pure DC-regulator.

Current diffusion effects in titanium-N silicon schottky diodes. J. M. WILKINSON. Solid St. Electron. 17, 583 (1974). Measurements of the reverse current-voltage characteristics of titanium-n silicon Schottky barrier diodes are presented which demonstrate that diffusion limited currents can occur in these diodes when the internal electric field is low. For the titanium-n silicon diodes, the low barrier height of (~51 e V and doping concentration of 10 is cm -3 result in an electric field of 8 × 103 V c m - 1 at zero bias. An observed decrease in the reverse saturation current at low bias, previously described as anomalous, is now reconciled with the thermionic-diffusion theory of current flow, which predicts a reduction in A**, the effective Richardson constant, at internal fields below 105 V c m - 1. Trapping, emission and generation in M N O S memory devices. L. S. WE1 and J. G. Stm~IONS.Solid St. Electron. 17, 591 (1974). This study is concerned with trapping phenomena occurring at the semiconductor-oxide interface and in the nitride layer of variable-threshold m e t a l - n i t d d e - o x i d e semiconductor (MNOS) memory devices. The technique consists of biasing the device in such a manner as to charge or discharge either the interface traps or the nitride traps, or both sets of traps simultaneously. The device is then cooled to low temperature with the bias still applied, and at the low temperature the biasing condition is changed, in order to induce the device into a non-steady-state mode that is quasistable at the low temperature. The temperature of the device is then raised at a constant rate, and the resulting current vs temperature (I-T) characteristics is found to be rich in structure. By means of a series of systematic experiments the various portions of the 1 - T characteristic are identified with emission of electrons from interface states and the nitride traps, and surface generation. From this data the energy

distribution of interface states is determined. It is shown that the memory charge in the nitride is distributed throughout the nitride, and temporary memory charge and semipermanent memory charge are distinguished. A static RAM with normally-off-type schottky barrier FET's. S. SUZUKI, Y. NAGAHASHI,T. TANAKA,T. YAMADA~ H. MUTU, H. OKABAYASHIand K. YAMADA. NEC Res. & Develop. 32, 19 (1974). A large-scale integrated (LSI) memory with low power consumption and high operating speed has been developed and evaluated. A fully decoded 256-b static random-access memory (RAM) chip was fabricated by using the Enhancement-type Schottky Barrier gate FET's (ESBT), having a threshold voltage of 0.1 V, obtained by ion-implanation. The memory chip was successfully operated with an access time of less than 150 nsec, and with active power consumption of 15 roW/chip A single power supply of - 1.3 V and CML input levels are additional features of the memory chip. A data modem--an application of I . s . i . B . S'FUTTARD. Electronics & Power 364 (16 May 1974). The applications of 1.s.i. in the electronics industry are growing daily, and the modem is an example in which a special l.s.i, chip can lead to increased cost-effectiveness and simplicity of operation. The full life-cycle cost of the modem can be considered, and internal test patterns and other features can be incorporated using l.s.i. Drain voltage limitations of M O S transistors. 1. M. BATEMAN, G. A. ARMSTRONGand J. A. MAGOWAN. Solid St. Electron 17, 539 (1974). A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an MOS transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through oravalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage Vet is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, Vno, however, is determined by