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Low-cost and high-efficiency single-mode-fiber interfaces to silicon photonic circuits
Optics Communications 465 (2020) 125554
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Optics Communications journal homepage: www.elsevier.com/locate/optcom
Low-cost and high-efficiency single-mode-fiber interfaces to silicon photonic circuits Xian Zhang a , Bin Chen a , Ziliang Ruan a , Weixi Liu b , Pengxin Chen a ,∗, Yaocheng Shi b , Liu Liu a ,∗ a
Centre for Optical and Electromagnetic Research, Guangdong Provincial Key Laboratory of Optical Information Materials and Technology, South China Academy of Advanced Optoelectronics, Sci. Bldg. No. 5, South China Normal University, Higher-Education Mega-Center, Guangzhou 510006, China b State Key Laboratory for Modern Optical Instrumentation, Centre for Optical and Electromagnetic Research, Zhejiang Provincial Key Laboratory for Sensing Technologies, East Building No. 5, Zijingang Campus, Zhejiang University, Hangzhou 310058, China
ABSTRACT A high-efficiency and large-alignment-tolerance fiber interface to silicon-on-insulator wire waveguides is introduced. A spot-size converter is built through a full three-dimensional polymer waveguide and a silicon inverse taper is employed to expand the optical mode field from a silicon sub-micro waveguide to a normal cleaved single-mode fiber with a mode size of about 10 μm. The fabrication for the three-dimensional structure relies on simple spin-coating processes. The coupling loss from the fiber to the silicon waveguide through the proposed structure reaches -1.0dB for both transverse electrical and transverse magnetic modes, respectively. The polarization-dependent loss for the best coupling case is kept within -0.6dB in the whole measured wavelength range. The coupling facet of the proposed fiber interface structure is polishable and facilitates an easy package procedure with standard fiber arrays.
1. Introduction In the past two decades, silicon photonics based on silicon-oninsulator (SOI) platform has shown great potential for building highdensity photonic integrated circuits [1,2]. Waveguides down to several hundred nanometers in cross-sectional dimensions have been widely used for such circuits. However, a practical issue is raised in this case, being the interfacing between such a tiny SOI waveguide to a standard optical fiber, which current communication networks are still based on [3,4]. The large optical mode field mismatch between them induces a significant light coupling loss. Common strategies to overcome this problem rely on grating couplers or edge couplers. Grating couplers are easy to fabricate on SOI, and can readily be used to interface with normal cleaved single-mode fibers (SMFs) [5,6]. This makes them very successful in, e.g., on-chip testing for photonic components. However, the coupling efficiency of a grating coupler is still relatively low, and the coupling wavelength bandwidth is limited due to the diffraction nature of a grating. Therefore, edge coupling is still of great importance if one has to minimize the coupling loss and maximize the coupling bandwidth in real products [7–16]. In this case, a spot size converter (SSC) should be employed for expanding the mode in an SOI waveguide to a larger one for better matching with the fiber mode. An SSC can normally be constructed through an SOI inverse or metamaterial taper [7,8]. A low-index-contrast waveguide made of polymer, silicon oxide, or silicon nitride on the SOI taper may also be included [9–11]. Using such a configuration, coupling losses down to about −0.6 dB and coupling bandwidth >100 nm for both polarizations have been demonstrated from a lensed fiber or a high numerical
aperture (HNA) fiber with a mode field size of about 3 μm [10,11]. Despite the fine performance, lensed or HNA fibers are still difficult to handle considering packaging and alignment tolerance. Recently, there attracts increasing attention for interfacing an SOI circuit directly to a normal cleaved SMF, e.g., an SMF-28 fiber, with a mode field diameter of about 10 μm at 1550 nm [12–16]. Using a suspended SiO2 waveguide/membrane by removing part of the silicon substrate and an embedded silicon inverse taper or a metamaterial taper, coupling losses have been pushed down to about −1.0 dB recently [15,16]. However, such a suspended membrane structure is fragile. Its coupling facet has to be fabricated through an additional etching process, and cannot rely on the well-adopted cutting and polishing technique. In this paper, we introduce an efficient SSC structure for interfacing a cleaved SMF to an SOI wire waveguide based on a full three dimensional (3D) polymer taper. The fabrication of this 3D taper relies on simple spin-coating processes, and can be readily implemented in any micro-fabrication facilities. Light from a fiber with a mode field diameter of 10.4 μm is successfully coupled to an SOI waveguide at 1550 nm band with the best coupling losses of −1.0 dB for both transverse electrical (TE) mode and transverse magnetic (TM) mode. The polarization-dependent loss (PDL) for the best cases is below 0.6 dB in the whole measured wavelength range. 2. Design and simulation The proposed fiber interface structure, i.e., SSC, is sketched in Fig. 1. The light coming from an SOI wire waveguide is first coupled, using
∗ Corresponding authors. E-mail addresses: [email protected] (P. Chen), [email protected] (L. Liu).
https://doi.org/10.1016/j.optcom.2020.125554 Received 19 November 2019; Received in revised form 16 February 2020; Accepted 17 February 2020 Available online 20 February 2020 0030-4018/© 2020 Elsevier B.V. All rights reserved.
X. Zhang, B. Chen, Z. Ruan et al.
Optics Communications 465 (2020) 125554
Fig. 1. Sketch of the proposed fiber interface structure from an SMF to an SOI waveguide.
an inverse taper, to a polymer waveguide, here made of SU8, with a size of about 𝑤SU8 = ℎSU8 = 3 μm [7]. This is a widely adopted strategy to convert the mode from a high-index-contrast waveguide, like an SOI waveguide, to a low-index-contrast one. The SU8 waveguide is then tapered in both width and height to a dimension of about the size of a normal SMF (which is attached at the end of the waveguide), whose mode fields are well matched with each other. By this means, a high coupling efficiency can be achieved between the fiber and the SOI waveguide. The size of the SU8 waveguide at the edge of the chip is first optimized as shown in Fig. 2(a). As the width 𝑤in and height ℎin of the SU8 waveguide are both 13.7 μm, the overlap integrations between the mode fields of the waveguide and an SMF (approximated using a Gaussian profile with a beam waist radius of 5.2 μm at 1550 nm) are at maxima of 98% for both TE and TM modes. Then, the taper length 𝑙SU8 of the SU8 waveguide is designed. The taper here is considered as a linear shape. One can find in Fig. 2(b) that the coupling efficiency curves reach their plateaus as long as the taper is longer than 600 μm. The design of the silicon inverse taper structure has been extensively discussed in literature [7]. As a result, we use a linear silicon taper with widths from 𝑤t = 80 nm to 𝑤si = 300 nm and a length of 𝑙si = 400 μm to achieve a coupling efficiency of about 97.2% for TE mode and 96.6% for TM mode in this section. Here, the height ℎsi of the SOI waveguide is 220 nm. The overall coupling efficiency of the whole structure from the SMF to the SOI waveguide is shown in Fig. 3(a), when the taper length of the polymer waveguide 𝑙SU8 is 800 μm. Due to the adiabatic nature of the present structure, the coupling efficiency exhibits a flat spectrum over a wide wavelength band. Theoretically, the best coupling loss of −0.4 dB with a PDL of 0.3 dB can be achieved in the proposed fiber interface. The coupling efficiency for a lateral misalignment between the SMF and the SU8 waveguide is also analyzed as shown in Fig. 3(b). The 1 dB misalignment tolerance, i.e., the amount of misalignment allowed for the coupling efficiency dropped 1 dB from the peak value, reaches ±2.4 μm in the present structure, thanks to the largely expanded mode profile at the end of the SU8 waveguide.
Fig. 2. (a) Coupling efficiency from the input SMF to the SU8 waveguide of different width 𝑤in and height ℎin . (b) Coupling efficiency of the 3D SU8 taper of different length 𝑙SU8 . Here, wavelength is 1550 nm.
Fig. 3. (a) Wavelength responses of the whole fiber interface structure from the input SMF to the final SOI waveguide. (b) Fiber misalignment tolerance of the structure at the wavelength of 1550 nm. The 1 dB range is also marked.
an easy and efficient spin-coating process to realize such a full 3D taper structure presented in Fig. 1(a). The critical process steps are sketched in Fig. 4, which essentially consist of two SU8 patterning processes. After fabricating the SOI chip, the first SU8 layer with a thickness of about 10.7 μm is patterned. This SU8 layer contains two dummy structures beside the path of the coupling waveguide. The spacing between the dummy structures increases towards the SOI inverse taper. Then, the second SU8 layer with a thickness of about 3 μm is spun on the chip. Notice that the nominal thickness of the second SU8 layer is much thinner than the first SU8 layer that has been fabricated on the chip. This high topology already on the chip causes a severe non-conform coating of the second SU8 layer during the spin-coating process. Especially, in between the dummy structures, the SU8 layer forms a bowl-like shape, whose thickness increases as the spacing between the dummy structures decreases. This effectively creates a vertically tapered structure along the path of the coupling
3. Fabrication and measurement Although the theoretical analyses discussed above for the present structure are fairly intuitive, its fabrication is of great challenges, especially for the 3D taper in the polymer waveguide. Normally, a 3D structure can be fabricated through gray-scale lithography [17] or mold embossing [18]. Alternatively, a multi-layered structure can be adopted to build a quasi-3D taper [19]. These demonstrations all require complex fabrication processes, and the best-achieved coupling loss to an SOI waveguide is limited to −2.8 dB [18,19]. Here, we adopt 2
X. Zhang, B. Chen, Z. Ruan et al.
Optics Communications 465 (2020) 125554
Fig. 4. Fabrication steps for the 3D SU8 taper. Sketches of the sample (a) after fabrication of the SOI circuits and the first SU8 pattern, (b) after spin-coating of the second SU8 layer, and (c) after patterning the second SU8 layer. Cross-sectional structures are also presented.
waveguide. In the area of the SOI structure, the dummy structures are far away from the silicon waveguide. The resulting thickness of the second SU8 layer would be 3 μm, which is the desired thickness for the SU8 waveguide over the SOI inverse taper coupler. However, on the other end of the coupling waveguide, the chip is mostly filled with the dummy structures. Only small trenches (∼6 μm wide) are made beside the target SU8 waveguide. Thus, the second SU8 layer would add up on top of the first one, and it would leave a total SU8 thickness of about 13.7 μm, which is the optimal height for coupling to the SMF. The final SU8 waveguide pattern, including the lateral taper and the straight waveguide on top of the SOI inverse taper, is then exposed, which gives a full 3D taper for the SU8 waveguide as shown in Fig. 1(a). We fabricated the proposed fiber interface structure according to the procedure discussed above. The SOI structures were fabricated using electron beam lithography and dry etching techniques on a standard SOI chip of 220 nm-thick top silicon layer and 2 μm-thick buried oxide layer. The first SU8 layer was spun and patterned using ultra-violate contact lithography, followed by hard baking at 250 ◦ C. The second SU8 layer was subsequently spun and patterned on the chip again using contact lithography. Before spinning of the second SU8 layer, the chip was treated by a short O2 plasma ashing, in order to increase the adhesion between the two SU8 layers. Finally, the chip was hard baked at 250 ◦ C to consolidate the whole SU8 structures. Fig. 5(a) and (b) show some microscope pictures of one fabricated chip at different processing steps. Each testing SOI structure consists of one proposed fiber interface connected directly to a grating coupler (GC) working for either TE or TM polarization. All the tapered dummy structures have lengths of 800 μm, which is the desired length for the SU8 waveguide taper 𝑙SU8 . Fig. 5(c) presents a three-dimensional mapping of the sample surface after the spin coating of the second SU8 layer. One can clearly see the variation of the SU8 thickness between the dummy structures. For characterization, the chip was cleaved perpendicularly to the SU8 waveguides for butt-coupling. First, the transmission spectra of the TE and TM GCs were measured using reference structures with two such GCs connected back to back, respectively. Testing structures for the present fiber interface were then measured, and its response was deducted by subtracting that of the corresponding GCs. Over the whole chip surface and between the fibers and the chip, index matching fluid was applied to avoid any interface reflections. Fig. 6(a) and (b) demonstrate coupling losses of the present fiber interface at different wavelengths for TE and TM polarizations, respectively. Responses for three identical structures on one chip are shown for each polarization. One can find that the best coupling loss reaches −1.0 dB for both TE and TM modes. For the worst case, the coupling loss is still better −2.3 dB. In the whole measured wavelength band, the coupling losses show flat spectra with a ∼0.8 dB fluctuation. Such fluctuation is also observable in the simulations shown in Fig. 3(a), although, with a smaller amplitude. This relatively large wavelength dependency in measurement results is probably due to a slight misalignment of the
Fig. 5. Microscope pictures of a fabricated chip. Top-views of (a) the finished sample and (b) the sample just after the spin coating of the second SU8 layer. The white dashed lines in (b) indicate the SU8 waveguide to be fabricated. (c) Three dimensional mapping of the sample surface in (b). The black dashed line indicates the center of the SU8 waveguide to be fabricated.
SU8 and the SOI waveguides [7]. The PDL for the best coupling case is also below 0.6 dB in the measured wavelength range as shown in Fig. 6(c). 4. Discussion and conclusion In this paper, we have demonstrated an efficient SSC structure for SOI waveguide based on a full 3D SU8 taper. Its fabrication, besides the standard silicon processes, consists of only two layers of SU8 spincoating and patterning. The first SU8 pattern does not contain any critical structures, i.e., no optical waveguides, and its alignment is therefore not important. Only the second SU8 pattern should be well aligned to the SOI structure. The critical dimension of all SU8 patterns here is the width of the SU8 waveguide on the SOI inverse taper, which is about 3 μm. The proposed SU8 structure could be fabricated much more easily as compared to quasi-3D structures, e.g., multilayer tapers [19], where the dimension control and alignment accuracy are important for all layers. To further study the reproducibility of the proposed 3D SU8 taper, we further tested the structures on a 2-inch wafer as shown in Fig. 7(a). 3
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Optics Communications 465 (2020) 125554
Fig. 7. Reproducibility study of the 3D SU8 structure. (a) Mapping of a 2-inch wafer showing positions of the 9 testing structures. (b) Measured SU8 thicknesses of the 9 testing structures on one wafer along the central line of the corresponding SU8 waveguide, i.e., the black line shown in Fig. 5(c).
Fig. 6. Coupling losses of the fiber interface structure for (a) TE and (b) TM polarizations at different wavelengths, and (c) the corresponding PDL.
The measured surface mapping of 3D SU8 structures fabricated at 9 different places on the wafer is presented in Fig. 7(b). All the structures show the desired taper shape in the thickness direction with some small differences in detail. The working principle of the proposed structure, either the 3D SU8 taper or the SOI inverse taper, is based on adiabatic mode conversion, which intrinsically ensures a large fabrication tolerance as long as the taper is long enough. The SU8 thicknesses at the input facet vary from 12.4 μm to 14.7 μm. From Fig. 2(a), one can find that such a variation would only induce a decrease of <2% in the coupling efficiency. This test confirms that the proposed fiber interface can be adopted for a large-scale wafer process. Another advantage of the present SSC structure is that the chip can be easily sealed and its facets are polishable as shown in Fig. 8. Here, the edge of the chip was covered using a quartz plate and a low-index adhesive. The polished facet is clear and flat. This facilitates an easy and matured package procedure with standard fiber arrays. We believe the SSC structure introduced here can be used for high-efficiency and large-tolerance fiber-to-SOI-waveguide coupling interfaces.
Fig. 8. Polished chip facet encapsulated by a quartz plate and a low-index adhesive.
Technology Program (2017A010101023), Guangzhou Science and Technology Program (201707010444) and the Special Funds for the Cultivation of Guangdong College Students’ Scientific and Technological Innovation (‘‘Climbing Program’’), China. References
CRediT authorship contribution statement
[1] W. Bogaerts, R. Baets, P. Dumon, V. Wiaux, S. Beckx, D. Taillaert, B. Luysseart, J. Van Campenhout, P. Bienstman, D. Van Thourhout, Nanophotonic waveguides in silicon-on-insulator fabricated with CMOS technology, J. Lightwave Technol. 23 (1) (2005) 401–412. [2] B. Jalali, S. Fathpour, Silicon photonics, J. Lightwave Technol. 24 (2006) 4600–4615. [3] R. Marchetti, C. Lacava, L. Carroll, K. Gradkowski, P. Minzioni, Coupling strategies for silicon photonics integrated chips [Invited], Photonics Res. 7 (2019) 201–239. [4] G. Son, S. Han, J. Park, K. Kwon, K. Yu, High-efficiency broadband light coupling between optical fibers and photonic integrated circuits, Nanophoton. 7 (2018) 1845–1864. [5] D. Taillaert, F. Van Laere, M. Ayre, W. Bogaerts, D. Van Thourhout, P. Bienstman, R. Baets, Grating couplers for coupling between optical fibers and nanophotonic waveguides, Japan. J. Appl. Phys. 45 (2006) 6071–6077.
Xian Zhang: Validation, Visualization, Formal analysis, Investigation. Bin Chen: Validation. Ziliang Ruan: Validation. Weixi Liu: Validation. Pengxin Chen: Validation, Formal analysis, Investigation, Writing - review & editing. Yaocheng Shi: Validation, Formal analysis. Liu Liu: Conceptualization, Methodology, Supervision, Writing original draft. Acknowledgments This work is partially supported by National Natural Science Foundation of China (61675069, 91833303), National Major Research and Development Program (2018YFB2200200), Guangdong Science and 4
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Optics Communications 465 (2020) 125554 [13] T. Barwicz, et al., A metamaterial converter centered at 1490 nm for interfacing standard fibers to nanophotonic waveguides, presented at the Opt. Fiber Commun. Conf. Exhib. Anaheim, CA, USA, 2016, Paper M2I.3. [14] Q. Fang, J.F. Song, X.G. Tu, L.X. Jia, M.B. Yu, G.Q. Lo, Low loss fiber-towaveguide converter with a 3D functional taper for silicon photonics, IEEE Photonics Technol. Lett. 28 (2016) 2533–2536. [15] T. Barwicz, et al., Integrated metamaterial interfaces for self-aligned fiber-tochip coupling in volume manufacturing, IEEE J. Sel. Top. Quantum Electron. 25 (2019) 1–13. [16] L. Jia, C. Li, T. Liow, G.Q. Lo, Efficient suspended coupler with loss less than -1.4 dB between Si-photonic waveguide and cleaved single mode fiber, J. Lightwave Technol. 36 (2018) 239–244. [17] C.C. Yang, T.C. Peng, Y.H. Huang, M.C. Wu, C.L. Ho, W.J. Ho, A simple and lowcost fabrication of polymeric vertical microlens using dip method, IEEE Photonics Technol. Lett. 17 (2005) 603–605. [18] K. Ku, M.M. Lee, Cascade of two opposite tapers for butt-coupling between fibers and silicon photonic wires with large misalignment tolerance and low polarization dependency, presented at the Opt. Fiber Commun. Conf. Exhib. Anaheim, CA, USA, 2013, Paper OTu2C.3. [19] H. Park, S. Kim, J. Park, J. Joo, G. Kim, A fiber-to-chip coupler based on Si/SiON cascaded tapers for Si photonic chips, Opt. Express 21 (2013) 29313–29319.
[6] L. Liu, M. Pu, K. Yvind, J.M. Hvam, High-efficiency, large-bandwidth siliconon-insulator grating coupler based on a fully-etched photonic crystal structure, Appl. Phys. Lett. 96 (2010) 051126. [7] V.R. Almeida, R.R. Panepucci, M. Lipson, Nanotaper for compact mode conversion, Opt. Lett. 28 (2003) 1302–1304. [8] P. Cheben, J.H. Schmid, S. Wang, D.-X. Xu, M. Vachon, S. Janz, J. Lapointe, Y. Painchaud, M.-J. Picard, Broadband polarization independent nanophotonic coupler for silicon waveguides with ultra-high efficiency, Opt. Express 23 (2015) 22553–22563. [9] T. Shoji, T. Tsuchizawa, T. Watanabe, K. Yamada, H. Morita, Low loss mode size converter from 0.3μm square si wire waveguides to single mode fibres, Electron. Lett. 38 (2002) 1669–1670. [10] B. Ben Bakir, A. Vazquez de Gyves, R. Orobtchouk, P. Lyan, C. Porzier, A. Roman, J.-M. Fedeli, Low-loss (<1dB) and polarization-insensitive edge fiber couplers fabricated on 200-mm silicon-on-insulator wafers, IEEE Photonics Technol. Lett. 22 (2010) 739–741. [11] M. Pu, L. Liu, H. Ou, K. Yvind, J.M. Hvam, Ultra-low-loss inverted taper coupler for silicon-on-insulator ridge waveguide, Opt. Commun. 283 (2010) 3678–3682. [12] L. Chen, C.R. Doerr, Y.-K. Chen, T.-Y. Liow, Low-loss and broadband cantilever couplers between standard cleaved fibers and high-index contrast Si3N4 or Si waveguides, IEEE Photonics Technol. Lett. 22 (2010) 1744–1746.
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Contents lists available at ScienceDirect
Optics Communications journal homepage: www.elsevier.com/locate/optcom
Low-cost and high-efficiency single-mode-fiber interfaces to silicon photonic circuits Xian Zhang a , Bin Chen a , Ziliang Ruan a , Weixi Liu b , Pengxin Chen a ,∗, Yaocheng Shi b , Liu Liu a ,∗ a
Centre for Optical and Electromagnetic Research, Guangdong Provincial Key Laboratory of Optical Information Materials and Technology, South China Academy of Advanced Optoelectronics, Sci. Bldg. No. 5, South China Normal University, Higher-Education Mega-Center, Guangzhou 510006, China b State Key Laboratory for Modern Optical Instrumentation, Centre for Optical and Electromagnetic Research, Zhejiang Provincial Key Laboratory for Sensing Technologies, East Building No. 5, Zijingang Campus, Zhejiang University, Hangzhou 310058, China
ABSTRACT A high-efficiency and large-alignment-tolerance fiber interface to silicon-on-insulator wire waveguides is introduced. A spot-size converter is built through a full three-dimensional polymer waveguide and a silicon inverse taper is employed to expand the optical mode field from a silicon sub-micro waveguide to a normal cleaved single-mode fiber with a mode size of about 10 μm. The fabrication for the three-dimensional structure relies on simple spin-coating processes. The coupling loss from the fiber to the silicon waveguide through the proposed structure reaches -1.0dB for both transverse electrical and transverse magnetic modes, respectively. The polarization-dependent loss for the best coupling case is kept within -0.6dB in the whole measured wavelength range. The coupling facet of the proposed fiber interface structure is polishable and facilitates an easy package procedure with standard fiber arrays.
1. Introduction In the past two decades, silicon photonics based on silicon-oninsulator (SOI) platform has shown great potential for building highdensity photonic integrated circuits [1,2]. Waveguides down to several hundred nanometers in cross-sectional dimensions have been widely used for such circuits. However, a practical issue is raised in this case, being the interfacing between such a tiny SOI waveguide to a standard optical fiber, which current communication networks are still based on [3,4]. The large optical mode field mismatch between them induces a significant light coupling loss. Common strategies to overcome this problem rely on grating couplers or edge couplers. Grating couplers are easy to fabricate on SOI, and can readily be used to interface with normal cleaved single-mode fibers (SMFs) [5,6]. This makes them very successful in, e.g., on-chip testing for photonic components. However, the coupling efficiency of a grating coupler is still relatively low, and the coupling wavelength bandwidth is limited due to the diffraction nature of a grating. Therefore, edge coupling is still of great importance if one has to minimize the coupling loss and maximize the coupling bandwidth in real products [7–16]. In this case, a spot size converter (SSC) should be employed for expanding the mode in an SOI waveguide to a larger one for better matching with the fiber mode. An SSC can normally be constructed through an SOI inverse or metamaterial taper [7,8]. A low-index-contrast waveguide made of polymer, silicon oxide, or silicon nitride on the SOI taper may also be included [9–11]. Using such a configuration, coupling losses down to about −0.6 dB and coupling bandwidth >100 nm for both polarizations have been demonstrated from a lensed fiber or a high numerical
aperture (HNA) fiber with a mode field size of about 3 μm [10,11]. Despite the fine performance, lensed or HNA fibers are still difficult to handle considering packaging and alignment tolerance. Recently, there attracts increasing attention for interfacing an SOI circuit directly to a normal cleaved SMF, e.g., an SMF-28 fiber, with a mode field diameter of about 10 μm at 1550 nm [12–16]. Using a suspended SiO2 waveguide/membrane by removing part of the silicon substrate and an embedded silicon inverse taper or a metamaterial taper, coupling losses have been pushed down to about −1.0 dB recently [15,16]. However, such a suspended membrane structure is fragile. Its coupling facet has to be fabricated through an additional etching process, and cannot rely on the well-adopted cutting and polishing technique. In this paper, we introduce an efficient SSC structure for interfacing a cleaved SMF to an SOI wire waveguide based on a full three dimensional (3D) polymer taper. The fabrication of this 3D taper relies on simple spin-coating processes, and can be readily implemented in any micro-fabrication facilities. Light from a fiber with a mode field diameter of 10.4 μm is successfully coupled to an SOI waveguide at 1550 nm band with the best coupling losses of −1.0 dB for both transverse electrical (TE) mode and transverse magnetic (TM) mode. The polarization-dependent loss (PDL) for the best cases is below 0.6 dB in the whole measured wavelength range. 2. Design and simulation The proposed fiber interface structure, i.e., SSC, is sketched in Fig. 1. The light coming from an SOI wire waveguide is first coupled, using
∗ Corresponding authors. E-mail addresses: [email protected] (P. Chen), [email protected] (L. Liu).
https://doi.org/10.1016/j.optcom.2020.125554 Received 19 November 2019; Received in revised form 16 February 2020; Accepted 17 February 2020 Available online 20 February 2020 0030-4018/© 2020 Elsevier B.V. All rights reserved.
X. Zhang, B. Chen, Z. Ruan et al.
Optics Communications 465 (2020) 125554
Fig. 1. Sketch of the proposed fiber interface structure from an SMF to an SOI waveguide.
an inverse taper, to a polymer waveguide, here made of SU8, with a size of about 𝑤SU8 = ℎSU8 = 3 μm [7]. This is a widely adopted strategy to convert the mode from a high-index-contrast waveguide, like an SOI waveguide, to a low-index-contrast one. The SU8 waveguide is then tapered in both width and height to a dimension of about the size of a normal SMF (which is attached at the end of the waveguide), whose mode fields are well matched with each other. By this means, a high coupling efficiency can be achieved between the fiber and the SOI waveguide. The size of the SU8 waveguide at the edge of the chip is first optimized as shown in Fig. 2(a). As the width 𝑤in and height ℎin of the SU8 waveguide are both 13.7 μm, the overlap integrations between the mode fields of the waveguide and an SMF (approximated using a Gaussian profile with a beam waist radius of 5.2 μm at 1550 nm) are at maxima of 98% for both TE and TM modes. Then, the taper length 𝑙SU8 of the SU8 waveguide is designed. The taper here is considered as a linear shape. One can find in Fig. 2(b) that the coupling efficiency curves reach their plateaus as long as the taper is longer than 600 μm. The design of the silicon inverse taper structure has been extensively discussed in literature [7]. As a result, we use a linear silicon taper with widths from 𝑤t = 80 nm to 𝑤si = 300 nm and a length of 𝑙si = 400 μm to achieve a coupling efficiency of about 97.2% for TE mode and 96.6% for TM mode in this section. Here, the height ℎsi of the SOI waveguide is 220 nm. The overall coupling efficiency of the whole structure from the SMF to the SOI waveguide is shown in Fig. 3(a), when the taper length of the polymer waveguide 𝑙SU8 is 800 μm. Due to the adiabatic nature of the present structure, the coupling efficiency exhibits a flat spectrum over a wide wavelength band. Theoretically, the best coupling loss of −0.4 dB with a PDL of 0.3 dB can be achieved in the proposed fiber interface. The coupling efficiency for a lateral misalignment between the SMF and the SU8 waveguide is also analyzed as shown in Fig. 3(b). The 1 dB misalignment tolerance, i.e., the amount of misalignment allowed for the coupling efficiency dropped 1 dB from the peak value, reaches ±2.4 μm in the present structure, thanks to the largely expanded mode profile at the end of the SU8 waveguide.
Fig. 2. (a) Coupling efficiency from the input SMF to the SU8 waveguide of different width 𝑤in and height ℎin . (b) Coupling efficiency of the 3D SU8 taper of different length 𝑙SU8 . Here, wavelength is 1550 nm.
Fig. 3. (a) Wavelength responses of the whole fiber interface structure from the input SMF to the final SOI waveguide. (b) Fiber misalignment tolerance of the structure at the wavelength of 1550 nm. The 1 dB range is also marked.
an easy and efficient spin-coating process to realize such a full 3D taper structure presented in Fig. 1(a). The critical process steps are sketched in Fig. 4, which essentially consist of two SU8 patterning processes. After fabricating the SOI chip, the first SU8 layer with a thickness of about 10.7 μm is patterned. This SU8 layer contains two dummy structures beside the path of the coupling waveguide. The spacing between the dummy structures increases towards the SOI inverse taper. Then, the second SU8 layer with a thickness of about 3 μm is spun on the chip. Notice that the nominal thickness of the second SU8 layer is much thinner than the first SU8 layer that has been fabricated on the chip. This high topology already on the chip causes a severe non-conform coating of the second SU8 layer during the spin-coating process. Especially, in between the dummy structures, the SU8 layer forms a bowl-like shape, whose thickness increases as the spacing between the dummy structures decreases. This effectively creates a vertically tapered structure along the path of the coupling
3. Fabrication and measurement Although the theoretical analyses discussed above for the present structure are fairly intuitive, its fabrication is of great challenges, especially for the 3D taper in the polymer waveguide. Normally, a 3D structure can be fabricated through gray-scale lithography [17] or mold embossing [18]. Alternatively, a multi-layered structure can be adopted to build a quasi-3D taper [19]. These demonstrations all require complex fabrication processes, and the best-achieved coupling loss to an SOI waveguide is limited to −2.8 dB [18,19]. Here, we adopt 2
X. Zhang, B. Chen, Z. Ruan et al.
Optics Communications 465 (2020) 125554
Fig. 4. Fabrication steps for the 3D SU8 taper. Sketches of the sample (a) after fabrication of the SOI circuits and the first SU8 pattern, (b) after spin-coating of the second SU8 layer, and (c) after patterning the second SU8 layer. Cross-sectional structures are also presented.
waveguide. In the area of the SOI structure, the dummy structures are far away from the silicon waveguide. The resulting thickness of the second SU8 layer would be 3 μm, which is the desired thickness for the SU8 waveguide over the SOI inverse taper coupler. However, on the other end of the coupling waveguide, the chip is mostly filled with the dummy structures. Only small trenches (∼6 μm wide) are made beside the target SU8 waveguide. Thus, the second SU8 layer would add up on top of the first one, and it would leave a total SU8 thickness of about 13.7 μm, which is the optimal height for coupling to the SMF. The final SU8 waveguide pattern, including the lateral taper and the straight waveguide on top of the SOI inverse taper, is then exposed, which gives a full 3D taper for the SU8 waveguide as shown in Fig. 1(a). We fabricated the proposed fiber interface structure according to the procedure discussed above. The SOI structures were fabricated using electron beam lithography and dry etching techniques on a standard SOI chip of 220 nm-thick top silicon layer and 2 μm-thick buried oxide layer. The first SU8 layer was spun and patterned using ultra-violate contact lithography, followed by hard baking at 250 ◦ C. The second SU8 layer was subsequently spun and patterned on the chip again using contact lithography. Before spinning of the second SU8 layer, the chip was treated by a short O2 plasma ashing, in order to increase the adhesion between the two SU8 layers. Finally, the chip was hard baked at 250 ◦ C to consolidate the whole SU8 structures. Fig. 5(a) and (b) show some microscope pictures of one fabricated chip at different processing steps. Each testing SOI structure consists of one proposed fiber interface connected directly to a grating coupler (GC) working for either TE or TM polarization. All the tapered dummy structures have lengths of 800 μm, which is the desired length for the SU8 waveguide taper 𝑙SU8 . Fig. 5(c) presents a three-dimensional mapping of the sample surface after the spin coating of the second SU8 layer. One can clearly see the variation of the SU8 thickness between the dummy structures. For characterization, the chip was cleaved perpendicularly to the SU8 waveguides for butt-coupling. First, the transmission spectra of the TE and TM GCs were measured using reference structures with two such GCs connected back to back, respectively. Testing structures for the present fiber interface were then measured, and its response was deducted by subtracting that of the corresponding GCs. Over the whole chip surface and between the fibers and the chip, index matching fluid was applied to avoid any interface reflections. Fig. 6(a) and (b) demonstrate coupling losses of the present fiber interface at different wavelengths for TE and TM polarizations, respectively. Responses for three identical structures on one chip are shown for each polarization. One can find that the best coupling loss reaches −1.0 dB for both TE and TM modes. For the worst case, the coupling loss is still better −2.3 dB. In the whole measured wavelength band, the coupling losses show flat spectra with a ∼0.8 dB fluctuation. Such fluctuation is also observable in the simulations shown in Fig. 3(a), although, with a smaller amplitude. This relatively large wavelength dependency in measurement results is probably due to a slight misalignment of the
Fig. 5. Microscope pictures of a fabricated chip. Top-views of (a) the finished sample and (b) the sample just after the spin coating of the second SU8 layer. The white dashed lines in (b) indicate the SU8 waveguide to be fabricated. (c) Three dimensional mapping of the sample surface in (b). The black dashed line indicates the center of the SU8 waveguide to be fabricated.
SU8 and the SOI waveguides [7]. The PDL for the best coupling case is also below 0.6 dB in the measured wavelength range as shown in Fig. 6(c). 4. Discussion and conclusion In this paper, we have demonstrated an efficient SSC structure for SOI waveguide based on a full 3D SU8 taper. Its fabrication, besides the standard silicon processes, consists of only two layers of SU8 spincoating and patterning. The first SU8 pattern does not contain any critical structures, i.e., no optical waveguides, and its alignment is therefore not important. Only the second SU8 pattern should be well aligned to the SOI structure. The critical dimension of all SU8 patterns here is the width of the SU8 waveguide on the SOI inverse taper, which is about 3 μm. The proposed SU8 structure could be fabricated much more easily as compared to quasi-3D structures, e.g., multilayer tapers [19], where the dimension control and alignment accuracy are important for all layers. To further study the reproducibility of the proposed 3D SU8 taper, we further tested the structures on a 2-inch wafer as shown in Fig. 7(a). 3
X. Zhang, B. Chen, Z. Ruan et al.
Optics Communications 465 (2020) 125554
Fig. 7. Reproducibility study of the 3D SU8 structure. (a) Mapping of a 2-inch wafer showing positions of the 9 testing structures. (b) Measured SU8 thicknesses of the 9 testing structures on one wafer along the central line of the corresponding SU8 waveguide, i.e., the black line shown in Fig. 5(c).
Fig. 6. Coupling losses of the fiber interface structure for (a) TE and (b) TM polarizations at different wavelengths, and (c) the corresponding PDL.
The measured surface mapping of 3D SU8 structures fabricated at 9 different places on the wafer is presented in Fig. 7(b). All the structures show the desired taper shape in the thickness direction with some small differences in detail. The working principle of the proposed structure, either the 3D SU8 taper or the SOI inverse taper, is based on adiabatic mode conversion, which intrinsically ensures a large fabrication tolerance as long as the taper is long enough. The SU8 thicknesses at the input facet vary from 12.4 μm to 14.7 μm. From Fig. 2(a), one can find that such a variation would only induce a decrease of <2% in the coupling efficiency. This test confirms that the proposed fiber interface can be adopted for a large-scale wafer process. Another advantage of the present SSC structure is that the chip can be easily sealed and its facets are polishable as shown in Fig. 8. Here, the edge of the chip was covered using a quartz plate and a low-index adhesive. The polished facet is clear and flat. This facilitates an easy and matured package procedure with standard fiber arrays. We believe the SSC structure introduced here can be used for high-efficiency and large-tolerance fiber-to-SOI-waveguide coupling interfaces.
Fig. 8. Polished chip facet encapsulated by a quartz plate and a low-index adhesive.
Technology Program (2017A010101023), Guangzhou Science and Technology Program (201707010444) and the Special Funds for the Cultivation of Guangdong College Students’ Scientific and Technological Innovation (‘‘Climbing Program’’), China. References
CRediT authorship contribution statement
[1] W. Bogaerts, R. Baets, P. Dumon, V. Wiaux, S. Beckx, D. Taillaert, B. Luysseart, J. Van Campenhout, P. Bienstman, D. Van Thourhout, Nanophotonic waveguides in silicon-on-insulator fabricated with CMOS technology, J. Lightwave Technol. 23 (1) (2005) 401–412. [2] B. Jalali, S. Fathpour, Silicon photonics, J. Lightwave Technol. 24 (2006) 4600–4615. [3] R. Marchetti, C. Lacava, L. Carroll, K. Gradkowski, P. Minzioni, Coupling strategies for silicon photonics integrated chips [Invited], Photonics Res. 7 (2019) 201–239. [4] G. Son, S. Han, J. Park, K. Kwon, K. Yu, High-efficiency broadband light coupling between optical fibers and photonic integrated circuits, Nanophoton. 7 (2018) 1845–1864. [5] D. Taillaert, F. Van Laere, M. Ayre, W. Bogaerts, D. Van Thourhout, P. Bienstman, R. Baets, Grating couplers for coupling between optical fibers and nanophotonic waveguides, Japan. J. Appl. Phys. 45 (2006) 6071–6077.
Xian Zhang: Validation, Visualization, Formal analysis, Investigation. Bin Chen: Validation. Ziliang Ruan: Validation. Weixi Liu: Validation. Pengxin Chen: Validation, Formal analysis, Investigation, Writing - review & editing. Yaocheng Shi: Validation, Formal analysis. Liu Liu: Conceptualization, Methodology, Supervision, Writing original draft. Acknowledgments This work is partially supported by National Natural Science Foundation of China (61675069, 91833303), National Major Research and Development Program (2018YFB2200200), Guangdong Science and 4
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