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Silicon Devices and Circuits
CHAPTER 2
Silicon Devices and Circuits E . A . Gutiérrez-D .,*
National Institute of Astrophysics Optics and Electronics Puebla, Méxic o C . Claeys and E . Simoen
IMEC, Leuven, Belgiu m Katholieke Universiteit Leuven (KU Leuven), Belgiu m 2 .1 . Introduction 2 .2 . The Bulk MOS Transistor 2 .3 . The Silicon-on-Insulator MOS Transistor 2 .4 . The Bipolar Transistor 2 .5 . Radiation Detectors 2 .6 . Circuits 2 .7 . Conclusions References
10 5 10 6 15 7 18 5 19 4 21 1 23 9 240
2 .1 . Introduction Electronic devices are fabricated with a wide variety of semiconducto r materials . Thus, these are high-speed devices made of III—V compounds, such as GaAs, InP, and AlGaAs, or photonic devices made of InGaAsP . However, an important spectrum of electronic devices are made o f II-based semiconductor materials, such as Si or Ge the bipolar transistor and metal oxide semiconductor field effect transistor (MOSFET ) transistors as well as the silicon-on-insulator (SOI) MOSFETs. The MOSFETs are widely used in the semiconductor industry for the design and fabrication of microprocessors for computer applications, for analog systems such as those for biomedical applications, or for low-powerlow-voltage applications . The bipolar in conjunction with the MOS are being used in the design and fabrication of bipolar complementary MO S *Now with Motorola-SPS, IC Design Center, Puebla, México . 105 © 2000 by Academic Press . All rights of reproduction in any form reserved . ISBN 0-12-310675-3/$35 .00
106
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
(BCMOS) systems, in which low-power consumption from CMOS an d high speed from bipolar are needed . The SOI MOSFETs have bee n traditionally used for systems exposed to hard irradiation, such as thos e in outer space or astronomy applications. Moreover, the SOI MOSFETs are by nature built in a high-resistivity substrate, which makes them ideal for high-frequency applications in which the parasitic coupling t o the substrate needs to be eliminated. On the other hand, the accelerated pace of the computer industry has pushed the development of near 0 .1-,um CMOS technologies to cope wit h the high-frequency requirements . However, Si is reaching the fundamental limits at which higher speed cannot be obtained by just shrinking th e channel length . Therefore, the semiconductor industry and researc h institutions have made an effort to incorporate higher mobility material s into the Si-based technologies . This resulted in the development of SiG e heterostructure bipolar transistors, widely known as SiGe HBTs . The HBTs have a larger carrier mobility and therefore a higher speed operation . The temperature dependence of these different Si-based devices i s reviewed in this chapter . We first discuss the bulk MOSFET by describing the CMOS technologies currently available, the electrical models fo r the three regions of operation, the impact of the parasitic effects such as series resistance, parasitic capacitances, quantum effects, polysilico n depletion effects, and electrothermal effects . In Section 2 .3 the different modes of operation of SOI MOS transistor s are reviewed, these include, inversion and accumulation . Also, device performance parameters such as the threshold voltage, the subthreshol d swing, the transient phenomena, and the floating body phenomena ar e analyzed . Alternative device concepts such as twin-gate or gate-allaround, are studied . In Section 2 .4 the standard, the polysilicon-emitter, and the SiGe HB transistors are studied . The radiation detectors are studied in Section 2 .5, in which a review of the optical properties is presented . Then, photoni c devices including photodiodes, Schottky barrier detectors, charge coupled devices (CCDs), and a-Si photodetectors are discussed . Section 2 .6 discusses circuits applications, such as CMOS-based digital and analog circuits, microprocessors, and imager systems such a s CCD arrays and focal plane arrays . SiGe HBT-based digital circuits ar e also reviewed .
2.2 . THE BULK MOS TRANSISTO R The MOS transistor has been (and continues to be) the most importan t semiconductor device in the semiconductor industry during the past 10
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years . The MOS transistor has evolved from a 5-to-3-µm CMOS technology in 1988 to a 0 .25- to-0 .1-pm CMOS technology in 1998 . The shrinkage is exponential and the number of transistors that are integrated per chi p has also increased exponentially (Fig . 2 .1) . Data gathered from articles and conferences published until 1998 are plotted in Fig . 2 .1 . However, an extrapolation based on experimental an d unpublished data that have demonstrated MOS transistors with mini mum dimensions of 40 nm (1) is done until the Year 2005 . Assuming the current pace is kept, a 70-nm CMOS technology could be commerciall y available for the Year 2001 . Under these conditions and assumptions, integrated systems with more than one gigatransistors and clock frequencies above 1 GHz are estimated to be available in the Year 200 1 (Fig . 2 .2) . Shrinkage of dimensions below 0 .1 µm poses an interesting challeng e not only for integrated circuit designers but also for device physicists . Wiring interconnection and power dissipation are very complex an d must be handled in a proper way to keep the chip temperature as clos e as possible to the room temperature and to minimize the cycle time due to wiring delay. Devices with nanometric dimensions are prone to second-orde r effects such as velocity overshoot, ballistic transport, subsurface positio n of the centroid of the inverted channel, and gate voltage-dependen t series resistance . Some of these effects are detrimental for the electrica l performance of the device, whereas others can be beneficial, such as th e velocity overshoot that enhances the device speed .
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In the following sections we discuss how the temperature impacts th e electrical performance of MOS transistors, the effects at the circuit / system level, and how effects pertaining to nanodevices are modified b y lowering the temperature . 2 .2 .1 . MOS Technologie s The physical structure of the MOS transistor has evolved through th e year as a response to the need to improve its electrical performance an d to reduce its parasitic effects . The most widely known structure is th e lightly doped drain (LDD) transistor, first introduced by Saito et al . (2 ) and intended to suppress hot electron effects by adding a buffer regio n to lower the magnitude of the internal electric field as shown in Fig . 2.3 . The LDD region is self-aligned to the gate, whereas the heavily dope d drain region is offset from the LDD with a spacer oxide . The internal distribution of the electric field in a conventional and a LDD MOSFET i s shown in the inset in Fig . 2 .3 . In the case of a conventional MOSFET, the peak of the electric field occurs at the drain–bulk metallurgical junction , whereas for the LDD the electric field peaks near the gate edge . The peaking of the electric field under the gate oxide thickness causes th e injection of electrons into the oxide; this charge injection degrades the electrical performance and in most cases leads to failure of integrate d circuits . With the LDD option the electric field peak shifts outside the active region, and the gate oxide, under the gate, becomes less prone t o becoming hot electron injected . Thus, the LDD has been the most suc-
2. Silicon Devices and Circuits
109
FIGURE 2 .3. A schematic representation of half of an LDD MOSFET and th e internal electric field E .
cessful structure and has remained in use for implementing MOSFET s with gate lengths from 1 .25 to 0 .1 pm . Other second-order effects have appeared with the inclusion of the LDD, for example, the reverse short-channel effect (3), the gate-voltagedependent series resistance (4), and the nonuniform substrate dopin g effect (5) . To alleviate these effects, other modifications to the structure of the MOS transistor have been proposed . Among the most popular structures in the industrial research are the delta-doped MOSFET (6) an d variants of it, such as the atomic layer doping MOSFET (7), the pocket implanted MOSFET (8), and the dual gate MOSFET (9) with its ow n variants (10—12) . All these structures have been implemented to improv e the threshold voltage control and subthreshold swing, to reduce short channel effects, to improve mobility and saturation current, and t o reduce capacitance and relative gate delay . Wann et al. (13) provide a detailed comparative study of these structures . A 10-nm MOSFET transistor has been proposed (14) . This structur e uses abrupt metal—silicon Schottky junctions as a source and drain and thus avoids short-channel effects . This proposal is interesting because it shows that the minimum channel length of 70 nm, which was predicte d for conventional MOSFET (15), can be overcome and thus opens the doo r for further miniaturization and development of nanometric devices . Furthermore, in 1995 a 40-nm n-MOSFET with ultrashallow source and drain junctions of approximately 10 nm was demonstrated for the first time (16) . With this 40-nm MOSFET, reliability with regard to degradation due to hot carriers was shown not to be a serious proble m for VDD 1 .5 V. The LDD structure with phosphosilicate glass sidewall s as spacers was implemented, and the gate oxide was grown to 3 nm , with a substrate concentration of 1 x 10 18 cm' . The resulting electric
110
E. A . Gutiérrez-D ., C. Claeys, and E . Simoen
threshold voltage was 0 .4 V, the subthreshold slope S was 87 .8 mV/dec. the transconductance g m was 371 mS / mm, and the drive current Id wa s 470 mA/ mm at Vd = Vg = 1 .5 V and T = 300 K . For the sake of complete ness, different 0 .1-µm and sub-0 .1-,um MOSFETs are mentioned here . To obtain highly nonuniform channel doping, indium has been use d as an alternative channel implant in 0 .17-gum MOSFETs (17) . A verticall y layered elevated drain structure for 0.25-,um CMOS technology was als o proposed to reduce hot carrier effects while keeping the supply voltag e at 3 .3 V (18) . On the other hand, to solve the problems of trade-of f between the short-channel effect and the performance enhancement o f sub-0 .25-,um MOSFETs, a recessed channel MOSFET structure called inverted-sidewall recessed channel was proposed (19) . Moreover, roomtemperature sub-10-ps CMOS ring oscillator delays have been reporte d using a 0 .07-,um CMOS technology with n-MOSFET cutoff frequencies fT of up to 135 GHz (20) . This has proven that sub-0 .1-,um CMOS is read y for multi-GHz digital applications and is also a strong candidate fo r high-speed data communications . There is another interesting approac h to improve the speed response : the use of SiGeC alloys in the channel of MOSFETs (21) . This has allowed an increase in the cutoff frequency o f up to 180 GHz at 77 K . Regarding low-temperature operation of CMOS technologies, th e LDD is the only one which has been studied and optimized to operat e at cryogenic temperatures : Examples are the work on 0 .25-µm CMO S devices optimized for cryogenic operation (22) and the work on LD D optimization for cryogenic operation (23) . In both cases, optimization was achieved at 77 K. In the first case, the technology was optimized t o obtain high-speed (22 .8 ps per gate) CMOS circuits at VDD = 1 V, where as in the second case the technology was designed to maximize ho t carrier device lifetime . In the following sections, the impact of temperature on the electrica l performance of MOS transistors will be analyzed . This analysis will consider deep submicrometer and nanometric devices and their relate d effects . 2.2 .2 . The Subthreshold Regim e The operation of MOS transistors in the subthreshold region is especially important for deep submicrometer devices and for low-voltage operation . Deep submicrometer and nano-devices must be operated at low voltages to reduce hot carrier effects and degradation . For instance, 0 .1-µm MOSFETs are operated at V DD = 1 .5 V to keep hot carrier generation low and improve reliability . Furthermore, the fabrication of 0 .1-,um MOSFETs requires the use of high substrate doping levels to keep good
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FIGURE 2.4. The inversion hole density ps versus gate voltage Vg for a p-MOSFET with three substrate doping concentrations Nb . The gate oxid e thickness TO is 14 nm for the three devices [replotted from Hu et al . (24)] © 198 0 IEEE . electrical performance, which implies a trade-off with keeping a lo w value for the threshold voltage . Calculations of the inversion hol e density p s for a pMOSFET (24) show that high substrate doping level s shift the p s curve to the right when plotted as a function of the gate voltage Vg (Fig . 2 .4) . It is important to note that the charge diffusion mechanism will b e more dominant, with respect to the drift mechanism, as the MO S technology shrinks to deep-submicron dimensions and as the suppl y voltage is reduced to 1 .5 V and lower . This is easily seen in Fig. 2.4 . (ps —Vg) plots in between 10 1 ' and 10 18 cm'3 bulk doping levels corresponding to typical technological parameters of 0 .1-pm MOS technologies . For this bulk doping level range, the V g voltage at which the ps —V g curve goes from the exponential increase to the saturation level lies i n the 1 or 2 V range, which means that a large percentage of the carrie r conduction in a 0 .1-pm MOS technology operated at VDD = 1 .5 V will b e due to diffusion. This can be confirmed by experimental results of a 0 .5-pm CMOS technology operated in the 60—200°C temperature range (25) . A very interesting feature shown in Fig . 2 .5 is the value of the Vgt i voltage at which the drain current is temperature independent . Figure 2 .5 indicates that for Vg < Vgti the Id current increases with T due to positive temperature dependence of the diffusion process, whereas fo r Vg > Vgti the current Id decreases with T due to the negative temperature
112
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen
FIGURE 2.5 . Experimental Id -Vg curves for a (W/ L) = 10/0 .5 n-MOST ET operated at VD = 0.1 V and T = 60, 80, . . . , 200°C . The current normalized to its value at 60°C is plotted on the right axis .
dependence of the carrier mobility. That is, diffusion of carriers dominates the Id current at the left of Vgti , and drift of carriers dominates the Id current to the right of Vgti . At V g = Vgti the transport mechanism s cancel each other, resulting in a bias condition in which the MOSFET i s temperature independent . When the temperature is decreased to that o f cryogenic temperatures, the Id current increases for Vg > Vgti and decreases for Vg < V gti . Thus, in the diffusion regime the leakage current due to thermal processes diminishes, enhancing the signal-to-nois e (S / N) behavior of the MOSFET at cryogenic temperatures . The use of discontinuous models is widely accepted in the integrate d circuit (IC) design field ; that is, a different mathematical function is use d for all three operating regimes of the MOSFET, and in most cases thes e functions have discontinuities at the border bias conditions in which th e transistor switches from the subthreshold to linear regime and from the linear to saturation regime . In the case of the subthreshold-to-linea r transition, it is a generalized practice to say that the I d curren t for Vg > Vth is completely due to drift and due to diffusion for Vg < Vth . This is the basic approximation used to derive simple electrical model s for the design of ICs . However, it is readily observed from Fig . 2 .5 tha t the diffusion process is still acting for Vg > Vth. In such a case
11 3
2 . Silicon Devices and Circuits
at Vg = V gti = 1 .2 V, in the linear regime of operation, 50% of the current is due to diffusion and 50% is due to drift . Thus, a crude assumptio n such as the one used to partition the operating regimes of the MOSFE T is no longer valid for submicron dimensions for which, due to the ver y short conduction path (the channel length), the distribution charge alon g the channel is never constant, and thus a charge gradient exists tha t helps the carriers to diffuse and drift along the channel. When an analysis or design of an IC is required to be done as a function of the temperature, the discontinuous model, even with th e smoothing functions used to smooth the transition regions, is no longer useful. Therefore, a fully physics-based and continuous model should b e developed and used for a proper analysis and design of ICs based o n submicron and nanometric CMOS technologies . Unfortunately, this is a complex task that requires solving the carrier transport equations b y numerical methods . Before taking on this complex task, one needs to fully realize that th e carrier transport in deep submicrometer MOS transistors is basically composed of two transport mechanisms : carrier diffusion and carrier drift . The driving force in the first case is the gradient of carriers, an d the electric field is the main force for the second mechanism . Thus, th e whole channel current I d of a MOSFET should be always written as . Id — (Idf
+
(2 .1 )
I dr)
where Idf is the diffusion term and Idr is the drift term of the current . How much these terms contribute to the whole current is not straight forward to determine . The evaluation of the Id current should be done based on the carrier transport equations, which are essentially th e Poisson's equation, the current continuity equations for electrons an d holes, and the current density equations for electrons and holes : div(grad klf ) = — div(Jn)
E
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= q • R( 1F,
ND + — NA
n, p)
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In =
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I p = — q • (u,, • p . grad'F
+ D p . grad p)
)
(2 .2 ) (2 .3 ) (2 .4 ) (2 .5 ) (2 .6)
where ND + and NA - are the ionized donors and ionized acceptor concentrations, respectively, n and p are the free electrons and holes, th e function R accounts for the Shockley-Read-Hall generation/recombination and impact ionization, D is the diffusion coefficient, and µ is the
114
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
FIGURE 2.6 . Schematic representation of the channel of a MOSFET . carrier mobility. The potential in the semiconductor is represented by T . These sets of nonlinear coupled equations must be solved by discretizin g the Poisson and continuity equations . The Gummel's method is preferred to discretize the current density equations because it helps stabilize the numerical process . The Poisson's equation is first discretized by Newton's method and then linearized for each decoupled iteratio n loop . This procedure helps to accelerate the convergence (26) . A detaile d description of the numerical calculation can be found in Ghazavi an d Duen Ho (27) . For the case of a MOS transistor, Eqs . (2 .2)—(2 .6) give the solution fo r the distribution of carriers, n and p, and for the potential T . These three parameters are then used in the DC state solution to evaluate th e diffusion and drift currents in the channel of the MOS transistor (Fig . 2 .6) . Thus, the whole Id current must be evaluated by integrating fro m x = xs to x = x d or using an equivalent nomenclature from 0 to L : L
‘vd
Id • dx = W
Ts
,u( — Q i )dtI' +
kT
Qid
,u,dQ i
(2.7 )
Q is
Although the two current terms are position dependent, the whol e current is independent of x ; therefore,
f
kT Qi d lu( — Qi)d + — 0Q. q Qis Ts
Wd
Id - L
Q (2 .8 )
In the source/drain-to-bulk metallurgical junctions the potentia l could have some nonmonothonical variation due to the presence of th e reverse-biased source/drain—bulk junctions; therefore, one should be
2 . Silicon Devices and Circuits
11 5
cautious when defining the physical borders for the beginning and en d of the channel. It should also be noted that the thickness of the inversion layer, in which the inversion charge Q i is evaluated, is finite, and thus th e evaluation of Eq. (2 .8) should be done as a function of the depth . On e can determine where the inversion channel ends by solving self-consistently the Schröedinger—Poisson equations . Deep submicrometer devices with ultrathin gate oxides and high bulk doping levels pose an additional problem the quantization of the inversion layer (28) that moves the maximum of the inversion layer toward the bulk and thus makes th e evaluation of the channel current I d difficult . Furthermore, as the channel length decreases below 0 .25 µm, the conventional drift-diffusion model (DD) fails to predict the electrica l performance . For dimensions below 0 .25 µm the lateral electric fields an d their gradients in the device can be of considerable magnitude, affectin g the electron energy distribution and making the electron energy t o deviate far from its value at thermal equilibrium . As a consequence, th e carrier temperature can be much higher than the lattice temperature . Thus, energy transport should also be considered when evaluatin g charge transport . The energy transport has been considered in simula tors based on the Monte Carlo method (29) . However, this method i s time-consuming and, hence, not practical to technology device designers . A more pragmatic approach is based on the hydrodynamic equation s (30) . However, the fully numerical solution to hydrodynamic equation s also requires a large computational effort, which makes this approac h unsuitable for the design of gigaintegrated systems . As the gigaintegration era approaches, a trade-off between deepsubmicrometer MOSFET modeling and simple models for VLSI/VLS I (Very Large Scale Integration/Ultra Large Scale Integration) design i s needed . To our knowledge, there have been only a few attempts to solve th e problem previously described . Ma and Kuo (31) proposed an analytical model with consideration of energy transport ; however, their results are not sufficiently accurate because the electric field in the channel is no t used in a self-consistent way with the energy, and thus loses validity and accuracy . Sim (32) noted Ma's model discrepancy and solved the energ y balance equation by considering the electric field in a self-consisten t way . This improved the accuracy of the results . However, due to the complexity of electric field dependence of the carrier mobility, Si m assumed an average value for the carrier mobility in the channel . Thi s assumption made this model lose its physics meaning . The carrie r mobility µ depends directly on the effective mass m*, and m* depend s on the energy distribution; hence, /2 cannot be decoupled from the
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energy balance equation . Recently, Jang and Hu (33) proposed a n analytical model for the drain current of submicrometer and dee p submicrometer MOSFETs . The model fits very well with the experimental data used in that work . However, this model is only valid for th e linear and saturation regions, and hence the subthreshold regime canno t be predicted with this model . Moreover, this model fails to predic t properly the temperature dependencies of the different operating regimes . We tried this model with experimental data for a 0 .5-pm CMO S technology in the 300–4 .2 K temperature range . First, we tested the Id —V g characteristics at low Vd and at different temperatures to search for the temperature dependence of the charge diffusion mechanism . Second, we increased the Vd voltage in order to diminish the diffusion mechanis m and enhance the drift mechanism . Because the Id current is composed o f both transport mechanisms, one expects that by sweeping the Vg voltage from low to high values, the carriers will first be moved by diffusion an d then by drift . Thus, there must be a Vg value at which both transpor t mechanisms have the same weight and the I d current becomes temperature independent . This is so because the diffusion increases with temperature, whereas the drift decreases . The experimental curves are shown in Figs . 2 .7 and 2 .8 . For both cases, Vd = 0.23 and Vd = 3 .5 V, there is a V g voltage of about 1 .0 V at which the Id current is temperatur e independent . Thus, we can say that Vg ,: 1 .0 V is the border betwee n diffusion and drift . However, note that the threshold voltage V T of this device is about 0 .6 V. This shows that diffusion is still important for
2 . Silicon Devices and Circuits
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FIGURE 2 .8. Experimental results of a (W/L) = 10/0 .5 n-MOSFET operated at Vd = 3 .5 V, with T = 300, 250, 200, 150, 100, 80, 60 K . The dashed lines correspond to the normalized Id current.
Vg
> VT . At Vg : 1 .0 V, the transistor is operating in the linear region ; thus, a well-defined border for the subthreshold-to-linear transitio n cannot be categorically given . Another relevant feature is that for V d = 0.23 V and Vg s larger than 1 .5 V, the Id current does not continue to increase for temperatures belo w 175 K but rolls off. For Vd = 3 .5 V the I d current for V g > 1 .5 V is alway s increasing as temperature reduces . This effect suggests that the surfac e scattering is reducing the carrier mobility at high transversal electri c fields, high V g voltages, and low Vd voltages . However, the temperature dependence of the surface scattering mechanism is not well-known, an d thus we cannot categorically affirm that surface scattering is responsibl e for the roll-off of Id . The other possible explanation for this effect is tha t the diffusion transport for low Vd s is still active for high Vg s and thu s compensates for the increase of Id due to the enhancement of carrie r mobility at low T. The carrier profile in the 0 .5-pm n-MOSFET wa s investigated through simulations with PISCES (a commercial devic e simulator) (Fig. 2 .9) . The electron concentration in the channel n (Fig. 2 .9, plot 3) is almos t independent of the position x for an uniform bulk doping (plot 2) an d has a considerable gradient (plot 4) for nonuniform bulk doping (plot 1) . The nonuniformity of the bulk doping in the channel is caused by th e proximity of the source and drain diffusions . On the other hand, as the channel length is reduced this mechanism becomes more pronounced .
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Based on the previously discussed reasons, experimental evidence , and considering that "compact models" (those used in the simulation o f integrated circuits) rely heavily on fitting parameters, the value of thes e parameters will likely be appropriate for one fabrication process bu t totally inadequate for another . We do not develop an electrical mode l but rather focus on two of the most popular models for the subthreshol d regime . The original model for the subthreshold current Idsth was based on a long-channel transistor (34) .
I
_ dsth —
(J(r)2
(Po"ç")
gESi NB
21, eff
e
q ~ vg - vT) r~kT
_
1—
e(
gVds nkT
(2 .9)
WB
where the slope factor j is taken a s ~ = 1 +
1jqcs i
2C oX
OB
(2 .10)
This model fails to reproduce experimental data of submicromete r devices since the bias-independent cofactor before the exponential ter m
2 . Silicon Devices and Circuits 2 .3
11 9 40
@L=07 p m
.2 — 0
r
t @L=0. 3 pm
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O
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o El
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.
=
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=
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=
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50
100
150
Temperature, T
vs..; 200
25 0
0
IC I
FIGURE 2 .10. Measured data for the parameters ri and i of a 0 .35-µm CMOS technology . The gate oxide thickness T o . is 10 nm, and the bulk doping level NB is 6 .8 x 10 17 cm'3 [data from Murphy (35)] .
in Eq . (2 .9) gives a value much lower than the experimental one . This i s remedied by using a multiplicative factor i that, according to experimental data, decreases with decreasing channel length and temperature , tending to a common and constant value as temperature increases (35) . The predicted temperature dependence of the slope factor (Eq . 2 .10) i s only given through the bulk potential 0B, but experimental data sho w that 17 is length dependent. This is further complicated as temperatur e varies . The temperature dependence of rj is much stronger as the channe l length is reduced (35) (Fig. 2 .10) . For the 0.7-pm n-MOSFET, zi closel y follows (Eq . 2 .10), but for the 0 .3-,um n-MOSFET the deviation from the predicted value is considerable . Transistors with intermediate length s were also studied, but for the sake of clarity their results are no t presented . The transistor with L = 0 .6 ,um follows (Eq . 2 .10), but fo r L = 0 .5 µm and L = 0 .4 pm the deviation from theory is evident . The effect observed for both 11 and t is similar when the temperature i s lowered . The factor ii is indicative of the turn-off characteristics for the transistor . The lower the value of rj, the faster the transistor switche s from on to off or vice versa . Klaasen et al (36) proposed a model that, with a proper choice of parameters and considering the threshold voltage shift due to draininduced barrier lowering (DIBL) and geometry, fits the experimenta l data very well . However, the dependence of the slope factor wit h
E . A. Gutiérrez-D ., C . Claeys, and E . Simoen
120
channel length is not included nor mentioned in their model : I
dst
=
Weff
I
1°
L eff eff
e[q/MkT(Vg – VT)][ 1 –e(-q/kT(Vd) ]
(2 .11 )
where the slope factor M is given by
M=1+
m 1/2 (/)B
+
(2.12) Vs B
where VsB is the source-to-bulk voltage, and 1 0 and m are fittin g parameters . For the simulation of ICs using SPICE, a popular model is BSIM (37) , which is a semiempirical model also based on fitting parameters . This model reads Idst
(kT)2
e 1 .8 ,e[ q/nk T (Vg – VT)] [ 1 – e(- q
ß
q
/nk T(Vds) ]
(2 .13 )
The slope factor n is assumed to be Vd S dependent, which is correc t based on the device physics, but it does not take its temperatur e dependence into account : n = (no + nBVSB + nDVds)
(2 .14)
where no, n B , and n D are fitting parameters . Both models for the subthreshold current analyzed previously can b e used to fit experimental results, but only if Io , m, and n are adjusted a s a function of temperature . Even with the temperature adjustment, thes e parameters have different values for different technologies . This i s shown in Fig . 2 .11, in which the subthreshold slope S is plotted as a function of T for the 0 .5- and 0 .7-,um CMOS technologies :
S=
dVg d lo g(Idst )
(2 .15 )
The Klaasen and BSIM models can be used to predict the behavior of S as a function of temperature, but only if the fitting parameters Io, m, and n are modified for every temperature . The fitting for temperatures below 150 K loses accuracy . The accuracy can be improved for one of thes e technologies, but it becomes worse for the other . This indicates tha t neither of these two models is universal . 2 .2.3 . The Linear Regim e This region of operation derives its name from the linear Id —Vd characteristics as shown in Fig . 2 .12 . An imaginary line (the dotted line in Fig .
2 . Silicon Devices and Circuits
121
r—,
•• •
.b
u
100
_
r r r r
90 80
• o •
-~ ^,
•
~
60
r
r,
l
r,
r r
1,
r,
r
r
r
r
r
l„
r
r
r
r
r
r
q L=0 .7 pm
-
~
-
- model
H H_
_
50
-
•
_
40 LO00000°000
. .c 30
c%
J
O L=0 .5 p m
70 . .~
I,
20
• 0
q oq ~YT„ ' 50
II
^
o
11
i
I
100
1
,
1
r
150
200
Temperature, T I K I
,
,
250
I
, -
300
35 0
FIGURE 2.11. Measured (symbols) subthreshold slope S for the 0 .5-µm and 0 .7-µm CMOS technologies, biased at V d = 0 .23 V, and calculated values usin g Eq . (2 .9) .
2 .12) borders the linear regime and the saturation regime . However, fo r very short transistors the current in the linear regime does not follow a linear behavior. The derivative of the Id —Vd characteristics is shown i n Fig . 2 .13, from which can be seen that the derivative Ai d / A Vd (i .e., the conductance) is not constant but is always decreasing with V d . O n
1 .0 104 V =4 V g
linear regime
V =3V g
-
V =2V bR
~-'
V=1V s
0 .0 1(~
1
1
0 .0
0 .5
1
1 , 1 .0
1
1
1 .5
1 „ 2 .0
1
1
1
2 .5
1
1
1
1
3 .0
1
1
-
l
3.5
Drain voltage, V o IV ]
FIGURE 2.12 . Measured Id —Vd characteristics of a (W/L) = 10/0 .5 n-MOSFE T operated at T = 300 K.
E . A . Gutiérrez-D ., C. Claeys, and E . Simoe n
122 150 .00
_
>
d 100.00 0
__
U
r...+
U
_ __
2V
^ _
=
50.00 --
O
V
_
3V
-
0.00
0 .0
-
g
0 .5
1 .0
. . ... 1 .5 2 .0 2 .5 Drain voltage, Vd (V ]
3 .0
3 .5
FIGURE 2.13 . Measured conductance G(AId /AVd) of the n-MOSFET of Fig. 2 .12.
the other hand, the border between the linear and saturation region s vanishes so that it is unclear where the saturation begins . The nonlinearity is due to the charge sharing effect (38) . As the channel is shrunk, a larger proportion of bulk (or substrate) charge is controlled by the drain and source and less by the gate ; hence, the surface inverts more readily. For device modeling purposes this effect can be taken into account by introducing the "charge sharing factor, " FOE , which indicates the proportion of substrate charge controlled by th e gate . This factor is evaluated from the body effect constant y
Y =
.\/2ESi qNB
(2 .16 )
Co x
that is extracted from calculated values of the threshold voltage fo r different bulk voltages . The average bulk concentration of a long-channel transistor is taken as indicative of the "real" average bulk doping . Measurements on shorter transistors produce a smaller value for y an d thus a smaller bulk concentration. FOE is the ratio of the average bul k concentration of any transistor to the one obtained from the longes t channel transistor. The extracted Fa factor for n- and p-MOSFETs is shown in Fig . 2 .14 . The Fa factor plotted in Fig . 2 .14 was extracted by taking a 20-,u m MOSFET as a long-channel reference, but the bulk concentration fo r these transistors was not very different from that of the ones wit h L = 2 µm. It is clear that n-MOSFETs are more affected by the charge
2. Silicon Devices and Circuits .E
1 .2
►
b
123 (
I
~
O p-channe l 1 .0 — _
ô
~
q n-channel e,
0 .8
~
ii
-
0 .6
~
I~
V
_
FA ~ a~
to Û
0.4 u
0 .2 0 .0
0 .5
I .O
2.0
1 .5
Channel length, L pm (
FIGURE 2.14. Extracted charge sharing factor Fcs evaluated from experimenta l curves of transistors of both channel types . sharing effect than are p-MOSFETs. Because the Fcs factor is only a multiplicative factor that adjusts the model to extract the threshol d voltage, its temperature dependence depends on the model used . Thus, the models by Klaassen et al ., and to a certain point the one used b y BSIM are based on the charge sharing effect . In the first case, the surfac e mobility is considered to be degraded by both the transversal and th e longitudinal fields and by an interaction of the square of the fields . Thus, the effective mobility is given b y lu eff -
1+
8 A (Vgs
_ VTKL)
+ OBVsb + eCVds +
9D (
V
gs — 2Vds)
2
(2 .17)
with 9 C
1
(2 .18)
Leff Ec
where Ec is the "critical field" value for velocity saturation, which i n practice is taken as a fitting parameter, which makes 9c also practically a fitting parameter . The model for the drain current in the linear regime i s then Id =
(V
1
gs
VTKL )
+ O A (Vgs — VTKL)
Vds
+ 9 BVsb
2 (1
+(S ) V ds2
+ 9C Vds + 9D
(vgs- 1/2vds)2
(2 .19 )
In this model, the threshold voltage is given b y VTKL — VTS — S(L eff) Vds 1/Os
+ Vsb
(2 .20)
E . A . Guti érrez -D ., C . Claeys, and E. Simoe n
124
The DIBL effect (discussed later) is modeled through the function s ( L eff ), and VT S is the zeroth-order threshold voltage measured at the source an d given by VTS — VTO
+
Yi [N/Os
(2 .21 )
+ Vsb — .\/Os ]
where y i is the body effect constant defined as its value for a longchannel device, y i °°, and as the change in its value as the channel lengt h and width are reduced, AyiL and DYiW , Yi = Yi
—
(2 .22)
DYiL+OYiW
For Vsb = 0 V, the model for the threshold voltage reduces to VTKL — VTO
[S(L eff)
A]Vds
(2 .23)
In the BSIMs model, mobility does not include a field-squared term bu t only degradation due to the transversal field and velocity saturation du e to the longitudinal field (2 .24)
U1
[1 + U0 (V— VTBS) ~ 1 + gs
V
Leff eff
where the threshold voltage VTBS is defined as VTBS —
VFB
K1 .3 (t)S +Vsb — K2(OS
+ +
+
Vsb) nVTVds
(2.25 )
The DIBL parameter rI VT is also a function of the transistor potential s 11VT — 11z
+
?1BV sb
+ 11D( Vds
(2 .26 )
Vdd)
K 1 is equal to the body effect constant y, and K2 accounts for the dual y factor . The dependence of current on back gate bias, which in Klaassen' s model is accounted for by the term O B Vsb , is taken into account in the fitting parameters U O and U 1 : (2 .27)
U0 = U0Z + UOB Vsb U 1 = U1Z + U1 BVsb + U 1D (Vds
(2 .28 )
Vdd)
where all the U's are constants as fitting parameters . Using all the previous definitions, the drain current for the linea r region used in BSIM is a I Ids
=
Weff ( PeffC"
Lff
(Vgs
VTBS) Vds
[1 +U V—V TBS) ~ 1+ 0 ( gs
Vds 2
(Ui (Leff/
`
( 2 .29
Vds
)
2 . Silicon Devices and Circuits The body effect coefficient value is calculated from
12 5
"a" has the same physical origin as 6, but its a=1+
gK
2 .\/4) S
i
(2 .30 )
+ Vsb
where 1 g= 1
1 .744 + 0 .8364 (O ~~ss
Vsb)
(2 .31 )
Both the Klaassen and BSIM models are able to reproduce experimenta l results at room temperature within an overall rms error of under 2% fo r 0 .7-, 0 .5-, and 0 .35-,um CMOS technologies. In the case of a 0 .5-µm CMO S technology, the values of the parameters used in the model is listed i n Table 2 .1 . The values of the parameters used for the simulations were extracte d using an optimization program called EXPER (39), which is able to fit a model of more than 25 parameters . However, when using optimizatio n programs one has to be very careful with the extracted values . Due to the nature of these programs, which only fit experimental data t o supplied database files, the results can be completely out of any physic s logic. Therefore, a background on device physics is a prerequisite t o better use and take advantage of these programs . The optimization program can also be used to extract the values for the parameters a t different temperatures . However, the results are not physics base d because they are mere fitting parameters. Table 2 .1 Values of the Parameters Used to Simulate a (20/0 .6) n-MOSFET in the Linear Region Klaasen's model VTO
= 0.7145 V
s ( L eff )
~s
= 9 .989 x 10 -2
µo = 385 .12 cm 2 / Vs
BSIM model VTO
= 0 .72273 V
rlvT
= 2 .9332 x 10 - 2
µo = 484 .16 cm 2 / Vs
LD
= 0.12065 µm
LD
eA
= 0 .31105 V -1
U0 = 0 .31699 V - 1
Oc
= 0.3312V -1
U 1 = 6.4316 x 10 -2 V -1
eD
=1 .9895 x 10 -2 V — 2
NB =2 .00 x 10 1 7 cm -3
= 0 .0385 µ m
NB =2.00 x 10 17 cm - 3
126
E . A . Gutiérrez-D ., C. Claeys, and E . Simoen 0 .8
... um -
►_,
0 .8 _ a.; • ra'
_
i
expected theoretica l result
`
hard
I freeze-out
I
o9
o
2
g.
8
• O
. _
10
III~II1IJII
0 .7
ô
E-H
I
soft freeze-out
o
^O , O * .0 0 Sk I O 0.6 1 • ~ 0 50 100
7 IA)
5
>
O
experimental V .1 . 1
I
I I 150
I
I
4
1
I
y
3 300
I I~
200
Temperature, T [K J
250
FIGURE 2 .15. Measured threshold voltage V T as a function of temperature T for a (W/L) = 10/0 .5 n-MOSFET operated at Vds = 0 .23 V. The Id current a t Vg = VT is plotted in the right axis .
One of the more important electrical parameters for the IC designer s and device physicists is the threshold voltage, V T , which is commonly extracted by fitting a straight line to the point of maximum transconductance gmmax in the Id —V g curve and taking its extrapolation to the V g axis as VT . Following this extraction procedure, the V T voltage as a function of temperature T for a (W/ L) = 10/0 .5 n-MOSFET is plotted as shown in Fig. 2.15 . For the sake of completeness, the I d current and transconductance g m as a function of temperature are plotted in Fig . 2 .16 .
450 =-•
, "T7
400
~.i
40
II
0
~
e ~~ i I'
o
_
k-1 o
35 A)
30 3 crc
>), V
0
50
100
150 200 250 Temperature, T ( K [
300
35 0
FIGURE 2 .16 . Measured Id current and max transconductance gmmax as a function of temperature for V g at which g m reaches its maximum value .
2. Silicon Devices and Circuits
12 7
Note that the behavior of the threshold voltage V T at temperatures below 100 K deviates from the theoretical predicted behavior . This can be attributed to freeze-out effects or to the combination of DD mechanisms that first increase the current as temperature is lowered and the n diffusion takes over to reduce the current for temperatures below 100 K . Examining the Id current at Vg = VT , one observes that the magnitude o f the current is always decreasing as temperature is lowered, which is a clear indication that at Vg = VT most of the current is due to diffusion . The effect is more clearly seen in Fig. 2 .16, in which the Id current and maximum transconductance gmmax are plotted as a function of temperature. At this bias condition, both diffusion and drift interplay to give the bell shape to the Id —T curve . 2 .2 .4 . The Saturation Regime In general, the voltage at which the transistor enters into the saturation regime, Vdsat is defined as the Vds value at which the inversion laye r charge at the drain side is zero . As previously discussed, the linear-tosaturation border vanishes as the channel becomes shorter . This make s it more difficult to find the value for Vdsat . Thus, to improve a drai n current model, Vdsat needs to be calculated properly . The two models described here have different definitions for this voltage . Klaassen et al . model the current in saturation a s Idsat
VT ) Vdsat( 1+ b) ,1 a ln e+ e + 1 + c E Vgs
[(Vus
= f~
Vdsa t
Vds
(2 .32)
p
The term in the second brackets accounts for the channel conductance i n saturation and is modeled by a Vds -dependent effective channel length : Leff '
= Leff L
1 + a In 1 +
_ Vds
Vdsa t
- 1
(2 .33)
aVP
where Vp and a are fitting parameters. The Vdsat voltage is obtained fro m equating Eqs . (2 .19) and (2 .32) for Vds = Vdsat, which gives a cubi c equation in Vdsat ,
Vdsat 3 + 2 eß —2 8D
+4
8D
[1 +0AVgs
Vgs -4V gs— +OBVsb )
8
4
VT (1 + b)
Vdsa t2
Vgs VT °EVgs VT + 1 + (S + 9.(I + 6 +
((1 +6AVTOBVsb) 8D
VT
(1 + 6)
+ Vgs 2
=0
2 Vgs
Vdsat
(2 .34)
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen
128
which has three roots . The roots or solutions to this cubic equation ar e gate voltage dependent (35) which means that only one of the roots wil l be purely real for the complete voltage range . When the root is obtaine d from the maximum of Eq . (2 .19), the Vdsat value is always smaller tha n the one predicted by Eq. (2 .34) . This implies that the current will be smaller than that in the linear region, and the conductance will b e negative in this transition region, which is not reasonable on physica l grounds . Another inconvenience of the analytical solution of Vdsat is the many conditional clauses needed to discern the real root from th e complex roots and to evaluate cubic roots, which makes it more computer intensive. In the BSIM model, the current in the saturation regime is given b y (Vgs — VT) 2 Idsat —
ß 2aKI1 + U V 0 ( gs
—
VT) ]
(2 .35)
where K is calculated from K = (1 +V+ .\/1 + 21/c ) 2
(2 .36)
and Vc is determined from the value of the fitting parameter U 1 :
=
(Vg .
U1 L eff
VT
a
(2 .37 )
In this model the saturation voltage is defined as the point where the I d current is limited by velocity saturation, and it is given b y = Vdsat
( Vgs
VT)
a /K
(2 .38 )
Channel length modulation is not taken into account directly, but th e experimental curves are well modeled in this region through the DIB L parameter. There is an experimental method to extract Vdsat . The method proposed by Jang et al . (40), based on general device theory, is virtuall y independent of any device model and quite versatile and applicable fo r small-geometry MOS transistors . This method is based in the construction of the function G : U(1/gds) G=gds
ôVds
(2 .39)
2 . Silicon Devices and Circuits
7 <
-
G@V
•
~,
1~
=I V
g
ô 10 -3 -
N--4, +s 6 10 -3 ~
r
129
- 8 V ~is
\
–
G@V
=2 V
~
_ 4 _ -
G~~ V =4 V~ 2 r
_
o
n. i
~,
'
'
w~l -~~.. . ....■~■i~■11111BRW —
0 .0
~
G(~~V „ =3V r
_
0 10°
6
-
` 4 10 -3 –
2 Io-'
.t(
~
0 .5
1 .0
=
~..-~Jw~` _ 1 .5 2 .0 2 .5
Drain voltage, V IV [
r 3 .0
- 0 3 .5
FIGURE 2.17. Experimental Id– V ds characteristics and function G of a 0 .5-µm n-MOSFET at 300 K . The open circles correspond to the extracted Vdsat values , and the dashed line is the fitted Vdsat .
where
gds
is the drain-to-source conductance defined b y gds
s
aid s
Vd s
(2.40)
The function G is an increasing function of the V ds voltage when the MOS transistor operates in the linear region, whereas it decreases wit h Vds when the transistor enters into the saturation region . Therefore, the Vds voltage at which the slope of the function G is zero should be equa l to the Vdsat voltage . An example of this method is shown in Fig . 2 .17 . The function G peaks at different Vds values for different Vg values, with each peak corresponding to a Vdsat voltage for a particular Vg voltage . The extracted Vdsat values (Fig . 2 .17, open circles) and the superimposed Vdsa t curve are also shown . This method is also used to extract Vdsat as a function of temperature . (Fig. 2 .18) . Note that the experimental Vdsat deviates from the one theoretically expected (continuous line) . The experimental Vdsat corresponds to the difference between the theoretical Vdsat and the VTd voltage . The VTd voltage is known as the drain threshold voltage (41) , which is due to the combination of freeze-out effects in the gate-tosource/drain overlapping regions . The freeze-out of the overlapping region makes a potential barrier appear at the gate edges, which in turn s becomes gate voltage-dependent series resistant, and makes the I d — Vds characteristics deviate from a linear behavior (Fig . 2 .19) . The Id —Vds
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
130 0.85 s-
_ 70
..
~.. .
0 .80
o
0 .75
.
-
o
o experimental o Vdsat
0 .70
e == ..~~ =.
A
_ .•i-:/'
~
0 .60
0
„►,I
,
.
V
/
a
O
= 40 Â. ~ o 30 ~-
~
=
`is`'t
theoretical ~
250
:1)
=- 20
°~
=-
a
10
~.to„b,oÔO
200 100 I50 Temperature, T [ K l
50
►~
50
=
o
0 .65
0 .55
60
rd
300
FIGURE 2.18. Extracted Vdsat as a function of temperature T of a 0 .5-µm n-MOSFET biased at Vg = 2 V. The open circles are the measured drain threshol d voltage VTD , and the continuous line is the theoretical Vdsat . curve does not increase linearly from 0 V, but it has a quasi-exponentia l behavior, until Vds reaches VTd , from which a linear behavior can be extrapolated . In the saturation regime the Id current is almost fully dominated b y drift; hence, the Id current and the conductance gds (aId / WVds ) should increase as temperature is lowered . Their experimental behavior i s shown in Fig . 2 .20 . Both Id and conductance g ds have a step increase at T = 30 K, which corresponds to the onset of strong freeze-out and th e occurrence of the kink effect (42) .
_
i
, linear fit
4 ►••-1
_
2
•~
'
3 _
(u
1
1
>
r
__- . - . . = -
-
,~
experimental I d
_ _
0 .0
_
__ : % '
_
V
0.2
0 .4
0 .6
0 .8
1 .0
Drain voltage, Vds [ V ]
FIGURE 2.19 . Measured I d –Vds characteristics of a 0 .5-µm n-MOSFET operate d at V g = 2 V and T = 4.2 K. The linear fit (continuous line) is extrapolated to th e Vds axis to get the VTd value .
2 . Silicon Devices and Circuits
~ M--~b a)
C -.
9 .5~..~ 9 .0
13 1
I I,1I
OA
_ 2 .510-4
8.5 e. ._`_
8 .0 7 .5
,
e....e
7 .0
.
6 .5 6 .0 5 .5
t
0
1
3 .010 — 4
„
1
1
1
1
!
50
~
1
l
100
l
1
~
1
_
t I I
150
2 .0 10-4
_ I .5 104 _
—>-
I
1
200
I 1
~ -
~
1
1
I
250
1 .0 10 - 4
o
a ~ (Al
,
5 .0 10- 5 30 0
ly
Temperature, T 1K ]
FIGURE 2.20. Measured I d current and conductance g ds of a 0 .5-µm n-MOSFE T biased at Vds = Vgs = 3 .0 V .
The two models described here are a consequence of multiple approximations and simplifications . First, it is assumed that the channel is everywhere strongly inverted, but this condition is not necessarily me t near the drain side as Vds increases since the charge sheet approximatio n breaks down . Second the model considers that current goes to zero a s the gate voltage approaches the threshold voltage from above, and it ca n even be negative for large values above threshold if Vds is large, which is not the case owing to the subthreshold current . Thus, the three region s of operation analyzed here have to be merged together so that curren t and its derivatives with respect to terminal voltages, which represen t conductance and transconductance, is continuous when going fro m region to region. Due to the complexity of using two-dimensional (43) and numerica l solutions (44, 45) to satisfy continuity between regions of operation , limiting functions are used to force the subthreshold current to remain constant above a determined value of the V g voltage . This constan t component is then added to the strong inversion current, in both th e linear and the saturation regions . In Klaassen's model, the subthreshold current is modified to I Idst =
(
Weff)e[ g/MkT(Vgs — VT)][1
— e(4/kT(vs) ]
Leff
1
+z
Weff e q/MkT(Vgs — VT )
(2 .41 )
L ef f
Here, z is another fitting parameter with a value of approximately 0 .5 . This expression predicts that as Vgs increases above the threshold
132
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
voltage, the Idst current tends to _2 [1 — e- ( q/k T (V ds )dst ]
I
z
(2 .42)
whereas for low values of Vgs, Idst tends to the value given by Eq . (2 .11) . This model works well for low values of V ds ; however, since th e current always saturates to this value, for large values of V ds the curves cannot be merged with the ones predicted by Eq . (2 .19) and thus current is modeled as discontinuous in this transition region . In addition, whe n modeling Idst as in Eq . (2 .41), the value of the limiting current also affect s the characteristics for low Vgs values . In the BSIM model, the expression for the subthreshold current Idst is modified to I dst
_ Idst • Ilim I m Idst + u
(2 .43)
where the limiting current Ilim is given b y
Ilim = 21 ß 3
kT
2
(2 .44)
q
For large values of Vgs , the Idst current tends to Ilim, whereas for lo w values Idst tends to Eq. (2 .13) . The transition region is well accounted fo r by this model, with only a slight discontinuity . For the linear-to-saturation transition the Klaassen's model present s a discontinuity when passing from the linear to the saturation regions i n general due to the way in which the Vdsat voltage is defined . In order to avoid this discontinuity, it is suggested that the Vdsat voltage be taken a t the value of the maximum current predicted by Eq. (2.19) : Vdsat = — 6(1
6)2
+ b) + .\/ 6[6(1 + [(1 +
+ 2(1
5)(0 c —
+ ô)(Vgs — VT)(0c — e D Vgs )
+ 6D (Vgs — VT) 2 ]
eD V gs ) + 2OD( Vgs — VT)]
(2 .45 ) where, for the sake of simplicity, 6 is defined a s 6 = 1 + O A (Vgs
VT)
+
OB Vsb + ODVgs2
(2 .46 )
With this definition of Vdsat, the accuracy of the transition regio n improves . However, the channel conductance g ds is affected by this definition since it assumes that when Vds = Vdsat, gds = 0, which is not true at all . The conductance predicted by BSIM also falls to zero mor e rapidly than it does in the experimental case, and the designer has t o keep this fact in mind since, especially in the design of analog ICs ,
2. Silicon Devices and Circuits
133
channel conductance is an important design parameter, which ideally i s equal to zero but never is in reality .
2.2 .5 . Series Resistance, Effective Gate Length, and Effectiv e Gate Width Series resistance has been widely discussed in the past decade as a resul t of the miniaturization of devices and the introduction of the LDD structure . In the past, the series resistance of MOS transistors had bee n considered as a constant value that added externally in series to the MO S transistor. This series resistance was essentially taken as the serie s connection of the contact resistance R se , the diffusion resistance between the contact and the gate edge RSd , and the crowding R sr resistance at gate edge as shown in Fig. 2 .21 . The current flow deflection under the contact is accounted for by th e contact resistance Rsc . The crowding resistance R sr also accounts for the resistance under the gate, where the current flow is pulled up the surfac e and continues toward the channel . Based on the assumption of constan t series resistance, several measurement methods have been proposed . A typical approach is that proposed by Chern et al . (45), in which the total measured resistance Rm of a MOSFET is taken as
Rm
=
(s) Ids
=
Rext +
(2 .47 )
Rchan
or R
m = Rext —
[ IUCox Weff
( Vgs
VT
lVds)] '
( L mask —
AL)
(2 .48 )
FIGURE 2 .21 . Schematic representation of the current flow between the contact to the source /drain and the gate edge of a MOSFET . The components of th e series resistance are also shown .
134
E . A . Gutiérrez-D ., C . Claeys, and E. Simoen 400
G
350
L.-
~
300
L
~
250 ~
..
200
-
150 2_ cu a~
V =2 V ~~
• R=70 S2
100 = 50 0 0.0
Vg =4 V
~ AL=0 .065 N m
0 .2
0 .4
0 .6
0 .8
1.0
Channel length on mask, Lmask [µm ] FIGURE 2 .22. Measured resistance R m versus channel length Lmask for a 0 .5-µm CMOS technology . n-MOS transistors with different channel lengths were measured at Vds = 0 .23 V at different V g voltages at 300 K .
where the transistor is considered to work in the linear region , Weff = ( Wmask — A W) is the effective gate width, and L eff = ( Lmask — 2AL) is the effective gate length . Plotting measured values of R m as a functio n of channel length Lmask, with constant V ds , and various values of V gs , gives a family of straight lines that cross each other at a common point that gives AL and Rext (or R s ) . As shown in Fig . 2 .22, extrapolated lines of experimental data, with different V g voltages, intersect each other a t the same point, from which AL is derived to be 0 .065 µm and the series resistance R s is 701 . This model of extraction assumes a constant valu e for R s and AL, independent of the bias condition . In this case, AL is defined as the portion of the MOSFET channel no t contributing to its electrical performance; this is the gate-to-source/drai n overlapping region . This model assumes a lightly gate voltage-dependent series resistance and that the channel conductance is independent o f the channel length, which has been shown not to be true in severa l published works. Among these, there are reported extraction procedure s based on the measured I—V characteristics (47—49), the measured capacitance—voltage (C—V) characteristics (50—52), charge-pumpin g techniques (53, 54), and combined measured /simulated characteristic s (55, 56) .
With the I— V method, as shown previously, the total resistanc e versus channel length, using an array of transistors, is measured at different gate voltages . Some of these methods extract Rs and AL usin g
2 . Silicon Devices and Circuits
135
constant values for the gate overdrive voltage defined as (V gs — VT ) . I n this way, the channel length dependence of V T is accounted for . Despite this modification, the Rm-Lmask lines for submicrometer MOSFETs do no t intersect at one point, making it difficult to determine AL and R s . In fact, AL can be negative, indicating that the effective channel length is longe r than the Lmask length . There are two reasons for the negative AL . First, i n submicrometer MOSFETs the fringing field lines at the gate edges exten d outside the gate, giving the impression that the gate is longer than it s mask length Lmask . The second reason is that it is assumed that either Rs or AL is independent of gate bias . C . Y. Hwang et al. (49) pointed ou t that Rs and AL should decrease as Vgs increases since a greater portion of the channel region can be modulated by the higher Vgs voltage . A t lower temperatures, the vertical electric field increases, which give s greater control over the modulated charge, leading to a stronger dependence of R s and AL on Vgs . Methods based on the measurement of the C-V characteristics were introduced to remove the effects of the series resistance on AL . The effective channel length Leff is extracted from the C-V measurements with the source and drain connected to an AC signal, the gate connecte d to a DC bias, and the body grounded . However, large MOS devices ar e needed in order to obtain measurable values for the capacitance . On th e other hand, the contribution of the source/drain-to-bulk capacitance s needs to be carefully decoupled . After the AL value has been extracted , the R s value is extracted using conventional I-V methods . The C-V methods also present inconsistencies as shown in Table 2 .2 (52), in which simulations are compared to measured results .
Table 2 .2 Effective Channel Lengths of a 0 .75-µm MOSFE T Extracted Using Various Methods (52 ) Method
Leff (um )
Defined Leff in simulations
0 .25
I-V [Chern et al. (46)]
0 .5 1
C-V by Sheu and Ko (58)
0 .20
C-V by Lee (50)
0 .1 3
C-V by Latif et al . (52)
0 .29
Simulations by Narayanan et al . (59)
0.5 1
I-V [Taur et al . (48)]
0.51
136
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen
Simulations performed by Latif et al . (52) and Narayanan et al . (59) with a defined L mask = 0 .75 pm and AL = 0 .25 µm coincide quite wel l with results of two of the C—V methods . However, these methods stil l fail to predict the gate voltage dependence of the effective channe l length . Most of the discrepancies of the I— V and C — V methods appear whe n sub-0 .5-µm devices require to be characterized . Submicrometer an d deep-submicrometer devices have additional complexities, such as a nonuniform substrate doping profile and large fringing capacitances . These problems can be handled by using the charge-pumping techniqu e (60), which consists of measuring the charge-pumping current of a set o f MOSFETs with different channel lengths . Plotting the charge-pumping current I, p versus the channel length (mask length) Lmask, the intercept of L, with the Lmask axis, gives AL. Accuracies to 0 .01 pm can be achieve d if the device doping profile is known . An improved technique, based o n charge pumping in a single device (53), has shown to give 0 .01- to 0 .02-,um accuracy . Extraction methods that combine measurements with simulation s also show good accuracy but require knowledge of the processing conditions and use of coupled process /device simulators . Extraction of the series resistance and gate-source/drain overlapping length AL, using the classical I—V methods, is shown in Fig . 2 .23 (61) . AL becomes negative for temperatures below 175 K, indicating a n overextension of the effective gate length, and the resistance R s shows a n
1 40
0 .2 0 .1
®'■' \ ,
bA
• � ~ U
-0. 1
4_, •
-
ra, cti
v
ô
13 0
~
'
0 .0 ~-
• o
•
.
D ~
--
-0 .4
G~
0
,
o
<
o
0
►\
~~ ~
—
11 0
_
100
—= 90 =
.
► 100
150
o V
* 00 50
120
-
~i
_
0.2 — -_ 0.3
—
~
200
.. ,
r
80
7d
r—, u
- 70 250
300
Temperature, T [K] FIGURE 2 .23 . Extracted Rs and AL as a function of temperature for a 0 .5-µm CMOS technology biased at V ds = 0 .1 V and Vgs = 2 .5 V .
2 . Silicon Devices and Circuits
13 7
increase . These effects have been attributed to freeze-out and the so called drain threshold voltage (61) . Physically, there is no way th e effective or electrical channel length is larger than the layout define d Lmask . As previously explained, the drain threshold voltage is a result o f the appearance of a potential barrier at the gate edges . This potentia l barrier has an impedance-like behavior, which emulates an additiona l series resistance and makes the Leff appear larger than L mask The effective width Weff of a MOSFET differs from the mask width Wmask due to systematic or random errors in the fabrication process, such as oxide encroachment, variations in linewidth, and photolithographi c undercut . One of these fabrication processes is the so-called loca l oxidation of silicon (LOCOS) process, which results in the bird's beak effect and a gate voltage-dependent width (62, 63) . In this case, the fringing fields invert the substrate in the vicinity of the channel as th e gate voltage increases, thus giving a wider effective width . The variation in effective channel width with gate voltage can be explained using a variable threshold voltage . The oxide thickness changes from that of th e gate thickness to that of the field oxide thickness, and the substrat e concentration varies from the channel value to the channel stop value , and therefore the threshold voltage increases from the edge of th e channel outward . As the gate voltage is increased, a larger portion of th e substrate becomes inverted, increasing the width of the transistor . The effect will be more pronounced for narrower channels since a large r fraction of the width will be affected . In this case, it must be considere d that the average value of the gate oxide will be larger than expected . The dependence of the effective channel width with voltage i s considered in the model presented by Deen and Zuo (63) in which th e two parallel conductances are considered to account for the edge effects, and whose value depends on gate voltage :
I= DS
RS µo C° VGTWeff (VDS — IDS + 2Gp VDS (2 .49 ) 9AVGT) Weff X
L (+ Leff
Ashton et al . (64) present a method to characterize the effective widt h as a function of gate voltage . The method is based on nonlinea r optimization using a model valid only in the strong inversion region fo r low values of Vas • Weff is defined as Weff = Wmask + 0 W0 + G W (Vgs — VT )
(2 .50 )
where A Wo is the difference between the mask and the effective widt h at threshold . The threshold voltage is modeled a s
v
T
=VTO —
ôVT ÔV
bs
ID Rs
(2.51)
138
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
where the current is the n IL OC ox Weff
V — VDS ) Is= DL (1 + A 8 GT V ) ( GT 2 DS ( mask -- AL)
DS
(2 .52 )
The limitations of these models occur because effective channel lengt h and series resistance is considered independent of gate voltage . Further more, as the surface potential varies with position, the effective channe l width also varies along the channel, and the value for Weff used in these expressions is thus an spatial average .
2 .2 .6. The Gate-to-Source/Drain Capacitance s The gate-to-source and gate-to-drain capacitances, Cgs and Co, are essentially the gate-to-source and gate-to-drain overlapping capacitances . The absolute value of these capacitances depends on the overlapping are a and gate oxide thickness Tox . However, from the previous discussion o n the effective channel length and width, the dimensions (width an d length) of this region change with bias, thus making the definition of thi s capacitance component also bias dependent and in general smaller tha n the one calculated from the metallurgical dimensions . A model for the overlapping capacitances, however, considers it to be larger than tha t calculated from the metallurgical dimensions (Lmet or Wmet) for eithe r source or drain (65) : Co ,, = Cox [(L mask — L met) + ] Weff
(2 .53)
The correction factor, , accounts for portions of the edges of th e transistor that are not considered even when the other components o f capacitance are calculated, and it is given by
rl — cos a L sin a l
= Tox
2
i + 1 —cos ; sin a 2
(2 .54)
where ; is the angle at which the gate wall forms with the normal, an d a2 is given by a2
= —1 7r
£ox
(2 .55)
E si
Another possible component of the gate capacitance is that associate d with the inner fringing field C if from the gate to the sidewall of th e source and drain diffusions on the channel side . This component is only present during depletion. When the transistor is in the accumulation o r inversion operating regimes, the electric field lines terminate at th e
2 . Silicon Devices and Circuits
13 9
charge in the surface, and this capacitance component is therefor e screened . An expression for this capacitance, but which does not includ e the bias dependence, is also given by Shrivastava and Fitzpatrick (65) : C if =
2e . X(ne w, s In 1 + ' sin n Tox 2ESi
Weft- =
.
s' In 1 + 0 .492
~
X. ' Weft. (2 .56 ) To x
The outer fringing capacitance Cof is due to the field lines originating on the gate and terminating on the outside portions of the source and drain diffusions through the oxide spacer . This model assumes no bias dependence, which in view of the previous discussion is questionable . Thi s capacitance can be calculated by the following expression (65) : e Cof = E°x in 1+ Tgat al lox
Wef f
(2.57 )
where Tgate is the thickness of the gate electrode. Another approach for this capacitance (66) divides it into three parallel capacitances obtained from a solution to Laplace's equation . These correspond to the field lines originating from the top of the gate, C t op, from the sidewall of the gate to the source/drain diffusions, Csw , and from the bottom of the gate to the source/drain diffusions, outside of the overlap region, Cbo . These components are obtained assuming tha t the sidewall normal is parallel to the substrate, whereas in the previou s approach the sidewall can form any angle with the substrate's normal . These components are modeled by the following equations : CtO p
= £°X
{2 — ln(4) — ln[1 — 2e - 26] } [2( Weff + Lmask)] C sw
Cbo
=
=
cox
~
ln(a)[2(Weff + L mask) ]
Eox In u ~ a
[2( Weff + Lmask)]
(2 .58)
(2 .59 )
(2 .60 )
In these expressions, mas k 8 = 1 + 7rL 2Tox
a=
2K.3K 2 — 1 + 2K2 — 1 e K = 1 + Tgat Tox
(2 .61) (2 .62 )
140
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
and u is the solution t o n Lmask 2 ToX
a—1
R+1 R ln I + Z (R — 1) 1-c-i R—1)
a+1 R+ 1 2 ln .63) ~R — ) (2 ~
with R=
/(u
-1 )
(2 .64)
(u — a )
The outer fringing capacitance is gate length dependent, as experiments and 2D simulations have shown (67) . However, Wang (67) attributed th e gate length dependence to only the capacitance originating on the top o f the gate C top , and when the drain (or source) is left floating it is calculated from Ctop
= EoxWmask ln 1 +
Lmas k Tgate + o x
(2 .65)
whereas if the source and drain are tied together, it is given by C top = 2Eox Wmask In 1 +
0 . 5L mask Tgate gate
(2 .66)
+ ox
So far, we have seen that the total gate parasitic capacitance is given b y the addition of the three parallel components and will be differen t depending on which definition is used to calculate it . The approach of Shrivastava and Fitzpatrick (65) is independent of gate length, whic h intuitively makes it wrong, but it also provides the only definition fo r the inner fringing capacitance . The temperature dependence of these capacitances is not straightforward . However, Gutiérrez-D . et al . (68) show that the capacitance of a MOS system in depletion, inversion, and accumulation is slightly temperature dependent (Fig . 2.24) . The capacitances shown in Fig . 2 .24 were measured at V = — 4 V fo r inversion (Cinv ), 0 V for depletion (Cdep), and 4 V for accumulation (C ac c ) at a frequency f of 1 MHz . The capacitor has an n-well bottom plate on a p-type substrate. The measured capacitances slightly decrease a s temperature is reduced from 300 K to about 50 K, below 50 K, all th e capacitances have a steep reduction . This reduction is partially due t o freeze-out near the n-well contacts . For the case of a n-MOSFET, th e surface at the gate-to-source overlapping region changes from depletio n to accumulation when the gate voltage changes from zero to the suppl y voltage value . Thus, at very low temperatures, the Cgs capacitanc e reduces .
2 . Silicon Devices and Circuits 12
14 1
n-
-
-
..
C
o
O
100
150
n
.
p~~~i~~•=
r-,
w
..
i►
-
~
10 s,,, n
__
_
V 8 cu 6 .;asi c.) • 4 as U
C acc C de p
6
~~
o
2 ►~, ,•~
0
CC ~
i~
0
i~ 50
200
250
300
Temperature, T [K ] FIGURE 2.24. Measured capacitance of a MOS capacitor on n-well, wit h ToX = 10 nm, Wmask = 20 µm, and Lmask = 200 µm . The frequency f was set to 1 MHz . The n-well doping level is 10 17 cm' .
2 .2 .7. The Source/Drain-to-Bulk Capacitance s The estimation of reverse-biased p—n junctions associated with th e source/drain—substrate is straightforward . These junction capacitance s C. are calculated according to the well-established models (Fig . 2 .25) :
C;
=A
Esi
=
ESi
A
Wrb
2 e si
\
qNB (1/
(2 .67)
+ V — 2V,) /
V bi is the built-in potential, V is the reverse-bias ,wher voltage, Vt is the thermal voltage, Wrb is the thickness of the depletion region, and A is the area of the p—n junction . The junction capacitance decreases wit h temperature because the depletion width increases due to freeze-out .
2.2.8 . The Polysilicon Depletion and Quantum Effect s MOS transistors (or capacitors) with very thin gate oxides may presen t lower than expected values of gate capacitance . This deviation from th e classical behavior has been determined to be a function of polysilico n concentration and processing conditions, oxide thickness, and substrat e concentration (69—71) . As ToX decreases, polysilicon concentration Np
142
E . A. Gutiérrez-D., C . Claeys, and E . Simoe n 102
a .^, V �
..
g
=
10 -2 10-4 10- 6
••
10-8
•
G
10
-12
1
I
"_
. o '
,%
.
~ -~
-~
Ii
=-
~ -~
~-
= -10 r° o 10
•
1
-
10°
'c
o
_
I
I
E
4 .
o
~~
~ ~ .
t
I►
50
~
,
~
I,
1(X)
I
I
150
~~~
~
I
~
200
~
►
~
I
250
~
<
300
Temperature, T [K] FIGURE 2.25 . Calculated junction capacitance C . versus temperature.
decreases and substrate concentration NB increases, leading to a highe r degradation of the C–V characteristics, which are the processing conditions used in submicrometer and deep submicrometer CMOS technologies . There are two physical causes for the reduction of the capacitance : the polysilicon depletion effect (PDE) (72), and the quantum effects (73 ) on the inversion layer . When the doping concentration in the polysilicon gate is not sufficiently high, or if only partial activation is achieved during the therma l batch, the polysilicon/SiO2 interface will present a depletion region which acts as an additional series capacitor with the gate oxide capacitor . The effect of this capacitor is to reduce the total gate capacitance an d therefore degrade the current driving capability of the transistor . This degradation has been reported to be up to 30% in 125-A thick oxide devices operated at room temperature (71) and up to 60% in 100-A thick oxide devices (74) operated at 4 .2 K. This effect can be avoided usin g polysilicon doping levels higher than 5 x 10 20 cm', when total activation is assumed . At low temperatures, the depletion of the polysilicon gate enhances PDE, and thus PDE is more pronounced at low temperatures . Quantum effects in inversion layers are a result of the strong surface electric field that produces a potential well whose width in the bulk direction is small compared to the wavelengths of the carriers . Thus, the energy levels of the carriers are grouped in electric subbands, each o f which corresponds to a quantized level for motion in the bulk direction , with a continuum for motion in the plane parallel to the surface . The splitting of the energy levels into subbands results in the lowest possible energy levels for free carriers in the well and does not coincide with the
2 . Silicon Devices and Circuits
o
143
2
4
6
8
10
depth from the surface, z [nm ]
FIGURE 2 .26 . The charge distribution in the inversion layer for both classical and quantum mechanical (QM) approaches .
bottom of the conduction or the valence band . As the surface electric field increases, the inverted layer becomes more quantized, thus requiring a larger gate voltage in order to populate a 2D inversion layer so tha t it has the same number of carriers as the corresponding 3D classical system . In the classical approach, the inverted charge distribution peaks a t the Si—SiO 2 interface because this is where the energy bands are mos t bent . However, in 2D quantized inverted layers, the surface carrie r concentration at the interface is very low, and the centroid of th e inversion layers moves away from the surface (Fig . 2 .26) . The effect o f quantization of the inversion layer has been analyzed by several group s (75-77) . Lopez-Villanueva et al. (76) proposed an analytical model base d on extensive numerical simulations . The expressions allow the calculation of the position Z I of the centroid :
ZI
=
1 x 106V cm
IQD(QD ESi. E Si.
1 Q,)] - ' I '
+ 2 ES i.
(2 .68 )
ZIO is a reference length acting as a fitting parameter . A constant value ZIO = 1 .2 nm provides good agreement with numerical results . However, an analytical expression for this fitting parameter is also provided b y Lopez-Villanueva et al . (76) : Zlo IO
[1 .783 — 0 .107 • ln
NB (1O1-3)]
(nm)
(2 .69)
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
144
The depletion and inversion charges, Q D and QI , are given by QD
= J2tsj qNB
T
(P&p —
(2.7 0 )
where (p dep is the potential associated with the depletion layer ban d bending dep
s
— 'Zi QI
(2 .71 )
ES i
where 'Ps is the surface potential . Also the inversion layer charge QI i s given by QI
= Cox*
(Vgs
VFB
(P dep
— QD
C ox
(
2 .7 2
)
with C ox*
I
\
Eox
T. + \
Eox E si
(2.73 )
ZI
The denominator of Eq . (2 .73) is termed the "electrical oxide thickness, " which can be interpreted as a series combination of Cox and a "centroi d capacitance" given by (esi /Z,) . This mechanism has also been addressed by Jallepali et al . (75), wh o analyzed the shift on the threshold voltage . The n- and p-MOS threshold voltage shifts are calculated as a function of temperature and bulk doping level . The results are shown in Fig . 2 .27 . r—,
~ ,160go 1 I
I
1 ) 1 I I 7
T
o x =4 n m
S
E--
d
4.;
140
120
~ 100 43
80
/1r
o 60 .--■
2
40 = _
20 , 0
-
17 1X10 c m 50
100
I50 200 250
300 350 400
Temperature, T [K ] FIGURE 2.27 . Electron threshold voltage shift AV T obtained from full band calculations [replotted from Jallepali et al . (75)] © 1997 IEEE .
2 . Silicon Devices and Circuits
145
The threshold shift OVT in Jallepali et al . (75) is defined as th e difference between the threshold voltage calculated with the QM approach and that calculated with the classical approach : AVT
=
[VT (QM) — VT (Classical) ]
(2 .74)
According to Jallepali et al . (75), threshold shifts due to holes sho w slightly stronger temperature dependence compared to those due t o electrons . Analytical expressions for 0 VT for both electrons and holes ar e also provided by Jallepali et al . (75) . The room-temperature threshol d shift for electrons and holes (in eV) is modeled as OVTe,h (Lx, Ne,h)
= fe, h (Ne, h ) + Toxg e,h (Ne,h )
(2 .75 )
where fe,h(Ne,h) and g e,h (Ne,h) are polynomial fits to the simulation data , with
fC (NA) = 0 .007 + 2 .083NA — 20 .583NA 2 + 95 . 738NA 3
— 149 .916NA 4
(2 .76 ) g e (NA ) = 0 .094NA — 0 .139NA 2 — 0 .432NA 3 — 0 .586NA 4 fh(ND)
=
-0 .002 — 1 .621 ND
+
13 .893ND 2 — 61 .847ND 3
+
(2.77 )
95 .149ND4 (2 .78 )
and gh (ND) = — 0 .067ND — 0 .106ND 2
+
0 .654ND 3 — 1 .073ND4
(2 .79 )
The previously described studies (75,76) confirm the large impact o f quantum effects on the electrical performance of submicrometer CMO S technologies and their degradation effects at low temperatures .
2.2 .9 . The Drain-Induce Barrier Lowering Effect For MOSFET devices with submicrometer channel lengths, the drain depletion region moves closer to the source depletion region, giving ris e to an electric field penetration from drain to source that results in a reduction of the potential barrier at the source side, which in turn result s in an increased injection of carriers from the source over the reduce d barrier, thus enhancing the subthreshold current . This is the so-calle d DIBL effect (78) . In submicrometer MOSFETs the DIBL effect results i n a threshold voltage reduction, which follows a linear relation with Vds . A modified empirical model for the VT that includes the DIBL effects i s given by VTDIBL = VTO
6Vds
(2 .80)
146
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
where a is the DIBL parameter which has been defined in different way s by different researchers . In Grotjohn and Hoefflinger (78) a is given as
a = a 0 E Si Cox Leff
(2 .81 )
n
where a 0 is a fitting parameter that accounts for the geometry dependence and the exponent n varies from 1 to 3 . Another definition of a that accounts for the substrate (or bulk) voltage dependence is given i n Troutman (79) as a
=
[L
6E si C . + CD) ( °
(2 .82)
where CD is the depletion capacitance, which is a function of the bul k voltage . Another expression for a has been given by Rantnakumar an d Meindel (80) : a
e–(7[Leffi4WD)
(
WD = (°')
2 .83
)
where WD is the depletion region width. Recently, technological considerations to reduce the DIBL effect have been given by Tsai et al . (81), where a DIBL voltage VDIBL is defined as the difference V T (at Vds 1) — VT (at Vds 2) with Vds 2 > Vds 1 • The experimental results of the VDIBL voltage for a (W/ L) = 10/0 .5 n-MOSFET biased at Vds 1 = 0 .13 V and V ds2 = 0 .27 V as a function of temperature are shown in Fig . 2 .2 8 (82) .
■
u
111111111111111111111111111
5
0
50
100
150
200
250
300
Temperature, T [K ]
FIGURE 2 .28 . Measured DIBL voltage V DIBL for a (W/L) = 10/0.5 n-MOSFET biased at Vds = 0 .23 and 0.27 V .
2. Silicon Devices and Circuits
147
The DIBL effect represented by the VDIBL voltage, increases at lo w temperatures, indicating that low-temperature operation worsens th e deleterious effect of the DIBL . 2.2 .10. The Gate-Induced Drain Leakage Effect This mechanism was defined for the first time by Chan et al . (83) as the drain leakage current measured at drain voltage much lower than the breakdown voltage . The origin of this mechanism was attributed to th e band-to-band tunneling occurring in the gate-to-drain overlap region , where the high electric field is induced by the high gate-to-drain voltag e difference, and a model was proposed to predict this leakage current : IGIDL
= AEse - (B/Es)
(2 .84 )
where A is a preexponential constant, B = 2 .13 x 1 0 ' V/ cm, and Es is the vertical field at silicon surface , E= s
(V1 .2) 3T
(2 .8 5 )
oX
with 3 as the ratio of Si permittivity to oxide permittivity, and 1 .2 V a s the minimum band bending required for tunneling process to occur . Note that the IGIDL current flows from drain to substrate, and that it i s not added to the drain-to-source current Ids . Nathan and Das (84) calculated IGIDL current for direct and indirec t tunneling from the valence band to the conduction band of silicon, a s well as tunneling from the conduction band minimum of silicon to th e interface traps, and compared these results to experimental data . It is concluded in this work that IGIDL is mainly produced by tunneling fro m the conduction band to the interface traps, where the contribution fro m both direct and indirect band-to-band tunneling is negligible . A more complete model is proposed as follows : 1)e-B(Eg+hw)" + ne-B(Eg-w)1 .5] (2 .86) IGIDL = SAV [(n + where S is the area, and A is given b y 2 A = q(E) .Jmvxmcxmvymeymv .m .Z
M2 21 1/4?t 5/2 13/2mrx1/4Eg0 .75(q00 .5
(2 ' 87)
n is the phonon occupation number, is the electric field given b y ( Vds Vgs) Vd s 3ToX + W
(2 .88)
148
E . A . Gutiérrez-D ., C . Claeys, and E. Simoe n
Vds and Vgs are the drain- and gate-to-source voltages, respectively, W i s
the depletion width, E g is the energy gap of silicon, an d
=
(2 205 ) 3 _
M
(2 .89 ) qC
C2gh 2cs p
(2 .90 )
where C is the coupling energy (85), c s is the speed of sound in th e material, p is the mass density, w is the phonon frequency, and m r is th e reduced effective mass given by
(1/m r )
=
[(1 /mv )
+
(1 /m e )]
(2 .91 )
where m, and m e are the valence band and conduction band effectiv e masses, respectively . Also in Eq . (2 .87), E is an energy parameter give n by
22 .5 gh I
E _
3n .3m r Eg
(2 .92)
The subscripts x, y, and z on the effective masses refer to their components along these directions . When direct tunneling is considered, the following model applies : I= GIDL
S
qmr 18h '
e-qv(E/2)[(ßj/ "`_ A)/21 .5ghC]
(2 .93 )
where V is the applied bias . When tunneling assisted by trap levels is considered, the energy ga p Eg is replaced by (E g -E t) in Eqs . (2.86) and (2 .93), where Et is the trap energy measured from the valence band edge . The other consideration i s that the right-hand side of these two equations should be multiplied b y a factor that accounts for the trap density of states . Equation (2 .86) is thu s valid for indirect tunneling . These models have been used to calculate th e IGIDL current and compare it to experimental results, which are shown in Fig . 2 .29 (84) . These results show that the GIDL current in MOSFETs arises fro m interface trap-assisted tunneling and not from band-to-band tunneling . In another work (86), the measurements of the surface leakag e current of the gate-controlled drain-substrate diode at different temperatures are presented . In Acovic et al . (86), in addition to considering the reverse-bias tunnel current as a limitation to device miniaturization , it is used as a monitor to learn about hot carrier degradation i n MOSFETs . In this work, the temperature dependence of the reverse biased drain-bulk junction was found to be negligible, but the tempera-
2.
14 9
Silicon Devices and Circuits 10.1 0 10-11 46 10~ `.~ 10-2 10_ 02 2
C7
10-24 1 0.2 8 10 -30 10 10 .3 4 1 ~ -36 38 1 0 -40 _
E]
experimenta l
RI
calculated with trap-assisted tunnelin g
indirect tunnelin g
c
direct tunnelin g f
I8' 44 -3 .5
-3 .0
-2 .5
-2 .()
-1 .5
-1 .0
-() . 5
Gate voltage, V„ [V ] FIGURE 2.29 . Calculated and measured GIDL current IGDL, with direct, in direct, and trap-assisted tunneling (84) © 1993 IEEE .
ture dependence of the forward-biased drain—bulk junction is mor e important than expected for a tunnel current . The experimental result s are shown in Fig . 2 .30 . The reverse tunnel currents are slightly sensitive to temperature , whereas under forward conditions the reduction of the currents is muc h
1
10-8 -
I
I
IRbefore ~
• u 1--1 .
~
10-9
,T
II ' Rafte r
-
-11—111—11—111 ^
10 -10 =
•
-~ i = - -
.. _
/■ o
=
O 1 Fhcforc 1 Faftc r
10-13 50
i
1(x)
150
,
I
200
25 0
Temperature, T [K ] FIGURE 2 .30. Measured temperature dependence of the drain-to-substrate current of a n-MOSFET in reverse IR (VG = -15 V, VD = 3 V) and forward I F (VG = — 20 V, VD = — 0.6 V) conditions . The currents were measured before an d after stress (VG = VD = 7 V for 160 s at 77 K) [replotted from Acovic et al . (86) ] © 1993 IEEE .
150
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
larger at low temperatures . This indicates that GIDL effects will be les s pronounced at cryogenic temperatures . On the other hand, these results show clear evidence of injection and trapping of hot electrons in th e gate—drain overlap region of n-MOSFETs . Therefore, this region be comes especially important at low temperatures, at which soft freeze-ou t occurs, and hence becomes sensitive to trapped charges . 2.2 .11. Electrothermal Effects The electrothermal effect is defined as the coupling between the hea t generated by power dissipation and the change in electrical parameter s due to changes in temperature . The high power dissipation arises from the high current driving capability of very dense IG . Different approaches have been implemented to help diffuse the heat out of th e silicon chip, including the use of fans, the use of metallic dissipators, an d even the use of cooling systems . However, before dissipating the hea t generated at the surface of silicon devices, away from the chip, it diffuse s across the silicon die affecting the neighbor devices . A schematic representation of a packaged MOS transistor is shown in Fig . 2 .31 . In packaged MOS transistors or circuits the heat source Q is confine d within the silicon very close to the surface, bounded by the silicon bul k below, the gate oxide on top, and the source and drain diffusions o n
FIGURE 2.31 . Schematic representation of a packaged MOS transistor .
2 . Silicon Devices and Circuits
15 1
both sides. The thermal conductivity of the SiO 2 at 300 K is about 0 .014 W/cmK, which is much smaller than that of Si (1 .5 W/cmK) . Therefore, silicon is the most probable path for the heat to diffuse awa y from the surface . If the heat is assumed to diffuse isotropically, then i t goes away through the source and drain diffusions, passing by the source /drain contacts, the bonding wires, the bonding pads, and finall y through the external terminals . The heat can also diffuse through the silicon bulk, passing by the interface silicon–air at the lateral silico n walls, or it can diffuse through the bottom plate . The heat has to transport through the silicon . How the heat diffuses also depends on the operating temperature conditions . Therefore, in this section particula r attention is paid to the generation (self-heating) of heat by the MO S transistor and its associated electrothermal effects in the 300-4 .2 K temperature range. An equivalent electrical model for the thermal generation /diffusio n process can be proposed . It is based on a very simple combination of a heat source Q and thermal resistance and capacitance R th and Ct h (Fig . 2 .32) . The heat can be generated at very low frequency; in such a case, the heat capacitance C th does not play any role, and the hea t dissipates like the power in an electric resistor, flowing from the silico n to the ambient . In this way, the silicon obtains a balance in which the Ts i temperature is as close as possible to the T A temperature . The genera l case occurs when the Cth capacitance is not neglected ; in such a case, the generated heat dissipates through the parallel combination of C th an d Rth , with a characteristic thermal time constant i t h T th - (Rth . C th )
(2 .94)
Silicon temperature Ts ; •
R th
C th
•
Ambient temperature T A FIGURE 2 .32. Equivalent electric circuit of a thermal generator Q in silicon .
152
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen
According to the equivalent electric circuit of the thermal generator (Fig . 2 .32), the silicon temperature T si can be modeled as
=
1 [R
h
(T
—TA )
+
Cth
d
(22 .95 )
TA)]
(TP
where P is the power being dissipated by the heat generator . The electric power P depends on the amount of free carriers available for conduction , which in turn depends on T si , and both C th and Rth are geometry an d temperature dependent (87) . It is very difficult to find a solution for thi s equation. A more elaborated theory with proposed solutions is presente d by Javier de la Hidalga-W . (87) . Therefore, here we discuss only experimental results . First, we treat the case of a simple set of resistors that act as eithe r heaters or thermometers . The test structure consists of a series of silico n resistors, n-well resistors Rnwell located in the n-well, and p-substrate resistors Rpsub located in the p-substrate of a CMOS technology, a s depicted in Fig . 2.33 . The separation between the different n + (p + ) contacts determines the length of the resistor L n (Lp) and width Wn (Wp ) is determined as a first approximation by the width W of the contacts . The distances between the reference contact Vnref and the contacts 1— 4 are 10, 30, 90 and 200 ,um, respectively. The separation between contact s in the p-substrate is the same as that in the n-well . The method (88 ) consists of calibrating every resistor as a function of temperature TA . The calibration is done at a low-current bias condition to avoid self-heating . One of the resistors either in the n-well or in the p-substrate, is used a s
25 , u Cr1
I
-
I
I
1 .
►~
_
S Ei J
0
1
1
1
-
~
T A =4 .2 K ,
ri~
0 . . ...
I
-
_
~
I
-
► ~~~ -
-
_
0
1
~
E 10 _ ~ ~
C/)
1
.
20 15
• •--,
1
- - ~
-
L=1Opm
_
--
~► I,
~~ ~~ ,I „►~, 5 10 n-well power, Pnwe1► [m'' ]
15
FIGURE 2 .33 . Experimental test structure used to measure the silicon temperature (88).
2 . Silicon Devices and Circuits
15 3
FIGURE 2 .34. Extracted silicon temperature Tsi as a function of the power dissipated in a n-well resistor of (W/L) = 200 / 10 operated at T A = 4 .2 K.
heater Rht , whereas the other is used as temperature sensor Rts . The hea t generated by R ht is sensed by Rts as changes in its current level I ts , and the new value of Its is associated with a new value of Tsi . In this way, a plot of Tsi versus power Pth(Vthlth) can be extracted (Fig . 2 .34) . The Tsi temperature starts rising at about 1 mW of dissipated power in a linear way up to about 1 .5 mW, then it tends to saturate at higher levels of power . This behavior is explained in terms of the temperature dependence of R th , which has a minimum value at about 30 K; thus, thi s feedback system tends to settle down to an stable value . The same tes t scheme can be used to extract Tsi as a function of position x (Fig. 2 .35) . 25
~
20
_
r
~ i~ .r
• E a~ ô
U
.:= .. ~
(/)
TA=4 .2 K
15 ---_
10 – -
5
_ -
0`~ 20
t
40
t
60
t
KO 100 position, x [[tm ]
t
t
120
140
16 0
FIGURE 2 .35 . Measured Ts i temperature as a function of position x . Th e (W/L) = 200/10 n-well resistor was used as a heater with a power P nwell = 13 .5 mW .
E . A . Guti érrez -D ., C . Claeys, and E. Simoen
154
I psu b
R nx
unt
Vnref
heat exchange
Vpt
Rpx
Vpre f
FIGURE 2.36. Experimental configuration used to measure the thermal tim e constant ith . TA = 4 .2 K, Vnref = 0 V, Vnref = 7V, R. . = 12012, RI, . = 12 Kn . The L = 30 µm n-well resistor is used as a heater and the L = 30 µm p-substrate resistor as a temperature sensor. The frequency of the square signal VHS was set to 10 Hz.
The temperature profile is a result of the heat flow through th e silicon die . The thermal time constant T th can be extracted by applying a squar e wave signal to the heater and examining the output response of th e temperature sensor . For this purpose, the same test structure is used, bu t under the configuration shown in Fig . 2 .36. The Ipsub current, which is used to bias the temperature sensor, is adjusted with the Vpsub voltage . In this case, Vpsub = 0 .8 V, which sets Ipsub = 10 nA . The square signal VH s is applied to the external resistor R., inducing a pulsed voltage Vn t through Rnwell, this Vnt pulse generates a heat pulse that propagate s through the silicon bulk reaching the Rpsub temperature sensor . The increase in the Tsi temperature changes the value of Rnwell, inducing a voltage pulse Vpt . By measuring the Vpt wave signal, the thermal constant can be extracted . The experimental measurements are shown in Fig . 2.37 . Two thermal constants are observed one for cooling down (tthc ) and one for heating up ( rthh) . A value of 5 ms is measured for rthc and of 1 µs for tthh . The larger value of Tthc is explained by the fact that when the heat pulse, controlled by the high level of Vnt , is in the high state , the silicon substrate is already heated giving a larger change in C th (see Chapter 1) that compensates the smaller change in Rth , which explain s the longer Tthc . When the heat pulse is in the low state the T si temperature remains closer to TA , which results in a smaller thermal tim e constant ( rthh) . From a practical point of view, in CMOS digital circuits operating at high speed, in which the time constants are very small
2 . Silicon Devices and Circuits
15 5
10 = 0
: thc
ti th h
-10 -
0
10
20
30
40
time, t [s]
50
60
70
FIGURE 2 .37. Measured thermal time response of the test structure of Fig . 2 .36 . The structure was operated at TA = 4 .2 K. compared to thermal time constants, the Tsi temperature can be regarde d as constant with its absolute value depending on the electric power dissipated by the circuit . In analog ICs (89) the heat source might interac t with the circuit behavior, causing distortion in the DC transfer characteristics (89, 90) . The same technique has been used to measure self-heating effects i n single MOSFETs and CMOS inverters (91) . The results are shown in Figs . 2 .38 and 2 .39 . The silicon temperature Tsi , in the case of a single 35
50
30 25
b
0
0
1
2 3 Drain voltage, V ets [V ]
4
5
0
FIGURE 2 .38 . Measured I d –Vd, characteristics of a (70/0 .7) n-MOSFET operated at TA = 4 .2 K. The right axis is the plot of the extracted Ts i temperatur e (dotted lines) for V g = 1 .5, 2 .0, . . . , 5 .0 V .
156
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n 6 5
-
= -
-
-!~~ Ii~ ~I
4 =
°
V a ut
_
3-
o
2
, ., ßa
n
`'~, .
= 15
►~
L►\ kv.
a~
= 10 ~H a~_. ~ 5 ~. ..
~&~
t)
0
ô
o,
_ 0
►_.
25
= ~ . ~ 20
_ _
5 O
+~~~• +`+!
30
2 3 4 Input voltage, Vin [V ]
1
5
0
FIGURE 2.39. Measured output voltage V0t and extracted Ts ; temperature of a CMOS inverter operated at TA = 4.2 K (91) © 1993 IEEE .
n-MOSFET, reaches 43 K at Vg = 5 V, which is quite high considering TA = 4.2 K . In the case of the CMOS inverter, the maximum of Tsi occur s at the Vin voltage where the current transient consumption occurs, an d it increases due to the thermal time constant ith, which results in an increased amount of time for the heat to dissipate. Finally, the tempera ture dependence of the selfheating effect is plotted in Fig . 2 .40 .
~
(1)
15 10
. .... ~ , 0
A1 40 60 80 Ambient temperature, T A [K] ,
20
100
FIGURE 2 .40. Experimental temperature dependence of the (Ts; -TA) differential temperature, measured from the resistor test structure (88) .
2. Silicon Devices and Circuits
15 7
The experimental temperature dependence of T si is due to th e temperature dependence of the Si thermal properties . The self-heating effect because considerable at temperatures below about 30 K . This is also due to the strong freeze-out effects . 2 .2.12 . Summary The electrical performance of the MOSFET as a function of temperatur e has been presented in this section . This analysis has been done based o n two of the most popular models used in literature, the Klassen and BSIM models . Predicted results were compared to experimental data, an d discrepancies were discussed and analyzed based on physical principles , outlining the future of deep submicrometer MOSFETs for low-temperature operation. This section also reviewed the evolution of MOSFE T technology from the mid 1980s to 1998 . The trend shows that the Year 2000 should be the date of the gigaintegrated CMOS systems with mor e than 10 9 transistors on chips operated at frequencies above 1 GHz . Second-order effects and quantum effects that pertain to submicrometer and deep submicrometer MOSFETs were also analyzed as a function of temperature . Effects such as bias-dependent series resistance , bias-dependent gate oxide thickness, bias-dependent gate-to-sourc e capacitance, polysilicon depletion, and electrothermal effects were all discussed in terms of published models and experimental results . It i s concluded that deep submicrometer and nano MOSFETs have a promising future in cryogenic applications .
2 .3 .
THE SILICON-ON-INSULATOR MOS TRANSISTO R
Interest in the use of SOI substrates began in the late 1970s and wa s aimed at finding a replacement for silicon-on-sapphire (SOS) . Although SOS was used for applications such as high-temperature operation i n automotive and fast A / D converters, its primary use was in military an d aerospace applications due to superior radiation hardness. In general, the driving force triggering worldwide research in SOI is its performance and cost advantage (93-95) . Reported advantages are; (i) latch-up immunity, (ii) higher packing density, (iii) higher speed performance, (iv ) lower power consumption, (v) lower leakage current, (vi) wide voltag e operation range, (vii) reduced short-channel effects, (viii) strong potential for both cryogenic applications and high-temperature electronics , and (ix) lower processing cost . Potential drawbacks are (i) floating body phenomena, (ii) parasitic effects, (iii) availability and cost of the substrates, and (iv) processing difficulties on thin film substrates .
158
E . A . Gutiérrez-D., C . Claeys, and E . Simoe n
FIGURE 2 .41 . Schematic illustration of the "smart-cut" process [after Bruel (92)] .
An important parameter influencing the use of SOI has been the substrate manufacturing and quality, which for many years had a strong negative effect on the material cost . Whereas in the early days zon e melting recrystallization by laser, e-beam, or graphite heating was th e key manufacturing technique for the thick film substrates (96), today the market is dominated by separation by implantation of oxygen (SIMOX ) (97) and wafer bonding and back-etch (BESOI) (98) . The recently developed smart-cut process (92, 99) for making high-quality wafers is reducing the difference in wafer cost between bulk and SOI . The process, which has been demonstrated on 300-mm wafers, is based on proto n implantation and wafer bonding as illustrated in Fig. 2 .41 . In a first ste p hydrogen with a dose in the range 2 x 10 16 -1 x 10 17 cm'2 is implante d in a wafer with a dielectric capping layer, which will become the BOX of the SOI structure . Subsequently, after cleaning the implanted wafer A is hydrophilically bonded to wafer B . The latter will later play the rol e of the bulk silicon. During a first heat treatment (400—600°C) the implanted wafer A will separate into two parts a thin monocrystalline silicon layer remaining bonded to wafer B and the rest of wafer A . A second temperature step (> 1000°C) is used to strengthen the chemica l bonds . Finally, after splitting chemical—mechanical polishing is used t o reduce the microroughness of the thin silicon film . The remaining wafer A can be used for another fabrication cycle . Compared to the standard BESOI process, only one silicon wafer is effectively used, whereas in th e other case one wafer is fully polished away . The used buried oxide (BOX) manufacturing technique has an impac t on the defect content of the layer and/or the substrate, on the uniformit y of the film thickness, and on the quality of the Si—SiO 2 interfaces . As will
2. Silicon Devices and Circuits
159
FIGURE 2 .42. Delay and power dissipation of a two-input NAND gate in bul k CMOS and SOI CMOS gate arrays (FO = 2- and 3-mm metal wires) [after Won g and Rigby (100)] .
be discussed in Section 2 .3 .3, especially the front- and back interfaces o f the silicon film have a direct impact on the electrical device performance . The continuous improvement in material quality leads to higher minority carrier lifetimes, which in turn may enhance the parasitic bipola r action . In general, it can be stated that the SOI materials are achieving the quality of bulk material. The pricing, however, is controlled by th e market demand . Whereas for 0 .7- to 0 .35-pm CMOS, it was difficult for SOI to compete with bulk CMOS, for the deep submicrometer technologies SOI is becoming a real challenger . It is generally believed that SOI CMO S technologies will no longer be restricted to niche applications, such a s radiation hard, low-voltage, and/or high-temperature applications, an d also will offer potential for volume production . An illustration of the benefit of SOI compared to bulk CMOS for digital applications in shown in Fig . 2 .42, which shows the delay time and power consumption of a two-input NAND gate in bulk and SOI CMOS gate arrays for a fan out = 2- and 3-mm metal wires (100) . It can clearly be seen that the SO I CMOS array consumes 65% less power than the bulk counterpart at th e same speed . An in-depth review of the design considerations an d advances of SOI for digital CMOS VLSI can be found in Chuang et al . (101) . There is strong interest in using CMOS SOI for memory and logic applications, although this requires the implementation of body contacts . A strong SOI CMOS potential is related to low-voltage/low-power applications . As will be outlined later SOI will be playing an importan t role in the deep submicrometer (i .e ., 100 nm and below) era .
160
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
FIGURE 2 .43 . Schematic representation of a SOI CMOS building block consisting of an n- and p-channel transistor .
2.3 .1 . Inversion Mode Device s A schematic cross section of a SOI CMOS building block, consisting of an n- and p-channel device, is given in Fig . 2.43 . The device uses LOCOS isolation and spacer oxides and LDD regions for the gate architecture . As can be clearly seen, the structure consists of a Si film in which the curren t conduction occurs . Although vertically limited by the BOX, the source — drain junctions determine the lateral dimension of the silicon cavities . Only so-called reach-through junctions, whereby the vertical junctio n depth is equal to the film thickness, are considered because of thei r importance for VLSI and ULSI applications and their strong benefit fro m a processing viewpoint . The bias voltage on the four electrodes (i .e ., the source and drain regions V ds , the front gate Vgf , and the back gate o r silicon substrate Vgb ) controls the device operation . As discussed later, in some cases one also uses an additional film contact to control th e potential of the film . Depending on the back-gate voltage, the back Si SiO2 interface can be accumulated, depleted, or inverted . In general, one can differentiate between fully and partially depleted devices and between the thin and thick film mode of operation . If the depletion widths at the front and back interfaces are overlap ping or the front depletion width extends throughout the whole silico n film thickness 41 one refers to a fully depleted (FD) device . The total silicon film is then depleted of carriers . In the other case, there remains a neutral silicon region in the film and one is dealing with a partiall y depleted (PD) device . Often, one also refers to the thin and thick film
2. Silicon Devices and Circuits
161
operation mode of an SOI transistor . A thin film device is a transistor i n which the silicon film thickness is smaller than twice the maximu m depletion width Wmax :
t f> Wmax -
4ESi
(2 .96)
qNA
where esi is the silicon permittivity, q is the electron charge, (' F is th e Fermi potential, and NA is the film doping concentration . This implie s that by applying the appropriate front and back gate biases, the silico n film can be fully depleted, or the device can operate either in th e partially or the fully depleted mode . In the case of a so-called thic k film regime there will always remain a neutral silicon region betwee n the front- and back gate depletion regions . An important difference in electrical performance exists between partially and fully deplete d devices.
2.3.1.1. Partially Depleted Device s For partially depleted devices the depletion layer under the gate electrode ends in the silicon film, leaving a neutral region in the silicon film . Under similar channel doping conditions and front gate oxide thickness , bulk and PD devices have the same threshold voltage, given b y VTf — C MS + 2(I)F
( gN it / Coif) (Qdep1
/ Coif)
(2 .97)
where OMS is the work function difference between the gate material an d the silicon film, Nit is the interface state charge density, Qdepl is the depletion charge given by q Wmax/NA, and C ox is the oxide capacitance . Equation (2 .97) is written for the threshold voltage of the front gate transistor, but a similar expression holds for the back gate transistor. In this type of device, there is no coupling between the front- and th e backside threshold voltage .
2.3.1.2. Fully Depleted Devices The front gate-related depletion region extends from the gate oxid e interface to the point of minimum potential, which for sufficiently larg e t f lies inside the silicon film. By increasing the back gate voltage, th e associated depletion width will increase at the expense of the fron t depletion width, thereby modifying the front gate threshold voltage . I n other words, the backside voltage will modulate the front threshold
162
E . A . Gutiérrez-D ., C. Claeys, and E . Simoe n
voltage . The threshold voltage for such a device is then given by (102 ) VTf
i~
Qoxf + + (1 CsiSi / MSf — C oxf
oxf)2O+ F
(0.5NAtf C
oxf
+ C
C siCoxb
C C
oxf ( Sioxb )
Vacc b
(2 .98 ) where f and b refer to the front and the back interface, respectively, Q o x is the fixed oxide charge density, Csi is equal to Es i / t f , and Vaccb is the back gate voltage corresponding to back accumulation given by (102 ) Qoxb
Vaccb =
MSb — C
—
Csi C
F
oxb
+
(O .5qNA tf C
oxb
(2 .99)
oxb
For FD devices, the saturation current can be written as (102 )
IDsat
= WµnCoxf
(VGf
2L(1 + a) (
_ Vtf) 2
(2 .100)
where tun the electron mobility, W and L are the effective gate width an d length, and 1 + a is the body factor corresponding for FD devices with
a
=
Csi C oxb Coxf (CSi
+
(2 .101 )
Coxb)
Fully depleted devices are sensitive to the uniformity in silicon fil m thickness. Equation (2 .98) and (2 .100) can be used to study the impact o f the film thickness nonuniformity on the electrical device performance . The special case of an ultrathin film, requiring that quantization effect s are taken into account, is addressed in Section 2 .3 .3 . Many analytical models have been proposed for fully deplete d devices, whereby it is commonly assumed that there is no potentia l decrease across the silicon substrate (102-104) . Although it has bee n pointed out that this assumption is not always valid (105, 106), more detailed models are either not sufficiently accurate or too complex. A more simple case is based on the assumption that the substrate potentia l decrease is linear (107), but the validity of this model is doubtful in th e case of a strong coupling between front- and back gate . The theory ha s also been extended to include the substrate effect down to 77 K fo r enhancement mode (108) and accumulation mode (109) FD SOI MOSFETs . Comparison with 2D MEDICI (a commercial device simulator ) simulations validate the approach, which provides more insight into th e substrate effect on the low-temperature threshold voltage and sub threshold slope . Although some basic electrical performance parameters of FD device s are discussed in Section 2 .3 .3, with special emphasis on low-temperature
2. Silicon Devices and Circuits
163
performance, it is important to mention that there also exists a differenc e between PD and FD devices from a reliability viewpoint (110) . In general, during hot carrier degradation the front channel of FD device s degrades less than the back channel, and FD devices are less vulnerable than PD devices . 2 .3 .2 . Accumulation Mode Devices Accumulation mode devices, such as p + —p—p + or n + —n—n + FETs, ca n be fabricated with a high reproducibility and controllability and have th e advantage of enabling good threshold voltage control without th e requirement of using a p + polysilicon gate material for the p-channe l devices (111) . This simplifies the process flow and reduces the manufacturing cost . These devices are characterized by a low leakage current an d a steep subthreshold slope. However, it has been reported that at both room (112,113) and liquid helium temperature (113) the current conduction mechanism is more complex than that for standard enhancemen t mode devices . This is illustrated for room temperature operation in the Ids - Vgf curve shown in Fig . 2 .44, demonstrating different kinks in the plot . This behavior points toward the existence of different threshold voltages , depending on the device biasing mode . The most common method used to experimentally determine th e threshold voltage is based on an extrapolation of the linear I ds Vs Vgf
x 1O-4 0.0 -0.2 -
-1 .0 ;
_
2 0 Front gate voltage, Vgf (V)
FIGURE 2.44. Drain current versus front gate voltage for a 2 x 20-µm accumulation-mode SOI MOSFET . The back gate voltage is varied between 15 and — 40 V in increments of 5 V [after Rotondaro et al . (113)] .
164
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen Vgb = -25v
Vgb = -25 V
Vgb = -25 V
~
-
~
E
•
.
-2 0 2 Front gate voltage Vgf (V )
FIGURE 2.45. Drain current, transconductance, and the derivative of the transconductance versus front gate voltage for a 2 x 10-µm accumulation mode p-channel device with Vgb = — 25 V [after Rotondaro et al . (113)] .
characteristic to zero drain current . This technique, however, results in large errors for accumulation mode compared to enhancement mode devices. A more consistent experimental method to determine the threshold voltage has been proposed by Terao et al . (114) and is base d on an extraction of the transconductance g m = dlds /dVgf and then the calculation of the derivative dgm /dVgf . The principle of the technique, which corresponds with the second derivative of the drain curren t versus front gate voltage and therefore is often referred to as th e double-derivative technique, is shown in Fig . 2 .45 . Each negative pea k corresponds to the threshold voltage of a different conduction mode, i .e . , for most positive Vgf to the onset of back gate accumulation, the second peak to body conduction, and the rightmost peak to back gate accumulation (113) . The same technique is also applicable to both FD and P D devices and remains valid to cryogenic temperatures (115) . However, at cryogenic temperatures care has to be taken to account for possible
2 . Silicon Devices and Circuits
165
transient effects, whereby the slow generation /recombination of minority carriers may lead to an apparent disappearance of the body curren t component (115) . At 4 .2 K extremely long time constants are ofte n observed, as will be discussed later . The use of either a light pulse or a large drain voltage can overcome this problem . A potential drawback o f the double-derivative technique to determine the threshold voltage i s related to the observation that the technique is sensitive to the impact o f the source—drain series resistance (116) . This will be particularly import ant for nonsilicided, LDD-type devices and in the case that freeze-ou t effects are dominant .
2 .3 .3 . Device Performance Parameter s The following sections give a brief discussion of important electrica l device performance parameters, which are discussed from a viewpoin t of the SOI CMOS potential for low-temperature applications .
2 .3 .3 .1 . Threshold Voltage For the different types of devices discussed previously, some genera l expressions for the threshold voltage have been given. It was als o mentioned that especially for accumulation mode devices the differen t conduction mechanisms have to be taken into account . The optimized extraction techniques are applicable to cryogenic temperatures . These observations are valid for silicon films that are not extremely thin . For state-of-the-art devices, the silicon film thickness is strongl y reduced, resulting in the use of ultrathin films . According to the classica l theory, the threshold voltage decreases monotonically with decreasin g film thickness due to a decrease of the charge in the depletion layer . For a buried channel MOSFET the threshold voltage is given by (117)
VTf—
VFB
+
(qNt
Coxf
(f
CSi sox),
C+S Si
1 S
+
CSiCoxb CSi
+
Coxb
+
C SiC oxbVg b
Coxf ( CSi + C oxb)
(2 .102 ) where VFB is the flat-band voltage, and Os is the surface potential a t threshold . However, when t f decreases below a critical value, quantization effects have to be taken into account, resulting in the occurrence o f 2D subbands (118) . This is schematically illustrated in Fig . 2 .46, which shows simulated results of the impact of the film thickness on the minimum channel length leading to punch-through . The strong quantization of the short-channel effects occurs for a film thickness less than
166
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
10-2 ~ Qa
1
. 10 1
Silicon Layer Thickness (nm)
FIGURE 2.46 . Simulated minimum channel length Lmin dependence on the silicon film thickness t f for surface channel (SC) and buried channel (BC ) MOSFETs / SOI at room temperature, according to the classical and quantu m mechanical approaches [after Omura et al. (118)] .
5 nm due to an increase in the effective band gap energy and a decreas e in the effective density of states resulting in an increase in the majorit y carrier extension . The figure also gives simulated results for surfac e channel devices, indicating that in surface channel MOSFETs quantizatio n effects are more severe as an increase in the energy band gap leads to a n increase in the depletion layer width with increasing built-in potential . The quantization effect becomes more pronounced for low-temperature operation . A representative parameter to study short-channel effect s is the drain–voltage derivative of the threshold voltage, g = (dVtf / dVds) . The classical and quantum mechanical simulated values of this parameter are shown in Fig . 2 .47 and are compared with experimenta l results for 0 .1-,um buried channel p-MOSFETs on SIMOX with an 8-n m film thickness . No quantization effects are noticed at 300 K and th e experimental results agree with the classical curve . The g increase fo r lower temperatures is caused by a decrease in the effective density o f states, leading to a decrease of the Debye length . Classically, the Debye length would increase with decreasing operating temperature (119) . Due to the quantization effects, the threshold voltage no longer decreases fo r decreasing film thickness but rather increases for a film thickness belo w
2. Silicon Devices and Circuits
167 Ume 0 . I p m
u
100
A
nm
N porlxlO tl tn;-3 Vo= V ' ..
Quantum
•
*d
R
o
►
w*v
\ Classical ~lassical
1ß i
102
10 3
Temperature (K) FIGURE 2.47 . Temperature dependence of the drain–voltage derivative of th e threshold voltage (g) for O .1-µm p-MOSFETs on SIMOX with t f = 8 nm. Th e experimental points are the average values for five measured devices [afte r Omura and Itzumi (119)] .
a critical value . The latter depends on technological (geometrical features and doping density) and operational parameters (voltages an d temperature) .
2.3.3.2. Oxide Charge s The essential difference between a bulk and a SOI device is the fact tha t the latter has a front gate oxide and back BOX . Although there has bee n much improvement, the quality of a gate oxide on a thin silicon film i s of a slightly inferior quality compared to the quality of a standard gat e oxide (120,121) . This results in a higher interface trap density, dependin g on the surface finishing technique that is used . However, of considerabl e inferior quality is the BOX . For thin silicon films there is a direc t coupling between the front and back interface . This necessitates the availability of accurate extraction procedures for the oxide and interfac e charges . As will be discussed later, the interface trap density determine s the subthreshold swing .
168
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
The standard capacitance and conductance techniques to determine the interface trap density are difficult to apply for SOI devices becaus e of the unpractically large capacitor areas involved and the large film series resistance. A better approach for SOI devices is based on using a charge-pumping technique (122) . When pulses from accumulation t o inversion are applied to the gate and the source and drain are kept at a small reverse bias, a net current can be measured at the film contac t (123) . The current corresponds with charge that is pumped from th e source and drain via the interface traps toward the film contact. The measured back interface trap density is a few times 10 11 cm - 2 eV -1 an d about an order of magnitude larger than that at the front interface (122) , which was also confirmed from measurements based on extrapolation of the threshold voltage (124) . A drawback of the charge-pumping technique is that one needs a film contact and a dedicated test structure . For accumulation mode devices the interface trap density can also b e determined from the temperature shift of the threshold voltage (125) because both at room temperature and at 77 K the flat-band voltage is equal to the front threshold voltag e Qox f MSf Coxf
V t f - VFB FB
c
(2 .103)
ox f
where Q . . f is the front oxide charge density and is about 4q .1 0 1 ° C / cm 2 (105) . The front threshold voltage can accurately be determined by th e previously discussed double-derivative technique . The interface tra p charge density corresponds t o Ei
Qit = q
J
EF
Nit (E)dE
(2 .104)
In general, it can be assumed that the interface traps act as donors i n the lower half of the band gap and as acceptors in the upper half . Normally, one has to take into account that the interface trap density is not constant over the band gap but shows a tendency to increase towar d the band edges . The exact amount of increase strongly depends on th e measurement technique used (126) . Exact calculations should also tak e into account the energy dependence of the capture cross sections . Therefore, it is common to define an effective density of interface trap s over the band gap, which corresponds with the value at midgap . Measurements as a function of temperature indicate that the interface trap density is increasing with decreasing temperature (127,128) . In the case of a nonuniform distribution of the interface trap density over th e band gap, the increase of the effective density with lower temperatur e can be explained by the temperature shift of the Fermi level E F .
169
2 . Silicon Devices and Circuits
2 .3 .3 .3 . Subthreshold Swin g The subthreshold swing for partially depleted devices is given by th e conventional relationship of bulk transistors :
s
_ dV gf
_ kT
d tog(Ids )
q
1 + C depl + Citf
l0 g
C
ox f
(2 .105 )
where Cdepl is the depletion layer capacitance and can be used t o characterize the interface trap density. In the case of fully deplete d devices, however, the expression has to be modified in order to take int o account the coupling between the front and the back interface . Thi s results in (129 )
s
=
kT q
log
[(i +
Citf Coxf
+
_
CSi
coil
(C Si 2/C oxb•Coxf) 1 + (Citb /C oxb) + (CSi. / Coxb)
(2 .106 )
Within a few percent accuracy, the same expression is valid for an accumulation mode device (130) . The subthreshold swing depends on the depth in the silicon fil m where conduction takes place and thus varies with the back gate bia s conditions (130,131) . Although this can be modeled, it leads to comple x analytical expressions . Figure 2 .48 illustrates the back gate bias depend ence for an accumulation mode p-channel SOI MOSFET . Equation (2 .106 ) corresponds with the minimum in the S curve . For another gate bias one has to add a correction term to the expression . An analysis of the subthreshold swing is also often used to characterize the interface trap density . However, Eq . (2 .106) points out that S depends on both the front and the back interface trap density . In the case
100 -g
.c~ .~ 2S
20
COI
Q, -10
AM SOI PMOS 1. .~ $ Lim W as 20 Vds a: -0.1 "K T as 300 K (?
j,,i.tt!
8 V (minimum point) 10
Back Gate Shia V 1,1 bl-V1
FIGURE 2 .48. Back gate bias dependence of the subthreshold swing for a L = 5 pm AM SOI p-MOSFET at 300 K and V DS = - 0 .1 V [after Martino et al . (125)] .
170
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
of accumulation mode devices it has therefore been suggested that th e front interface trap density should be determined first, based on th e determination of the threshold voltage at two different temperatures (e .g ., room temperature and 77 K) . Afterwards the minimum in the S curve can be used to determine the back interface trap density . This method is called the one swing and dual-threshold voltage measurement (125) . Care has to be taken, however, to optimize during the subthreshold swing measurement the rate of the change of the front gate bias i n order to ensure a stable swing value determination .
2 .3.3.4. Series Resistance As discussed previously, an LDD is commonly used in scaled technologies to reduce hot carrier degradation effects . Although SOI should b e more resistant, LDDs are also being implemented routinely . An important drawback of LDDs is that they increase the parasitic series resistanc e of the MOSFET, which may become even more pronounced at lo w temperatures due to freeze-out of free carriers . The total device resistance consists of the sum of the series resistance RS and the channel resistance R eh . Optimized techniques for the determination of the series resistance have recently been proposed and are based on a compariso n of the experimental device characteristics with MEDICI simulations, taking into account second-order effects impacting on the carrier mobility (132,133) . It is essential that the resistance is also gate voltag e dependent (134), as illustrated in Fig . 2 .49 for the channel and series resistance of PD MOSFETs operating at 77 K . A simple technique base d
FIGURE 2.49 . Channel and series resistance versus gate overdrive voltag e (VG* = VGf – VT ) for 10- and 2-µm SOI PD n-MOSFETs operating at 77 K . (134)
17 1
2 . Silicon Devices and Circuits 0.36 T=77 K
i
PD SUI n- MOSFET
0.34 -
_ _
0.32 E 0 .30 - RT value
X
0 .28 -
0 .26
0
1 2 3 Gate Overdrive Voltage (V )
4
FIGURE 2 .50 . AL versus gate overdrive voltage (VG * = VGf — VT) for 10- and 2-µm SOI PD n-MOSFETs operating at 77 K (134) . on the combination of a long reference device and a shorter L-arra y transistor can be used to determine the series resistance (135, 136) . To derive the effective gate length or AL, one has to take into account the series resistance (134) . A crucial question is whether or not the effective gate length is temperature dependent due to the occurrence of carrie r freeze-out in the LDD regions . Figure 2 .50 illustrates that in the appropriate voltage range, the same AL value is found at 77 K and at roo m temperature . It has been noted in the past that the series resistance not onl y impacts the characteristics but also the extraction of the device parameters in linear operation, such as the threshold voltage, the sub threshold slope, and the transconductance (135-137) . This is particularl y pronounced for FD SOI MOSFETs (137) . In order to reduce the series resistance effect on the VT extraction, a modified technique has bee n proposed (138), which is particularly suitable for SOI .
2 .3 .3 .5 . Transient Effects When applying a bias step to the front or the back gate of an SO I MOSFET, carriers have to be supplied in order to establish the steadystate channel. Especially in weak inversion and at small drain bias Vds , where the supply from the source is small, carrier generation/recombination processes will dominate the transistor response . As a result, the measured channel current will show a transient behavior, whereby th e time constants will be more pronounced for low bias values . Since the generation of carriers at low electric fields is thermally activated, th e
172
E . A . Gutiérrez-D ., C. Claeys, and E . Simoe n
FIGURE 2.51. VT instability in a PD SOI n-MOSFET at 4 .2 K . Curve 1 is the initial measurement just after cooling the unbiased device . Curves 2 and 3 are recorded after the drain has been swept to 3 and 5 V, respectively . Curve 4 ha s been registered after 24-h•unbiased relaxation at 4 .2 K after measurement 3 (140) .
typical response time will increase drastically upon cooling, giving ris e to time constants of microseconds at 300 K, seconds at 77 K, and up to hours at 4 .2 K (139-141) . In the latter case, the transients last so long tha t the device can be switched to a metastable charge state . As a result of the slow transistor response at cryogenic temperatures , determination of the primary device parameters, such as the threshol d voltage VT or the subthreshold slope S, becomes delicate. An example is shown in Fig . 2 .51 for a PD SOI n-MOSFET at 4 .2 K, demonstrating th e shift of the input characteristics for different device history (140) . Another consequence is that one has to optimize the step in the gate voltage for accurate subthreshold slope determination, as illustrated in Fig . 2 .52 for an accumulation mode SOI p-MOSFET (142) . For too high DVgf (or too few points per decade), erroneous S values will be obtained . Too many data points will result in a noisy measurement and a loss o f accuracy. It has been observed that these transient phenomena are particularl y pronounced for long-channel devices, whereas they improve for shorter effective lengths at the same temperature . The V T instabilities are
2 . Silicon Devices and Circuits
173 12
40 E
10
stability 6
AM SOI p-MO S L =5p m W = 20 p m T – 77K
a
.o■il
4 2
O ~0 3
.
i
.
a~. ~ ~
10
.
10
10
Front Gate Bias Step (mV) FIGURE 2 .52 . Subthreshold swing as a function of the front gate voltage ste p at 77 K for a 20 x 5-µm AM SOI p-MOSFET (142) .
pronounced for PD devices, whereas they are small to negligible for full y depleted architectures . The use of a body tie for PD transistors only partially removes the anomalies, and particularly at low cryogeni c temperatures transients will remain prominent . A practical way to avoid these problems is to cool the device unde r the appropriate biases and then measure the characteristics at lo w temperatures . However, any subsequent abrupt bias change will pro duce new transient effects and hence measurement instabilities . This i s illustrated by the results of Figs 2 .53a (300 K) and 2 .53b (77 K) showin g the input characteristics in linear operation for a PD SOI n-MOSFE T before and after a so-called "latch" measurement, whereby the front gat e bias is swept from 0 V to strong inversion at high drain bias . In such a case, carrier generation by band-to-band multiplication will occur in th e large lateral field near the drain . Part of the created charge will b e retained in the film at low temperature, whereas the created hole s (n-MOSFET) will be swiftly removed at room temperature, thus explain ing the negligible VT shift observed there . Therefore, great care must b e taken in the cryogenic characterization of SOI components since it is not obvious to develop a consistent and reliable extraction technique eve n for the basic device parameters .
174
E . A . Gutiérrez-D., C . Claeys, and E . Simoe n
FIGURE 2.53 . Input curves for a 20 x I-µm PD SOI n-MOSFET at 300 K (a) an d 77 K (b) . Curve 1 is the starting measurement in linear operation . Curve 2 i s measured after latching the device for a V ds = 3 V, and curve 3 is the relaxatio n of curve 2 to the original state.
2 . Silicon Devices and Circuits
17 5
2 .3.3.6. Floating Body Phenomen a From a design standpoint, it is often preferred not to use a film contac t because this lowers the packing density . Some pros and cons of buried contacts are addressed in Section 2 .3 .4 .3 . Omitting these contacts implie s that the silicon film remains floating during operation, forming the basi s of undesired physical effects which are called floating body effects . The most important phenomena are (i) a kink in the drain current characteristics, (ii) the observation of threshold voltage instabilities, (iii) pronounced hysteresis and transient effects, and (iv) parasitic bipolar action . These effects will strongly manifest themselves especially during cryogenic device operation (143) . The physical basis for most of these floating body effects in, fo r example, n-MOSFETs is related to impact ionization in the pinch-of f region near the drain which is caused by channel electrons accelerate d by the high lateral electrical field, and the charge storage in the silicon film . Generally, this impact ionization-related floating body effects are far less pronounced for p-channel devices (see Chapter 3) and shoul d also be less important in accumulation mode transistors . A schematic illustration of the impact ionization-generated current flow and th e charge buildup in the associated silicon cavity, formed by front, back, and sidewall oxides and by the source and drain junction, is given i n Fig. 2 .54 . For low to moderate carrier generation levels, the holes in a n n-channel device are annihilated by recombination in the silicon film . However, for higher carrier generation levels only a part of the generated carriers recombines, whereas the majority will be driven by the electric field toward the source . The gradual carrier accumulation raise s the potential near the source and may forward bias the source—fil m junction. The potential change depends on the film resistivity and i s strongly temperature dependent . At low temperatures carrier freeze-out has to be taken into account, as will be discussed in detail in Chapter 3 . The forward biasing of the junction results in a decrease in the threshol d voltage and consequently in an increase in the channel current . The amount of charge stored in the silicon cavity depends on the size of the cavity, the operating conditions, and the time constant of the involve d carrier trapping/ detrapping and generation /recombination mechanisms . For cryogenic temperatures these time constants are relatively long , i.e ., up to several minutes at liquid helium and resulting in the observe d hysteresis and transient effects . A theoretical analysis of several floatin g body phenomena, including the kink effect, is given in Chapter 3 . It i s important to note that floating body effects do not always have to b e considered as negative . By controlling the transient effects it is possible
176
E . A . Gutiérrez-D ., C. Claeys, and E . Simoe n
FIGURE 2 .54. Schematic representation of the impact ionization-generated current flow in a SOI nMOST (a) and the SOI cavity which can be considered a s a potential well formed by the front, back, and sidewall oxides and by the sourc e and drain junctions (b) .
to design a device with a metastable charge state, whereby the threshol d voltage of the device can be preset . Based on this multistable charg e controlled memory (MCCM) effect, new applications such as a singl e transistor memory cell and an optical detector can be envisaged operating at cryogenic temperature (144) . The concept of a silicon cavity fo r future microelectronic devices such as single electron transistors an d quantum wells will be discussed later . Although the kink effect leads to a higher drive current, it i s undesirable because it causes current overshoots, is difficult to mode l and to implement in circuit simulators, and prevents the use of CMO S SOI circuits for analog applications . Most of the floating body effects can
2 . Silicon Devices and Circuits
177
be suppressed or even eliminated by implementing a film contact, as wil l be discussed later . In addition, various technological modifications t o reduce floating body effects have been proposed (145—147) . The main idea is to apply an extra ion implantation by inert atoms (Ge, Ar, . . .) to create adjacent to the source (drain) junction lattice damage, whic h recombines the injected holes and therefore strongly reduces the curren t gain of the parasitic bipolar transistor . Another solution is the use of fully depleted devices (148) . The kin k effect is then suppressed because of the reduction of the electrical fiel d near the drain leading to a lower impact ionization probability and th e prevention of carrier accumulation in the film . Fully depleted device s have the additional benefits of larger drain saturation currents and superior subthreshold leakage . However, depending on the film thickness used, these devices may be prone to the parasitic bipolar transistor action leading to latch-up problems (149) . 2 .3 .4 . Alternative Device Concept s In addition to the large variety of technological options to improve th e electrical device performance, it is also possible to rely on desig n optimizations . The following sections address some design considerations that are important for the use of SOI circuits in cryogeni c applications .
2.3.4.1. Body Contacts For partially depleted devices the floating body effects can be avoide d by grounding the silicon film . However, the use of so-called body ties o r body contacts have a negative impact on the silicon estate, thereb y reducing the packing density. The typical loss of 15—25% in silicon are a per device can be reduced by using bottom body contacts, whereb y locally the silicon film makes contact with the silicon substrate (150) . Although these body ties result in a speed penalty due to the increase i n gate area and capacitance, the increased radiation hardness and th e potential for use in high-temperature applications such as automotiv e are benefits (151) . Whereas at room temperature the floating body effect s can be eliminated, this is only partially the case at cryogenic temperatures, as illustrated in Fig . 2 .55 for a 2 x 1-µm SOI nMOST operating a t 4 .2 K (152) . By grounding the film, the drain current is much flatter an d the hysteresis is suppressed . However, the kink effect is not avoided bu t rather increased . The reduction of the hysteresis and the suppression o f threshold voltage instabilities are related to the fact that a major part o f the multiplication-generated carriers is drained away by the contact and
E . A. Gutiérrez-D ., C . Claeys, and E . Simoe n
178 0 .-..
,–p Q
0 .01 0
float .
SQ 1 nMOST 20 µrnxi µm
VOS::5 V
0.00$ ` T=4 .2 K
" 4 V
3 V 2
0:0000
f
4MPdr#r 1
2
A
~
5
6
I V
3
4
Drain Voltage VDS (V)
0 .010 4C
0
~
coon,
SOI nMOST
,
0
20
6 V
~~.tnx! g.m
T=4 .2 K.
"e
s v 0 00e
w A... 0404
4
V
3
~,x
.e..«.
0
0,002 0 .000
VaS .:2 V
. 0
V
~
.-^~
1
2
3
4
Drain Voltage VDS
5
.
.s..
6
(V )
FIGURE 2.55. Output curves for a partially depleted SOI n-MOST at 4 .2 K with the body contact floating (a) or grounded (b) [after Simoen and Claeys (152)] .
thus not available for trapping or for charging the silicon film . The lower trapping probability will facilitate the forward biasing of the source—fil m junction and thereby enhancing the kink effect . In addition, one has t o take into account the high series resistance of the body contact a t cryogenic operation (153) . To some extent, this problem can be reduce d by implementing multiple or distributed film contacts at the expense of silicon area .
2 . Silicon Devices and Circuits
17 9
2 .3 .4 .2 . Twin-Gate Device s A very interesting design concept to avoid floating body effects is th e use of a so-called twin-gate structure (154) . As schematically illustrated in Fig . 2 .56, the twin-gate structure is realized by putting two commo n gate transistors in series . The middle reach-through n + region has a floating potential and serves to recombine the impact ionization generated holes . In fact, the structure consists of a master transistor TM with gate length LM and a slave transistor TS with gate length LS . Only the slave transistor will suffer from the floating body effects so that for sufficien t large LM / LS ratios the master transistor will have ideal output character istics . Not only the kink effect but also the parasitic bipolar effect are suppressed in the master transistor . This is illustrated in Fig . 2 .57, which shows the output characteristics of a single 1- and 2-,um transistor an d the twin-gate structure with a master of 1 pm and a slave of 2 µm an d with a master of 2 ,um and a slave of 1,um . It can clearly be seen that the latter structure is effective in suppressing the kink, in which case it ha s been made more pronounced by applying a negative back gate bias . From a design standpoint, the structure looks like a well-know n cascode MOS configuration . However, the basic operating principle i s different because the twin-gate essentially operates as a single transisto r according to the master—slave mode, whereas the cascode configuration operates like a tetrode and therefore requires a uniform voltage distribution over the two transistors . The twin structure is also very effective in suppressing the kink-related low-frequency noise (155), as discussed in
FIGURE 2 .56 . Schematic illustration of the twin-gate structure, together wit h the measurement configuration . The structure consists of a master (T M) and a slave (TS ) transistor in series, with a common source and gate [after Gao et al . (154)] .
180
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
~
;
r
S I n #s. k
.F
Twin, r ., . 2 .0
~;..~a ,;
4 [,t't,.>.'t` 'Twin., o,5
Li , ~
•Y
o
/
s
i
y{
)
~
~wv
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e
♦ r
4
lr.
f :l
n.
4.i3't:~?,., . âY
~~
•
v
^-
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,~„~• h'
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er°~^fi
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FIGURE 2 .57 . Comparison of the measured output characteristics for VGS = 3 V between twin MOSFETs with two different configuration of LM = 2 pm, LS = 1 pm (curve 3) and the case of an inverse twin with L M = 1 pm, LS = 2 pm (curve 4) . A negative back gate bias has been applied in order to make the kin k effect more pronounced and to assess the effectiveness of the kink suppressio n of the twin structure [after Gao et al . (154)] .
Chapter 3 . The practical applicability of the twin-gate concept fo r cryogenic applications has been demonstrated by studying the cryogenic performance of inverter structures (156) . 2 .3 .4.3. Gate-All-Around Device s Enhanced electrical device performance of thin film devices can b e achieved by using dual-gate devices with volume inversion, resulting in a significant improvement in the subthreshold swing, the transconductance, and the current drive capability (157) . The device is biased so tha t there is strong inversion through the entire silicon film . The curren t enhancement is much higher than expected due to the fact that there ar e two channels present. An optimized practical realization of the concep t is the so-called gate-all-around (GAA) structure, first proposed by Colinge et al . (158) (Fig . 2 .58) . The front and back gate oxides have th e same thickness and are of identical quality . For the device fabrication, only a few additional processing steps are needed compared to standar d SOI processing. After definition of the active areas, a cavity must b e etched so that the subsequent gate oxidation grows a thin oxide laye r around the resulting silicon bridge . The threshold voltage adjustment implantation is then followed by a low-pressure chemical vapour de -
2 . Silicon Devices and Circuits
18 1
FIGURE 2 .58 . Schematic illustration of the gate-all-around device for obtainin g volume inversion (158) .
position of polysilicon and patterning step . Both standard and GAA devices can be processed simultaneously . The superior performance of GAA devices is related to the higher transconductance and a subthreshold slope approaching the theoretica l limit of 60 mV/ decade at room temperature . The I ds – Vgf characteristic s for a 3 x 3-,um standard and GAA transistor are shown in Fig . 2 .59, clearly demonstrating the significantly improved subthreshold slope fo r the GAA device. Related to the subthreshold slope and coupled with th e volume inversion is the considerable reduction of the low-frequenc y
FIGURE 2.59 . Drain current in linear operation of a 30-nm, 3 x 3-µm GAA n-MOST compared with the drain current of standard SOI n-MOST of the sam e dimension [after Colinge et al . (158)] .
182
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
input referred noise (159) rendering these devices suitable for analo g applications . GAA devices show remarkable total dose hardness up t o the 30 Mrad level (160,161) . GAA devices also perform very well a t cryogenic temperatures down to liquid helium, although they migh t suffer from some voltage instability (162) . Somewhat unexpected is th e observation that the back gate has an impact on the GAA characteristics . This allows exploition of the previously mentioned MCCM effect .
2 .3 .5 . Deep Submicrometer Devices For ultra-thin film devices, quantization effects are not only importan t for the threshold voltage, but also may influence the transport propertie s in the silicon film, thereby modifying the transconductance . The trans conductance curve can exhibit oscillations and a step-like behavio r (117, 163, 164) . Although the scattering processes governing the carrie r mobility may cause oscillations, it has been postulated that local deviations in the film thickness are the underlying cause . These are relate d to the morphology roughness of the film—BOX interface . It should b e mentioned, however, that local fluctuations of the oxide charge at the to p BOX layer cannot be excluded . The anomalous transconductance behavior has been observed at both room and cryogenic temperatures . To model the mobility variations, one has to take into account that th e surface inversion layer can be larger than the silicon film thickness . To study the impact of quantum mechanical effects on the transpor t properties experimentally, silicon quantum wire structures have bee n fabricated (165—167) . The carrier confinement in the 2D electron gas i n the silicon film results in a splitting of the conduction band int o subbands . The filling of these subbands with electrons appears as a n oscillation in the current transport and associated transconductance . Th e potential change DF in the film can be modeled by the following equation (165) :
A O (vGf) -
h2 8m
~
t f2
[n 2 — (n — 1) 2 ]
(2 .107)
where h is the Planck's constant, m* is the effective electron mass i n silicon, and n is the quantum number for the different subbands . A typical transconductance curve for a 50-nm-wide GAA quantum wire fabricated on a SIMOX substrate is shown in Fig . 2 .60 for operation at 1 .5 K . The quantization of the drain current can be clearly observed a s local kinks . The oscillations remain present up to about 40 K and 20 mV source—drain voltage (165) .
2 . Silicon Devices and Circuits
70 60 50
183
~. Vsd..–.200 g V
f=14 .aH z .,. T.=1 ..5 K L=.2$.Lm pm
oVg -0 .7 V ~----.~~•+
C75" 40
C5
(9 30 20 10
—
0 .0
VT 1 .0
2 .0 Vg [V ]
3 .0
FIGURE 2.60 . Transconductance as a function of the gate voltage for a 50-nmwide silicon quantum wire GAA structure operating at 1 .5 K [after Morimoto et al. (167)] .
Figure 2 .61 illustrates the conductance fluctuations in a 200-nm-lon g and 100-nm-wide channel of an SOI MOSFET operating at 300 mK (168) . The spatial potential variations in the channel lead to the formation o f islands or quantum dots, the size of which determines the oscillatio n period of the conductance modulation . The spikes observed in Fig . 2 .61
~.Ox104 -
a 4 .Ox104 , ...
~
ca
'g 2 8 2.0004 -
0 .0 ,/ f8
1 .0
~
1 .2 Gate Voltage (v)
... . ..
t
1 ..4
FIGURE 2.61 . Transconductance as a function of the gate voltage for a 200-nmlong and 100-nm-wide SOI MOSFET at 300 mK [after Peters et al . (168)] .
184
E . A . Gutiérrez-D ., C . Claeys, and E. Simoe n
(e .g ., at Vgf = 1 .3 V) are caused by random telegraph signals in the drai n current with typical time constants from hundreds of microseconds t o tens of seconds (169) . Future scaling down of the device geometries will be limited b y physical constraints so that phenomena such as ballistic transport , tunneling, and quantum mechanical effects may control the devic e operation. Although 70-nm MOSFETs have already been fabricated, the 1997 Semiconductor Industry Association (170) road map is predictin g that in approximately the Year 2015 a 30-nm feature size will be revised . This implies that research into so-called nanoelectronics will become o f key importance . Whereas for a long time this research domain wa s reserved for III—V compounds, silicon-based devices are just around the corner . A particular class of devices gaining increasingly more interest i s the single electron transistors, based on the Coulomb blockade . Although currently processed mainly on bulk material, SOI substrates may provide some benefits . The operation of single electron transistors (SETs) is based on the fac t that the device capacitance is sufficiently small so that a single electro n leads to a detectable voltage change . These structures require a smal l silicon island separated from the source and drain electron reservoirs b y tunnel barriers and capacitively coupled to the gate electrode . The device performance strongly depends on the operating temperature . In general, the minimum operating temperature is given by
T « (q 2 /2kC)
(2 .108)
The Coulomb charging energy of a single electron must be larger tha n the energy of the thermal fluctuation kT. Therefore, the original SETs were operating at liquid helium temperature or below ; otherwise, the needed capacitance was too small, imposing difficulties from a fabrication standpoint. If the dielectric layer between the two capacitor plate s is sufficiently small, an electron can tunnel from one capacitor plate t o the other . A recent in-depth overview of the different theoretical an d experimental aspects of SETs was given by Smith (171) . For 77 K operation, it is required that the capacitance be strongly reduced (to a few aF) by, for example, using extremely small geometries, whic h imposes tremendous technological challenges . However, SETs successfully operating at 20 K have been reported (172) for devices processed b y using the so-called step edge cutoff (SECO) fabrication scheme, allowin g less stringent lithographic techniques to be used . A further optimization of these SECO SETs recently resulted in 77 K operation of SETs fabricated in a 0 .1-,um technology (173) . In principle, the operation of a SE T can be explained by studying the charging effects in the silicon cavity , which are also the basis of the MCCM effect . In this case, however, the
2 . Silicon Devices and Circuits
18 5
size of the cavity is so small that charging by a single electron has a measurable effect on the electrical performance of the structure . In th e 1980s most of the SETs were fabricated in III—V materials . A popular fabrication concept to study the physical aspects involved, such a s Coulomb blockade and quantum effects, is based on the split-gate desig n (174, 175) . The split gate can be either the upper or the lower level . Such a dual-gate concept has also been successfully applied to SOI structures (176) . The Coulomb blockade oscillations were demonstrated at 15 mK , in which case the observed 16 .4 mA periodicity allows the estimation o f an involved capacitance of about 13 aF . The development of single transistor memory cells provides a grea t potential for SETs to be used in the design of nonvolatile RAMs, fo r example, for mobile computer and communication applications (177) . The real breakthrough will of course depend on the required operatin g temperature, although there are strong indications that further improvements may eliminate the requirement for cryogenic operation . The feasibility of a room temperature SET memory, processed on a SO I substrate, has been demonstrated (178) . The operation is based on a narrow-channel transistor with 10-nm width, i .e ., smaller than the Debye screening length, and the use of a very small (7 x 7-nm) floating gate between the channel and the control gate . A single electron on th e floating gate will, even at room temperature, lead to a quantize d threshold voltage shift . 2 .3 .6 . Summary This section outlined the basic operating principles of the different type s of SOI transistors . Special attention was given to the potential for usin g SOI CMOS in cryogenic applications . SOI technologies are no longer restricted to niche markets but are gaining increasingly more interest fo r technologies with deep submicrometer feature size . It is expected that a real commercial use of high-volume products will be developed in the near future . Additionally, for future nanoelectronic applications, such a s single electron devices and quantum wires in silicon, the unique feature s of SOI devices may lead to a real breakthrough . Although the market o f commercial applications will increase, SOI also has a strong potential for cryogenic electronics .
2 .4 . THE BIPOLAR TRANSISTO R The bipolar transistor has been and is currently one of the leadin g devices that has pushed the evolution of high-speed communication
186
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
systems . Bipolar technology evolved from the traditional bipolar structure (179) to the polysilicon emitter bipolar structure (180) and to the most advanced heterojunction bipolar transistor (HBT) (181) . This evolution has led to an impressive advancement in the high-speed communi cation systems, in which cutoff frequencies of 115 GHz (182), have been reached . The bipolar transistor has been combined with MOS transistor s in the BiCMOS technology (183) to obtain the best of both technologies : high speed from the bipolar transistors and low power consumption from MOS. For applications in which the operating temperature need s to be lowered to cryogenic temperatures, the MOS transistor behave s well, whereas the bipolar transistor suffers from freeze-out in the bas e which inhibits its use as a transistor . However, the bipolar transisto r which has a base made of a SiGe alloy, the HBT, does not suffer fro m freeze-out effects and is able to operate properly down to temperature s below 77K . In this section, the main figures-of-merit of the bipolar transistor will be presented and analyzed as a function of the operating temperature . The different bipolar technologies available today will also be presented, and their advantages and disadvantages as devices for cryogenic applications will be discussed . 2 .4 .1 . Bipolar Technologie s As in the case of MOS transistors, there exists a considerable variety o f technologies to fabricate bipolar transistors . However, we will restric t our discussion to the most representative ones, namely, the standar d bipolar transistor (SBT), the polysilicon emitter bipolar transistor (PEBT) , and the HBT . 2 .4.1 .1 .
The Standard Bipolar Transisto r
The SBT was first developed by Bardeen and Brattain (184) in 1948 . However, the structure first developed in 1948 was not of a practical us e for high-speed electronics because of the thick base dimensions . Thus, the development of solid-state impurity diffusion technology in 196 5 gave birth to the so-called planar bipolar transistor, which for practica l purposes we consider standard . The cross section of this SBT is shown in Fig . 2 .62 . The p-type base and n + -type emitter are implanted in such a wa y that the thickness of the base region, the region between the bottom o f the emitter and the top of the collector, is well controlled and kept short . By keeping a short base width, the speed of the transistor increases . The previously described technology has several limitations, including a
2 . Silicon Devices and Circuits
18 7
FIGURE 2 .62 . Cross section of a SBT fabricated with impurity implantation an d diffusion technology.
large parasitic capacitance and resistance and a relatively deep base junction that does not allow for high cutoff frequency fT . To overcome this problem, the PEBT is introduced .
2 .4 .1 .2. The Polysilicon Emitter Bipolar Transisto r The first PEBT was proposed in 1973 by Takagi et al (185) . They utilized a doped polysilicon layer as a diffusion source to form the emitter . Thi s layer also serves as a contact for the emitter . The structure looks like the one shown in Fig . 2 .63 . This structure has the advantages of reducin g parasitic components, reducing contact resistances, reducing size, an d increasing cutoff frequency, and it is less sensitive to temperatur e compared with the SBT . This structure is about one-third the size of th e standard planar bipolar transistor .
FIGURE 2.63 . A PEBT structure using the super-self-aligned technique .
188
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
The electrical characteristics of a PEBT differ from those of a SBT in that the carrier transport takes place through the interfacial layer between the polysilicon and the monosilicon layers . A complete study an d technological description of the PEBT can be found in Kapoor an d Roulston (186) .
2 .4.1 .3 . The SiGe Heterojunction Bipolar Transistor The SiGe HBT is the only Si-based device with electrical characteristic s comparable to those of III—V-based devices . The SiGe HBT perform s much better than the standard bipolar and the PEBT, and it is als o compatible with existing Si technology . The HBT was first demonstrated in the late 1980s (187) . Actual SiGe HBT fabricated with selectivel y grown SiGe base (188) is shown in Fig . 2 .64 . Devices fabricated with thi s technology have reached fT frequencies in the range of 30 GHz (189) . An excellent review of the technological characteristics of SiGe HBTs can b e found in Luy and Russer (190) .
2 .4 .2. Electrical Performance In order to understand the differences in performance among these thre e technologies and their behavior as a function of temperature, it i s necessary to examine their operating principles .
FIGURE 2.64 . Cross section of a SiGe HBT fabricated with selectively grow n SiGe base.
2 . Silicon Devices and Circuits
189
2 .4.2 .1 . The Collector/Base Currents and the DC Gain hF E We consider npn transistors only . Thus, the collector le current of a standard bipolar transistor lc , (191), a PEBT J,p (192), and a SiGe HBT Ic h (193), are modeled by Ics
qD n n i
=
2 [
eVBE/Vt
_ 11
(2 .109 )
QBeff T4
Icp —
Cc
, e(RVBE —Egb/kT )
(2 .110 )
(\Pb T )
and Ich
qD n n iSiGe
2
,
QB eff
[
eVBE/vt —
1]
(2 .11 1 )
where D. is the diffusion constant for electrons in the base, n i is the Si intrinsic concentration, VBE is the emitter-base voltage, Vt is the thermal voltage, and QBeff is the integral of the base dopant inside the neutral base known as the Gummel number . This "effective" Gummel number which accounts for degeneracy and band gap narrowing effects i s modeled by (194) 2
QBeff
ni0 n ib
•
Na
L tanh (Z5b)
(2 .11 2 )
where n î0 2 is the equilibrium pn product in undoped silicon, n ib 2 is the intrinsic concentration in the base, L n is the diffusion length for electron s in the base, and Wb is the base width. The following parameters are used in Jcp : C c is a constant (195), p b (T) is the temperature-dependent sheet resistance of the base, which ac counts for the temperature dependence of the carrier mobility, and E gb is the band gap in the base . For the Ich current, the only difference is the nisiGe, which is the intrinsic carrier concentration of the SiGe layer, given by (196 )
n iStGe • 2 = n i Si 2
e(oEg/kT)
= n iSi 2
2 ~
F 1/2
Ev
k1, EF
e [(EF — Ev) — BGN /k T]
( 2 . 113)
where nisi is calculated following the Boltzman statistics, whereas n isiG e considers Fermi—Dirac statistics to account for band gap narrowing (BGN) occurring in the highly doped base of the HBT . The base currents JB for these three different bipolar devices are written as follows : For the SBT, if recombination in the neutral base a s well as in the emitter—base space charge layers is neglected, the bas e
190
E . A . Gu tiérrez-D ., C. Claeys, and E . Simoe n
current IBs is considered to be formed of pure injected holes into th e emitter:
Dp ni 2_ Ls
[e
Q Eeff
VBE/vt —
(2 .114 )
]
where QEeff is the Gummel number for electrons in the emitter, simila r to Eq . (2 .112) except that Na is replaced by Nd , D. by Dp, n ib by nie, Wb by We , and L n by L p . The base current for PEBTs, 'Bp, consists of tunneled holes into the emitter (192) : 'Bp =
kT
n1e2
27cmh*
Nde
e_1
(1
(gVBE/kT )
C hkT)
(2 .115 )
where
Ch =
(2ic5)
/2mh *
h
g xh
4 c~ )\/2mh*qxh 7
bh
h
(2 .116 )
(2.117 )
where, x h is the barrier height of the emitter—base potential barrier, and b is the thickness of the emitter—base interfacial oxide . The base current, IBh, for the SiGe HBT is given b y IBh
( D P n iSiGe2 )
QEef f
eVBE/vt , e — AEg/kT —
1 []
Under BE forward bias conditions, the DC current gain hFE can be defined for each of these devices . For the SBT, the current gain, hFEs, is given by h FEs=
DnNE
WE Dp NB WB
(2 .11 8 )
= (IC /IB )
(2 .119 )
where NE and NB are the doping concentration of the emitter and base , respectively. For the PEBTs the current gain, h FEP , is given by T° . 5
(1 — Chloe — (AEge — AEgb/kT)
h FEP = C e
(2 .120)
Pb
and for the SiGe HBTs, the current gain, hFEh, is given by
h FEh
(Dfl NE WE . e(AEg/kT ) Dp NN WB
(2 .121)
2 . Silicon Devices and Circuits
191
It can be readily seen that for achieving a high h FE in SBTs a high emitter-to-base doping ratio is needed, which implies a low base doping level . On the other hand, low emitter current crowding and low nois e require a low resistive base, which leads to slow switching devices tha t require a thin base . In the case of PEBTs, faster switching devices can be obtaine d because a thinner base can be obtained . At the same time the base current is reduced due to the presence of a potential barrier and a remnant native oxide layer in the EB interface . For the case of SiGe HBTs, the intrinsic concentration n isiGe plays an important role . For instance, a band gap difference AEg between the Si and SiGe systems of, for example, 200 mV, implies an increase of 2300 i n the ratio (nisi / iSiGe), which reflects a similar increase in the collecto r current, whereas the base current remains constant . In other words, the current gain of a SiGe HBT will be higher than that of a SBT by a facto r of e (AEglkT) . However, the advantage of the HBT resides not in the curren t gain but in the base that can be highly doped . This means that the base doping level can be much higher than the emitter doping level, where the high current gain is kept by the exponential factor . A high base doping level allows a reduction of the base resistance as well as the bas e thickness, which results in a short transit time and a high cutof f frequency . Now the question is how do these technologies behave as the temperature is lowered to the cryogenic regime . The answer is given in Fig. 2 .65 . The subscripts a and b in Fig . 2 .65 indicate two different EB interface oxide thicknesses for the PEBTs reported in Ashburn and Soerowirdj o (192) and Van Halen and Pulfrey (197), respectively . The subscripts 0 . 5 and 1 .0% indicate two different contents of C in the base of the SiGe HBTs as reported in Jayanarayanan et al . (198) . When lowering the operating temperature, the SBTs and PEBTs sho w a decrease in the current gain h FE due to freeze-out of the base . A theoretical extrapolation to 77 K would give a negligible value for hFE . The opposite behavior is observed for the SiGe HBTs . Because th e current gain hFE depends exponentially on the amount of Ge in the bas e divided by kT. The introduction of Ge into the Si base reduces the band gap by a AE g amount . Also, the temperature dependence of h FE depend s on the absolute value of AE g : The larger the AE g , the larger the increas e in h FE at low temperatures . However, the amount of Ge that can be introduced into Si is limited by the stability of the SiGe alloy . This constraint can be alleviated by introducing C into the SiGe alloy as proposed by Jayanarayanan et al . (198) . This is shown in Fig . 2 .66, whic h indicates the AE g dependence on the contents of Ge and C .
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
192 105
I
I
I
I
I
=
HBT~ .0 % PEBT b . :
_ ._~_~:__ - -
. .., â~10 3 _
, . .. . . . . HBT
100
,
_
0 .5%
PEBTa -
_
-°-
'
SB T
10 0
, ,
„
„ . , „ i 200 300 400 Temperature, T [K ]
100
►
►.
500
.
600
FIGURE 2.65. Current gain h FE as a function of temperature for standar d bipolar SBT, PEBT, and SiGe HBT transistors (with 0 .5 and 1 .0% of carbon in the base) . The experimental data have been replotted from Ashburn and Soerowirdj o (192), Van Halen and Pulfrey (197), and Jayanarayanan et al . (98) .
300 0 _
4
8
Ge fraction [% ]
12
16
20
24
28
32
~
0 .0 0 .50 1 .0
1 .5 2 .0 2 .5 3 .0 3 .5 4 . 0 C fraction [% ]
FIGURE 2.66 . Band gap shift for SiGe alloys as a function of C and Ge fractions [replotted from Jayanarayanan et al . (198)] .
2 . Silicon Devices and Circuits
19 3
200 2 .0 % C r-, N
-
150
C7
1 .5 % C 1 .0 % C
`
50
• 1
50
1•
,
1 100
• ~
1
1
1
150
1
1
1
1 200
1
1
1
1
250
1
1
1
1 300
1
1
1
350
Temperature, T [K ]
FIGURE 2 .67. Cutoff frequency f, as a function of temperature for Si SBT an d SiGeC HBTs with various percentages of C in the base [replotted fro m Jayanarayanan et al . (198)] .
Another figure-of-merit is the cutoff frequency fT' which is also a function of temperature . A straightforward implication of freeze-ou t effects in the base of SBTs and PEBTs is a drastic reduction of the fT a t cryogenic temperatures . The inclusion of C into the SiGe base reduce s both the emitter and the base transit times at low temperatures, whic h results in an enhancement of fT (Fig . 2 .67) . The enhancement of fT at cryogenic temperatures is obvious for C contents above 1 .0%, and it can reach a fT of 180 GHz at 77 K. The Early voltage VA has a temperature dependence similar to that of fT• The h FE , fT' and VA , depending on the application, can be traded by tailoring th e band gap guarding in the base region . 2 .4.3 . Summar y The fundamentals of the three main bipolar transistor structures an d their electrical performance as a function of temperature have bee n analyzed in this section . The best bipolar device in terms of speed i s the HBT, with its base made of a SiGe alloy . Thus, this band gapengineered Si-based technology provides better cost performance tha n compound semiconductor technologies while maintaining compatibility with BiCMOS processes .
194
E . A. Gutiérrez-D., C . Claeys, and E . Simoe n
On the other hand, in terms of cryogenic performance, the SiGe HB T is the only bipolar device capable of operating properly . If SiGe HBT ca n be combined with Si CMOS, then this combination will offer uniqu e advantages for cryogenic systems in which very high-speed systems , with low power-delay product will be able to be fabricated in a monolithic way .
2.5 . RADIATION DETECTORS A radiation detector can be defined as a transducer that creates an electronic signal in the presence of an optical signal, in which the electroni c signal is correlated to the optical power and wavelength of the optica l signal . A large variety of devices exist that detect an optical signal fro m soft X-ray to deep ultraviolet (UV), UV, visible, near infrared (IR) , medium IR, and the far IR wavelength range . These devices are used in a large variety of applications . The CCD is the most versatile among the optical detectors . The CCD is capable of detecting signals from 1 x 10 - 4 up to the 1 .1-µm wavelength range, with a quantum efficiency of 40% , high spatial resolution of up to 2048 x 2048 pixels, and a noise leve l below 7 e - rms. This gives the CCD a competitive edge over other U V imaging detectors (199) . In the visible range of the optical spectrum, from about 0 .38 to 0.77-µm wavelength range, the photodiode has become the most widely used photosensor as well as the most used device for solar conversio n in both terrestrial and space applications. Silicon photodiodes are particularly outstanding in applications requiring high accuracy . During the 1980s, high-quality silicon photodiodes were developed that had a high level of accuracy and precision in the visible range which exceeded tha t available from calibration against the radiometric standards and tech niques existing at that time (200) . This resulted in the creation of ne w calibration techniques for radiometric instrumentation and calibration standards (201) . Recently, radiometers based on planar silicon photo diodes have been shown to have calibration uncertainties on the orde r of + 0.0003 at 0 .855 and at 0 .442 ,im (202) . Further development of this kind of radiometer has shown an uncertainty smaller than 0 .0001 (203) . For the IR wavelength range detectors are used to detect, image, an d measure patterns of thermal heat radiation that many kind of object s emit . The PbS detector was the first IR detector and was developed in the early 1940s (204) . A decade later a wide variety of new materials were developed, giving rise to the next generation of IR sensors (205) and extending the spectral range to the 3- to 5-,um mid-IR range . Thes e materials included PbSe, PbTe, and InSb . The use of other materials,
2. Silicon Devices and Circuits
19 5
such as copper, zinc, and gold impurity levels in Ge, made possible the development of extrinsic photoconductors in the 8- to 14-µm long wavelengths IR spectrum . By the early 1960s, the semiconductor alloy s in III—V, IV—VI, and II—VI appeared . The appearance of these alloy s gave rise to band gap engineering, allowing for the possibility to tailo r the energy band gap for specific applications . The most representative alloy of that time was HgCdTe (206), which remains the most widely used of the tunable band gap materials . At the same time, the development of the IC fabrication techniques, especially photolithography mad e possible the fabrication of IR sensor arrays . Thus, linear array technolog y was applied to PbS, PbSe, InSb, and Hg-doped germanium detector s (207) . Because the activation energy of Hg—Ge is 0 .09 eV, it had to be cooled down to 25 K . The development of HgCdTe photoconductive detectors (208) allowed IR systems to operate at 80 K. Since then , due to the compactness and lightness of cryosystems, the HgCdT e linear arrays have been produced in high scale . When the HgCdTe linear arrays were being produced on a large scale for use in tactica l imaging systems, extrinsic silicon devices were being developed to largely replace extrinsic Ge in many applications in the 14- to 30µm IR wavelength range . Extrinsic silicon detectors can be made with significantly larger IR absorption coefficients than Ge in the 20-,um range (209) (Fig. 2 .68) . The intensive and extensive development of modern IC fabrication technology during the past 10 years has resulted in a strong impact o n
I
-
Ge:Au
_ //'--\
N
1012
* 10 A^
/
!,)(u
PbTe ,. . .
PbS
(77 K)
11
. ..,
-
_
-
101 0
Cc:Ca (4. .2 K)
_ ^
ti
(77 K)
HgCdTc
(77 K )
(4 .2 K)
Ge :Cu
~
~ ,.
(77 K )
=
_
- ,
[nSb (77 K ) ,~ -' ~i
~ Ge :Au . = _ ~`,., --~ -
I
(77 K)
Si :P
; .
.
(4 .2 K ) Ge :Zn (4.2 K )
.
PhSnTe (77 K)
10 9
1
10
, 100
Wavelength, X [pm ]
FIGURE 2.68 . Detectivity D* versus wavelength 2 for several differen t detectors (209) .
196
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
the development of new types of silicon-based IR radiation detectors . This has provided the opportunity to integrate the detector with th e silicon signal processor on the same chip (210) . However, for far IR, Ge continues to be the dominant material in the production of detectors . Strained Ge detectors have extended the spectral response of IR detectors up to about 200 µm (211) . Under very low background radiation levels , there are dielectric relaxation effects in extrinsic devices, which make th e device less immune to the noise . These effects have been eliminated with the introduction of the so-called blocked impurity band detectors (BIBs) . These detectors are based on light detection in a thin, highly doped , sensitive layer . They feature less radiation sensitivity, increased spectra l coverage, less cross talk, and higher stability after irradiation tha n standard photoconductors . BIB detectors are ideal for the realization o f large arrays with far IR response down to 250 ,um . Si :P BIB detectors have also been successfully flown in the Kuyper aircraft observator y (212) . In the 1990s, Si-based detectors reappeared as a leading technology . Silicide Schottky barrier detectors (SBDs) are now widely used a s vacuum and UV detectors (213) . Further development of SBDs ha s resulted in an extension of the cutoff wavelength from the conventiona l 3- to 5-,um mid-IR to the 5 .7- to 22-µm range by incorporating a thin p + doping spike layer at the PtSi—silicon interface (214, 215) . Anothe r development in the IR range is the 1040 x 1040 IR charge sweep devic e imager based on PtSi Schottky barrier detectors (216) . Recently a VLSIcompatible, high-speed silicon photodetectors for optical data link applications has been proposed (217) . Following the trend in the development of radiation detectors, the evolution toward monolithic radiation detector systems is evident. As such, the potential of Si-based detectors is very promising. Because of the low-temperature operability of the CMO S technology, the CMOS-compatible radiation detectors seem to be th e natural candidates to occupy the leading position as cryodetectors . The purpose of the following sections is to describe the optical properties o f silicon at low temperature, give a review of the several Si-based radiation detectors for low-temperature operation, and outline the curren t trend and future perspectives for low-temperature optoelectronics .
2 .5.1 . Optical Properties and Extrinsic Detection Silicon is one of the most extensively used semiconductors in th e fabrication of radiation detectors for low-temperature operation . Most o f the observed optical, electrical, and thermal parameters of silicon, suc h as energy band gap, carrier mobility, and thermal conductivity, ar e available in analytical forms, based on either known theories or experimental data . However, in an attempt to discuss the optical properties o f Si as a function of temperature, we were not able to obtain from the
2 . Silicon Devices and Circuits
-
19 7
Si:P
_
\►
~/~ - "i~ - ~
Si :A s
Si :B 0
1111111111111111111111
5
10
15
20
25
30
Wavelength, k [pm ] FIGURE 2 .69 . Spectral response of the detectivity D* for n-type (Si :P and Si:As) and p-type (Si :B) extrinsic detectors (209) .
literature a complete description of the temperature dependence of all the optical properties of Si . Therefore, we focus on the extrinsic photo conductivity of several impurity atoms in Si at 4.2 K and the absorption coefficient of Si . Many impurity elements produce energy levels in Si that allow Si t o be used as an IR detector . Some of these energy levels are below or abou t 0 .045 eV, including phosphorous (P) and boron (B), from either ban d edge which means the detector's spectral response can be extended t o 28 µm (Fig . 2 .69) . Another interesting feature of silicon is its high absorp tion coefficient a (Fig . 2 .70), which allows for the possibility of smalle r size detectors (218) . Extrinsic detectors are fabricated by the addition of impurity atom s into the Si host crystal . Thus, the properties of these detectors resul t more from the characteristics of the impurity atoms than from the hos t crystal. Therefore, the photosensivity of these detectors is called "extrinsic" detectivity. Impurity ionization energies in Si range from 0 .033 t o 0 .41 eV (Table 2 .1) . Therefore, the long-wavelength cutoff for conductivity can range from 3 to 28 ,um . This wavelength spectrum span o f sensitivity gives Si a versatility that has been one of the key factors i n their use as a IR detector during the past 20 years . Among the most use d detectors for the mid- and far IR spectral region are the stressed Ge :G a IR detectors (219) and the extrinsic Si :P mid- and far IR detector (220) . The stressed Ge :Ga photoconductors are the most sensitive low back ground currently available for the spectral region between 120 an d 200 µm . They have been used in the Infrared Space Observatory (221) . On the other hand, for the spectral range of about 2 = 20 ,um, Si :P has proven to be integratable and submicrometer CMOS compatible (220) . I n
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this approach the n-well of a submicrometer CMOS technology has bee n implemented as the photodetector . The spectral response of the stresse d Ge :Ga detectors operated at 4 K is shown in Fig . 2 .71 . The n-well detector connected to an n-MOS transistor was radiate d with a 2 = 0 .768 pm laser pulsed at a frequency f = 5 Mhz (Fig . 2.72) . The output voltage Vo as a function of time is shown in Fig . 2 .73 . The response time of this detector is on the order of 15 ns, and the dark-tolight current ratio is on the order of 5 x 10 6 . However, extrinsic Si photodetectors when placed in arrays have several drawbacks, such a s
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2 . Silicon Devices and Circuits
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FIGURE 2.72 . A 4 .2 K CMOS optical detector (220) . cross talk between closely spaced detectors, spatial nonuniformity of the optoelectrical response, "memory effects," and spurious current spikes . One way to circumvent these problems is by using BIB detector (222) . These detectors are based on light detection in a thin, highly doped, sensitive layer (Fig . 2 .74) . They feature less radiation sensitivity, large r spectral coverage for constant responsivity, less cross talk, and superio r uniformity of response over the detector area and from detector to detector. The BIB detector employs a thin undoped blocking layer (BL ) between a heavily doped infrared active layer (IRL) and a transparen t contact layer, which is formed in the BL by implantation of As . The structure lies on a silicon substrate . The IRL is doped with As .
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This structure makes possible the creation of avalanches in a 4-µm (W) high electric field region of the device in response to photo n absorption . This Si-based device is capable of detecting individua l photons in the 0 .4- to 28-,um wavelength range, with submicrosecond response to incident radiation, at T = 7 K . At a bias voltage of 5 V, th e gain M of this device is 2 x 10 4 . 2 .5 .2 .
Photodiodes
and Schottky Barrier Detector s
Basically there are two devices capable of detecting radiation from th e soft X-ray (1 x 10 - 4 ,um) to the UV (0 .33 pm) ; the SBD and the CCD. Both devices are capable of increasing their spectral response up to the IR range . However, here we focus on photodiodes and SBDs; the CCDs wil l be discussed later . Semiconductor photodiodes, originally designed for the visible spectral range, can also be used in the X-ray region . In the vacuum UV and sof t X-ray regions, however, the absorption lengths of all materials are ver y small, typically on the order of 20—200 nm. Therefore, semiconducto r detectors suffer from absorption losses in insensitive layers near the surface and thus have not been used . However, diffused and Schottky diodes have been shown to operate very well as soft X-ray and UV detectors (223 -225) . In the diffusion diode a depletion layer is formed between the p- an d n-doped layers (Fig . 2 .75a) . For the Schottky diode (Fig. 2 .75b) the depletio n layer is formed in the metal—semiconductor interface . Any photon absorbed in the semiconductor will produce man y electron—hole (e—h) pairs . When these e—h pairs are created in the depletion layer, they are swept by the electric field and collected as a n external photocurrent . In both detectors the radiation is mostly absorbe d in a "dead layer," which in the case of the diffusion diodes is composed
2 . Silicon Devices and Circuits
201
FIGURE 2.75. Device structure of diffusion and Schottky Si diodes . of SiO2 and part of the p-type material and has a thickness of 30–100 nm . For Schottky diodes, this layer consists of a thin metal film of abou t 10 nm . The absorption length in this spectral range is very small ; therefore, the response of these diodes is strongly reduced by th e absorption in the dead layer . The response of a radiation detector i s generally defined by its quantum efficiency r~(E) or by the responsivity s(E) . The quantum efficiency of a semiconductor photodiode is define d as the number of e—h pairs created by an incident photon of energy E, whereas the responsivity is the photocurrent per incident radiatio n power . Both n(E) and s(E) are related b y
s(E) = q where q is the electronic charge . Because the mean e–h pair energy w i s independent of the energy of the absorbed radiation (E » w) (225), the quantum efficiency of a perfect semiconductor detector should increas e linearly with the radiation energy, whereas the responsivity would be a constant, corresponding to the reciprocal of w . This behavior is modified by the absorption in the dead layer, which is most important at lo w energies, and by the penetration of photons through the depletio n regions at higher energies . The semiconductor diodes investigated b y Krumrey et al . (225) were commercially available photodiodes in which the glass or silica window were removed . The devices were tested in the photoamperic mode at a 2 = 0 .01 µm (E = 124 eV) . The stability of the photodiodes under ionizing radiation was measured . The experimental results are shown in Fig . 2.76 . The quantum efficiency decreases from it s initial value of = 27 to 10 at 400 s and to 8 at 1500 s. It is easily observed that these Si photodiodes show radiation-induced instabilitie s which would make them unsuitable for use as radiometric standards
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FIGURE 2.77. Device structure of the photodiode proposed by Krumrey et al. (225) .
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The efficiencies of several devices with different oxide thicknesses are shown in Fig . 2 .79 . The oscillations in efficiency suggest optical interference related to oxide thickness . Experimental results of these kinds o f detectors show a very good stability for oxide thicknesses thicker tha n 46 A . With careful processing and control of passivation layer thicknesses, predictable efficiencies and relative immunity to exposure dam age can be achieved with these detectors . The operation of SBDs is based on internal emission at the interfac e between a thin PtSi and a p—Si substrate . Conventionally, these device s are operated in the back-illumination mode . IR photons with energie s
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FIGURE 2.80 . Schematic diagram of a PtSi/p—Si Schottky barrier detector . less than the band gap of Si are transmitted through the substrate an d absorbed in the silicide film, where they generate the photocurrent . On the other hand, visible and UV photons, which have energy higher tha n the band gap, are absorbed in the Si . The absorption depth, whic h decreases rapidly with increasing photon energy, is approximately 5 p m at energy E = 1 .55 eV (2 = 0 .8 um) and reaches a value of approximatel y 0 .004 pm at E = 4 .428 eV (2 = 0.28 ,um) . Because the thickness of a typica l Si wafer is 400—500 pm and transport of photogenerated carriers towar d the silicide—Si Schottky barrier junction occurs primarily by diffusion , carrier collection is slow and inefficient . Furthermore, for the shorte r absorption lengths, especially in the blue and UV regions, a larg e fraction of the carriers generated in the Si can easily be lost by surfac e recombination . Consequently, UV/visible response of back-illuminate d detectors is generally too low to be of practical interest . Front-illuminated PtSi/p—Si SBDs exhibit excellent UV/visible photorespons e with little loss of IR response (229) . Front-illuminated detectors can b e useful for applications requiring multispectral imaging . The schematic diagram of a PtSi/p—Si SBD is shown in Fig . 2 .80 . This PtSi/p—Si SB D has been tested in a front-illuminated 160 x 244 element focal plane array integrated with a monolithic CCD readout circuitry (230) . This array was cooled to 77 K. The temporal UV, visible, and IR response of p-type detectors in both front- and back-illuminated operation has bee n measured for temperatures ranging from 10 to 80 K . The response is fas t enough for operation at video frame rates, except for back-illuminate d operation at temperatures of 30 K or below for values of 2 close to the S i absorption edge . The experimental results for the p-type detector operated in the front-illumination mode is given in Fig . 2 .81 . The kink observed in ii around 1 .0 eV in Fig. 2 .81 corresponds to the band gap of Si at 40 K. Note that ii decreases gradually with increasin g 2, exhibiting the wavelength dependence that is characteristic of interna l photoemission in a Schottky barrier . In the wavelength region beyond 1 .0 um the photoresponse is due to carriers generated by absorption in the PtSi film. The reduction in 17 for larger wavelengths is due to
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206
E. A . Gutiérrez-D ., C. Claeys, and E . Simoe n
FIGURE 2.82 . Pixel cross section of the 1040 x 1040 PtSi SBD (232) .
ground-based imaging, spectroscopic, and radiometric applications . Pro posed space applications include an X-ray imager on NASA's Advance d X-ray Astronomical Facility, a space telescope Imaging spectrometer, the solar optical telescope, and the comet rendezvous /asteroid flyby imaging subsystem . Despite the wide variety of applications for CCDs, ther e remain some drawbacks for their use . CCDs are very expensive ; a backside illuminated 2048 x 2048 CCD costs about $80,000, and CCD s with standard TV resolution range cost from $2000 to $10,000, depending on their performance and quality . However, what is most expensive in the use of CCDs are the auxiliary electronics and computers used t o make them work . CCD cameras and imagers generate a huge amount o f data . For example, a single 2048 x 2048 CCD image holds the same information as a 7-million-word book . This implies a very heavy data processing task, which requires expensive storage media. The high quantum efficiency performance of the CCDs has bee n possible because of the implementation of two techniques to control the backside surface potential: backside charging (233) and flash gate (234) . 4 Using either of these techniques, excellent photoresponse from 1 x 10 to 1 .1-,um wavelength range are obtained for soft X-ray to near IR . For front-illuminated CCD the transmittance of the signal contains bot h reflectance and significant absorbance components from the gate oxide structure . As a result of this absorption and scattering loss term in th e polysilicon, front-illuminated CCDs have poor quantum efficiency, especially in the blue and near UV spectral range . To overcome this problem, backside illumination has been implemented . In this technique,
2 . Silicon Devices and Circuits
207
the substrate of the CCD is etched away or thinned until only th e epitaxial silicon remains . In this way, it is possible to absorb inciden t photons directly into the silicon at the back surface of the CCD unimpeded by the polysilicon structure present at the front, resulting in a much higher quantum efficiency, especially in the blue and near U V spectral regions . One of the most widely used varieties of backside illuminated CCDs is the so-called flash gate . This approach requires tha t a substantial part of the bulk silicon be removed by an etching technique . Also, a growth of a passivating oxide layer on the backside is essential . However, this device shows an instability of the quantum efficienc y known as hysteresis due to trapping and emission of signal carriers i n the surface states at the Si/SiO 2 interface . This problem is worst for UV photons, which are absorbed almost immediately near the back surface . The solution to this problem lies in the growth of an oxide on the silicon back surface that can be negatively charged to negate the effect of the positively charged interface states . An additional key step for providin g good backside response in a CCD is to implement the method o f negatively charging the oxide (backside charging) . One approach is t o charge the oxide with UV photons . This has the effect of bending the energy bands upward into accumulation, driving signal electrons awa y from the Si / SiO 2 interface, thus eliminating the quantum efficienc y instability and providing 100% internal quantum efficiency. By floodin g the CCD back surface with intense UV light, electrons are excited to the conduction band of the Si O 2 , resulting in a negative charge on the oxide . Although very effective, this technique has the disadvantage of discharging over a period of time unless the CCD is held at temperatures below — 70°C . The flash gate technique is the most efficient among the othe r approaches used for CCDs. In this approach, a metal is deposited on th e backside of the CCD over the oxide (235, 236) . Because the work function of the metal is higher than that of the CCD, it permanently accumulate s the back surface with a negative charge and will then repel minorit y carriers (electrons) away from the back surface toward the desire d potential wells under the clock gates at the front of the device . Platinum has proven to be a good material for the flash gate because it is quit e stable . This flash gate process can optionally be followed by the application of an antireflection coating to further enhance the quantum efficiency of the CCD . The performance of the CCD, with the different approaches, is summarized in Fig . 2 .83 .
2.5.4. Amorphous Silicon-Based Photodetector s The performance of the InGaAsP / InP and GaAs-Al 1 _GaAs avalanch e photo detectors (APDs), used in the fiber optic communication
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wavelength range 0 .9 to 1 .55 pm (237, 238), is limited by the fact that i n InP the ionization coefficient ratio is close to unity over the entire rang e of the useful electric field range . The quantum efficiency of thes e separated absorption multiplication avalanche photodiodes (SAMAPDs ) is determined by the properties of the absorption layer and the hetero interface, whereas the multiplication and excess noise properties ar e determined by the avalanche multiplication process in the wide ban d gap semiconductor. In exporting the SAMAPD idea to silicon, two majo r facts should be considered : (i) The ionization coefficient ratio in Si is ver y different from unity and (ii) the absorption coefficient of amorphous S i is very large compared to its crystalline counterpart. For the absorption layer of the SAMAPD, amorphous silicon (a-Si) and its alloys (a-SiGe ) are a good option because they show at least one order of magnitud e higher absorption coefficient with respect to crystalline material . Additionally, amorphous materials have a very low deposition temperatur e (when PECVD is used) and do not contain any materials harmful to th e fabrication processing of the Si ICs . a-Si and a-SiGe alloys, used a s absorption layers in a SAMAPD structure, do not need to have smalle r band gap than the crystalline silicon, as in III—V-based APDs . Becaus e a-Si and its alloys have optical absorption coefficients larger tha n 10 4 cm' (for energies 0 .2 eV larger than the optical gap), only a 1-pmthick absorption layer is sufficient, which is two or three orders o f magnitude thinner than that needed in crystalline silicon . One of the important characteristics of amorphous materials is that materials o f arbitrary composition can be obtained . Alloying hydrogenated amor-
2 . Silicon Devices and Circuits
209
FIGURE 2.84 . Cross section of the a-SiGe SAMAPD (242) . phous silicon (a-Si :H) with carbon (239) or nitrogen (240) raises the band gap . Alloying a-Si :H with Ge or Sn lowers the band gap (241) . A cross section of the a-SiGe SAMAPD, fabricated in an n-type S i wafer (100), p = 3—5 0-cm of the INAOE 10-pm CMOS IC' s process, i s shown in Fig. 2 .84 . Only one extra implantation step is required t o prepare the substrate for the SAMAPD fabrication, and the IC's fabrication is not altered (242) . From the IR absorption spectrum of an 0 .8-pm a-SiGe layer we obtained values of the band gap Eg of 1 .72, 1 .33, and 1 .25 eV for x value s of 0 .0, 0 .33, and 0 .66, respectively, which correspond to 0 .720, 0 .933, an d 0 .992 pm wavelengths . As the Ge content is increased, the absorptio n coefficient also increases, suggesting that the higher the x value, the better the response of the material at higher wavelengths . However, the value of diffusion length determines the x value to be used in the absorption layer . If the thickness of the absorption layer is larger tha n the diffusion length of the material, there is a strong possibility that the photogenerated carriers will be lost in this layer before they reach th e multiplication region . An a-Sio .67Geo .33 :H,F alloy showed a diffusion length of 0 .08 pm and a lifetime of 79 .6 /is . From the point of view of process repeatability, a thickness of 0.08 pm can be easily obtained in the deposition system, and the risk of carrier recombination inside the absorption layer is therefore minimized . This is the main reason why the x = 0 .33 material wa s chosen as the absorption material . The measured dark current at a reverse bias voltage VD of — 20 V was 2 .22 nA and 2 .98 nA for a a-SiG e thickness of 0 .8 and 0 .065 pm, respectively . The on-wafer measurements gave a diode resistance R D of 25 .8 MQ and 4 .9 Gil at VD = — 20 and 0 V , respectively. The measured series resistance R S is 28 Q. The high frequency C—V characteristics were measured under dark conditions , giving a capacitance of 0 .5 pF at VD = — 20 V and 2 pF at VD = 0 V. A 100-mW-output laser, with a beam area of 0 .1256 cm 2 , was focused on the detector to measure the responsivity as a function of the wavelength . The results are shown in Fig . 2 .85 . The experimental results of the a-SiGe SAMAPD are compared to those of an MBE GaAs—Al 0 .4Ga0 .6 As super-
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lattice photodiode (SLPD) (238) . The responsivity R of the a-SiGe SAMAPD presented here is superior to that of the SLPD at wavelength s larger than 0.9 ,um. The S/N at B = 3.13 GHz (as calculated with SPICE) and VD = — 20 V is equal to 1819 .2, which ensures the operation of the device in optica l fiber communication systems . This device has been tested and proved to work very well in the 300 to 4 .2 K temperature range (243) . 2 .5 .5 . Summary The versatility of Si-based detectors is remarkable . We have seen tha t CCDs are capable of detecting radiation from the soft X-ray up to the IR spectral regime, and for all these applications CCDs can be operate d from 300 to 4.2 K. The camcorder systems are a very good example of a high-performance application of the CCDs in the visible (V) spectra l range . CCDs are also a very good option for radiometry, as has bee n demonstrated for the detection of vacuum UV and near UV signals . For the UV, V, and IR the photodiodes, and especially the SBDs, have bee n shown to be excellent candidates for integration as monolithic detectio n systems . New technology developments have made possible the extention of the spectral range of the SBDs down to the vacuum UV and u p to the mid-IR ranges . The SBDs are also capable of operating from room temperature to below 4 .2 K . A recent development of CMOS-compatible SAMAPD has opened the possibility of CMOS monolithic short-distanc e fiber optical telecommunication systems . This SAMAPD is based on a n amorphous Si :Ge device. This shows that not only crystalline Si but als o amorphous Si and its alloys with Ge can be used as high-speed IR
2 . Silicon Devices and Circuits
211
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detectors . We have also tested this SAMAPD from 300 to 4 .2 K. For the far IR regime Si:P and Si :B extrinsic detectors have been shown to hav e an equivalent performance to that of the stressed Ge :Ga detectors near the 20-,um wavelength range . These Si-based extrinsic detectors operate at or below 4 .2 K. This review shows a trend toward the implementation of monolithi c Si-based technology. This is more clear for the IR spectral regime in which SBDs have been shown to be CMOS technology compatible . Thi s review can be summarized in Fig . 2.86, in which the different kinds o f detectors are shown in a wavelength 2 versus temperature T scheme . A review of the state of the art on silicon-based radiation detectors , their IC technology compatibility, and the optoelectronics properties o f silicon at low temperatures was presented . Future trends and perspectives of Si-based radiation detectors for low-temperature optoelectronics were also addressed .
2.6 . CIRCUITS The following sections summarize the most widespread applications an d published works on cryoelectronics, including CMOS, SOI, and SiGe HBT digital and analog circuits for specific applications such as readou t electronics for imager systems or nuclear instrumentation, digital micro-
212
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
processors such as the one used in the ETA cryocomputer, image r systems for IR detection, CCD arrays, IR SBD systems for night surveillance, and focal plane arrays for astronomy applications . This review on applications concludes with a summary in which future applications and trends are predicted based on the recent advancements in cryogenic SiGe technologies and hybrid semiconductor — superconductor systems .
2.6.1. CMOS Digital Circuits, Microprocessors, and Memorie s CMOS technology has been the most widely used for cryogenic applications due to its freeze-out immunity. For this reason, several attempt s have been made to integrate digital and analog circuits for cryogeni c operation . The first attempt was the testing at 77 K of the commerciall y available 16-bit DCJ11 microprocessor in 1986 by Colonna-R . and Deverell (244) . This 3-µm CMOS chip consists of two chips mounted i n individual ceramic packages in which both are surface mounted onto a 60-pin cofired ceramic hybrid . The first chip contains the primary execution data path, the memory management logic, the input/outpu t state sequencer, and the floating point and cache registers, whereas th e second chip contains the microprogram control store and sequencer . The results of this test are shown in Fig. 2 .87 . The instruction set diagnostic fI and the floating point diagnostic f F
FIGURE 2 .87. Experimental data (symbols) for the 16-bit DCJ11 micro processor. The solid lines represent fittings . The dashed lines represent percentage enhancement (244) © 1986 IEEE .
2 . Silicon Devices and Circuits
213
frequencies are shown in Fig . 2 .87 . Both frequencies increase when the CMOS microprocessor is cooled to 77 K . The average increase is fro m about 22 to 40 MHz, which represents an average percentage improve ment of 80% (see right axis of Fig . 2 .87) . The solid lines are fittings base d on the typical temperature dependence of the electrical parameters of the MOS transistor such as the threshold voltage and the transconductance . According to these results, 77 K is the best compromise in terms of cos t performance . Cooling below 77 K does not result in significant electrica l improvement, but the cost of the cooling system increases . As noted by Longsworth and Steyert (245), computers that require 1–400 W of refrigeration at 77 K can use refrigerators that are essentially the same as thos e that are in widespread use in small cryopumps . For systems dissipating less that 1 W at 77 K, a Joule–Thomson refrigerator is suggested . For 1 W to more than 100 W of power dissipation, a Gifford–McMahon cycl e refrigerator is suggested, whereas for systems requiring several hundre d watts of power dissipation, a Brayton cycle refrigerator can be a goo d choice . A prediction of cost C (in dollars) of the refrigeration system fo r computers in the 10- to 1000-W power range is approximately given b y
C = 750 •
Q0
.52
(2 .123 )
where Q is the power load in W at 77 K . In 1987, Hanamura et al. (246) demonstrated the operation of 1 .3-ym CMOS 8 x 8 bit multipliers at 77 and 4 .2 K They tested two types o f multipliers : full CMOS and pulsed pload logic (PPL) based . The results for the delay time per gate T g and the power dissipation P d at 10 MHz are shown in Fig . 2 .88 . The delay time per gate 2 g in both cases decrease s
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I
l
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ô
â
–
Temperature, T (Kl
FIGURE 2 .88. Measured results for the 8 x 8 bit multipliers of Hanamura et al . (246) . The squares indicate the CMOS-type and the circles indicate the PPL-typ e delay time per gate T g and power consumption Pd (246) © 1987 IEEE .
214
E . A. Gutiérrez-D., C . Claeys, and E . Simoen ti
10000
PP L
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w
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100 150 200 Temperature, T [K]
1
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FIGURE 2 .89. Experimental energy consumption E d from Hanamura et al . (246) © 1987 IEEE .
as temperature is lowered . However, the power consumption in the PPL case increases at low temperatures . A better figure-of-merit is the energy consumption Ed or the product T mPd , where tm is the delay time of th e multiplier (Fig . 2 .89) . The delay time per gate ' rg reduces 52% at 77 K and 66% at 4 .2 K for the CMOS multiplier, whereas the energy consumptio n E d reduces 52% at 77 K and 68% at 4 .2 K. Also, Sun et al . (247) demonstrated a twofold improvement in bot h the speed and the power-delay product over room-temperature value , where a 0 .5-,um CMOS ring oscillator was used as a test vehicle . In 1988 , Deen et al . (248) reported experimental results on a commercial CMOS based microprocessor operated at 77 K . The maximum input frequenc y increased up to 32 MHz at 77 K compared to 19 MHz at 300 K . An example with a more complex system is the cryocooled ET A computer (249) . The ETA is a 10 GFLOP computer with 3M circuits, 4 Mbit SRAM, and 2 .3 Gbit of disk storage . Its CPU reliability was im proved by minimizing the number of interconnections and circuits . The CPU boards and the ICs were the only cooled parts, which resulted in a twofold speed improvement . The performance of this 77 K ETA computer was superior to that of similar room-temperature-operated super computers, such as the Cray X-MP, the Cyber 205, and the NEC SX-2 . The comparison was made by implementing the Los Alamos vecto r kernel benchmark, with an average performance, in megaflops, of 150 fo r the ETA, 55 for the Cyber 205, and 50 for the CRAY X-MP . This performance enhancement is due to the reduction of power consumption, heat dissipation, and speed increase at 77 K . Another interesting example is the cryogenic operation of Si DRAMs by Wyns and Anderson (250) . The 16-, 64-, and 256-kbit DRAMs fro m
2 . Silicon Devices and Circuits
21 5
different manufacturers were operated at low temperatures to investi gate their performance. It was observed that 89 K is the lowest temperature at which a 256-kbit DRAM can operate . Below this critica l temperature the sense circuits fail to operate properly . It was als o observed that below 240 K, the minimum refresh frequency is temperature independent but strongly voltage dependent. Above the typica l temperature value of 240 K, which can vary depending on the memory family, the Shockley—Hall—Read electron generation rate is the dominant mechanism . Below the typical temperature value the strong voltag e dependence results from band-to-band tunneling in the Si depletio n region under the memory capacitor . Another interesting result from thi s experiment is that the times between required refresh cycles are as lon g as 4 .6 days at 183 K . This suggests that DRAMs, when designed specifically for cryogenic operation, could operate properly at 77 K as stati c RAMs, thus giving the designer the chance to reduce the circuit complexity and the power dissipation . Experimental results on the numbe r of failures versus retention time are shown in Fig . 2 .90 . It is expected tha t with the advent of advanced DRAM and SRAM technologies, the result s at 77 K obtained from memory technologies from the 1980s will be outperformed . A detailed study of the voltage transfer characteristics of commercia l CMOS inverters for temperatures between 77 and 300 K, and for voltage s between 3 and 20 V, was presented by Deen (251) . In these experiments,
104 -
T=293 K T=273 K T=253 K T=233 K
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FIGURE 2.90 . Measured number of failures versus retention time for capacito r voltage Vcc = 5 V, with temperature as a parameter, for one-sixteenth of a 256-kbit NEC DRAM [replotted from Wyns and Anderson (250)] © 1989 IEEE .
216
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
v ~~ tl
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V ih
Vinv
Input voltage, V in [V ]
FIGURE 2 .91 . The DC transfer characteristics of a CMOS inverter .
different commercial CMOS devices were used : RCA CD4007UBE, M C 14069UBE, and MC 74HCU04 . The DC transfer characteristics of a CMOS inverter are depicted in Fig. 2 .91 . The output high voltage is denoted by V oh , the output low voltage i s denoted by Vol , the input low voltage is denoted by Vil , and the inpu t high voltage is denoted by Vih . Thus, the low noise margin NM L and the high noise margin NM H are defined as follows :
NM L
— Vol 1
(2 .124 )
Voh — Vihl
(2 .125 )
= I Vi,
and
NM H
= I
The noise immunity NI is defined a s NI =
(NM H +NM L )
(2 .126)
where VDD is the supply voltage . The noise margin NI is a parameter related to the transfer characteristics of the inverter. This parameter defines the allowable noise voltage in the input of a gate so that th e output will not be affected . The threshold of the inverter Vin,, is define d at the Vin voltage, where Vo „t voltage is equal to VDD /2 . The experimental study presented by Deen (251) was later extende d to 4 .2 K and to submicrometer technologies by Gutiérrez-D . et al . (252) . The experimental results of these two works are shown in Fig . 2 .92 . For CMOS inverters, it is usually desirable to have the difference Vih —Vil close to zero or equivalently a high noise immunity NI . Both Deen and
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0 50 100 150 200 250 30 0 Temperature, T [K ]
FIGURE 2 .92. Experimental results of the inverter threshold voltage and noise immunity NI for the inverters of Deen (251) (a) and Gutiérrez-D . et al. (252 ) (b) © 1989, 1992 IEEE .
Gutiérrez-D . et al . observed an increase in NI as temperature wa s lowered. The inverter threshold voltage also increased with the reduction of the temperature . The inverter of Gutiérrez-D. et al . (252 ) was made with a 0 .7-ym n-well CMOS technology (253), with TO = 15 nm, L. = L p = 0 .7 ,um, and Wn = Wp = 70 pm . In the 50—300 K range, the DC characteristics have the same behavior . It can be concluded that submicrometer CMOS inverters approach ideal behavior a t T = 50 K . For temperatures below 50 K, the combination of freeze-ou t and carrier multiplication degrades the DC characteristics and increase s the current consumption . However, the critical temperature at which the inverter performance is maximum may be lowered if the supply voltag e is reduced and the resistivity of the substrate and the well is optimized . Commercial 555 and 551 CMOS timer ICs were also evaluated fo r cryogenic use by Haruyama and Kirschman (254) . The general result is that these ICs are suitable for operation in the 300-80 K temperatur e range in a stable mode as R—C controlled oscillators . These ICs with stand repeated thermal cycles without their electrical characteristic s being noticeably altered . Thus, these CMOS IC timers are suitable for cryogenic applications requiring oscillation, timing, sequencing, an d pulse generation . The causes of the misfunctioning of CMOS digital circuits at temperatures below 77 K were identified by Gutiérrez-D . et al . (255) as substrate current due to carrier multiplication and freeze-out effects . As VLS I technology continues to develop, we must deal with problems such a s
218
E . A . Gutiérrez -D ., C . Claeys, and E. Simoen
carrier multiplication due to high-field impact ionization and self-heating (256) due to power dissipation . Moreover, the increased carrie r multiplication together with freeze-out, occurring at low ambient ternperatures, can have a major effect on the electrical performance o f submicrometer MOS transistors, which in turn affects the electrica l performance of circuits . At very low temperatures (below 50 K), many second-order parasitic effects, such as carrier multiplication, self-heating , freeze-out, and series resistance, which result from the use of LD D devices, combine to make the analysis and characterization of submicrometer MOS transistors very complex . The combination of these effects, obviously, affects the performance of cryogenic CMOS circuits . A n example of this is a 211 inverters chain ring oscillator (RO) fabricate d with the 0 .7-,um CMOS IMEC technology . The power consumption P an d the delay time per gate tg as a function of temperature of the RO biase d at different supply voltages are plotted in Fig . 2 .93 . All the plots show a plateau region in the 250—100 K range, an extended kink that goes fro m 100 to 50 K, and a second plateau from 30 to 4 .2 K. The first platea u region is attributed to the flattening of the current drive capability of th e MOS transistors, which is due to the series resistance effects . The extended kink is due to the soft freeze-out effect that combines with the generation of substrate currents to increase the substrate voltage an d reduce the threshold voltage . Finally, the second plateau region, in th e 30—4 .2 K range, is due to the combination of hard freeze-out that
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Temperature, T [K ] FIGURE 2.93. Experimental results of the power consumption P and the dela y time per gate t g as a function of temperature, with the supply voltage V DD as a parameter.
2. Silicon Devices and Circuits
21 9
increases the resistance of the substrate/well to values into the 10 g K2 range and of substrate currents that flow through the high-valu e substrate/well resistances R b . Thus, the product (R b • Ib ) clamps at a value near the source—substrate/well junction forward bias, whic h causes the P and 'cg parameters to also clamp at their constant values . The low-temperature effects cause a drastic reduction in the dela y time per gate, which results in an increase in the power consumption . The twofold reduction of ' cg at 4 .2 K compared to 300 K is compensate d by a twofold increase in P . In addition to the temperature dependence o f these two parameters, which is usually considered as a figure-of-meri t to evaluate the electrical performance of digital circuits, the temperatur e dependence of the product (P • 'c g ), which is equal to the consumed energy E d , serves much better as a universal figure-of-merit to compare the electrical performance of CMOS digital circuits at cryogenic temperatures. This consumption energy E d is plotted in Fig . 2 .94 . In general, the consumption of energy, as shown in Fig . 2 .94, reduce s as temperature is lowered, which is a good feature of cryogenic CMO S digital circuits . It is also observed from Fig . 2 .94 that the reduction of 'c g prevails over the increase of P, except in the extended kink (100—50 K) in which a noticeable bump is observed at high supply voltages becaus e the carrier multiplication effect is more pronounced at high suppl y voltages . The previous results call for an optimization of CMOS technologie s for cryogenic operation . This has already been done by Kakumu et al . (257), who theoretically and experimentally examined the tradeoff belb
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220
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
tween circuit performance and reliability for a 0 .3-,um CMOS technology at low-temperature operation . A simulator based on physics-base d models was used to determine power supply voltage and process / device parameters for proper low-temperature operation . The optimization procedure was demonstrated on a 0 .3-,um CMOS RO tested at 77 K. The measured delay time per stage is about 40 ps compared to 60 ps a t 300 K, which represents a 50% improvement in circuit performance . On the other hand, extremely low power-delay product, less than 1 fJ, wa s observed at 77 K with power supply voltage less than 1 V . Thus, thi s guideline optimization, combined with an advanced CMOS process , appears to offer extremely high speed and low energy consumption , which should be employed in future ULSI applications . Following the same trend of CMOS process optimization fo r cryogenic applications, a process modification for improved low-temperature CMOS performance was proposed by Hwang et al . (258) . TCAD (Technology Computer-Aided Design) tools are proposed to study an d optimize the room-temperature process for low-temperature operation . Room-temperature CMOS technologies, when operated at low tempera tures, only give a minimal performance improvement . However, by modifying the process flow, a two- or threefold increase in performanc e is possible . The TCAD tools proposed for this low-temperature proces s optimization are shown in Fig . 2 .95 . Process changes are first run through SUPREM (a device fabricatio n simulator) to obtain a new profile . MEDICI then imports the profile, producing the low-temperature optimized I—V characteristics . These I—V curves are then compared to the originals, and the measurement of th e circuit-level improvement is done with HSPICE . Optimization using these TCAD tools leads to modification of the threshold voltage implant s to reduce the high value of the threshold voltage at low temperature s and to modification of the LDD implant to reduce the high parasiti c
propose d process current RT process flow change
new LT process flow
SUPREM III I -D doping profile
lateral diffusio n
optimize HSPICE parameters circuit performance
I-V HSPICE (circuit level) curves
t
HSPICE HSPICE (device level) parameters
parameter extraction
improved I-V curves
must match
FIGURE 2 .95. Schematic representation of the flow of TCAD tools for th e CMOS process optimization for low-temperature applications [after Hwang et al. (258)] .
2 . Silicon Devices and Circuits
221
resistance and increase reliability . With these modifications, delay improvements of up to 100% in ROs operated at 77 K with a supply voltag e of 2 .8 V can be obtained at 300 K .
2 .6.2 . CMOS Analog Circuits, Readout Electronics, and Detecto r Arrays Analog functions implemented with CMOS circuits are crucial fo r proper functioning of cryogenic preamplification stages . Most of the cryogenic systems are used to sense and process physical variables, suc h as light, IR radiation, magnetic fields, temperature radiation, and energ y radiation in general, that are analog signals by nature and thus requir e preamplification by an analog circuit, readout, and send out to a n analog-to-digital conversion system for further digital processing . Thi s circuit chain must be carefully designed in order to maximize th e impedance coupling and reduce spurious noise . One of the first attempts to establish a guideline for the design o f analog circuits for cryogenic applications was made by Fox and Jaege r in 1987 (259) . In this work simple scaling rules are used to predict th e 77 K performance of CMOS operational amplifiers . The basic CMOS op amp analyzed is shown in Fig. 2 .96 . The differential mode voltage gain of the first stage is Al =
gmp2 gdp2 ava + + 8an dn2z
(2 .127)
V DD
P4
P3
P5
V+
V-
Pl
Nl VSS
FIGURE 2 .96 . Diagram of the CMOS op amp studied by Fox and Jaeger (259 ) © 1987 IEEE .
222
E. A . Gutiérrez-D ., C. Claeys, and E . Simoen
and the gain of the second stage i s A2
=
g mn3
(2 .128 )
dp4 + gdn 3
The subscript d refers to output conductance and the subscript m to transconductance. The dominant pole wd is provided by the compensation capacitor Co . At frequencies above COd the open-loop gain reduces to unity at the frequency co, ~r =
(2 .128 )
(g mp2/ Co)
Both the conductance gd and transconductance gm increase as the ternperature is reduced . However, the rate of increase is also a function o f the bias conditions and the channel length . Figures 2.97—2.100 show the temperature dependence of the conductance g d and transconductance gm of an array of n-MOS transistors fabricated with a 0 .5-µm IMEC CMO S technology (260) . In Figs . 2 .97—2 .100, the rate of increase at lower temperatures i s always higher for longer transistors than for shorter ones . This is shown in Fig . 2.101, in which the 77 K values of gd and gm , normalized to 300 K, are plotted as a function of the channel length . The increase in gd and gm at 77 K with respect to 300 K is also a function of the bias condition . In general, the increase of g d and gm at 77 K is higher when the transistor s are operated in the linear region than in the saturation regime . Thi s
conductance g d (AN) @ 300 IC 2.73X10-3 1 .50X10-3
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2 . Silicon Devices and Circuits
223
conductance gd (A/V) at 300 K 7 .50X10 -5 @ L=O .S µ m I .6OX 10" 5 @ L=1 .0 µ m
5 .03X I0-6 @ L=2 .0 µ m 1 .10X10-6 @ L=5 .0 p m 2 .50X 10-7 @ L=10 .0 pm
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L=5 .0p m
L=1 .0 pm
0
100
50
150
200
300
250
Temperature, T [K]
Normalized conductance g d (AId /Vd) versus temperature for a n array of n-MOS transistors fabricated with a 0 .5-µm CMOS technology . Th e transistors were biased in the saturation regime ; VD = 3 .0 V, VG = 2 .0 V . Th e values at 300 K are shown in the inset . FIGURE 2 .98.
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g m=3 . 12X 10- 5 (A/V), 10 .0 p V
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♦ ♦♦♦ ♦ ♦
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100
t
l
1
L=I .O µ m 1 1 I 1 1 1 1 150 200
1
I
l
250
1
I
300
Temperature, T [K ]
Normalized transconductance g m (AId /Vg) versus temperature for an array of n-MOS transistors fabricated with a 0 .5-µm CMOS technology. The transistors were biased in the linear regime ; V D = 0 .25 V. The values at 300 K are shown in the inset. FIGURE 2.99.
224
E . A . Guti érrez -D ., C . Claeys, and E. Simoe n 4.0 b4
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ô
3.5
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I
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L=10.0 p m
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11111111
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L=0 .5 pm L=1 .0 Nm L=2 .0 }~m 1 1 1 1 0 .50 - I I , l I I l 1 I 100 150 0 50 _
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Temperature, T [K ] FIGURE 2.100. Normalized transconductance gm (AId /V g) versus temperature for an array of n-MOS transistors fabricated with a 0 .5-µm CMOS technology . The transistors were biased in the saturation regime ; VD = 3.0 V. The values are 300 K are shown in the inset.
FIGURE 2 .101 . Normalized (77 K/300 K) conductance gd and transconductance gm versus channel length L for an array of n-MOS transistors . The subscripts lin and sat indicate linear and saturation regions, respectively .
2 . Silicon Devices and Circuits
22 5
temperature dependence is due to the different components of the carrier mobility, which have different temperature dependences . Thus , in the saturation regime the velocity saturation plays a key role, wherea s in the linear region components such as surface scattering and carrier-to carrier scattering are more important . At temperatures below 50 K anomalous behavior is observed in the conductance and sometimes i n the transconductance . This is due to the combination of three effects : the freeze-out, the drain threshold voltage (261), and generation of substrate currents (262) . The impact of these effects on the I - V characteristics o f MOS transistors at 4 .2 K is shown in Figs . 2.102 and 2 .103 . At low values of Vd the Id -Vd characteristics deviate from linear to a quasi-exponential behavior . This is due to the so-called "drain threshol d voltage" which is caused by a potential barrier at the edges of the gat e in the overlapping gate-to-source/drain regions . This quasi-exponential behavior causes the conductance g d to slightly increase at temperature s below 50 K . It is also important to note that this effect is channel lengt h dependent . As the channel length increases the I d -V d characteristic s suffer less of the drain threshold voltage . At high values of the Vd voltage, the combination of freeze-out and substrate current increases th e substrate voltage, thus reducing the threshold voltage and increasing the Id current and the conductance g, . The transition temperature at which freeze-out affects the electrica l performance of the MOS transistor is apparent in Fig . 2 .103 . From 50 K (continuous curve in Fig . 2 .103) upwards the substrate current lb gener ated by the MOS transistor flows through the substrate to the substrat e
14
111111111
1
I
quasi-exponentia l 1behavior due to the drain-threshol d voltage effect
I
1
1
~
I
V~, =4 V
-
3V
:–.
increase of the conductance due to the "kink" effect
o '/
0
0 .0
d
0 .50
1 .0
1 .5
l
1
1
i
1
1
1
2 .0
l I
2 .5
1
1 V I
1
L
1
3 .0
1
I
3 .5
Drain voltage, V d [V]
FIGURE 2.102. Experimental Id -Vd characteristics of a (W/L) = 10/0 .5 n-MOS transistor operated at 4 .2 K .
226
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen 2.5
16 50 K
14
~
r--, 12
=
~
_
„
►—+
1
10 —
-
/
/
i
40 K 30 K
(n a
-
—_
2 .0 5r
6-1
1
,'
~,,
8
V
1
L V
4 — _
0 0 .0
;•.
. I; •
1!
~
0 .50>
~' ~•.~ .
~
,.
t~I/~
I
1 .0
.
_
._. l I 1" I 1 1 I 1 2 .0 3 .0 4 .0 Gate voltage, V g [V ] ~ I
~
~
~
}
1-
l
~,
0.0 5 .0
FIGURE 2 .103. Experimental Id —Vg characteristic of a (W/L) = 10/0 .5 n-MOS
transistor biased at Vd = 3 .0 V and operated at 4 .2 K . contact, causing a slight voltage drop through the substrate . At T = 40 K (short dashed curve in Fig. 2 .103), the top part of the lb current is cut off . The cutoff lb current is now flowing through the source–substrat e junction, which became forward biased due to the increase in the substrate voltage caused, by the flow of l b through a semifrozen high-resistive substrate . At 30 K (long dashed curve in Fig. 2 .103) the substrate is fully frozen and all the lb current flows through the source–substrate junction. The increase in the substrate voltage cause s the variation in the Id current, which also changes to conductance g d . Fox and Jaeger (259) proposed two ways to exploit low-temperatur e operation by using the same geometry as that of 300 K and b y reducing geometries . In both cases, the performance and geometry o f circuits are described in terms of the scale factors aµ and al . In the firs t case, a change of gm and gd at 77 K with respect to 300 K is given approximately b y and
gm177 K —
~ a µ al
gd177 K —
a
*
gm1300 K
I . gd1300 K
(2 .130 ) (2 .131 )
Because the gain of each stage is proportional to the (gm /gd ) ratio, the change in the DC open-loop gain Ao is given by
a
A
o177 K — () . AO I 3 ~ O K a
I
(2 .132)
2. Silicon Devices and Circuits
22 7
The slew rate depends on the capacity of transistors P 2 or N 2 to charge the C . capacitor, which is proportional to ai . The unity gain frequency co , at 77 K is given by W tI77K
= N,/ a µ aI
' Wt I300 K
(2 .133 )
The phase margin `l' m depends on the relation between co, and the lowes t frequency nondominant poles. The poles due to parasitic capacitance s increase by an amount between N/aµ a I and aI . Then, if a l < aµ , these poles may not increase in frequency as much as does co t , which implie s a degradation of qm at 77 K . However, as demonstrated for the channel and bias dependence of gm and gd, the bias can be adjusted to get a l > aµ for an improvement in 4m at 77 K. The second alternative to exploit low-temperature operation is t o reduce geometries at a constant performance . If the operating current s are kept constant and all the channel widths are reduced by a factor a µ , then a I ti 1, gm at 77 K will equal gm at 300 K, and gd at 77 K will equal g d at 300 K. Under these conditions the DC voltage gain and the power consumption remain unchanged . Then, as the areas of the parasiti c capacitances scale down with the channel width and the conductance s are unchanged, the nondominat poles scale up in frequency by a factor a µ . Therefore, the compensation capacitor C. can be reduced in area without degrading the phase margin, which results in an increase in th e slew rate . Fox and Jaeger (259) tested this model using a series o f measurements on op amps fabricated in an 8-,um Al-gate p-well CMOS process. The op amp shown in Fig . 2 .96 was biased at VDD = 5 V , Vss = — 5 V, with an external compensation capacitor C . = 54 pF. At 77 K the input stage transconductance G . increased by a factor of 2 .8 . These authors found discrepancies between the G . versus 'bias variation and the transconductance variation measured for the p-MOS transistors . They attributed this to a µ sensitivity to interface charge densities . However, a s discussed previously, these discrepancies can be attributed to the channel length and bias dependence of the temperature dependencies of gm and gd . The measured unity-gain frequency ft = (co t /2n) matched very well that calculated from ft = G m / (2itC°) . These results are shown in Fig . 2 .104 . The input-referred noise level (in decibels below 1 V rms / ./Hz ) measured at 77 K with 'bias = 400 ,uA is about 1 .5-2 dB lower than that at room temperature . The measured slew rate shows a nontemperaturedependence behavior . The overall voltage gain A . for this structure is given by the product of the gains of each of the two stages : A = °
G. 2 1 I3
gmn3 . 22Ibias
(2
.134
)
228
E . A . Gutiérrez-D ., C. Claeys, and E . Simoen N
2000-, 77 K
c,._,- 1500 — Û a) 4
1000 – _
-4
_
~
ân ~
calculated
_ -
300 K
-
500
FA _ measured
0
^ 1
1
0
1
1 1
1
1
1
100
1
1
1
200
1
1
l l l l l 1
1
300
1
1
400
Current bias, 'bias [µ
1
1
500
I
I I
I
I
1
600
1
1
1 700
A]
FIGURE 2 .104 . Unity-gain frequency f, versus 'bias at 300 and 77 K [replotte d from Fox and Jaeger (259)] © 1987 IEEE . where 2 1 = 0 .0143 V -1, 2 = 0 .022 V -1 , and G m , 13, and g. 3 are measured values . The measured overall DC voltage gain versus Ibias at 30 0 and 77 K is shown in Fig . 2 .105 . In a study by Schoeneberg et al. (263) the CMOS readout circuitry fo r a liquid argon calorimeter was optimized for 83 K operation . This chip, fabricated using n-well 2-µm CMOS technology, contains 16 analo g channels with switched-capacitor circuits for charge collection, storage , amplification, and averaging and correlated double-sampling circuits fo r
5000 0 0
40000 L
.• 8 aA a) bcdA
30000 _ 20000 ~~
O >
10000 =
–_
calculate d ~ , .
~
!
77 K
2
300 K O 0L~~~I~ „ ► I ► Ei) 400 500 600 0 100 200 300 Bias current, Ibias [µA ]
_700
FIGURE 2.105 . Measured and calculated voltage gain A. versus bias current 'bia s at 300 and 77 K [replotted from Jaeger (259) © 1987 IEEE .
2 . Silicon Devices and Circuits
22 9
noise reduction. This readout system is used for reading out the signal s from many capacitive sensors . These signals are generated by the secondary emission of an accelerator, in which the occurrence of thi s event depends on the collision and can occur only every 100 ns . The system and a trigger generator, an analog multiplexer, and digita l circuits for analog switching are operated at 83 K. Experimental results of this system operated at 77 K show a considerable reduction of whit e noise but a slight increase in flicker noise, suggesting that the S / N rati o of the system can be improved at cryogenic temperatures . It is als o shown in this experiment that the operation of high-performance CMO S analog circuits is feasible for readouts of capacitive detectors in the nanofarad range . Another interesting example of CMOS analog applications t o cryogenic systems is the ISOPHOT cryogenic readout electronics (264) . This Infrared Space Observatory is a project funded by the Europea n Space Agency (ESA) and will be used for astronomical satellite applications, in which the IR spectrum from 3 to 200 µm will be investigated . This instrument contains a cryogenically cooled telescope with focal plane instruments that allow imaging and photometric, spectroscopic , and polarometric observations . The specifications for this IRdetection system are very strong; fo r instance, a NEP of 10 - l ' W/ .3Hz, a dynamic range of 10 5 , a responsivity on the order of 1–10 A/W, a charge noise specification o f 100–1000 e -, a maximum detector current rate of 10' to 10 8 e - /s, and overall power dissipation per detector below 300 µW, are required . To eliminate the inherent problems related to low-temperature operation such as low response time, reduced output signal dynamic range , and charging of stray capacitances, Dierickx (264) proposed an integrating feedback amplifier (Fig . 2 .106) . The detector current is accumulated on the feedback capacitor C and the detector bias is kept constant at th e virtual ground level of the amplifier input-node . By resetting the ampli fier the 1/f noise and cryogenic drifts in the input MOS transistors ar e
rese t detector ti bias
1111
output to mux .
FIGURE 2.106 . Integrating feedback amplifier (264) .
230
E. A . Gutiérrez-D ., C . Claeys, and E. Simoen
partially alleviated . The power dissipation and the bandwidth of th e amplifier are both controlled by a current mirror stage . Two cascod e transistors are added to the basic amplifier scheme to further increase the amplifier gain and to keep the voltage over the transistors sufficient ly low to avoid excessive kink noise of the cryogenic amplifier . The charge integration capacitor is designed to have a minimum size and a minimal value. A sample and hold stage to synchronize the readout of the pixel s precedes the integrating stage . The system is calibrated by adding tw o supplementary inputs; one serves as a reference for the zero bias leve l ("dark" condition), and the second is connected to a 5 GSZ detector tha t emulates a resistor to determine the DC transfer function of the device . Most of the control pulses are generated on-chip . The system has a standby function that deactivates the clock generator and limits the current through the amplifier to reduce power dissipation . The experimental results of this initial experiment showed that requirements ar e met, and that CMOS analog circuitry is sufficiently reliable to operate a t 4 .2 K . The design has been recently optimized to be used in the ESA satellite FIRST (Far Infrared and Submillimeter Space Telescope) to be launched in 2005 (265) . This readout will be used for imaging signals i n the 100-ym to 1-mm wavelength range . This system will be operated a t 1 .6 K . Operation at this temperature requires a careful design . The modified readout circuit is shown in Fig. 2 .107. The Cac capacitor decouples the detector from the amplifier and cancels the variation of th e bias voltage over the detector . The feedback from the input to the direc t injection transistor is done with an AC-coupled amplifier . The photocur -
V DD
reset
rese t
outpu t signa l reset C ac zero bias
detecto r
uc OTA
Bias FIGURE 2 .107.
(265)] .
Modified direct-injection readout circuit [after Seijnaeve et al.
2 . Silicon Devices and Circuits
231 V
C~
MP2
1 Mpl
DD Mp 3
I
~--
MP 5 MP6 M P4
vo O MN3
MNI ~
FIGURE 2.108. Circuit scheme of the folded cascode amplifier [after Kleine e t al. (266)] © 1994 IEEE. rent is integrated on a capacitor C 1 . The variation and drift of the bia s voltage are very low . The main advantage of this scheme is that ful l integration on-chip is possible . A low-noise CMOS readout preamplifier operated at 4 .2 K has been reported by Kleine et al . (266) . This circuit is applied to a SQUID t o measure biomagnetic fields . It is a folded cascode amplifier with it s input attached directly to a low-impedance SQUID output . An equivalent noise voltage density of 0.3 nV .3Hz at 500 kHz at 4 .2 K has bee n measured . This preamplifier has proved to be essential in lowering th e costs of biomagnetic systems by simplifying the expensive shielding . Th e circuit diagram of the folded cascode amplifier is shown in Fig . 2 .108 . The magnitude of the input signal Vin is in the range of 100 ,uV and ha s a low linearity . Therefore, the preamplifier is in an open-loop configuration . Moreover, the folded cascode configuration prevents the circui t from displaying kink effects . The circuit is biased with an externa l current source I . The C 3 is an external capacitor (1 nF) used to ensure a common source operation of transistor MP4 . To achieve the required high-noise performance, the input transistor M P4 is made large (W/ L = 1000/2 ,um), and the resistive poly gate noise is reduced b y using a finger-like structure with 20 identical poly stripes .
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
232 104
W
I
111111
1
111111
q
°
0 .1
1111111
1
1
1111111
10
1
1
1111111
1
1
1
1
.
IT1 1
°
1 1111
100
1000
1
1
11111 1
104
Frequency, f [KHz ]
Measured equivalent input noise voltage density at 4 .2 K for the amplifier of Fig . 2 .22 [replotted from Kleine et al . (266)] . FIGURE 2 .109.
The measured gain of the preamplifier, fabricated using a 1-gu m p-well CMOS technology, was 24 dB at 300 KHz with a power suppl y voltage of + 2 .5 V . The measured equivalent input noise density i s shown in Fig . 2 .109 . The 1/f is the dominant noise component and i s approximately threefold higher than its value at 300 K . The complete performance of the amplifier is characterized by a gain at 300 KHz o f 24 dB, an output swing of 400 mV, a bandwidth with a C L = 600 pF of 22-308 KHz, an output resistance of 3 k1, a power consumption of 9 mW , and a chip area of 0 .3 mm 2 . The 1/f noise can be reduced by using buried channel MOSFET s (267) in which implanted impurities in the channel, as opposed to tha t of the substrate, are biased to form the conducting channel away from the Si/SiO2 interface. In this way, noise sources other than the therma l and flicker noise are revealed, as is the 1/f 2 , which is attributed t o generation—recombination either in bulk silicon traps or in traps a t mid-band gap (268) . This 1 /f2 noise is largely dependent on gate an d substrate voltages, that with a careful choice of bias conditions, lead t o extremely low noise performance . The device discussed here was fabricated in a standard CCD process, in which the buried channel transis tor had a P implant of a dose of 8 x 10 11 ions / cm 2 at 180 keV tha t resulted in a channel junction depth of 1 .08 pm with a net surface donor concentration of 1 .5 x 1 0 16 cm - 3 . Thus, a deep buried channel is formed and the device behavior is studied in either the depletion or th e inversion mode by properly biasing the gate and bulk . The gate oxide
233
2 . Silicon Devices and Circuits
thickness is 50 nm, and the transistor has a square geometr y (10 x 10 µm2 ) . The drain voltage was kept at 5 V, the gate voltage wa s swept from 0 to — 8 V, and the bulk voltage was adjusted to maintain a constant drain current of 1 µA. Noise was measured, under these bia s conditions, over the frequency range of 1 Hz to 10 kHz . The measured o. s noise current at 1 Hz with Id = 0 .1,uA reduces from 20 to 0 .6 pA / Hz when the bulk-to-gate voltage Vbg changes from 0 to 4 .5 V . Kandiah and Whiting (268) conclude that a very low noise in a depletion-mod e MOSFET can be achieved only if the surface is inverted, which th e prominent G—R noise is totally suppressed . Thus, very low-frequency noise circuits are achievable in MOS technology . An experimental characterization of four different architectures o f CMOS amplifiers was presented by Daud et al . (269) . An n-channel input two-stage Miller amplifier (NDV), a p-channel input two-stage operational transconductance amplifier (POTA), an n-channel folded cascod e two-stage amplifier (NDC), and a low-power version of the NDC wit h input stage in weak inversion (DCL) were characterized at 300, 77, an d 4 .2 K . The four architectures are shown in Figs . 2 .110 and Fig . 2 .111 . Th e experimental results of these configurations operated at 300 and 4 .2 K ar e shown in Table 2 .3 . Another interesting application is the neural network requiring hig h speed and intensive image processing capability, which inherently re quires a fully parallel hardware embodiment . Recognition of targets in a few seconds is one of the specifications that must be met using a 64 x 6 4 pixel IR image sensor mated to a 3D stack (cube) of 64 neural networ k ICs along each of the edges . Daud et al . (269) propose the "cube" t o operate at 90 K with a signal processing speed lower than 250 ns an d approximately 2 W of power dissipation . Special designs of analo g neuron and synapse, implemented in VLSI, are presented which bear ou t
vss 'a
vss b
FIGURE 2 .110 . Architecture of the NDV (a) and POTA (b) amplifiers .
E . A . Gutiérrez-D ., C . Claeys, and E. Simoen
234
13 1M—I
El
j
I I
M13
b
M3
14
1:
M4
M7 ~
M6
5 14
Vou t
V ou t 8
I 6
M5
M 15
VD D
V DD M 10 M8 M 16 C f 34 10 M2 I- 2 12 E2 1 17 •
M9
M 12
I
15
1
v ss a FIGURE 2 .111 .
b
Architecture of the NDC (a) and DCL (b) amplifiers .
high-speed response at room temperature with synapse—neuron signa l propagation times lower than 150 ns . In order to increase the size of th e VLSI networks, die stacking is used to form a cube constructed fro m many thinned die that occupy the same footprint as a single die . In this case, a 64 x 64 image sensor is mated to a stack of 64 neural networks . The idea of this proposal is shown in Fig . 2 .112 . The demonstration of high-speed, low-power neuron and synapse circuits enables the realization of a 3D neural network architecture for high-speed pattern recognition. Power dissipation estimated with circuit simulation is expecte d to be less than 30 mW for each neural network IC . The neural ICs wit h
Table 2 .3 Measured Results for T = 4 .2 K and T = 300 K T =300K
T =4 .2 K
Parameter
NDV
POTA NDC
DCL
NDV
POTA NDC
DC L
fT (kHz)
100
100
3800
100
360
130
322
52
lb (µA)
25
50
20
50
11
25
21
40
VB (V)
±7
±5
±5
±5
±3
±3
±5.9
±5
A0, (dB)
42
60
66
42
36
42
43
28
C~ (pF)
10
10
0
10
22
22
0
100
v 1f (1 kHz) [nV /Hz ° 5 1
71
71
45
158
56
40
P(mW) lowest
0.18
0.2
0 .5
1 .2
0 .15
6.4
16
1 .0
2. Silicon Devices and Circuits
235
FIGURE 2.112 . The 3D cube architecture (a) and the circuit diagram of a variable sigmoidal neuron (b) (269) .
64 inputs, up to 64 hidden units, and six outputs are designed fo r stacking in a 64-chip cube, resulting in more than 1 trillion connection s per second potential. This very high processing power system allows th e spatiotemporal recognition of both point and resolved objects in a constrained time . These researchers anticipate stackings of up to 1024 ICs, mated to a 1024 x 1024 imager systems . Among the imager systems, the most widely used in the field o f cryoelectronics are the IR focal plane arrays . As mentioned previously, these are mated to silicon readout circuitry. This hybrid configuration is the most convenient for high-performance applications, in which the
236
E . A . Guti érrez -D ., C . Claeys, and E . Simoe n
Table 2 .4 Predicted Characteristics of the HAWAII-2 IR FPA Parameter
Minimum
Format
2048 x 2048
Pixel pitch
Off-chip temporal nois e suppressio n
µm
128 pin
Die size
Units Pixels
18
Chip package (optional)
Input circuit
Maximum
ZIF PG A
u 39 x 39
mm2
Direct detector integration correlated double sampling, Fowle r sampling 8-tap video averaging
Spatial noise suppression Supply voltage Integration capacitance Charge capacity at 0 .5 V
5 20
35
0 .102
0.105
Input offset nonuniformity Dynamic range Output taps
Conversion gain (Sv)
10 -15 F
<5 > 0 .8
1
4
32
Data rate per output tap Read noise
V
mV p—p 10 3
2 <3 ti 3 .5
10 6 e
MHz
<9
e7
µV /e
detector array and the circuit can be optimized in an independent way . It is important to note that although the materials used to fabricate th e detectors are HgCdTe, InSb, Si :Ga, Si :Ge, or doped silicon, the circuit that reads the signal from them is always silicon based . The most widely used is the submicrometer CMOS applied to IR astronomy . The most advanced approach is the HAWAII-2 2048 x 2048 CMO S FPA currently being developed by Rockwell Science Center (270) . This has four independent 1024 x 1024 quadrants combined with a 0 .8-,um CMOS circuitry . The expected characteristics of HAWAII-2 CMOS FP A are shown in Table 2 .4. Twelve 2048 x 2048 CMOS readouts will b e fabricated in a 200-mm wafer, in which each readout will be an array o f MOSFET switches comprising cascaded source follower stages that ar e separated by MOSFET switches . The signal voltage from each pixel in the array is read through the first stage source follower consisting of a pixel-based driver MOSFET and a current source FET shared among the
2 . Silicon Devices and Circuits
237
1024 elements in each column . The whole chip will be packaged using the zero insertion force pin grid array . This design anticipates about 4 . 2 million pixels, a read noise after correlated double sampling lower tha n 10 e -, a dark current at 78 K lower than 0 .1 e - Is, and a broadban d quantum efficiency larger than 50% from 0 .85 to 2 .5 ,um .
2 .6 .3 . SiGe HBT Circuits Among the SiGe-based technologies, the emitter-coupled logic bipola r technology is one of the most used for fast digital applications . The propagation delay time 'rd is the main figure-of-merit that determines th e switching speed. Increasing the cutoff frequency fT of the transistor only gives a slight reduction of T d . However, a reduction of the base resistanc e R B results in a significant reduction of T d , both of which are possible with SiGe-based bipolar technology. The first experimental examples of thi s performance improvement are those reported by Harame et al . (271) , who noted delay times of 18 .9 ps from ring oscillators fabricated wit h SiGe HBTs . A remarkable feature of SiGe HBTs is that their low bas e resistance makes it unnecessary to scale them down to submicrometer emitter widths . For instance, a gate delay of 15 ps can be obtained wit h a 1-µm SiGe HBT technology (272) compared with 20 ps of a 0 .25-µ m BJT technology (273) . The SiGe HBT technology has been modified so that two bases ca n be added, providing the chance to independently control the transisto r current, and thus forming a single-transistor NAND gate for operatio n at 77 K (274) . Low noise amplification is another potential application for SiG e HBTs . The high-frequency noise is determined by the base emitte r capacitance CBE , the base resistance RB , and the base transit time T B of the bipolar transistor . In the case of the SiGe HBTs, these parameters ca n technologically be made very small, which leads to low noise data . Fo r instance, unpassivated mesa structures used in a 9 .6-GHz hybrid dielectric resonator oscillator (275) showed — 85 dB noise at 100 KHz of f carrier . This noise level is comparable to that of III—V devices . Furthermore, the SiGe HBT has been used in very high-performance analo g applications, such as the 1 .0 Gs/s 12-bit digital-to-analog converter (276) . The most recent progress and future prospects for the cryogenic operation of SiGe technologies have been reviewed by Cressler (277) , who mentioned that the SiGe HBT technology can be successfull y manufactured on 200-mm wafers with integration levels, performance , reliability, and yield that will make it useful for realizing commercial RF and microwave integrated circuits in the 1- to 20-GHz domain . Here, the
238
E. A . Gu tiérrez-D ., C. Claeys, and E . Simoen
integration of conventional Si CMOS and BiCMOS with SiGe HBT technology is anticipated to offer considerable leverage for cryo applications because of the superior cryogenic properties of both SiGe HBT an d CMOS/BiCMOS technologies . It is also anticipated that SiGe HBT / BiCMOS technology will be required to implement "system-on-a-chip " for the emerging wireless market, and that the extension of the combination of technologies to the cryogenic environment should naturally follow . Jayanarayanan et al. (278) also reviewed the potential of silicongermanium—carbon HBTs for cryogenic application . Simulation results of the strain-compensated SiGeC HBT are presented in the 300—77 K temperature range, where the limitation on the amount of Ge that can b e introduced into the Si lattice can be alleviated by introducing C into the SiGe alloy . Due to the smaller lattice constant of C, very little amount s of C suffice for giving a free-strain material that offers the same devic e possibilities as SiGe . It is shown through simulations that the curren t gain and cutoff frequency for a graded-base SiGeC HBT increase substantially with cooling, yielding very high-performance transistors a t
77 K. Regarding the possible applications of SiGe HBTs for cryogeni c instruments, the radiation hardness can be a restriction for space-borne instruments such as space telescopes . However, studies on the effects o f neutron irradiation on the cryogenic performance of UHV / CVD SiG e HBTs (279), show that SiGe HBTs exposed to 1 MeV neutrons at doses ranging from 10 11 to 10 15 n / cm 2 at 300 K, and characterized over the temperature range of 300 to 8 .4 K, are sufficiently robust to bear such an irradiation without affecting their electrical performance . Further studies on the static and dynamic characteristics of SiG e HBTs operated in the 300—50 K temperature range were performed b y Aniel et al . (280) . The unity current gain frequency fT' which is extrapolated from the — 6 dB/octave roll-off of h 21 , and the maximum frequenc y frnax' which is the 0 dB frequency of the maximum available power gain , increase 75% (fT = 52 GHz at 50 K) and 30% (fmax = 68 GHz at 50 K) with respect to 300 K .
2.6 .4 .
SOI Circuits
It has been difficult to prepare SOI technology for commercialization , especially because of the high defect density, which is the major obstacl e for mass production . However, in 1998 IBM announced that it woul d produce the first SOI-based circuits (281) . IBM has prototyped micro processors, 4 MB SRAMs, and phase-locked loop circuits on SOI wafers .
2 . Silicon Devices and Circuits
239
2 .6 .5. Summary The electrical performance as a function of temperature of CMOS digita l and analog circuits was reviewed. Digital circuits, such as microprocessors and multiplexers, work well at 77 and 4 .2 K, with an enhancemen t of about 1 .7 in frequency response at 77 K compared to room temperature. CMOS analog circuits works well down to 4 .2 K as preamplifier s for SQUIDs . DRAMs were observed to work to 89 K (a 256 Kb DRAM), wit h failures of the sense circuit . However, it is expected that with new technologies the results at 77 K obtained in the 1980s will be improved . Moreover, for the CMOS technologies designed for cryogenic operation , it is expected that additional improvement will be obtained for bot h digital and analog circuits. Among the bipolar-based circuits, only those fabricated with SiG e HBTs are appropriate for cryogenic application . The SiGe HBT technology is ready for mass production in 200-mm wafers for commercial RF applications in the 1- to 20-GHz range . This technology, combined with CMOS (BiCMOS), is anticipated to offer considerable leverage fo r cryogenic applications because of the superior cryogenic properties o f both SiGe HBT and CMOS / BiCMOS technologies .
2 .7 . CONCLUSION S This chapter discussed the most important and widely used Si-base d technologies, from the device level to the circuit level . Thus, the electrica l performance of MOS transistors was reviewed as a function of temperature . The review was based on two of the most popular models used b y IC designers . The predicted results were compared to experimental data , and discrepancies were discussed based on physical properties . W e discussed the future of deep submicrometer MOSFETs for cryogeni c operation . Following the trend of the CMOS evolution, we conclude that by th e end of the Year 2000 gigaintegrated CMOS systems, with more than 10 9 transistors on chip operated at frequencies above 1 GHz, will be available, and that deep submicrometer and nano MOSFETs indicate a promising future for cryogenic applications . SOI MOS transistors were also reviewed, including the basic operatin g principles and the different structures . It is expected that commercial us e of high-volume products will become feasible in the near future, indicated by research at IBM . SOI also has a strong potential for cryogeni c applications, in which it can be applied for hard-radiation systems .
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Bipolar technology was also discussed in this chapter . The different topologies of bipolar transistors were reviewed, and we concluded tha t the only bipolar transistor appropriate for cryogenic applications is th e SiGe HBT, which shows a remarkable performance at temperatures as low as 77 K . The SiGe HBT can be combined with CMOS to exploit th e cryogenic benefits of both technologies . In addition to transistors, radiation detectors were also analyzed a s possible prospects for cryogenic applications . The versatility of Si-base d photodetectors is remarkable; they are able to cover the spectral rang e from soft X-ray up to mid-IR, passing through the visible range . They are also able to operate at room temperature to 4 .2 K with excellen t electrooptical performance. Among these photodetectors, the CCDs, photodiodes, and SBDs are the most versatile . They cover the soft X-ray to the IR wavelength range and work well in the 300-4 .2 K temperature range. Furthermore, there is a trend toward the implementation of monolithic Si-based technology detectors . This is more clear fo r the IR spectral region, for which SBDs have been shown to be CMO S compatible . In the field of circuits applications, CMOS technology has bee n shown to be ready for digital and analog application for temperatures a s low as 4.2 K. The SiGe HBT is a good candidate for RF and wireless applications in the 1- to 20-GHz range . This technology combined wit h CMOS (BiCMOS) is anticipated to offer considerable leverage fo r cryogenic applications because of the superior cryogenic properties o f both SiGe HBT and CMOS/BiCMOS technologies .
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E . A. Gutiérrez-D., C . Claeys, and E . Simoen micrometer CMOS device at low-temperature operation, " IEEE Trans . Electron Devices 39(2), 370–378 (1992) . C. Hwang et al., "Process modification for improved low temperature CMOS performance," Proceeding of the WOLTE 2, published in J . Physiqu e IV 6, 193–197 (1996, April) . R . M . Fox and R . C. Jaeger, "MOSFET behavior and circuit consideration s for analog applications at 77 K," IEEE Trans . Electron Devices ED-34, 114–123 (1987) . E. A . Gutiérrez-D ., "Electrical performance of submicron CMOS technologies from 300 K to 4 .2 K," Ph .D . dissertation, pp . 29—41, Catholic University of Leuven, Belgium (1993, May) . E . A. Gutiérrez-D ., "The drain threshold voltage in submicron MO S transistors at 4 .2 K," IEEE Electron Device Lett . 16, 85–87 (1995, March) . E . A . Gutiérrez D ., L. Deferm, and G . Declerck, "Transconductance degradation and its correlation to the second substrate current hump o f submicron NMOS LDD transistors," Microelectron . Eng . 15, 449–452 (1991) . [Also in Proceedings of the ESSDERC '91 Conference.] U. Schoeneberg et al., "CMOS readout electronics for operation at cryogenic temperatures, " IEEE J. Solid-State Circuits 24(3), 718–722 (1989) . B . Dierickx, "Transient phenomena and noise in silicon MOSFETs a t cryogenic temperatures," Ph .D . dissertation, Catholic University o f Leuven, Belgium (1990, May) . J . Seijnaeve et al., "Cryogenic readout electronics & technology for FIRST' s stressed array, " Proceedings of the WOLTE 2 conference, held in Leuven, Belgium, June 26–28, 1996, pp . 187–191 . U . Kleine, J. Bieger, and H . Seifert, "A low-noise CMOS preamplifier operating at 4 .2 K," IEEE J . Solid-State Circuits 29(8), 921–926 (1994) . P . Martin and J . J. Yon, "Achieving very low LF noise in depletion-mod e MOSFETs, " Low Temperature Electronics and High Temperature Super conductivity Symposium, Reno, Nevada, May 21—26, 1995, Electrochem . Soc . Proc. 95-9, 321–327 . S.-L. Chen and S .-H. Chen, "The drain-bias-variable characteristics o f exponent y on 1/f noise in DDD n-MOSFETS at 77 K and 300 K, " Proceedings of the WOLTE conference, pp . 33–35, held at San Miniato , Italy (June 24—26, 1998), EDP Sciences, ?? ? T. Daud et al., "Low temperature performance of high-speed neura l network circuits," Low Temperature Electronics and High Temperatur e Superconductivity Symposium, Reno, Nevada, May 21-26, 1995, Electrochem . Soc . Proc . 95-9, 334-344. L. J. Kozlowski et al ., "Next generation focal plane array for infrared astronomy," Proceedings of the 3rd European Workshop on Low Temperature Electronics WOLTE 3, San Miniato, Italy, June 24–26, 1998, pp . 141–146, EDP Sciences, Paris . D . L. Harame et al ., "A high performance epitaxial SiGe-base EC L BICMOS technology," IEDM 92, 19–22 (1992) . Z . A. Shafi et al., "Predicted propagation delay of Si/SiGe heterojunctio n bipolar ECL circuits, " IEEE J . Solid-State Circuits 25, 1268—1276 (1990) .
2 . Silicon Devices and Circuits
25 7
273. J . D . Cressler et al ., "A scaled 0 .25 pm bipolar technology using full e-bea m lithography," IEEE Electron Device Lett. EDL-13, 262—264 (1992) . 274. E. J . Prinz et al ., "A novel double base HBT for low temperature bipola r logic," Proc . DRC, IIA-2 (1992) . 275. U . Güttich et al ., "A SiGe HBT dielectric resonator stabilized microstri p oscillator at X-band frequencies," Microwave Guide Wave Lett . 2, 281—283 (1992) . 276. D . L . Harame et al ., "Optimization of SiGe HBT technology for high spee d analog and mixed-signal applications," IEDM, 71 (1993) . 277. J . D . Cressler, "Prospects for the cryogenic operation of silicon-germanium technology," Electrochem . Soc. Proc. 97-2, 215—231 (1997) . 278. S . Jayanarayanan et al., "Potential for silicon-germanium-carbon HB T operation at cryogenic temperatures," Electrochem . Soc. Proc . 97-2, 240—245 (1997) . 279. J . M . Roldân et al., "The effects of neutron irradiation on the cryogeni c properties of UHV/CVD SiGe HBTs , " Electrochem . Soc . Proc . 97-2, 246—253 (1997) . 280. F . Aniel et al., "Temperature dependence of SiGe HBT static and dynami c characteristics," in Proceedings of the 3rd European Workshop on Low Temperature Electronics WOLTE3, San Miniato, Italy, June 24—26, 1998, ED P Sciences, pp . 81—86 . 281. L. Geppert, "Solid state," IEEE Spectrum, 52—56 (1999, January) .
Silicon Devices and Circuits E . A . Gutiérrez-D .,*
National Institute of Astrophysics Optics and Electronics Puebla, Méxic o C . Claeys and E . Simoen
IMEC, Leuven, Belgiu m Katholieke Universiteit Leuven (KU Leuven), Belgiu m 2 .1 . Introduction 2 .2 . The Bulk MOS Transistor 2 .3 . The Silicon-on-Insulator MOS Transistor 2 .4 . The Bipolar Transistor 2 .5 . Radiation Detectors 2 .6 . Circuits 2 .7 . Conclusions References
10 5 10 6 15 7 18 5 19 4 21 1 23 9 240
2 .1 . Introduction Electronic devices are fabricated with a wide variety of semiconducto r materials . Thus, these are high-speed devices made of III—V compounds, such as GaAs, InP, and AlGaAs, or photonic devices made of InGaAsP . However, an important spectrum of electronic devices are made o f II-based semiconductor materials, such as Si or Ge the bipolar transistor and metal oxide semiconductor field effect transistor (MOSFET ) transistors as well as the silicon-on-insulator (SOI) MOSFETs. The MOSFETs are widely used in the semiconductor industry for the design and fabrication of microprocessors for computer applications, for analog systems such as those for biomedical applications, or for low-powerlow-voltage applications . The bipolar in conjunction with the MOS are being used in the design and fabrication of bipolar complementary MO S *Now with Motorola-SPS, IC Design Center, Puebla, México . 105 © 2000 by Academic Press . All rights of reproduction in any form reserved . ISBN 0-12-310675-3/$35 .00
106
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
(BCMOS) systems, in which low-power consumption from CMOS an d high speed from bipolar are needed . The SOI MOSFETs have bee n traditionally used for systems exposed to hard irradiation, such as thos e in outer space or astronomy applications. Moreover, the SOI MOSFETs are by nature built in a high-resistivity substrate, which makes them ideal for high-frequency applications in which the parasitic coupling t o the substrate needs to be eliminated. On the other hand, the accelerated pace of the computer industry has pushed the development of near 0 .1-,um CMOS technologies to cope wit h the high-frequency requirements . However, Si is reaching the fundamental limits at which higher speed cannot be obtained by just shrinking th e channel length . Therefore, the semiconductor industry and researc h institutions have made an effort to incorporate higher mobility material s into the Si-based technologies . This resulted in the development of SiG e heterostructure bipolar transistors, widely known as SiGe HBTs . The HBTs have a larger carrier mobility and therefore a higher speed operation . The temperature dependence of these different Si-based devices i s reviewed in this chapter . We first discuss the bulk MOSFET by describing the CMOS technologies currently available, the electrical models fo r the three regions of operation, the impact of the parasitic effects such as series resistance, parasitic capacitances, quantum effects, polysilico n depletion effects, and electrothermal effects . In Section 2 .3 the different modes of operation of SOI MOS transistor s are reviewed, these include, inversion and accumulation . Also, device performance parameters such as the threshold voltage, the subthreshol d swing, the transient phenomena, and the floating body phenomena ar e analyzed . Alternative device concepts such as twin-gate or gate-allaround, are studied . In Section 2 .4 the standard, the polysilicon-emitter, and the SiGe HB transistors are studied . The radiation detectors are studied in Section 2 .5, in which a review of the optical properties is presented . Then, photoni c devices including photodiodes, Schottky barrier detectors, charge coupled devices (CCDs), and a-Si photodetectors are discussed . Section 2 .6 discusses circuits applications, such as CMOS-based digital and analog circuits, microprocessors, and imager systems such a s CCD arrays and focal plane arrays . SiGe HBT-based digital circuits ar e also reviewed .
2.2 . THE BULK MOS TRANSISTO R The MOS transistor has been (and continues to be) the most importan t semiconductor device in the semiconductor industry during the past 10
2 . Silicon Devices and Circuits 10 .00
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years . The MOS transistor has evolved from a 5-to-3-µm CMOS technology in 1988 to a 0 .25- to-0 .1-pm CMOS technology in 1998 . The shrinkage is exponential and the number of transistors that are integrated per chi p has also increased exponentially (Fig . 2 .1) . Data gathered from articles and conferences published until 1998 are plotted in Fig . 2 .1 . However, an extrapolation based on experimental an d unpublished data that have demonstrated MOS transistors with mini mum dimensions of 40 nm (1) is done until the Year 2005 . Assuming the current pace is kept, a 70-nm CMOS technology could be commerciall y available for the Year 2001 . Under these conditions and assumptions, integrated systems with more than one gigatransistors and clock frequencies above 1 GHz are estimated to be available in the Year 200 1 (Fig . 2 .2) . Shrinkage of dimensions below 0 .1 µm poses an interesting challeng e not only for integrated circuit designers but also for device physicists . Wiring interconnection and power dissipation are very complex an d must be handled in a proper way to keep the chip temperature as clos e as possible to the room temperature and to minimize the cycle time due to wiring delay. Devices with nanometric dimensions are prone to second-orde r effects such as velocity overshoot, ballistic transport, subsurface positio n of the centroid of the inverted channel, and gate voltage-dependen t series resistance . Some of these effects are detrimental for the electrica l performance of the device, whereas others can be beneficial, such as th e velocity overshoot that enhances the device speed .
108
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_ 101 1 1985
a a •~ 1
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yea r FIGURE 2.2 . Evolution of the clock frequency f of integrated CMOS system s from 1988 to 1998.
In the following sections we discuss how the temperature impacts th e electrical performance of MOS transistors, the effects at the circuit / system level, and how effects pertaining to nanodevices are modified b y lowering the temperature . 2 .2 .1 . MOS Technologie s The physical structure of the MOS transistor has evolved through th e year as a response to the need to improve its electrical performance an d to reduce its parasitic effects . The most widely known structure is th e lightly doped drain (LDD) transistor, first introduced by Saito et al . (2 ) and intended to suppress hot electron effects by adding a buffer regio n to lower the magnitude of the internal electric field as shown in Fig . 2.3 . The LDD region is self-aligned to the gate, whereas the heavily dope d drain region is offset from the LDD with a spacer oxide . The internal distribution of the electric field in a conventional and a LDD MOSFET i s shown in the inset in Fig . 2 .3 . In the case of a conventional MOSFET, the peak of the electric field occurs at the drain–bulk metallurgical junction , whereas for the LDD the electric field peaks near the gate edge . The peaking of the electric field under the gate oxide thickness causes th e injection of electrons into the oxide; this charge injection degrades the electrical performance and in most cases leads to failure of integrate d circuits . With the LDD option the electric field peak shifts outside the active region, and the gate oxide, under the gate, becomes less prone t o becoming hot electron injected . Thus, the LDD has been the most suc-
2. Silicon Devices and Circuits
109
FIGURE 2 .3. A schematic representation of half of an LDD MOSFET and th e internal electric field E .
cessful structure and has remained in use for implementing MOSFET s with gate lengths from 1 .25 to 0 .1 pm . Other second-order effects have appeared with the inclusion of the LDD, for example, the reverse short-channel effect (3), the gate-voltagedependent series resistance (4), and the nonuniform substrate dopin g effect (5) . To alleviate these effects, other modifications to the structure of the MOS transistor have been proposed . Among the most popular structures in the industrial research are the delta-doped MOSFET (6) an d variants of it, such as the atomic layer doping MOSFET (7), the pocket implanted MOSFET (8), and the dual gate MOSFET (9) with its ow n variants (10—12) . All these structures have been implemented to improv e the threshold voltage control and subthreshold swing, to reduce short channel effects, to improve mobility and saturation current, and t o reduce capacitance and relative gate delay . Wann et al. (13) provide a detailed comparative study of these structures . A 10-nm MOSFET transistor has been proposed (14) . This structur e uses abrupt metal—silicon Schottky junctions as a source and drain and thus avoids short-channel effects . This proposal is interesting because it shows that the minimum channel length of 70 nm, which was predicte d for conventional MOSFET (15), can be overcome and thus opens the doo r for further miniaturization and development of nanometric devices . Furthermore, in 1995 a 40-nm n-MOSFET with ultrashallow source and drain junctions of approximately 10 nm was demonstrated for the first time (16) . With this 40-nm MOSFET, reliability with regard to degradation due to hot carriers was shown not to be a serious proble m for VDD 1 .5 V. The LDD structure with phosphosilicate glass sidewall s as spacers was implemented, and the gate oxide was grown to 3 nm , with a substrate concentration of 1 x 10 18 cm' . The resulting electric
110
E. A . Gutiérrez-D ., C. Claeys, and E . Simoen
threshold voltage was 0 .4 V, the subthreshold slope S was 87 .8 mV/dec. the transconductance g m was 371 mS / mm, and the drive current Id wa s 470 mA/ mm at Vd = Vg = 1 .5 V and T = 300 K . For the sake of complete ness, different 0 .1-µm and sub-0 .1-,um MOSFETs are mentioned here . To obtain highly nonuniform channel doping, indium has been use d as an alternative channel implant in 0 .17-gum MOSFETs (17) . A verticall y layered elevated drain structure for 0.25-,um CMOS technology was als o proposed to reduce hot carrier effects while keeping the supply voltag e at 3 .3 V (18) . On the other hand, to solve the problems of trade-of f between the short-channel effect and the performance enhancement o f sub-0 .25-,um MOSFETs, a recessed channel MOSFET structure called inverted-sidewall recessed channel was proposed (19) . Moreover, roomtemperature sub-10-ps CMOS ring oscillator delays have been reporte d using a 0 .07-,um CMOS technology with n-MOSFET cutoff frequencies fT of up to 135 GHz (20) . This has proven that sub-0 .1-,um CMOS is read y for multi-GHz digital applications and is also a strong candidate fo r high-speed data communications . There is another interesting approac h to improve the speed response : the use of SiGeC alloys in the channel of MOSFETs (21) . This has allowed an increase in the cutoff frequency o f up to 180 GHz at 77 K . Regarding low-temperature operation of CMOS technologies, th e LDD is the only one which has been studied and optimized to operat e at cryogenic temperatures : Examples are the work on 0 .25-µm CMO S devices optimized for cryogenic operation (22) and the work on LD D optimization for cryogenic operation (23) . In both cases, optimization was achieved at 77 K. In the first case, the technology was optimized t o obtain high-speed (22 .8 ps per gate) CMOS circuits at VDD = 1 V, where as in the second case the technology was designed to maximize ho t carrier device lifetime . In the following sections, the impact of temperature on the electrica l performance of MOS transistors will be analyzed . This analysis will consider deep submicrometer and nanometric devices and their relate d effects . 2.2 .2 . The Subthreshold Regim e The operation of MOS transistors in the subthreshold region is especially important for deep submicrometer devices and for low-voltage operation . Deep submicrometer and nano-devices must be operated at low voltages to reduce hot carrier effects and degradation . For instance, 0 .1-µm MOSFETs are operated at V DD = 1 .5 V to keep hot carrier generation low and improve reliability . Furthermore, the fabrication of 0 .1-,um MOSFETs requires the use of high substrate doping levels to keep good
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FIGURE 2.4. The inversion hole density ps versus gate voltage Vg for a p-MOSFET with three substrate doping concentrations Nb . The gate oxid e thickness TO is 14 nm for the three devices [replotted from Hu et al . (24)] © 198 0 IEEE . electrical performance, which implies a trade-off with keeping a lo w value for the threshold voltage . Calculations of the inversion hol e density p s for a pMOSFET (24) show that high substrate doping level s shift the p s curve to the right when plotted as a function of the gate voltage Vg (Fig . 2 .4) . It is important to note that the charge diffusion mechanism will b e more dominant, with respect to the drift mechanism, as the MO S technology shrinks to deep-submicron dimensions and as the suppl y voltage is reduced to 1 .5 V and lower . This is easily seen in Fig. 2.4 . (ps —Vg) plots in between 10 1 ' and 10 18 cm'3 bulk doping levels corresponding to typical technological parameters of 0 .1-pm MOS technologies . For this bulk doping level range, the V g voltage at which the ps —V g curve goes from the exponential increase to the saturation level lies i n the 1 or 2 V range, which means that a large percentage of the carrie r conduction in a 0 .1-pm MOS technology operated at VDD = 1 .5 V will b e due to diffusion. This can be confirmed by experimental results of a 0 .5-pm CMOS technology operated in the 60—200°C temperature range (25) . A very interesting feature shown in Fig . 2 .5 is the value of the Vgt i voltage at which the drain current is temperature independent . Figure 2 .5 indicates that for Vg < Vgti the Id current increases with T due to positive temperature dependence of the diffusion process, whereas fo r Vg > Vgti the current Id decreases with T due to the negative temperature
112
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen
FIGURE 2.5 . Experimental Id -Vg curves for a (W/ L) = 10/0 .5 n-MOST ET operated at VD = 0.1 V and T = 60, 80, . . . , 200°C . The current normalized to its value at 60°C is plotted on the right axis .
dependence of the carrier mobility. That is, diffusion of carriers dominates the Id current at the left of Vgti , and drift of carriers dominates the Id current to the right of Vgti . At V g = Vgti the transport mechanism s cancel each other, resulting in a bias condition in which the MOSFET i s temperature independent . When the temperature is decreased to that o f cryogenic temperatures, the Id current increases for Vg > Vgti and decreases for Vg < V gti . Thus, in the diffusion regime the leakage current due to thermal processes diminishes, enhancing the signal-to-nois e (S / N) behavior of the MOSFET at cryogenic temperatures . The use of discontinuous models is widely accepted in the integrate d circuit (IC) design field ; that is, a different mathematical function is use d for all three operating regimes of the MOSFET, and in most cases thes e functions have discontinuities at the border bias conditions in which th e transistor switches from the subthreshold to linear regime and from the linear to saturation regime . In the case of the subthreshold-to-linea r transition, it is a generalized practice to say that the I d curren t for Vg > Vth is completely due to drift and due to diffusion for Vg < Vth . This is the basic approximation used to derive simple electrical model s for the design of ICs . However, it is readily observed from Fig . 2 .5 tha t the diffusion process is still acting for Vg > Vth. In such a case
11 3
2 . Silicon Devices and Circuits
at Vg = V gti = 1 .2 V, in the linear regime of operation, 50% of the current is due to diffusion and 50% is due to drift . Thus, a crude assumptio n such as the one used to partition the operating regimes of the MOSFE T is no longer valid for submicron dimensions for which, due to the ver y short conduction path (the channel length), the distribution charge alon g the channel is never constant, and thus a charge gradient exists tha t helps the carriers to diffuse and drift along the channel. When an analysis or design of an IC is required to be done as a function of the temperature, the discontinuous model, even with th e smoothing functions used to smooth the transition regions, is no longer useful. Therefore, a fully physics-based and continuous model should b e developed and used for a proper analysis and design of ICs based o n submicron and nanometric CMOS technologies . Unfortunately, this is a complex task that requires solving the carrier transport equations b y numerical methods . Before taking on this complex task, one needs to fully realize that th e carrier transport in deep submicrometer MOS transistors is basically composed of two transport mechanisms : carrier diffusion and carrier drift . The driving force in the first case is the gradient of carriers, an d the electric field is the main force for the second mechanism . Thus, th e whole channel current I d of a MOSFET should be always written as . Id — (Idf
+
(2 .1 )
I dr)
where Idf is the diffusion term and Idr is the drift term of the current . How much these terms contribute to the whole current is not straight forward to determine . The evaluation of the Id current should be done based on the carrier transport equations, which are essentially th e Poisson's equation, the current continuity equations for electrons an d holes, and the current density equations for electrons and holes : div(grad klf ) = — div(Jn)
E
(p — n +
= q • R( 1F,
ND + — NA
n, p)
diva') = —q • R(`P, n, p)
In =
—q •
(,u n n • grad'F — D . . gradn) •
I p = — q • (u,, • p . grad'F
+ D p . grad p)
)
(2 .2 ) (2 .3 ) (2 .4 ) (2 .5 ) (2 .6)
where ND + and NA - are the ionized donors and ionized acceptor concentrations, respectively, n and p are the free electrons and holes, th e function R accounts for the Shockley-Read-Hall generation/recombination and impact ionization, D is the diffusion coefficient, and µ is the
114
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
FIGURE 2.6 . Schematic representation of the channel of a MOSFET . carrier mobility. The potential in the semiconductor is represented by T . These sets of nonlinear coupled equations must be solved by discretizin g the Poisson and continuity equations . The Gummel's method is preferred to discretize the current density equations because it helps stabilize the numerical process . The Poisson's equation is first discretized by Newton's method and then linearized for each decoupled iteratio n loop . This procedure helps to accelerate the convergence (26) . A detaile d description of the numerical calculation can be found in Ghazavi an d Duen Ho (27) . For the case of a MOS transistor, Eqs . (2 .2)—(2 .6) give the solution fo r the distribution of carriers, n and p, and for the potential T . These three parameters are then used in the DC state solution to evaluate th e diffusion and drift currents in the channel of the MOS transistor (Fig . 2 .6) . Thus, the whole Id current must be evaluated by integrating fro m x = xs to x = x d or using an equivalent nomenclature from 0 to L : L
‘vd
Id • dx = W
Ts
,u( — Q i )dtI' +
kT
Qid
,u,dQ i
(2.7 )
Q is
Although the two current terms are position dependent, the whol e current is independent of x ; therefore,
f
kT Qi d lu( — Qi)d + — 0Q. q Qis Ts
Wd
Id - L
Q (2 .8 )
In the source/drain-to-bulk metallurgical junctions the potentia l could have some nonmonothonical variation due to the presence of th e reverse-biased source/drain—bulk junctions; therefore, one should be
2 . Silicon Devices and Circuits
11 5
cautious when defining the physical borders for the beginning and en d of the channel. It should also be noted that the thickness of the inversion layer, in which the inversion charge Q i is evaluated, is finite, and thus th e evaluation of Eq. (2 .8) should be done as a function of the depth . On e can determine where the inversion channel ends by solving self-consistently the Schröedinger—Poisson equations . Deep submicrometer devices with ultrathin gate oxides and high bulk doping levels pose an additional problem the quantization of the inversion layer (28) that moves the maximum of the inversion layer toward the bulk and thus makes th e evaluation of the channel current I d difficult . Furthermore, as the channel length decreases below 0 .25 µm, the conventional drift-diffusion model (DD) fails to predict the electrica l performance . For dimensions below 0 .25 µm the lateral electric fields an d their gradients in the device can be of considerable magnitude, affectin g the electron energy distribution and making the electron energy t o deviate far from its value at thermal equilibrium . As a consequence, th e carrier temperature can be much higher than the lattice temperature . Thus, energy transport should also be considered when evaluatin g charge transport . The energy transport has been considered in simula tors based on the Monte Carlo method (29) . However, this method i s time-consuming and, hence, not practical to technology device designers . A more pragmatic approach is based on the hydrodynamic equation s (30) . However, the fully numerical solution to hydrodynamic equation s also requires a large computational effort, which makes this approac h unsuitable for the design of gigaintegrated systems . As the gigaintegration era approaches, a trade-off between deepsubmicrometer MOSFET modeling and simple models for VLSI/VLS I (Very Large Scale Integration/Ultra Large Scale Integration) design i s needed . To our knowledge, there have been only a few attempts to solve th e problem previously described . Ma and Kuo (31) proposed an analytical model with consideration of energy transport ; however, their results are not sufficiently accurate because the electric field in the channel is no t used in a self-consistent way with the energy, and thus loses validity and accuracy . Sim (32) noted Ma's model discrepancy and solved the energ y balance equation by considering the electric field in a self-consisten t way . This improved the accuracy of the results . However, due to the complexity of electric field dependence of the carrier mobility, Si m assumed an average value for the carrier mobility in the channel . Thi s assumption made this model lose its physics meaning . The carrie r mobility µ depends directly on the effective mass m*, and m* depend s on the energy distribution; hence, /2 cannot be decoupled from the
116
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0.0
FIGURE 2.7. Experimental results of a (W/L) = 10/0 .5 n-MOSFET operated at Vd = 0 .23 V, with T = 300, 275, . . . , 150 K .
energy balance equation . Recently, Jang and Hu (33) proposed a n analytical model for the drain current of submicrometer and dee p submicrometer MOSFETs . The model fits very well with the experimental data used in that work . However, this model is only valid for th e linear and saturation regions, and hence the subthreshold regime canno t be predicted with this model . Moreover, this model fails to predic t properly the temperature dependencies of the different operating regimes . We tried this model with experimental data for a 0 .5-pm CMO S technology in the 300–4 .2 K temperature range . First, we tested the Id —V g characteristics at low Vd and at different temperatures to search for the temperature dependence of the charge diffusion mechanism . Second, we increased the Vd voltage in order to diminish the diffusion mechanis m and enhance the drift mechanism . Because the Id current is composed o f both transport mechanisms, one expects that by sweeping the Vg voltage from low to high values, the carriers will first be moved by diffusion an d then by drift . Thus, there must be a Vg value at which both transpor t mechanisms have the same weight and the I d current becomes temperature independent . This is so because the diffusion increases with temperature, whereas the drift decreases . The experimental curves are shown in Figs . 2 .7 and 2 .8 . For both cases, Vd = 0.23 and Vd = 3 .5 V, there is a V g voltage of about 1 .0 V at which the Id current is temperatur e independent . Thus, we can say that Vg ,: 1 .0 V is the border betwee n diffusion and drift . However, note that the threshold voltage V T of this device is about 0 .6 V. This shows that diffusion is still important for
2 . Silicon Devices and Circuits
11 7
1 .5 104
1 .4
-
_ 0 .6 ô o — 0 .4 ----,
T=300 K
-- 0 . 2
4 ;, . 0
1 .0 H--, A.
= H — 0 .8 ' '"••■
60 K
0 .0 1Oo
_
2 3 Gate voltage, Vg [ V
4
- 0.0 5
FIGURE 2 .8. Experimental results of a (W/L) = 10/0 .5 n-MOSFET operated at Vd = 3 .5 V, with T = 300, 250, 200, 150, 100, 80, 60 K . The dashed lines correspond to the normalized Id current.
Vg
> VT . At Vg : 1 .0 V, the transistor is operating in the linear region ; thus, a well-defined border for the subthreshold-to-linear transitio n cannot be categorically given . Another relevant feature is that for V d = 0.23 V and Vg s larger than 1 .5 V, the Id current does not continue to increase for temperatures belo w 175 K but rolls off. For Vd = 3 .5 V the I d current for V g > 1 .5 V is alway s increasing as temperature reduces . This effect suggests that the surfac e scattering is reducing the carrier mobility at high transversal electri c fields, high V g voltages, and low Vd voltages . However, the temperature dependence of the surface scattering mechanism is not well-known, an d thus we cannot categorically affirm that surface scattering is responsibl e for the roll-off of Id . The other possible explanation for this effect is tha t the diffusion transport for low Vd s is still active for high Vg s and thu s compensates for the increase of Id due to the enhancement of carrie r mobility at low T. The carrier profile in the 0 .5-pm n-MOSFET wa s investigated through simulations with PISCES (a commercial devic e simulator) (Fig. 2 .9) . The electron concentration in the channel n (Fig. 2 .9, plot 3) is almos t independent of the position x for an uniform bulk doping (plot 2) an d has a considerable gradient (plot 4) for nonuniform bulk doping (plot 1) . The nonuniformity of the bulk doping in the channel is caused by th e proximity of the source and drain diffusions . On the other hand, as the channel length is reduced this mechanism becomes more pronounced .
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
118
z
-
•a~~~~~~~a~~~~~~~~~~~r~~~~~~~~~,■ ~~~~~~~~~~~~~,•,~. ;; ;;,,,~• :'~ :'•'~~~~ra~~~~~~~~ ~~.~ ~. ~ ~ AL L"'
~11
Cu
-
~ ,11r,„.„.„s, /~
2
b
LDD -
/1 /1
~
1 1 0
•~
1
1
1 1
0 .1
1 1
1
I
1
0 .2
0 ~
1 l
l l
l l
l
l l
l l
l l
l l
0 .3 0 .4 0 .5 position, x [pm]
l
l l
11111111
0 .6
0 .7
0 .8
FIGURE 2 .9 . PISCES simulation of a (W/L) = 10/0 .5 n-MOSFET biased at Vd = 0 .23 V, Vg =1 .0 V . Plot 1 corresponds to a nonuniform bulk doping, 2 to a uniform bulk doping, 3 to the inverted electron concentration n for uniform doping, and 4 to n for nonuniform bulk doping .
Based on the previously discussed reasons, experimental evidence , and considering that "compact models" (those used in the simulation o f integrated circuits) rely heavily on fitting parameters, the value of thes e parameters will likely be appropriate for one fabrication process bu t totally inadequate for another . We do not develop an electrical mode l but rather focus on two of the most popular models for the subthreshol d regime . The original model for the subthreshold current Idsth was based on a long-channel transistor (34) .
I
_ dsth —
(J(r)2
(Po"ç")
gESi NB
21, eff
e
q ~ vg - vT) r~kT
_
1—
e(
gVds nkT
(2 .9)
WB
where the slope factor j is taken a s ~ = 1 +
1jqcs i
2C oX
OB
(2 .10)
This model fails to reproduce experimental data of submicromete r devices since the bias-independent cofactor before the exponential ter m
2 . Silicon Devices and Circuits 2 .3
11 9 40
@L=07 p m
.2 — 0
r
t @L=0. 3 pm
2 .1 =
o
O
O
T1 @L=0 .3 p m
1 .9 =
O
..
o El
1 .8
= 30
:
.
=
25
=
20
q
~
= 15 ~ @L=0 .7 pm 1 0
O
1 .7
5 4
0
35
=
o
2.0
1 .6
--=
O
t @L=0.5 .2 pm
50
100
150
Temperature, T
vs..; 200
25 0
0
IC I
FIGURE 2 .10. Measured data for the parameters ri and i of a 0 .35-µm CMOS technology . The gate oxide thickness T o . is 10 nm, and the bulk doping level NB is 6 .8 x 10 17 cm'3 [data from Murphy (35)] .
in Eq . (2 .9) gives a value much lower than the experimental one . This i s remedied by using a multiplicative factor i that, according to experimental data, decreases with decreasing channel length and temperature , tending to a common and constant value as temperature increases (35) . The predicted temperature dependence of the slope factor (Eq . 2 .10) i s only given through the bulk potential 0B, but experimental data sho w that 17 is length dependent. This is further complicated as temperatur e varies . The temperature dependence of rj is much stronger as the channe l length is reduced (35) (Fig. 2 .10) . For the 0.7-pm n-MOSFET, zi closel y follows (Eq . 2 .10), but for the 0 .3-,um n-MOSFET the deviation from the predicted value is considerable . Transistors with intermediate length s were also studied, but for the sake of clarity their results are no t presented . The transistor with L = 0 .6 ,um follows (Eq . 2 .10), but fo r L = 0 .5 µm and L = 0 .4 pm the deviation from theory is evident . The effect observed for both 11 and t is similar when the temperature i s lowered . The factor ii is indicative of the turn-off characteristics for the transistor . The lower the value of rj, the faster the transistor switche s from on to off or vice versa . Klaasen et al (36) proposed a model that, with a proper choice of parameters and considering the threshold voltage shift due to draininduced barrier lowering (DIBL) and geometry, fits the experimenta l data very well . However, the dependence of the slope factor wit h
E . A. Gutiérrez-D ., C . Claeys, and E . Simoen
120
channel length is not included nor mentioned in their model : I
dst
=
Weff
I
1°
L eff eff
e[q/MkT(Vg – VT)][ 1 –e(-q/kT(Vd) ]
(2 .11 )
where the slope factor M is given by
M=1+
m 1/2 (/)B
+
(2.12) Vs B
where VsB is the source-to-bulk voltage, and 1 0 and m are fittin g parameters . For the simulation of ICs using SPICE, a popular model is BSIM (37) , which is a semiempirical model also based on fitting parameters . This model reads Idst
(kT)2
e 1 .8 ,e[ q/nk T (Vg – VT)] [ 1 – e(- q
ß
q
/nk T(Vds) ]
(2 .13 )
The slope factor n is assumed to be Vd S dependent, which is correc t based on the device physics, but it does not take its temperatur e dependence into account : n = (no + nBVSB + nDVds)
(2 .14)
where no, n B , and n D are fitting parameters . Both models for the subthreshold current analyzed previously can b e used to fit experimental results, but only if Io , m, and n are adjusted a s a function of temperature . Even with the temperature adjustment, thes e parameters have different values for different technologies . This i s shown in Fig . 2 .11, in which the subthreshold slope S is plotted as a function of T for the 0 .5- and 0 .7-,um CMOS technologies :
S=
dVg d lo g(Idst )
(2 .15 )
The Klaasen and BSIM models can be used to predict the behavior of S as a function of temperature, but only if the fitting parameters Io, m, and n are modified for every temperature . The fitting for temperatures below 150 K loses accuracy . The accuracy can be improved for one of thes e technologies, but it becomes worse for the other . This indicates tha t neither of these two models is universal . 2 .2.3 . The Linear Regim e This region of operation derives its name from the linear Id —Vd characteristics as shown in Fig . 2 .12 . An imaginary line (the dotted line in Fig .
2 . Silicon Devices and Circuits
121
r—,
•• •
.b
u
100
_
r r r r
90 80
• o •
-~ ^,
•
~
60
r
r,
l
r,
r r
1,
r,
r
r
r
r
r
l„
r
r
r
r
r
r
q L=0 .7 pm
-
~
-
- model
H H_
_
50
-
•
_
40 LO00000°000
. .c 30
c%
J
O L=0 .5 p m
70 . .~
I,
20
• 0
q oq ~YT„ ' 50
II
^
o
11
i
I
100
1
,
1
r
150
200
Temperature, T I K I
,
,
250
I
, -
300
35 0
FIGURE 2.11. Measured (symbols) subthreshold slope S for the 0 .5-µm and 0 .7-µm CMOS technologies, biased at V d = 0 .23 V, and calculated values usin g Eq . (2 .9) .
2 .12) borders the linear regime and the saturation regime . However, fo r very short transistors the current in the linear regime does not follow a linear behavior. The derivative of the Id —Vd characteristics is shown i n Fig . 2 .13, from which can be seen that the derivative Ai d / A Vd (i .e., the conductance) is not constant but is always decreasing with V d . O n
1 .0 104 V =4 V g
linear regime
V =3V g
-
V =2V bR
~-'
V=1V s
0 .0 1(~
1
1
0 .0
0 .5
1
1 , 1 .0
1
1
1 .5
1 „ 2 .0
1
1
1
2 .5
1
1
1
1
3 .0
1
1
-
l
3.5
Drain voltage, V o IV ]
FIGURE 2.12 . Measured Id —Vd characteristics of a (W/L) = 10/0 .5 n-MOSFE T operated at T = 300 K.
E . A . Gutiérrez-D ., C. Claeys, and E . Simoe n
122 150 .00
_
>
d 100.00 0
__
U
r...+
U
_ __
2V
^ _
=
50.00 --
O
V
_
3V
-
0.00
0 .0
-
g
0 .5
1 .0
. . ... 1 .5 2 .0 2 .5 Drain voltage, Vd (V ]
3 .0
3 .5
FIGURE 2.13 . Measured conductance G(AId /AVd) of the n-MOSFET of Fig. 2 .12.
the other hand, the border between the linear and saturation region s vanishes so that it is unclear where the saturation begins . The nonlinearity is due to the charge sharing effect (38) . As the channel is shrunk, a larger proportion of bulk (or substrate) charge is controlled by the drain and source and less by the gate ; hence, the surface inverts more readily. For device modeling purposes this effect can be taken into account by introducing the "charge sharing factor, " FOE , which indicates the proportion of substrate charge controlled by th e gate . This factor is evaluated from the body effect constant y
Y =
.\/2ESi qNB
(2 .16 )
Co x
that is extracted from calculated values of the threshold voltage fo r different bulk voltages . The average bulk concentration of a long-channel transistor is taken as indicative of the "real" average bulk doping . Measurements on shorter transistors produce a smaller value for y an d thus a smaller bulk concentration. FOE is the ratio of the average bul k concentration of any transistor to the one obtained from the longes t channel transistor. The extracted Fa factor for n- and p-MOSFETs is shown in Fig . 2 .14 . The Fa factor plotted in Fig . 2 .14 was extracted by taking a 20-,u m MOSFET as a long-channel reference, but the bulk concentration fo r these transistors was not very different from that of the ones wit h L = 2 µm. It is clear that n-MOSFETs are more affected by the charge
2. Silicon Devices and Circuits .E
1 .2
►
b
123 (
I
~
O p-channe l 1 .0 — _
ô
~
q n-channel e,
0 .8
~
ii
-
0 .6
~
I~
V
_
FA ~ a~
to Û
0.4 u
0 .2 0 .0
0 .5
I .O
2.0
1 .5
Channel length, L pm (
FIGURE 2.14. Extracted charge sharing factor Fcs evaluated from experimenta l curves of transistors of both channel types . sharing effect than are p-MOSFETs. Because the Fcs factor is only a multiplicative factor that adjusts the model to extract the threshol d voltage, its temperature dependence depends on the model used . Thus, the models by Klaassen et al ., and to a certain point the one used b y BSIM are based on the charge sharing effect . In the first case, the surfac e mobility is considered to be degraded by both the transversal and th e longitudinal fields and by an interaction of the square of the fields . Thus, the effective mobility is given b y lu eff -
1+
8 A (Vgs
_ VTKL)
+ OBVsb + eCVds +
9D (
V
gs — 2Vds)
2
(2 .17)
with 9 C
1
(2 .18)
Leff Ec
where Ec is the "critical field" value for velocity saturation, which i n practice is taken as a fitting parameter, which makes 9c also practically a fitting parameter . The model for the drain current in the linear regime i s then Id =
(V
1
gs
VTKL )
+ O A (Vgs — VTKL)
Vds
+ 9 BVsb
2 (1
+(S ) V ds2
+ 9C Vds + 9D
(vgs- 1/2vds)2
(2 .19 )
In this model, the threshold voltage is given b y VTKL — VTS — S(L eff) Vds 1/Os
+ Vsb
(2 .20)
E . A . Guti érrez -D ., C . Claeys, and E. Simoe n
124
The DIBL effect (discussed later) is modeled through the function s ( L eff ), and VT S is the zeroth-order threshold voltage measured at the source an d given by VTS — VTO
+
Yi [N/Os
(2 .21 )
+ Vsb — .\/Os ]
where y i is the body effect constant defined as its value for a longchannel device, y i °°, and as the change in its value as the channel lengt h and width are reduced, AyiL and DYiW , Yi = Yi
—
(2 .22)
DYiL+OYiW
For Vsb = 0 V, the model for the threshold voltage reduces to VTKL — VTO
[S(L eff)
A]Vds
(2 .23)
In the BSIMs model, mobility does not include a field-squared term bu t only degradation due to the transversal field and velocity saturation du e to the longitudinal field (2 .24)
U1
[1 + U0 (V— VTBS) ~ 1 + gs
V
Leff eff
where the threshold voltage VTBS is defined as VTBS —
VFB
K1 .3 (t)S +Vsb — K2(OS
+ +
+
Vsb) nVTVds
(2.25 )
The DIBL parameter rI VT is also a function of the transistor potential s 11VT — 11z
+
?1BV sb
+ 11D( Vds
(2 .26 )
Vdd)
K 1 is equal to the body effect constant y, and K2 accounts for the dual y factor . The dependence of current on back gate bias, which in Klaassen' s model is accounted for by the term O B Vsb , is taken into account in the fitting parameters U O and U 1 : (2 .27)
U0 = U0Z + UOB Vsb U 1 = U1Z + U1 BVsb + U 1D (Vds
(2 .28 )
Vdd)
where all the U's are constants as fitting parameters . Using all the previous definitions, the drain current for the linea r region used in BSIM is a I Ids
=
Weff ( PeffC"
Lff
(Vgs
VTBS) Vds
[1 +U V—V TBS) ~ 1+ 0 ( gs
Vds 2
(Ui (Leff/
`
( 2 .29
Vds
)
2 . Silicon Devices and Circuits The body effect coefficient value is calculated from
12 5
"a" has the same physical origin as 6, but its a=1+
gK
2 .\/4) S
i
(2 .30 )
+ Vsb
where 1 g= 1
1 .744 + 0 .8364 (O ~~ss
Vsb)
(2 .31 )
Both the Klaassen and BSIM models are able to reproduce experimenta l results at room temperature within an overall rms error of under 2% fo r 0 .7-, 0 .5-, and 0 .35-,um CMOS technologies. In the case of a 0 .5-µm CMO S technology, the values of the parameters used in the model is listed i n Table 2 .1 . The values of the parameters used for the simulations were extracte d using an optimization program called EXPER (39), which is able to fit a model of more than 25 parameters . However, when using optimizatio n programs one has to be very careful with the extracted values . Due to the nature of these programs, which only fit experimental data t o supplied database files, the results can be completely out of any physic s logic. Therefore, a background on device physics is a prerequisite t o better use and take advantage of these programs . The optimization program can also be used to extract the values for the parameters a t different temperatures . However, the results are not physics base d because they are mere fitting parameters. Table 2 .1 Values of the Parameters Used to Simulate a (20/0 .6) n-MOSFET in the Linear Region Klaasen's model VTO
= 0.7145 V
s ( L eff )
~s
= 9 .989 x 10 -2
µo = 385 .12 cm 2 / Vs
BSIM model VTO
= 0 .72273 V
rlvT
= 2 .9332 x 10 - 2
µo = 484 .16 cm 2 / Vs
LD
= 0.12065 µm
LD
eA
= 0 .31105 V -1
U0 = 0 .31699 V - 1
Oc
= 0.3312V -1
U 1 = 6.4316 x 10 -2 V -1
eD
=1 .9895 x 10 -2 V — 2
NB =2 .00 x 10 1 7 cm -3
= 0 .0385 µ m
NB =2.00 x 10 17 cm - 3
126
E . A . Gutiérrez-D ., C. Claeys, and E . Simoen 0 .8
... um -
►_,
0 .8 _ a.; • ra'
_
i
expected theoretica l result
`
hard
I freeze-out
I
o9
o
2
g.
8
• O
. _
10
III~II1IJII
0 .7
ô
E-H
I
soft freeze-out
o
^O , O * .0 0 Sk I O 0.6 1 • ~ 0 50 100
7 IA)
5
>
O
experimental V .1 . 1
I
I I 150
I
I
4
1
I
y
3 300
I I~
200
Temperature, T [K J
250
FIGURE 2 .15. Measured threshold voltage V T as a function of temperature T for a (W/L) = 10/0 .5 n-MOSFET operated at Vds = 0 .23 V. The Id current a t Vg = VT is plotted in the right axis .
One of the more important electrical parameters for the IC designer s and device physicists is the threshold voltage, V T , which is commonly extracted by fitting a straight line to the point of maximum transconductance gmmax in the Id —V g curve and taking its extrapolation to the V g axis as VT . Following this extraction procedure, the V T voltage as a function of temperature T for a (W/ L) = 10/0 .5 n-MOSFET is plotted as shown in Fig. 2.15 . For the sake of completeness, the I d current and transconductance g m as a function of temperature are plotted in Fig . 2 .16 .
450 =-•
, "T7
400
~.i
40
II
0
~
e ~~ i I'
o
_
k-1 o
35 A)
30 3 crc
>), V
0
50
100
150 200 250 Temperature, T ( K [
300
35 0
FIGURE 2 .16 . Measured Id current and max transconductance gmmax as a function of temperature for V g at which g m reaches its maximum value .
2. Silicon Devices and Circuits
12 7
Note that the behavior of the threshold voltage V T at temperatures below 100 K deviates from the theoretical predicted behavior . This can be attributed to freeze-out effects or to the combination of DD mechanisms that first increase the current as temperature is lowered and the n diffusion takes over to reduce the current for temperatures below 100 K . Examining the Id current at Vg = VT , one observes that the magnitude o f the current is always decreasing as temperature is lowered, which is a clear indication that at Vg = VT most of the current is due to diffusion . The effect is more clearly seen in Fig. 2 .16, in which the Id current and maximum transconductance gmmax are plotted as a function of temperature. At this bias condition, both diffusion and drift interplay to give the bell shape to the Id —T curve . 2 .2 .4 . The Saturation Regime In general, the voltage at which the transistor enters into the saturation regime, Vdsat is defined as the Vds value at which the inversion laye r charge at the drain side is zero . As previously discussed, the linear-tosaturation border vanishes as the channel becomes shorter . This make s it more difficult to find the value for Vdsat . Thus, to improve a drai n current model, Vdsat needs to be calculated properly . The two models described here have different definitions for this voltage . Klaassen et al . model the current in saturation a s Idsat
VT ) Vdsat( 1+ b) ,1 a ln e+ e + 1 + c E Vgs
[(Vus
= f~
Vdsa t
Vds
(2 .32)
p
The term in the second brackets accounts for the channel conductance i n saturation and is modeled by a Vds -dependent effective channel length : Leff '
= Leff L
1 + a In 1 +
_ Vds
Vdsa t
- 1
(2 .33)
aVP
where Vp and a are fitting parameters. The Vdsat voltage is obtained fro m equating Eqs . (2 .19) and (2 .32) for Vds = Vdsat, which gives a cubi c equation in Vdsat ,
Vdsat 3 + 2 eß —2 8D
+4
8D
[1 +0AVgs
Vgs -4V gs— +OBVsb )
8
4
VT (1 + b)
Vdsa t2
Vgs VT °EVgs VT + 1 + (S + 9.(I + 6 +
((1 +6AVTOBVsb) 8D
VT
(1 + 6)
+ Vgs 2
=0
2 Vgs
Vdsat
(2 .34)
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen
128
which has three roots . The roots or solutions to this cubic equation ar e gate voltage dependent (35) which means that only one of the roots wil l be purely real for the complete voltage range . When the root is obtaine d from the maximum of Eq . (2 .19), the Vdsat value is always smaller tha n the one predicted by Eq. (2 .34) . This implies that the current will be smaller than that in the linear region, and the conductance will b e negative in this transition region, which is not reasonable on physica l grounds . Another inconvenience of the analytical solution of Vdsat is the many conditional clauses needed to discern the real root from th e complex roots and to evaluate cubic roots, which makes it more computer intensive. In the BSIM model, the current in the saturation regime is given b y (Vgs — VT) 2 Idsat —
ß 2aKI1 + U V 0 ( gs
—
VT) ]
(2 .35)
where K is calculated from K = (1 +V+ .\/1 + 21/c ) 2
(2 .36)
and Vc is determined from the value of the fitting parameter U 1 :
=
(Vg .
U1 L eff
VT
a
(2 .37 )
In this model the saturation voltage is defined as the point where the I d current is limited by velocity saturation, and it is given b y = Vdsat
( Vgs
VT)
a /K
(2 .38 )
Channel length modulation is not taken into account directly, but th e experimental curves are well modeled in this region through the DIB L parameter. There is an experimental method to extract Vdsat . The method proposed by Jang et al . (40), based on general device theory, is virtuall y independent of any device model and quite versatile and applicable fo r small-geometry MOS transistors . This method is based in the construction of the function G : U(1/gds) G=gds
ôVds
(2 .39)
2 . Silicon Devices and Circuits
7 <
-
G@V
•
~,
1~
=I V
g
ô 10 -3 -
N--4, +s 6 10 -3 ~
r
129
- 8 V ~is
\
–
G@V
=2 V
~
_ 4 _ -
G~~ V =4 V~ 2 r
_
o
n. i
~,
'
'
w~l -~~.. . ....■~■i~■11111BRW —
0 .0
~
G(~~V „ =3V r
_
0 10°
6
-
` 4 10 -3 –
2 Io-'
.t(
~
0 .5
1 .0
=
~..-~Jw~` _ 1 .5 2 .0 2 .5
Drain voltage, V IV [
r 3 .0
- 0 3 .5
FIGURE 2.17. Experimental Id– V ds characteristics and function G of a 0 .5-µm n-MOSFET at 300 K . The open circles correspond to the extracted Vdsat values , and the dashed line is the fitted Vdsat .
where
gds
is the drain-to-source conductance defined b y gds
s
aid s
Vd s
(2.40)
The function G is an increasing function of the V ds voltage when the MOS transistor operates in the linear region, whereas it decreases wit h Vds when the transistor enters into the saturation region . Therefore, the Vds voltage at which the slope of the function G is zero should be equa l to the Vdsat voltage . An example of this method is shown in Fig . 2 .17 . The function G peaks at different Vds values for different Vg values, with each peak corresponding to a Vdsat voltage for a particular Vg voltage . The extracted Vdsat values (Fig . 2 .17, open circles) and the superimposed Vdsa t curve are also shown . This method is also used to extract Vdsat as a function of temperature . (Fig. 2 .18) . Note that the experimental Vdsat deviates from the one theoretically expected (continuous line) . The experimental Vdsat corresponds to the difference between the theoretical Vdsat and the VTd voltage . The VTd voltage is known as the drain threshold voltage (41) , which is due to the combination of freeze-out effects in the gate-tosource/drain overlapping regions . The freeze-out of the overlapping region makes a potential barrier appear at the gate edges, which in turn s becomes gate voltage-dependent series resistant, and makes the I d — Vds characteristics deviate from a linear behavior (Fig . 2 .19) . The Id —Vds
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
130 0.85 s-
_ 70
..
~.. .
0 .80
o
0 .75
.
-
o
o experimental o Vdsat
0 .70
e == ..~~ =.
A
_ .•i-:/'
~
0 .60
0
„►,I
,
.
V
/
a
O
= 40 Â. ~ o 30 ~-
~
=
`is`'t
theoretical ~
250
:1)
=- 20
°~
=-
a
10
~.to„b,oÔO
200 100 I50 Temperature, T [ K l
50
►~
50
=
o
0 .65
0 .55
60
rd
300
FIGURE 2.18. Extracted Vdsat as a function of temperature T of a 0 .5-µm n-MOSFET biased at Vg = 2 V. The open circles are the measured drain threshol d voltage VTD , and the continuous line is the theoretical Vdsat . curve does not increase linearly from 0 V, but it has a quasi-exponentia l behavior, until Vds reaches VTd , from which a linear behavior can be extrapolated . In the saturation regime the Id current is almost fully dominated b y drift; hence, the Id current and the conductance gds (aId / WVds ) should increase as temperature is lowered . Their experimental behavior i s shown in Fig . 2 .20 . Both Id and conductance g ds have a step increase at T = 30 K, which corresponds to the onset of strong freeze-out and th e occurrence of the kink effect (42) .
_
i
, linear fit
4 ►••-1
_
2
•~
'
3 _
(u
1
1
>
r
__- . - . . = -
-
,~
experimental I d
_ _
0 .0
_
__ : % '
_
V
0.2
0 .4
0 .6
0 .8
1 .0
Drain voltage, Vds [ V ]
FIGURE 2.19 . Measured I d –Vds characteristics of a 0 .5-µm n-MOSFET operate d at V g = 2 V and T = 4.2 K. The linear fit (continuous line) is extrapolated to th e Vds axis to get the VTd value .
2 . Silicon Devices and Circuits
~ M--~b a)
C -.
9 .5~..~ 9 .0
13 1
I I,1I
OA
_ 2 .510-4
8.5 e. ._`_
8 .0 7 .5
,
e....e
7 .0
.
6 .5 6 .0 5 .5
t
0
1
3 .010 — 4
„
1
1
1
1
!
50
~
1
l
100
l
1
~
1
_
t I I
150
2 .0 10-4
_ I .5 104 _
—>-
I
1
200
I 1
~ -
~
1
1
I
250
1 .0 10 - 4
o
a ~ (Al
,
5 .0 10- 5 30 0
ly
Temperature, T 1K ]
FIGURE 2.20. Measured I d current and conductance g ds of a 0 .5-µm n-MOSFE T biased at Vds = Vgs = 3 .0 V .
The two models described here are a consequence of multiple approximations and simplifications . First, it is assumed that the channel is everywhere strongly inverted, but this condition is not necessarily me t near the drain side as Vds increases since the charge sheet approximatio n breaks down . Second the model considers that current goes to zero a s the gate voltage approaches the threshold voltage from above, and it ca n even be negative for large values above threshold if Vds is large, which is not the case owing to the subthreshold current . Thus, the three region s of operation analyzed here have to be merged together so that curren t and its derivatives with respect to terminal voltages, which represen t conductance and transconductance, is continuous when going fro m region to region. Due to the complexity of using two-dimensional (43) and numerica l solutions (44, 45) to satisfy continuity between regions of operation , limiting functions are used to force the subthreshold current to remain constant above a determined value of the V g voltage . This constan t component is then added to the strong inversion current, in both th e linear and the saturation regions . In Klaassen's model, the subthreshold current is modified to I Idst =
(
Weff)e[ g/MkT(Vgs — VT)][1
— e(4/kT(vs) ]
Leff
1
+z
Weff e q/MkT(Vgs — VT )
(2 .41 )
L ef f
Here, z is another fitting parameter with a value of approximately 0 .5 . This expression predicts that as Vgs increases above the threshold
132
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
voltage, the Idst current tends to _2 [1 — e- ( q/k T (V ds )dst ]
I
z
(2 .42)
whereas for low values of Vgs, Idst tends to the value given by Eq . (2 .11) . This model works well for low values of V ds ; however, since th e current always saturates to this value, for large values of V ds the curves cannot be merged with the ones predicted by Eq . (2 .19) and thus current is modeled as discontinuous in this transition region . In addition, whe n modeling Idst as in Eq . (2 .41), the value of the limiting current also affect s the characteristics for low Vgs values . In the BSIM model, the expression for the subthreshold current Idst is modified to I dst
_ Idst • Ilim I m Idst + u
(2 .43)
where the limiting current Ilim is given b y
Ilim = 21 ß 3
kT
2
(2 .44)
q
For large values of Vgs , the Idst current tends to Ilim, whereas for lo w values Idst tends to Eq. (2 .13) . The transition region is well accounted fo r by this model, with only a slight discontinuity . For the linear-to-saturation transition the Klaassen's model present s a discontinuity when passing from the linear to the saturation regions i n general due to the way in which the Vdsat voltage is defined . In order to avoid this discontinuity, it is suggested that the Vdsat voltage be taken a t the value of the maximum current predicted by Eq. (2.19) : Vdsat = — 6(1
6)2
+ b) + .\/ 6[6(1 + [(1 +
+ 2(1
5)(0 c —
+ ô)(Vgs — VT)(0c — e D Vgs )
+ 6D (Vgs — VT) 2 ]
eD V gs ) + 2OD( Vgs — VT)]
(2 .45 ) where, for the sake of simplicity, 6 is defined a s 6 = 1 + O A (Vgs
VT)
+
OB Vsb + ODVgs2
(2 .46 )
With this definition of Vdsat, the accuracy of the transition regio n improves . However, the channel conductance g ds is affected by this definition since it assumes that when Vds = Vdsat, gds = 0, which is not true at all . The conductance predicted by BSIM also falls to zero mor e rapidly than it does in the experimental case, and the designer has t o keep this fact in mind since, especially in the design of analog ICs ,
2. Silicon Devices and Circuits
133
channel conductance is an important design parameter, which ideally i s equal to zero but never is in reality .
2.2 .5 . Series Resistance, Effective Gate Length, and Effectiv e Gate Width Series resistance has been widely discussed in the past decade as a resul t of the miniaturization of devices and the introduction of the LDD structure . In the past, the series resistance of MOS transistors had bee n considered as a constant value that added externally in series to the MO S transistor. This series resistance was essentially taken as the serie s connection of the contact resistance R se , the diffusion resistance between the contact and the gate edge RSd , and the crowding R sr resistance at gate edge as shown in Fig. 2 .21 . The current flow deflection under the contact is accounted for by th e contact resistance Rsc . The crowding resistance R sr also accounts for the resistance under the gate, where the current flow is pulled up the surfac e and continues toward the channel . Based on the assumption of constan t series resistance, several measurement methods have been proposed . A typical approach is that proposed by Chern et al . (45), in which the total measured resistance Rm of a MOSFET is taken as
Rm
=
(s) Ids
=
Rext +
(2 .47 )
Rchan
or R
m = Rext —
[ IUCox Weff
( Vgs
VT
lVds)] '
( L mask —
AL)
(2 .48 )
FIGURE 2 .21 . Schematic representation of the current flow between the contact to the source /drain and the gate edge of a MOSFET . The components of th e series resistance are also shown .
134
E . A . Gutiérrez-D ., C . Claeys, and E. Simoen 400
G
350
L.-
~
300
L
~
250 ~
..
200
-
150 2_ cu a~
V =2 V ~~
• R=70 S2
100 = 50 0 0.0
Vg =4 V
~ AL=0 .065 N m
0 .2
0 .4
0 .6
0 .8
1.0
Channel length on mask, Lmask [µm ] FIGURE 2 .22. Measured resistance R m versus channel length Lmask for a 0 .5-µm CMOS technology . n-MOS transistors with different channel lengths were measured at Vds = 0 .23 V at different V g voltages at 300 K .
where the transistor is considered to work in the linear region , Weff = ( Wmask — A W) is the effective gate width, and L eff = ( Lmask — 2AL) is the effective gate length . Plotting measured values of R m as a functio n of channel length Lmask, with constant V ds , and various values of V gs , gives a family of straight lines that cross each other at a common point that gives AL and Rext (or R s ) . As shown in Fig . 2 .22, extrapolated lines of experimental data, with different V g voltages, intersect each other a t the same point, from which AL is derived to be 0 .065 µm and the series resistance R s is 701 . This model of extraction assumes a constant valu e for R s and AL, independent of the bias condition . In this case, AL is defined as the portion of the MOSFET channel no t contributing to its electrical performance; this is the gate-to-source/drai n overlapping region . This model assumes a lightly gate voltage-dependent series resistance and that the channel conductance is independent o f the channel length, which has been shown not to be true in severa l published works. Among these, there are reported extraction procedure s based on the measured I—V characteristics (47—49), the measured capacitance—voltage (C—V) characteristics (50—52), charge-pumpin g techniques (53, 54), and combined measured /simulated characteristic s (55, 56) .
With the I— V method, as shown previously, the total resistanc e versus channel length, using an array of transistors, is measured at different gate voltages . Some of these methods extract Rs and AL usin g
2 . Silicon Devices and Circuits
135
constant values for the gate overdrive voltage defined as (V gs — VT ) . I n this way, the channel length dependence of V T is accounted for . Despite this modification, the Rm-Lmask lines for submicrometer MOSFETs do no t intersect at one point, making it difficult to determine AL and R s . In fact, AL can be negative, indicating that the effective channel length is longe r than the Lmask length . There are two reasons for the negative AL . First, i n submicrometer MOSFETs the fringing field lines at the gate edges exten d outside the gate, giving the impression that the gate is longer than it s mask length Lmask . The second reason is that it is assumed that either Rs or AL is independent of gate bias . C . Y. Hwang et al. (49) pointed ou t that Rs and AL should decrease as Vgs increases since a greater portion of the channel region can be modulated by the higher Vgs voltage . A t lower temperatures, the vertical electric field increases, which give s greater control over the modulated charge, leading to a stronger dependence of R s and AL on Vgs . Methods based on the measurement of the C-V characteristics were introduced to remove the effects of the series resistance on AL . The effective channel length Leff is extracted from the C-V measurements with the source and drain connected to an AC signal, the gate connecte d to a DC bias, and the body grounded . However, large MOS devices ar e needed in order to obtain measurable values for the capacitance . On th e other hand, the contribution of the source/drain-to-bulk capacitance s needs to be carefully decoupled . After the AL value has been extracted , the R s value is extracted using conventional I-V methods . The C-V methods also present inconsistencies as shown in Table 2 .2 (52), in which simulations are compared to measured results .
Table 2 .2 Effective Channel Lengths of a 0 .75-µm MOSFE T Extracted Using Various Methods (52 ) Method
Leff (um )
Defined Leff in simulations
0 .25
I-V [Chern et al. (46)]
0 .5 1
C-V by Sheu and Ko (58)
0 .20
C-V by Lee (50)
0 .1 3
C-V by Latif et al . (52)
0 .29
Simulations by Narayanan et al . (59)
0.5 1
I-V [Taur et al . (48)]
0.51
136
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen
Simulations performed by Latif et al . (52) and Narayanan et al . (59) with a defined L mask = 0 .75 pm and AL = 0 .25 µm coincide quite wel l with results of two of the C—V methods . However, these methods stil l fail to predict the gate voltage dependence of the effective channe l length . Most of the discrepancies of the I— V and C — V methods appear whe n sub-0 .5-µm devices require to be characterized . Submicrometer an d deep-submicrometer devices have additional complexities, such as a nonuniform substrate doping profile and large fringing capacitances . These problems can be handled by using the charge-pumping techniqu e (60), which consists of measuring the charge-pumping current of a set o f MOSFETs with different channel lengths . Plotting the charge-pumping current I, p versus the channel length (mask length) Lmask, the intercept of L, with the Lmask axis, gives AL. Accuracies to 0 .01 pm can be achieve d if the device doping profile is known . An improved technique, based o n charge pumping in a single device (53), has shown to give 0 .01- to 0 .02-,um accuracy . Extraction methods that combine measurements with simulation s also show good accuracy but require knowledge of the processing conditions and use of coupled process /device simulators . Extraction of the series resistance and gate-source/drain overlapping length AL, using the classical I—V methods, is shown in Fig . 2 .23 (61) . AL becomes negative for temperatures below 175 K, indicating a n overextension of the effective gate length, and the resistance R s shows a n
1 40
0 .2 0 .1
®'■' \ ,
bA
• � ~ U
-0. 1
4_, •
-
ra, cti
v
ô
13 0
~
'
0 .0 ~-
• o
•
.
D ~
--
-0 .4
G~
0
,
o
<
o
0
►\
~~ ~
—
11 0
_
100
—= 90 =
.
► 100
150
o V
* 00 50
120
-
~i
_
0.2 — -_ 0.3
—
~
200
.. ,
r
80
7d
r—, u
- 70 250
300
Temperature, T [K] FIGURE 2 .23 . Extracted Rs and AL as a function of temperature for a 0 .5-µm CMOS technology biased at V ds = 0 .1 V and Vgs = 2 .5 V .
2 . Silicon Devices and Circuits
13 7
increase . These effects have been attributed to freeze-out and the so called drain threshold voltage (61) . Physically, there is no way th e effective or electrical channel length is larger than the layout define d Lmask . As previously explained, the drain threshold voltage is a result o f the appearance of a potential barrier at the gate edges . This potentia l barrier has an impedance-like behavior, which emulates an additiona l series resistance and makes the Leff appear larger than L mask The effective width Weff of a MOSFET differs from the mask width Wmask due to systematic or random errors in the fabrication process, such as oxide encroachment, variations in linewidth, and photolithographi c undercut . One of these fabrication processes is the so-called loca l oxidation of silicon (LOCOS) process, which results in the bird's beak effect and a gate voltage-dependent width (62, 63) . In this case, the fringing fields invert the substrate in the vicinity of the channel as th e gate voltage increases, thus giving a wider effective width . The variation in effective channel width with gate voltage can be explained using a variable threshold voltage . The oxide thickness changes from that of th e gate thickness to that of the field oxide thickness, and the substrat e concentration varies from the channel value to the channel stop value , and therefore the threshold voltage increases from the edge of th e channel outward . As the gate voltage is increased, a larger portion of th e substrate becomes inverted, increasing the width of the transistor . The effect will be more pronounced for narrower channels since a large r fraction of the width will be affected . In this case, it must be considere d that the average value of the gate oxide will be larger than expected . The dependence of the effective channel width with voltage i s considered in the model presented by Deen and Zuo (63) in which th e two parallel conductances are considered to account for the edge effects, and whose value depends on gate voltage :
I= DS
RS µo C° VGTWeff (VDS — IDS + 2Gp VDS (2 .49 ) 9AVGT) Weff X
L (+ Leff
Ashton et al . (64) present a method to characterize the effective widt h as a function of gate voltage . The method is based on nonlinea r optimization using a model valid only in the strong inversion region fo r low values of Vas • Weff is defined as Weff = Wmask + 0 W0 + G W (Vgs — VT )
(2 .50 )
where A Wo is the difference between the mask and the effective widt h at threshold . The threshold voltage is modeled a s
v
T
=VTO —
ôVT ÔV
bs
ID Rs
(2.51)
138
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
where the current is the n IL OC ox Weff
V — VDS ) Is= DL (1 + A 8 GT V ) ( GT 2 DS ( mask -- AL)
DS
(2 .52 )
The limitations of these models occur because effective channel lengt h and series resistance is considered independent of gate voltage . Further more, as the surface potential varies with position, the effective channe l width also varies along the channel, and the value for Weff used in these expressions is thus an spatial average .
2 .2 .6. The Gate-to-Source/Drain Capacitance s The gate-to-source and gate-to-drain capacitances, Cgs and Co, are essentially the gate-to-source and gate-to-drain overlapping capacitances . The absolute value of these capacitances depends on the overlapping are a and gate oxide thickness Tox . However, from the previous discussion o n the effective channel length and width, the dimensions (width an d length) of this region change with bias, thus making the definition of thi s capacitance component also bias dependent and in general smaller tha n the one calculated from the metallurgical dimensions . A model for the overlapping capacitances, however, considers it to be larger than tha t calculated from the metallurgical dimensions (Lmet or Wmet) for eithe r source or drain (65) : Co ,, = Cox [(L mask — L met) + ] Weff
(2 .53)
The correction factor, , accounts for portions of the edges of th e transistor that are not considered even when the other components o f capacitance are calculated, and it is given by
rl — cos a L sin a l
= Tox
2
i + 1 —cos ; sin a 2
(2 .54)
where ; is the angle at which the gate wall forms with the normal, an d a2 is given by a2
= —1 7r
£ox
(2 .55)
E si
Another possible component of the gate capacitance is that associate d with the inner fringing field C if from the gate to the sidewall of th e source and drain diffusions on the channel side . This component is only present during depletion. When the transistor is in the accumulation o r inversion operating regimes, the electric field lines terminate at th e
2 . Silicon Devices and Circuits
13 9
charge in the surface, and this capacitance component is therefor e screened . An expression for this capacitance, but which does not includ e the bias dependence, is also given by Shrivastava and Fitzpatrick (65) : C if =
2e . X(ne w, s In 1 + ' sin n Tox 2ESi
Weft- =
.
s' In 1 + 0 .492
~
X. ' Weft. (2 .56 ) To x
The outer fringing capacitance Cof is due to the field lines originating on the gate and terminating on the outside portions of the source and drain diffusions through the oxide spacer . This model assumes no bias dependence, which in view of the previous discussion is questionable . Thi s capacitance can be calculated by the following expression (65) : e Cof = E°x in 1+ Tgat al lox
Wef f
(2.57 )
where Tgate is the thickness of the gate electrode. Another approach for this capacitance (66) divides it into three parallel capacitances obtained from a solution to Laplace's equation . These correspond to the field lines originating from the top of the gate, C t op, from the sidewall of the gate to the source/drain diffusions, Csw , and from the bottom of the gate to the source/drain diffusions, outside of the overlap region, Cbo . These components are obtained assuming tha t the sidewall normal is parallel to the substrate, whereas in the previou s approach the sidewall can form any angle with the substrate's normal . These components are modeled by the following equations : CtO p
= £°X
{2 — ln(4) — ln[1 — 2e - 26] } [2( Weff + Lmask)] C sw
Cbo
=
=
cox
~
ln(a)[2(Weff + L mask) ]
Eox In u ~ a
[2( Weff + Lmask)]
(2 .58)
(2 .59 )
(2 .60 )
In these expressions, mas k 8 = 1 + 7rL 2Tox
a=
2K.3K 2 — 1 + 2K2 — 1 e K = 1 + Tgat Tox
(2 .61) (2 .62 )
140
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
and u is the solution t o n Lmask 2 ToX
a—1
R+1 R ln I + Z (R — 1) 1-c-i R—1)
a+1 R+ 1 2 ln .63) ~R — ) (2 ~
with R=
/(u
-1 )
(2 .64)
(u — a )
The outer fringing capacitance is gate length dependent, as experiments and 2D simulations have shown (67) . However, Wang (67) attributed th e gate length dependence to only the capacitance originating on the top o f the gate C top , and when the drain (or source) is left floating it is calculated from Ctop
= EoxWmask ln 1 +
Lmas k Tgate + o x
(2 .65)
whereas if the source and drain are tied together, it is given by C top = 2Eox Wmask In 1 +
0 . 5L mask Tgate gate
(2 .66)
+ ox
So far, we have seen that the total gate parasitic capacitance is given b y the addition of the three parallel components and will be differen t depending on which definition is used to calculate it . The approach of Shrivastava and Fitzpatrick (65) is independent of gate length, whic h intuitively makes it wrong, but it also provides the only definition fo r the inner fringing capacitance . The temperature dependence of these capacitances is not straightforward . However, Gutiérrez-D . et al . (68) show that the capacitance of a MOS system in depletion, inversion, and accumulation is slightly temperature dependent (Fig . 2.24) . The capacitances shown in Fig . 2 .24 were measured at V = — 4 V fo r inversion (Cinv ), 0 V for depletion (Cdep), and 4 V for accumulation (C ac c ) at a frequency f of 1 MHz . The capacitor has an n-well bottom plate on a p-type substrate. The measured capacitances slightly decrease a s temperature is reduced from 300 K to about 50 K, below 50 K, all th e capacitances have a steep reduction . This reduction is partially due t o freeze-out near the n-well contacts . For the case of a n-MOSFET, th e surface at the gate-to-source overlapping region changes from depletio n to accumulation when the gate voltage changes from zero to the suppl y voltage value . Thus, at very low temperatures, the Cgs capacitanc e reduces .
2 . Silicon Devices and Circuits 12
14 1
n-
-
-
..
C
o
O
100
150
n
.
p~~~i~~•=
r-,
w
..
i►
-
~
10 s,,, n
__
_
V 8 cu 6 .;asi c.) • 4 as U
C acc C de p
6
~~
o
2 ►~, ,•~
0
CC ~
i~
0
i~ 50
200
250
300
Temperature, T [K ] FIGURE 2.24. Measured capacitance of a MOS capacitor on n-well, wit h ToX = 10 nm, Wmask = 20 µm, and Lmask = 200 µm . The frequency f was set to 1 MHz . The n-well doping level is 10 17 cm' .
2 .2 .7. The Source/Drain-to-Bulk Capacitance s The estimation of reverse-biased p—n junctions associated with th e source/drain—substrate is straightforward . These junction capacitance s C. are calculated according to the well-established models (Fig . 2 .25) :
C;
=A
Esi
=
ESi
A
Wrb
2 e si
\
qNB (1/
(2 .67)
+ V — 2V,) /
V bi is the built-in potential, V is the reverse-bias ,wher voltage, Vt is the thermal voltage, Wrb is the thickness of the depletion region, and A is the area of the p—n junction . The junction capacitance decreases wit h temperature because the depletion width increases due to freeze-out .
2.2.8 . The Polysilicon Depletion and Quantum Effect s MOS transistors (or capacitors) with very thin gate oxides may presen t lower than expected values of gate capacitance . This deviation from th e classical behavior has been determined to be a function of polysilico n concentration and processing conditions, oxide thickness, and substrat e concentration (69—71) . As ToX decreases, polysilicon concentration Np
142
E . A. Gutiérrez-D., C . Claeys, and E . Simoe n 102
a .^, V �
..
g
=
10 -2 10-4 10- 6
••
10-8
•
G
10
-12
1
I
"_
. o '
,%
.
~ -~
-~
Ii
=-
~ -~
~-
= -10 r° o 10
•
1
-
10°
'c
o
_
I
I
E
4 .
o
~~
~ ~ .
t
I►
50
~
,
~
I,
1(X)
I
I
150
~~~
~
I
~
200
~
►
~
I
250
~
<
300
Temperature, T [K] FIGURE 2.25 . Calculated junction capacitance C . versus temperature.
decreases and substrate concentration NB increases, leading to a highe r degradation of the C–V characteristics, which are the processing conditions used in submicrometer and deep submicrometer CMOS technologies . There are two physical causes for the reduction of the capacitance : the polysilicon depletion effect (PDE) (72), and the quantum effects (73 ) on the inversion layer . When the doping concentration in the polysilicon gate is not sufficiently high, or if only partial activation is achieved during the therma l batch, the polysilicon/SiO2 interface will present a depletion region which acts as an additional series capacitor with the gate oxide capacitor . The effect of this capacitor is to reduce the total gate capacitance an d therefore degrade the current driving capability of the transistor . This degradation has been reported to be up to 30% in 125-A thick oxide devices operated at room temperature (71) and up to 60% in 100-A thick oxide devices (74) operated at 4 .2 K. This effect can be avoided usin g polysilicon doping levels higher than 5 x 10 20 cm', when total activation is assumed . At low temperatures, the depletion of the polysilicon gate enhances PDE, and thus PDE is more pronounced at low temperatures . Quantum effects in inversion layers are a result of the strong surface electric field that produces a potential well whose width in the bulk direction is small compared to the wavelengths of the carriers . Thus, the energy levels of the carriers are grouped in electric subbands, each o f which corresponds to a quantized level for motion in the bulk direction , with a continuum for motion in the plane parallel to the surface . The splitting of the energy levels into subbands results in the lowest possible energy levels for free carriers in the well and does not coincide with the
2 . Silicon Devices and Circuits
o
143
2
4
6
8
10
depth from the surface, z [nm ]
FIGURE 2 .26 . The charge distribution in the inversion layer for both classical and quantum mechanical (QM) approaches .
bottom of the conduction or the valence band . As the surface electric field increases, the inverted layer becomes more quantized, thus requiring a larger gate voltage in order to populate a 2D inversion layer so tha t it has the same number of carriers as the corresponding 3D classical system . In the classical approach, the inverted charge distribution peaks a t the Si—SiO 2 interface because this is where the energy bands are mos t bent . However, in 2D quantized inverted layers, the surface carrie r concentration at the interface is very low, and the centroid of th e inversion layers moves away from the surface (Fig . 2 .26) . The effect o f quantization of the inversion layer has been analyzed by several group s (75-77) . Lopez-Villanueva et al. (76) proposed an analytical model base d on extensive numerical simulations . The expressions allow the calculation of the position Z I of the centroid :
ZI
=
1 x 106V cm
IQD(QD ESi. E Si.
1 Q,)] - ' I '
+ 2 ES i.
(2 .68 )
ZIO is a reference length acting as a fitting parameter . A constant value ZIO = 1 .2 nm provides good agreement with numerical results . However, an analytical expression for this fitting parameter is also provided b y Lopez-Villanueva et al . (76) : Zlo IO
[1 .783 — 0 .107 • ln
NB (1O1-3)]
(nm)
(2 .69)
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
144
The depletion and inversion charges, Q D and QI , are given by QD
= J2tsj qNB
T
(P&p —
(2.7 0 )
where (p dep is the potential associated with the depletion layer ban d bending dep
s
— 'Zi QI
(2 .71 )
ES i
where 'Ps is the surface potential . Also the inversion layer charge QI i s given by QI
= Cox*
(Vgs
VFB
(P dep
— QD
C ox
(
2 .7 2
)
with C ox*
I
\
Eox
T. + \
Eox E si
(2.73 )
ZI
The denominator of Eq . (2 .73) is termed the "electrical oxide thickness, " which can be interpreted as a series combination of Cox and a "centroi d capacitance" given by (esi /Z,) . This mechanism has also been addressed by Jallepali et al . (75), wh o analyzed the shift on the threshold voltage . The n- and p-MOS threshold voltage shifts are calculated as a function of temperature and bulk doping level . The results are shown in Fig . 2 .27 . r—,
~ ,160go 1 I
I
1 ) 1 I I 7
T
o x =4 n m
S
E--
d
4.;
140
120
~ 100 43
80
/1r
o 60 .--■
2
40 = _
20 , 0
-
17 1X10 c m 50
100
I50 200 250
300 350 400
Temperature, T [K ] FIGURE 2.27 . Electron threshold voltage shift AV T obtained from full band calculations [replotted from Jallepali et al . (75)] © 1997 IEEE .
2 . Silicon Devices and Circuits
145
The threshold shift OVT in Jallepali et al . (75) is defined as th e difference between the threshold voltage calculated with the QM approach and that calculated with the classical approach : AVT
=
[VT (QM) — VT (Classical) ]
(2 .74)
According to Jallepali et al . (75), threshold shifts due to holes sho w slightly stronger temperature dependence compared to those due t o electrons . Analytical expressions for 0 VT for both electrons and holes ar e also provided by Jallepali et al . (75) . The room-temperature threshol d shift for electrons and holes (in eV) is modeled as OVTe,h (Lx, Ne,h)
= fe, h (Ne, h ) + Toxg e,h (Ne,h )
(2 .75 )
where fe,h(Ne,h) and g e,h (Ne,h) are polynomial fits to the simulation data , with
fC (NA) = 0 .007 + 2 .083NA — 20 .583NA 2 + 95 . 738NA 3
— 149 .916NA 4
(2 .76 ) g e (NA ) = 0 .094NA — 0 .139NA 2 — 0 .432NA 3 — 0 .586NA 4 fh(ND)
=
-0 .002 — 1 .621 ND
+
13 .893ND 2 — 61 .847ND 3
+
(2.77 )
95 .149ND4 (2 .78 )
and gh (ND) = — 0 .067ND — 0 .106ND 2
+
0 .654ND 3 — 1 .073ND4
(2 .79 )
The previously described studies (75,76) confirm the large impact o f quantum effects on the electrical performance of submicrometer CMO S technologies and their degradation effects at low temperatures .
2.2 .9 . The Drain-Induce Barrier Lowering Effect For MOSFET devices with submicrometer channel lengths, the drain depletion region moves closer to the source depletion region, giving ris e to an electric field penetration from drain to source that results in a reduction of the potential barrier at the source side, which in turn result s in an increased injection of carriers from the source over the reduce d barrier, thus enhancing the subthreshold current . This is the so-calle d DIBL effect (78) . In submicrometer MOSFETs the DIBL effect results i n a threshold voltage reduction, which follows a linear relation with Vds . A modified empirical model for the VT that includes the DIBL effects i s given by VTDIBL = VTO
6Vds
(2 .80)
146
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
where a is the DIBL parameter which has been defined in different way s by different researchers . In Grotjohn and Hoefflinger (78) a is given as
a = a 0 E Si Cox Leff
(2 .81 )
n
where a 0 is a fitting parameter that accounts for the geometry dependence and the exponent n varies from 1 to 3 . Another definition of a that accounts for the substrate (or bulk) voltage dependence is given i n Troutman (79) as a
=
[L
6E si C . + CD) ( °
(2 .82)
where CD is the depletion capacitance, which is a function of the bul k voltage . Another expression for a has been given by Rantnakumar an d Meindel (80) : a
e–(7[Leffi4WD)
(
WD = (°')
2 .83
)
where WD is the depletion region width. Recently, technological considerations to reduce the DIBL effect have been given by Tsai et al . (81), where a DIBL voltage VDIBL is defined as the difference V T (at Vds 1) — VT (at Vds 2) with Vds 2 > Vds 1 • The experimental results of the VDIBL voltage for a (W/ L) = 10/0 .5 n-MOSFET biased at Vds 1 = 0 .13 V and V ds2 = 0 .27 V as a function of temperature are shown in Fig . 2 .2 8 (82) .
■
u
111111111111111111111111111
5
0
50
100
150
200
250
300
Temperature, T [K ]
FIGURE 2 .28 . Measured DIBL voltage V DIBL for a (W/L) = 10/0.5 n-MOSFET biased at Vds = 0 .23 and 0.27 V .
2. Silicon Devices and Circuits
147
The DIBL effect represented by the VDIBL voltage, increases at lo w temperatures, indicating that low-temperature operation worsens th e deleterious effect of the DIBL . 2.2 .10. The Gate-Induced Drain Leakage Effect This mechanism was defined for the first time by Chan et al . (83) as the drain leakage current measured at drain voltage much lower than the breakdown voltage . The origin of this mechanism was attributed to th e band-to-band tunneling occurring in the gate-to-drain overlap region , where the high electric field is induced by the high gate-to-drain voltag e difference, and a model was proposed to predict this leakage current : IGIDL
= AEse - (B/Es)
(2 .84 )
where A is a preexponential constant, B = 2 .13 x 1 0 ' V/ cm, and Es is the vertical field at silicon surface , E= s
(V1 .2) 3T
(2 .8 5 )
oX
with 3 as the ratio of Si permittivity to oxide permittivity, and 1 .2 V a s the minimum band bending required for tunneling process to occur . Note that the IGIDL current flows from drain to substrate, and that it i s not added to the drain-to-source current Ids . Nathan and Das (84) calculated IGIDL current for direct and indirec t tunneling from the valence band to the conduction band of silicon, a s well as tunneling from the conduction band minimum of silicon to th e interface traps, and compared these results to experimental data . It is concluded in this work that IGIDL is mainly produced by tunneling fro m the conduction band to the interface traps, where the contribution fro m both direct and indirect band-to-band tunneling is negligible . A more complete model is proposed as follows : 1)e-B(Eg+hw)" + ne-B(Eg-w)1 .5] (2 .86) IGIDL = SAV [(n + where S is the area, and A is given b y 2 A = q(E) .Jmvxmcxmvymeymv .m .Z
M2 21 1/4?t 5/2 13/2mrx1/4Eg0 .75(q00 .5
(2 ' 87)
n is the phonon occupation number, is the electric field given b y ( Vds Vgs) Vd s 3ToX + W
(2 .88)
148
E . A . Gutiérrez-D ., C . Claeys, and E. Simoe n
Vds and Vgs are the drain- and gate-to-source voltages, respectively, W i s
the depletion width, E g is the energy gap of silicon, an d
=
(2 205 ) 3 _
M
(2 .89 ) qC
C2gh 2cs p
(2 .90 )
where C is the coupling energy (85), c s is the speed of sound in th e material, p is the mass density, w is the phonon frequency, and m r is th e reduced effective mass given by
(1/m r )
=
[(1 /mv )
+
(1 /m e )]
(2 .91 )
where m, and m e are the valence band and conduction band effectiv e masses, respectively . Also in Eq . (2 .87), E is an energy parameter give n by
22 .5 gh I
E _
3n .3m r Eg
(2 .92)
The subscripts x, y, and z on the effective masses refer to their components along these directions . When direct tunneling is considered, the following model applies : I= GIDL
S
qmr 18h '
e-qv(E/2)[(ßj/ "`_ A)/21 .5ghC]
(2 .93 )
where V is the applied bias . When tunneling assisted by trap levels is considered, the energy ga p Eg is replaced by (E g -E t) in Eqs . (2.86) and (2 .93), where Et is the trap energy measured from the valence band edge . The other consideration i s that the right-hand side of these two equations should be multiplied b y a factor that accounts for the trap density of states . Equation (2 .86) is thu s valid for indirect tunneling . These models have been used to calculate th e IGIDL current and compare it to experimental results, which are shown in Fig . 2 .29 (84) . These results show that the GIDL current in MOSFETs arises fro m interface trap-assisted tunneling and not from band-to-band tunneling . In another work (86), the measurements of the surface leakag e current of the gate-controlled drain-substrate diode at different temperatures are presented . In Acovic et al . (86), in addition to considering the reverse-bias tunnel current as a limitation to device miniaturization , it is used as a monitor to learn about hot carrier degradation i n MOSFETs . In this work, the temperature dependence of the reverse biased drain-bulk junction was found to be negligible, but the tempera-
2.
14 9
Silicon Devices and Circuits 10.1 0 10-11 46 10~ `.~ 10-2 10_ 02 2
C7
10-24 1 0.2 8 10 -30 10 10 .3 4 1 ~ -36 38 1 0 -40 _
E]
experimenta l
RI
calculated with trap-assisted tunnelin g
indirect tunnelin g
c
direct tunnelin g f
I8' 44 -3 .5
-3 .0
-2 .5
-2 .()
-1 .5
-1 .0
-() . 5
Gate voltage, V„ [V ] FIGURE 2.29 . Calculated and measured GIDL current IGDL, with direct, in direct, and trap-assisted tunneling (84) © 1993 IEEE .
ture dependence of the forward-biased drain—bulk junction is mor e important than expected for a tunnel current . The experimental result s are shown in Fig . 2 .30 . The reverse tunnel currents are slightly sensitive to temperature , whereas under forward conditions the reduction of the currents is muc h
1
10-8 -
I
I
IRbefore ~
• u 1--1 .
~
10-9
,T
II ' Rafte r
-
-11—111—11—111 ^
10 -10 =
•
-~ i = - -
.. _
/■ o
=
O 1 Fhcforc 1 Faftc r
10-13 50
i
1(x)
150
,
I
200
25 0
Temperature, T [K ] FIGURE 2 .30. Measured temperature dependence of the drain-to-substrate current of a n-MOSFET in reverse IR (VG = -15 V, VD = 3 V) and forward I F (VG = — 20 V, VD = — 0.6 V) conditions . The currents were measured before an d after stress (VG = VD = 7 V for 160 s at 77 K) [replotted from Acovic et al . (86) ] © 1993 IEEE .
150
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
larger at low temperatures . This indicates that GIDL effects will be les s pronounced at cryogenic temperatures . On the other hand, these results show clear evidence of injection and trapping of hot electrons in th e gate—drain overlap region of n-MOSFETs . Therefore, this region be comes especially important at low temperatures, at which soft freeze-ou t occurs, and hence becomes sensitive to trapped charges . 2.2 .11. Electrothermal Effects The electrothermal effect is defined as the coupling between the hea t generated by power dissipation and the change in electrical parameter s due to changes in temperature . The high power dissipation arises from the high current driving capability of very dense IG . Different approaches have been implemented to help diffuse the heat out of th e silicon chip, including the use of fans, the use of metallic dissipators, an d even the use of cooling systems . However, before dissipating the hea t generated at the surface of silicon devices, away from the chip, it diffuse s across the silicon die affecting the neighbor devices . A schematic representation of a packaged MOS transistor is shown in Fig . 2 .31 . In packaged MOS transistors or circuits the heat source Q is confine d within the silicon very close to the surface, bounded by the silicon bul k below, the gate oxide on top, and the source and drain diffusions o n
FIGURE 2.31 . Schematic representation of a packaged MOS transistor .
2 . Silicon Devices and Circuits
15 1
both sides. The thermal conductivity of the SiO 2 at 300 K is about 0 .014 W/cmK, which is much smaller than that of Si (1 .5 W/cmK) . Therefore, silicon is the most probable path for the heat to diffuse awa y from the surface . If the heat is assumed to diffuse isotropically, then i t goes away through the source and drain diffusions, passing by the source /drain contacts, the bonding wires, the bonding pads, and finall y through the external terminals . The heat can also diffuse through the silicon bulk, passing by the interface silicon–air at the lateral silico n walls, or it can diffuse through the bottom plate . The heat has to transport through the silicon . How the heat diffuses also depends on the operating temperature conditions . Therefore, in this section particula r attention is paid to the generation (self-heating) of heat by the MO S transistor and its associated electrothermal effects in the 300-4 .2 K temperature range. An equivalent electrical model for the thermal generation /diffusio n process can be proposed . It is based on a very simple combination of a heat source Q and thermal resistance and capacitance R th and Ct h (Fig . 2 .32) . The heat can be generated at very low frequency; in such a case, the heat capacitance C th does not play any role, and the hea t dissipates like the power in an electric resistor, flowing from the silico n to the ambient . In this way, the silicon obtains a balance in which the Ts i temperature is as close as possible to the T A temperature . The genera l case occurs when the Cth capacitance is not neglected ; in such a case, the generated heat dissipates through the parallel combination of C th an d Rth , with a characteristic thermal time constant i t h T th - (Rth . C th )
(2 .94)
Silicon temperature Ts ; •
R th
C th
•
Ambient temperature T A FIGURE 2 .32. Equivalent electric circuit of a thermal generator Q in silicon .
152
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen
According to the equivalent electric circuit of the thermal generator (Fig . 2 .32), the silicon temperature T si can be modeled as
=
1 [R
h
(T
—TA )
+
Cth
d
(22 .95 )
TA)]
(TP
where P is the power being dissipated by the heat generator . The electric power P depends on the amount of free carriers available for conduction , which in turn depends on T si , and both C th and Rth are geometry an d temperature dependent (87) . It is very difficult to find a solution for thi s equation. A more elaborated theory with proposed solutions is presente d by Javier de la Hidalga-W . (87) . Therefore, here we discuss only experimental results . First, we treat the case of a simple set of resistors that act as eithe r heaters or thermometers . The test structure consists of a series of silico n resistors, n-well resistors Rnwell located in the n-well, and p-substrate resistors Rpsub located in the p-substrate of a CMOS technology, a s depicted in Fig . 2.33 . The separation between the different n + (p + ) contacts determines the length of the resistor L n (Lp) and width Wn (Wp ) is determined as a first approximation by the width W of the contacts . The distances between the reference contact Vnref and the contacts 1— 4 are 10, 30, 90 and 200 ,um, respectively. The separation between contact s in the p-substrate is the same as that in the n-well . The method (88 ) consists of calibrating every resistor as a function of temperature TA . The calibration is done at a low-current bias condition to avoid self-heating . One of the resistors either in the n-well or in the p-substrate, is used a s
25 , u Cr1
I
-
I
I
1 .
►~
_
S Ei J
0
1
1
1
-
~
T A =4 .2 K ,
ri~
0 . . ...
I
-
_
~
I
-
► ~~~ -
-
_
0
1
~
E 10 _ ~ ~
C/)
1
.
20 15
• •--,
1
- - ~
-
L=1Opm
_
--
~► I,
~~ ~~ ,I „►~, 5 10 n-well power, Pnwe1► [m'' ]
15
FIGURE 2 .33 . Experimental test structure used to measure the silicon temperature (88).
2 . Silicon Devices and Circuits
15 3
FIGURE 2 .34. Extracted silicon temperature Tsi as a function of the power dissipated in a n-well resistor of (W/L) = 200 / 10 operated at T A = 4 .2 K.
heater Rht , whereas the other is used as temperature sensor Rts . The hea t generated by R ht is sensed by Rts as changes in its current level I ts , and the new value of Its is associated with a new value of Tsi . In this way, a plot of Tsi versus power Pth(Vthlth) can be extracted (Fig . 2 .34) . The Tsi temperature starts rising at about 1 mW of dissipated power in a linear way up to about 1 .5 mW, then it tends to saturate at higher levels of power . This behavior is explained in terms of the temperature dependence of R th , which has a minimum value at about 30 K; thus, thi s feedback system tends to settle down to an stable value . The same tes t scheme can be used to extract Tsi as a function of position x (Fig. 2 .35) . 25
~
20
_
r
~ i~ .r
• E a~ ô
U
.:= .. ~
(/)
TA=4 .2 K
15 ---_
10 – -
5
_ -
0`~ 20
t
40
t
60
t
KO 100 position, x [[tm ]
t
t
120
140
16 0
FIGURE 2 .35 . Measured Ts i temperature as a function of position x . Th e (W/L) = 200/10 n-well resistor was used as a heater with a power P nwell = 13 .5 mW .
E . A . Guti érrez -D ., C . Claeys, and E. Simoen
154
I psu b
R nx
unt
Vnref
heat exchange
Vpt
Rpx
Vpre f
FIGURE 2.36. Experimental configuration used to measure the thermal tim e constant ith . TA = 4 .2 K, Vnref = 0 V, Vnref = 7V, R. . = 12012, RI, . = 12 Kn . The L = 30 µm n-well resistor is used as a heater and the L = 30 µm p-substrate resistor as a temperature sensor. The frequency of the square signal VHS was set to 10 Hz.
The temperature profile is a result of the heat flow through th e silicon die . The thermal time constant T th can be extracted by applying a squar e wave signal to the heater and examining the output response of th e temperature sensor . For this purpose, the same test structure is used, bu t under the configuration shown in Fig . 2 .36. The Ipsub current, which is used to bias the temperature sensor, is adjusted with the Vpsub voltage . In this case, Vpsub = 0 .8 V, which sets Ipsub = 10 nA . The square signal VH s is applied to the external resistor R., inducing a pulsed voltage Vn t through Rnwell, this Vnt pulse generates a heat pulse that propagate s through the silicon bulk reaching the Rpsub temperature sensor . The increase in the Tsi temperature changes the value of Rnwell, inducing a voltage pulse Vpt . By measuring the Vpt wave signal, the thermal constant can be extracted . The experimental measurements are shown in Fig . 2.37 . Two thermal constants are observed one for cooling down (tthc ) and one for heating up ( rthh) . A value of 5 ms is measured for rthc and of 1 µs for tthh . The larger value of Tthc is explained by the fact that when the heat pulse, controlled by the high level of Vnt , is in the high state , the silicon substrate is already heated giving a larger change in C th (see Chapter 1) that compensates the smaller change in Rth , which explain s the longer Tthc . When the heat pulse is in the low state the T si temperature remains closer to TA , which results in a smaller thermal tim e constant ( rthh) . From a practical point of view, in CMOS digital circuits operating at high speed, in which the time constants are very small
2 . Silicon Devices and Circuits
15 5
10 = 0
: thc
ti th h
-10 -
0
10
20
30
40
time, t [s]
50
60
70
FIGURE 2 .37. Measured thermal time response of the test structure of Fig . 2 .36 . The structure was operated at TA = 4 .2 K. compared to thermal time constants, the Tsi temperature can be regarde d as constant with its absolute value depending on the electric power dissipated by the circuit . In analog ICs (89) the heat source might interac t with the circuit behavior, causing distortion in the DC transfer characteristics (89, 90) . The same technique has been used to measure self-heating effects i n single MOSFETs and CMOS inverters (91) . The results are shown in Figs . 2 .38 and 2 .39 . The silicon temperature Tsi , in the case of a single 35
50
30 25
b
0
0
1
2 3 Drain voltage, V ets [V ]
4
5
0
FIGURE 2 .38 . Measured I d –Vd, characteristics of a (70/0 .7) n-MOSFET operated at TA = 4 .2 K. The right axis is the plot of the extracted Ts i temperatur e (dotted lines) for V g = 1 .5, 2 .0, . . . , 5 .0 V .
156
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n 6 5
-
= -
-
-!~~ Ii~ ~I
4 =
°
V a ut
_
3-
o
2
, ., ßa
n
`'~, .
= 15
►~
L►\ kv.
a~
= 10 ~H a~_. ~ 5 ~. ..
~&~
t)
0
ô
o,
_ 0
►_.
25
= ~ . ~ 20
_ _
5 O
+~~~• +`+!
30
2 3 4 Input voltage, Vin [V ]
1
5
0
FIGURE 2.39. Measured output voltage V0t and extracted Ts ; temperature of a CMOS inverter operated at TA = 4.2 K (91) © 1993 IEEE .
n-MOSFET, reaches 43 K at Vg = 5 V, which is quite high considering TA = 4.2 K . In the case of the CMOS inverter, the maximum of Tsi occur s at the Vin voltage where the current transient consumption occurs, an d it increases due to the thermal time constant ith, which results in an increased amount of time for the heat to dissipate. Finally, the tempera ture dependence of the selfheating effect is plotted in Fig . 2 .40 .
~
(1)
15 10
. .... ~ , 0
A1 40 60 80 Ambient temperature, T A [K] ,
20
100
FIGURE 2 .40. Experimental temperature dependence of the (Ts; -TA) differential temperature, measured from the resistor test structure (88) .
2. Silicon Devices and Circuits
15 7
The experimental temperature dependence of T si is due to th e temperature dependence of the Si thermal properties . The self-heating effect because considerable at temperatures below about 30 K . This is also due to the strong freeze-out effects . 2 .2.12 . Summary The electrical performance of the MOSFET as a function of temperatur e has been presented in this section . This analysis has been done based o n two of the most popular models used in literature, the Klassen and BSIM models . Predicted results were compared to experimental data, an d discrepancies were discussed and analyzed based on physical principles , outlining the future of deep submicrometer MOSFETs for low-temperature operation. This section also reviewed the evolution of MOSFE T technology from the mid 1980s to 1998 . The trend shows that the Year 2000 should be the date of the gigaintegrated CMOS systems with mor e than 10 9 transistors on chips operated at frequencies above 1 GHz . Second-order effects and quantum effects that pertain to submicrometer and deep submicrometer MOSFETs were also analyzed as a function of temperature . Effects such as bias-dependent series resistance , bias-dependent gate oxide thickness, bias-dependent gate-to-sourc e capacitance, polysilicon depletion, and electrothermal effects were all discussed in terms of published models and experimental results . It i s concluded that deep submicrometer and nano MOSFETs have a promising future in cryogenic applications .
2 .3 .
THE SILICON-ON-INSULATOR MOS TRANSISTO R
Interest in the use of SOI substrates began in the late 1970s and wa s aimed at finding a replacement for silicon-on-sapphire (SOS) . Although SOS was used for applications such as high-temperature operation i n automotive and fast A / D converters, its primary use was in military an d aerospace applications due to superior radiation hardness. In general, the driving force triggering worldwide research in SOI is its performance and cost advantage (93-95) . Reported advantages are; (i) latch-up immunity, (ii) higher packing density, (iii) higher speed performance, (iv ) lower power consumption, (v) lower leakage current, (vi) wide voltag e operation range, (vii) reduced short-channel effects, (viii) strong potential for both cryogenic applications and high-temperature electronics , and (ix) lower processing cost . Potential drawbacks are (i) floating body phenomena, (ii) parasitic effects, (iii) availability and cost of the substrates, and (iv) processing difficulties on thin film substrates .
158
E . A . Gutiérrez-D., C . Claeys, and E . Simoe n
FIGURE 2 .41 . Schematic illustration of the "smart-cut" process [after Bruel (92)] .
An important parameter influencing the use of SOI has been the substrate manufacturing and quality, which for many years had a strong negative effect on the material cost . Whereas in the early days zon e melting recrystallization by laser, e-beam, or graphite heating was th e key manufacturing technique for the thick film substrates (96), today the market is dominated by separation by implantation of oxygen (SIMOX ) (97) and wafer bonding and back-etch (BESOI) (98) . The recently developed smart-cut process (92, 99) for making high-quality wafers is reducing the difference in wafer cost between bulk and SOI . The process, which has been demonstrated on 300-mm wafers, is based on proto n implantation and wafer bonding as illustrated in Fig. 2 .41 . In a first ste p hydrogen with a dose in the range 2 x 10 16 -1 x 10 17 cm'2 is implante d in a wafer with a dielectric capping layer, which will become the BOX of the SOI structure . Subsequently, after cleaning the implanted wafer A is hydrophilically bonded to wafer B . The latter will later play the rol e of the bulk silicon. During a first heat treatment (400—600°C) the implanted wafer A will separate into two parts a thin monocrystalline silicon layer remaining bonded to wafer B and the rest of wafer A . A second temperature step (> 1000°C) is used to strengthen the chemica l bonds . Finally, after splitting chemical—mechanical polishing is used t o reduce the microroughness of the thin silicon film . The remaining wafer A can be used for another fabrication cycle . Compared to the standard BESOI process, only one silicon wafer is effectively used, whereas in th e other case one wafer is fully polished away . The used buried oxide (BOX) manufacturing technique has an impac t on the defect content of the layer and/or the substrate, on the uniformit y of the film thickness, and on the quality of the Si—SiO 2 interfaces . As will
2. Silicon Devices and Circuits
159
FIGURE 2 .42. Delay and power dissipation of a two-input NAND gate in bul k CMOS and SOI CMOS gate arrays (FO = 2- and 3-mm metal wires) [after Won g and Rigby (100)] .
be discussed in Section 2 .3 .3, especially the front- and back interfaces o f the silicon film have a direct impact on the electrical device performance . The continuous improvement in material quality leads to higher minority carrier lifetimes, which in turn may enhance the parasitic bipola r action . In general, it can be stated that the SOI materials are achieving the quality of bulk material. The pricing, however, is controlled by th e market demand . Whereas for 0 .7- to 0 .35-pm CMOS, it was difficult for SOI to compete with bulk CMOS, for the deep submicrometer technologies SOI is becoming a real challenger . It is generally believed that SOI CMO S technologies will no longer be restricted to niche applications, such a s radiation hard, low-voltage, and/or high-temperature applications, an d also will offer potential for volume production . An illustration of the benefit of SOI compared to bulk CMOS for digital applications in shown in Fig . 2 .42, which shows the delay time and power consumption of a two-input NAND gate in bulk and SOI CMOS gate arrays for a fan out = 2- and 3-mm metal wires (100) . It can clearly be seen that the SO I CMOS array consumes 65% less power than the bulk counterpart at th e same speed . An in-depth review of the design considerations an d advances of SOI for digital CMOS VLSI can be found in Chuang et al . (101) . There is strong interest in using CMOS SOI for memory and logic applications, although this requires the implementation of body contacts . A strong SOI CMOS potential is related to low-voltage/low-power applications . As will be outlined later SOI will be playing an importan t role in the deep submicrometer (i .e ., 100 nm and below) era .
160
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
FIGURE 2 .43 . Schematic representation of a SOI CMOS building block consisting of an n- and p-channel transistor .
2.3 .1 . Inversion Mode Device s A schematic cross section of a SOI CMOS building block, consisting of an n- and p-channel device, is given in Fig . 2.43 . The device uses LOCOS isolation and spacer oxides and LDD regions for the gate architecture . As can be clearly seen, the structure consists of a Si film in which the curren t conduction occurs . Although vertically limited by the BOX, the source — drain junctions determine the lateral dimension of the silicon cavities . Only so-called reach-through junctions, whereby the vertical junctio n depth is equal to the film thickness, are considered because of thei r importance for VLSI and ULSI applications and their strong benefit fro m a processing viewpoint . The bias voltage on the four electrodes (i .e ., the source and drain regions V ds , the front gate Vgf , and the back gate o r silicon substrate Vgb ) controls the device operation . As discussed later, in some cases one also uses an additional film contact to control th e potential of the film . Depending on the back-gate voltage, the back Si SiO2 interface can be accumulated, depleted, or inverted . In general, one can differentiate between fully and partially depleted devices and between the thin and thick film mode of operation . If the depletion widths at the front and back interfaces are overlap ping or the front depletion width extends throughout the whole silico n film thickness 41 one refers to a fully depleted (FD) device . The total silicon film is then depleted of carriers . In the other case, there remains a neutral silicon region in the film and one is dealing with a partiall y depleted (PD) device . Often, one also refers to the thin and thick film
2. Silicon Devices and Circuits
161
operation mode of an SOI transistor . A thin film device is a transistor i n which the silicon film thickness is smaller than twice the maximu m depletion width Wmax :
t f> Wmax -
4ESi
(2 .96)
qNA
where esi is the silicon permittivity, q is the electron charge, (' F is th e Fermi potential, and NA is the film doping concentration . This implie s that by applying the appropriate front and back gate biases, the silico n film can be fully depleted, or the device can operate either in th e partially or the fully depleted mode . In the case of a so-called thic k film regime there will always remain a neutral silicon region betwee n the front- and back gate depletion regions . An important difference in electrical performance exists between partially and fully deplete d devices.
2.3.1.1. Partially Depleted Device s For partially depleted devices the depletion layer under the gate electrode ends in the silicon film, leaving a neutral region in the silicon film . Under similar channel doping conditions and front gate oxide thickness , bulk and PD devices have the same threshold voltage, given b y VTf — C MS + 2(I)F
( gN it / Coif) (Qdep1
/ Coif)
(2 .97)
where OMS is the work function difference between the gate material an d the silicon film, Nit is the interface state charge density, Qdepl is the depletion charge given by q Wmax/NA, and C ox is the oxide capacitance . Equation (2 .97) is written for the threshold voltage of the front gate transistor, but a similar expression holds for the back gate transistor. In this type of device, there is no coupling between the front- and th e backside threshold voltage .
2.3.1.2. Fully Depleted Devices The front gate-related depletion region extends from the gate oxid e interface to the point of minimum potential, which for sufficiently larg e t f lies inside the silicon film. By increasing the back gate voltage, th e associated depletion width will increase at the expense of the fron t depletion width, thereby modifying the front gate threshold voltage . I n other words, the backside voltage will modulate the front threshold
162
E . A . Gutiérrez-D ., C. Claeys, and E . Simoe n
voltage . The threshold voltage for such a device is then given by (102 ) VTf
i~
Qoxf + + (1 CsiSi / MSf — C oxf
oxf)2O+ F
(0.5NAtf C
oxf
+ C
C siCoxb
C C
oxf ( Sioxb )
Vacc b
(2 .98 ) where f and b refer to the front and the back interface, respectively, Q o x is the fixed oxide charge density, Csi is equal to Es i / t f , and Vaccb is the back gate voltage corresponding to back accumulation given by (102 ) Qoxb
Vaccb =
MSb — C
—
Csi C
F
oxb
+
(O .5qNA tf C
oxb
(2 .99)
oxb
For FD devices, the saturation current can be written as (102 )
IDsat
= WµnCoxf
(VGf
2L(1 + a) (
_ Vtf) 2
(2 .100)
where tun the electron mobility, W and L are the effective gate width an d length, and 1 + a is the body factor corresponding for FD devices with
a
=
Csi C oxb Coxf (CSi
+
(2 .101 )
Coxb)
Fully depleted devices are sensitive to the uniformity in silicon fil m thickness. Equation (2 .98) and (2 .100) can be used to study the impact o f the film thickness nonuniformity on the electrical device performance . The special case of an ultrathin film, requiring that quantization effect s are taken into account, is addressed in Section 2 .3 .3 . Many analytical models have been proposed for fully deplete d devices, whereby it is commonly assumed that there is no potentia l decrease across the silicon substrate (102-104) . Although it has bee n pointed out that this assumption is not always valid (105, 106), more detailed models are either not sufficiently accurate or too complex. A more simple case is based on the assumption that the substrate potentia l decrease is linear (107), but the validity of this model is doubtful in th e case of a strong coupling between front- and back gate . The theory ha s also been extended to include the substrate effect down to 77 K fo r enhancement mode (108) and accumulation mode (109) FD SOI MOSFETs . Comparison with 2D MEDICI (a commercial device simulator ) simulations validate the approach, which provides more insight into th e substrate effect on the low-temperature threshold voltage and sub threshold slope . Although some basic electrical performance parameters of FD device s are discussed in Section 2 .3 .3, with special emphasis on low-temperature
2. Silicon Devices and Circuits
163
performance, it is important to mention that there also exists a differenc e between PD and FD devices from a reliability viewpoint (110) . In general, during hot carrier degradation the front channel of FD device s degrades less than the back channel, and FD devices are less vulnerable than PD devices . 2 .3 .2 . Accumulation Mode Devices Accumulation mode devices, such as p + —p—p + or n + —n—n + FETs, ca n be fabricated with a high reproducibility and controllability and have th e advantage of enabling good threshold voltage control without th e requirement of using a p + polysilicon gate material for the p-channe l devices (111) . This simplifies the process flow and reduces the manufacturing cost . These devices are characterized by a low leakage current an d a steep subthreshold slope. However, it has been reported that at both room (112,113) and liquid helium temperature (113) the current conduction mechanism is more complex than that for standard enhancemen t mode devices . This is illustrated for room temperature operation in the Ids - Vgf curve shown in Fig . 2 .44, demonstrating different kinks in the plot . This behavior points toward the existence of different threshold voltages , depending on the device biasing mode . The most common method used to experimentally determine th e threshold voltage is based on an extrapolation of the linear I ds Vs Vgf
x 1O-4 0.0 -0.2 -
-1 .0 ;
_
2 0 Front gate voltage, Vgf (V)
FIGURE 2.44. Drain current versus front gate voltage for a 2 x 20-µm accumulation-mode SOI MOSFET . The back gate voltage is varied between 15 and — 40 V in increments of 5 V [after Rotondaro et al . (113)] .
164
E. A . Gutiérrez-D ., C . Claeys, and E . Simoen Vgb = -25v
Vgb = -25 V
Vgb = -25 V
~
-
~
E
•
.
-2 0 2 Front gate voltage Vgf (V )
FIGURE 2.45. Drain current, transconductance, and the derivative of the transconductance versus front gate voltage for a 2 x 10-µm accumulation mode p-channel device with Vgb = — 25 V [after Rotondaro et al . (113)] .
characteristic to zero drain current . This technique, however, results in large errors for accumulation mode compared to enhancement mode devices. A more consistent experimental method to determine the threshold voltage has been proposed by Terao et al . (114) and is base d on an extraction of the transconductance g m = dlds /dVgf and then the calculation of the derivative dgm /dVgf . The principle of the technique, which corresponds with the second derivative of the drain curren t versus front gate voltage and therefore is often referred to as th e double-derivative technique, is shown in Fig . 2 .45 . Each negative pea k corresponds to the threshold voltage of a different conduction mode, i .e . , for most positive Vgf to the onset of back gate accumulation, the second peak to body conduction, and the rightmost peak to back gate accumulation (113) . The same technique is also applicable to both FD and P D devices and remains valid to cryogenic temperatures (115) . However, at cryogenic temperatures care has to be taken to account for possible
2 . Silicon Devices and Circuits
165
transient effects, whereby the slow generation /recombination of minority carriers may lead to an apparent disappearance of the body curren t component (115) . At 4 .2 K extremely long time constants are ofte n observed, as will be discussed later . The use of either a light pulse or a large drain voltage can overcome this problem . A potential drawback o f the double-derivative technique to determine the threshold voltage i s related to the observation that the technique is sensitive to the impact o f the source—drain series resistance (116) . This will be particularly import ant for nonsilicided, LDD-type devices and in the case that freeze-ou t effects are dominant .
2 .3 .3 . Device Performance Parameter s The following sections give a brief discussion of important electrica l device performance parameters, which are discussed from a viewpoin t of the SOI CMOS potential for low-temperature applications .
2 .3 .3 .1 . Threshold Voltage For the different types of devices discussed previously, some genera l expressions for the threshold voltage have been given. It was als o mentioned that especially for accumulation mode devices the differen t conduction mechanisms have to be taken into account . The optimized extraction techniques are applicable to cryogenic temperatures . These observations are valid for silicon films that are not extremely thin . For state-of-the-art devices, the silicon film thickness is strongl y reduced, resulting in the use of ultrathin films . According to the classica l theory, the threshold voltage decreases monotonically with decreasin g film thickness due to a decrease of the charge in the depletion layer . For a buried channel MOSFET the threshold voltage is given by (117)
VTf—
VFB
+
(qNt
Coxf
(f
CSi sox),
C+S Si
1 S
+
CSiCoxb CSi
+
Coxb
+
C SiC oxbVg b
Coxf ( CSi + C oxb)
(2 .102 ) where VFB is the flat-band voltage, and Os is the surface potential a t threshold . However, when t f decreases below a critical value, quantization effects have to be taken into account, resulting in the occurrence o f 2D subbands (118) . This is schematically illustrated in Fig . 2 .46, which shows simulated results of the impact of the film thickness on the minimum channel length leading to punch-through . The strong quantization of the short-channel effects occurs for a film thickness less than
166
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
10-2 ~ Qa
1
. 10 1
Silicon Layer Thickness (nm)
FIGURE 2.46 . Simulated minimum channel length Lmin dependence on the silicon film thickness t f for surface channel (SC) and buried channel (BC ) MOSFETs / SOI at room temperature, according to the classical and quantu m mechanical approaches [after Omura et al. (118)] .
5 nm due to an increase in the effective band gap energy and a decreas e in the effective density of states resulting in an increase in the majorit y carrier extension . The figure also gives simulated results for surfac e channel devices, indicating that in surface channel MOSFETs quantizatio n effects are more severe as an increase in the energy band gap leads to a n increase in the depletion layer width with increasing built-in potential . The quantization effect becomes more pronounced for low-temperature operation . A representative parameter to study short-channel effect s is the drain–voltage derivative of the threshold voltage, g = (dVtf / dVds) . The classical and quantum mechanical simulated values of this parameter are shown in Fig . 2 .47 and are compared with experimenta l results for 0 .1-,um buried channel p-MOSFETs on SIMOX with an 8-n m film thickness . No quantization effects are noticed at 300 K and th e experimental results agree with the classical curve . The g increase fo r lower temperatures is caused by a decrease in the effective density o f states, leading to a decrease of the Debye length . Classically, the Debye length would increase with decreasing operating temperature (119) . Due to the quantization effects, the threshold voltage no longer decreases fo r decreasing film thickness but rather increases for a film thickness belo w
2. Silicon Devices and Circuits
167 Ume 0 . I p m
u
100
A
nm
N porlxlO tl tn;-3 Vo= V ' ..
Quantum
•
*d
R
o
►
w*v
\ Classical ~lassical
1ß i
102
10 3
Temperature (K) FIGURE 2.47 . Temperature dependence of the drain–voltage derivative of th e threshold voltage (g) for O .1-µm p-MOSFETs on SIMOX with t f = 8 nm. Th e experimental points are the average values for five measured devices [afte r Omura and Itzumi (119)] .
a critical value . The latter depends on technological (geometrical features and doping density) and operational parameters (voltages an d temperature) .
2.3.3.2. Oxide Charge s The essential difference between a bulk and a SOI device is the fact tha t the latter has a front gate oxide and back BOX . Although there has bee n much improvement, the quality of a gate oxide on a thin silicon film i s of a slightly inferior quality compared to the quality of a standard gat e oxide (120,121) . This results in a higher interface trap density, dependin g on the surface finishing technique that is used . However, of considerabl e inferior quality is the BOX . For thin silicon films there is a direc t coupling between the front and back interface . This necessitates the availability of accurate extraction procedures for the oxide and interfac e charges . As will be discussed later, the interface trap density determine s the subthreshold swing .
168
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
The standard capacitance and conductance techniques to determine the interface trap density are difficult to apply for SOI devices becaus e of the unpractically large capacitor areas involved and the large film series resistance. A better approach for SOI devices is based on using a charge-pumping technique (122) . When pulses from accumulation t o inversion are applied to the gate and the source and drain are kept at a small reverse bias, a net current can be measured at the film contac t (123) . The current corresponds with charge that is pumped from th e source and drain via the interface traps toward the film contact. The measured back interface trap density is a few times 10 11 cm - 2 eV -1 an d about an order of magnitude larger than that at the front interface (122) , which was also confirmed from measurements based on extrapolation of the threshold voltage (124) . A drawback of the charge-pumping technique is that one needs a film contact and a dedicated test structure . For accumulation mode devices the interface trap density can also b e determined from the temperature shift of the threshold voltage (125) because both at room temperature and at 77 K the flat-band voltage is equal to the front threshold voltag e Qox f MSf Coxf
V t f - VFB FB
c
(2 .103)
ox f
where Q . . f is the front oxide charge density and is about 4q .1 0 1 ° C / cm 2 (105) . The front threshold voltage can accurately be determined by th e previously discussed double-derivative technique . The interface tra p charge density corresponds t o Ei
Qit = q
J
EF
Nit (E)dE
(2 .104)
In general, it can be assumed that the interface traps act as donors i n the lower half of the band gap and as acceptors in the upper half . Normally, one has to take into account that the interface trap density is not constant over the band gap but shows a tendency to increase towar d the band edges . The exact amount of increase strongly depends on th e measurement technique used (126) . Exact calculations should also tak e into account the energy dependence of the capture cross sections . Therefore, it is common to define an effective density of interface trap s over the band gap, which corresponds with the value at midgap . Measurements as a function of temperature indicate that the interface trap density is increasing with decreasing temperature (127,128) . In the case of a nonuniform distribution of the interface trap density over th e band gap, the increase of the effective density with lower temperatur e can be explained by the temperature shift of the Fermi level E F .
169
2 . Silicon Devices and Circuits
2 .3 .3 .3 . Subthreshold Swin g The subthreshold swing for partially depleted devices is given by th e conventional relationship of bulk transistors :
s
_ dV gf
_ kT
d tog(Ids )
q
1 + C depl + Citf
l0 g
C
ox f
(2 .105 )
where Cdepl is the depletion layer capacitance and can be used t o characterize the interface trap density. In the case of fully deplete d devices, however, the expression has to be modified in order to take int o account the coupling between the front and the back interface . Thi s results in (129 )
s
=
kT q
log
[(i +
Citf Coxf
+
_
CSi
coil
(C Si 2/C oxb•Coxf) 1 + (Citb /C oxb) + (CSi. / Coxb)
(2 .106 )
Within a few percent accuracy, the same expression is valid for an accumulation mode device (130) . The subthreshold swing depends on the depth in the silicon fil m where conduction takes place and thus varies with the back gate bia s conditions (130,131) . Although this can be modeled, it leads to comple x analytical expressions . Figure 2 .48 illustrates the back gate bias depend ence for an accumulation mode p-channel SOI MOSFET . Equation (2 .106 ) corresponds with the minimum in the S curve . For another gate bias one has to add a correction term to the expression . An analysis of the subthreshold swing is also often used to characterize the interface trap density . However, Eq . (2 .106) points out that S depends on both the front and the back interface trap density . In the case
100 -g
.c~ .~ 2S
20
COI
Q, -10
AM SOI PMOS 1. .~ $ Lim W as 20 Vds a: -0.1 "K T as 300 K (?
j,,i.tt!
8 V (minimum point) 10
Back Gate Shia V 1,1 bl-V1
FIGURE 2 .48. Back gate bias dependence of the subthreshold swing for a L = 5 pm AM SOI p-MOSFET at 300 K and V DS = - 0 .1 V [after Martino et al . (125)] .
170
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
of accumulation mode devices it has therefore been suggested that th e front interface trap density should be determined first, based on th e determination of the threshold voltage at two different temperatures (e .g ., room temperature and 77 K) . Afterwards the minimum in the S curve can be used to determine the back interface trap density . This method is called the one swing and dual-threshold voltage measurement (125) . Care has to be taken, however, to optimize during the subthreshold swing measurement the rate of the change of the front gate bias i n order to ensure a stable swing value determination .
2 .3.3.4. Series Resistance As discussed previously, an LDD is commonly used in scaled technologies to reduce hot carrier degradation effects . Although SOI should b e more resistant, LDDs are also being implemented routinely . An important drawback of LDDs is that they increase the parasitic series resistanc e of the MOSFET, which may become even more pronounced at lo w temperatures due to freeze-out of free carriers . The total device resistance consists of the sum of the series resistance RS and the channel resistance R eh . Optimized techniques for the determination of the series resistance have recently been proposed and are based on a compariso n of the experimental device characteristics with MEDICI simulations, taking into account second-order effects impacting on the carrier mobility (132,133) . It is essential that the resistance is also gate voltag e dependent (134), as illustrated in Fig . 2 .49 for the channel and series resistance of PD MOSFETs operating at 77 K . A simple technique base d
FIGURE 2.49 . Channel and series resistance versus gate overdrive voltag e (VG* = VGf – VT ) for 10- and 2-µm SOI PD n-MOSFETs operating at 77 K . (134)
17 1
2 . Silicon Devices and Circuits 0.36 T=77 K
i
PD SUI n- MOSFET
0.34 -
_ _
0.32 E 0 .30 - RT value
X
0 .28 -
0 .26
0
1 2 3 Gate Overdrive Voltage (V )
4
FIGURE 2 .50 . AL versus gate overdrive voltage (VG * = VGf — VT) for 10- and 2-µm SOI PD n-MOSFETs operating at 77 K (134) . on the combination of a long reference device and a shorter L-arra y transistor can be used to determine the series resistance (135, 136) . To derive the effective gate length or AL, one has to take into account the series resistance (134) . A crucial question is whether or not the effective gate length is temperature dependent due to the occurrence of carrie r freeze-out in the LDD regions . Figure 2 .50 illustrates that in the appropriate voltage range, the same AL value is found at 77 K and at roo m temperature . It has been noted in the past that the series resistance not onl y impacts the characteristics but also the extraction of the device parameters in linear operation, such as the threshold voltage, the sub threshold slope, and the transconductance (135-137) . This is particularl y pronounced for FD SOI MOSFETs (137) . In order to reduce the series resistance effect on the VT extraction, a modified technique has bee n proposed (138), which is particularly suitable for SOI .
2 .3 .3 .5 . Transient Effects When applying a bias step to the front or the back gate of an SO I MOSFET, carriers have to be supplied in order to establish the steadystate channel. Especially in weak inversion and at small drain bias Vds , where the supply from the source is small, carrier generation/recombination processes will dominate the transistor response . As a result, the measured channel current will show a transient behavior, whereby th e time constants will be more pronounced for low bias values . Since the generation of carriers at low electric fields is thermally activated, th e
172
E . A . Gutiérrez-D ., C. Claeys, and E . Simoe n
FIGURE 2.51. VT instability in a PD SOI n-MOSFET at 4 .2 K . Curve 1 is the initial measurement just after cooling the unbiased device . Curves 2 and 3 are recorded after the drain has been swept to 3 and 5 V, respectively . Curve 4 ha s been registered after 24-h•unbiased relaxation at 4 .2 K after measurement 3 (140) .
typical response time will increase drastically upon cooling, giving ris e to time constants of microseconds at 300 K, seconds at 77 K, and up to hours at 4 .2 K (139-141) . In the latter case, the transients last so long tha t the device can be switched to a metastable charge state . As a result of the slow transistor response at cryogenic temperatures , determination of the primary device parameters, such as the threshol d voltage VT or the subthreshold slope S, becomes delicate. An example is shown in Fig . 2 .51 for a PD SOI n-MOSFET at 4 .2 K, demonstrating th e shift of the input characteristics for different device history (140) . Another consequence is that one has to optimize the step in the gate voltage for accurate subthreshold slope determination, as illustrated in Fig . 2 .52 for an accumulation mode SOI p-MOSFET (142) . For too high DVgf (or too few points per decade), erroneous S values will be obtained . Too many data points will result in a noisy measurement and a loss o f accuracy. It has been observed that these transient phenomena are particularl y pronounced for long-channel devices, whereas they improve for shorter effective lengths at the same temperature . The V T instabilities are
2 . Silicon Devices and Circuits
173 12
40 E
10
stability 6
AM SOI p-MO S L =5p m W = 20 p m T – 77K
a
.o■il
4 2
O ~0 3
.
i
.
a~. ~ ~
10
.
10
10
Front Gate Bias Step (mV) FIGURE 2 .52 . Subthreshold swing as a function of the front gate voltage ste p at 77 K for a 20 x 5-µm AM SOI p-MOSFET (142) .
pronounced for PD devices, whereas they are small to negligible for full y depleted architectures . The use of a body tie for PD transistors only partially removes the anomalies, and particularly at low cryogeni c temperatures transients will remain prominent . A practical way to avoid these problems is to cool the device unde r the appropriate biases and then measure the characteristics at lo w temperatures . However, any subsequent abrupt bias change will pro duce new transient effects and hence measurement instabilities . This i s illustrated by the results of Figs 2 .53a (300 K) and 2 .53b (77 K) showin g the input characteristics in linear operation for a PD SOI n-MOSFE T before and after a so-called "latch" measurement, whereby the front gat e bias is swept from 0 V to strong inversion at high drain bias . In such a case, carrier generation by band-to-band multiplication will occur in th e large lateral field near the drain . Part of the created charge will b e retained in the film at low temperature, whereas the created hole s (n-MOSFET) will be swiftly removed at room temperature, thus explain ing the negligible VT shift observed there . Therefore, great care must b e taken in the cryogenic characterization of SOI components since it is not obvious to develop a consistent and reliable extraction technique eve n for the basic device parameters .
174
E . A . Gutiérrez-D., C . Claeys, and E . Simoe n
FIGURE 2.53 . Input curves for a 20 x I-µm PD SOI n-MOSFET at 300 K (a) an d 77 K (b) . Curve 1 is the starting measurement in linear operation . Curve 2 i s measured after latching the device for a V ds = 3 V, and curve 3 is the relaxatio n of curve 2 to the original state.
2 . Silicon Devices and Circuits
17 5
2 .3.3.6. Floating Body Phenomen a From a design standpoint, it is often preferred not to use a film contac t because this lowers the packing density . Some pros and cons of buried contacts are addressed in Section 2 .3 .4 .3 . Omitting these contacts implie s that the silicon film remains floating during operation, forming the basi s of undesired physical effects which are called floating body effects . The most important phenomena are (i) a kink in the drain current characteristics, (ii) the observation of threshold voltage instabilities, (iii) pronounced hysteresis and transient effects, and (iv) parasitic bipolar action . These effects will strongly manifest themselves especially during cryogenic device operation (143) . The physical basis for most of these floating body effects in, fo r example, n-MOSFETs is related to impact ionization in the pinch-of f region near the drain which is caused by channel electrons accelerate d by the high lateral electrical field, and the charge storage in the silicon film . Generally, this impact ionization-related floating body effects are far less pronounced for p-channel devices (see Chapter 3) and shoul d also be less important in accumulation mode transistors . A schematic illustration of the impact ionization-generated current flow and th e charge buildup in the associated silicon cavity, formed by front, back, and sidewall oxides and by the source and drain junction, is given i n Fig. 2 .54 . For low to moderate carrier generation levels, the holes in a n n-channel device are annihilated by recombination in the silicon film . However, for higher carrier generation levels only a part of the generated carriers recombines, whereas the majority will be driven by the electric field toward the source . The gradual carrier accumulation raise s the potential near the source and may forward bias the source—fil m junction. The potential change depends on the film resistivity and i s strongly temperature dependent . At low temperatures carrier freeze-out has to be taken into account, as will be discussed in detail in Chapter 3 . The forward biasing of the junction results in a decrease in the threshol d voltage and consequently in an increase in the channel current . The amount of charge stored in the silicon cavity depends on the size of the cavity, the operating conditions, and the time constant of the involve d carrier trapping/ detrapping and generation /recombination mechanisms . For cryogenic temperatures these time constants are relatively long , i.e ., up to several minutes at liquid helium and resulting in the observe d hysteresis and transient effects . A theoretical analysis of several floatin g body phenomena, including the kink effect, is given in Chapter 3 . It i s important to note that floating body effects do not always have to b e considered as negative . By controlling the transient effects it is possible
176
E . A . Gutiérrez-D ., C. Claeys, and E . Simoe n
FIGURE 2 .54. Schematic representation of the impact ionization-generated current flow in a SOI nMOST (a) and the SOI cavity which can be considered a s a potential well formed by the front, back, and sidewall oxides and by the sourc e and drain junctions (b) .
to design a device with a metastable charge state, whereby the threshol d voltage of the device can be preset . Based on this multistable charg e controlled memory (MCCM) effect, new applications such as a singl e transistor memory cell and an optical detector can be envisaged operating at cryogenic temperature (144) . The concept of a silicon cavity fo r future microelectronic devices such as single electron transistors an d quantum wells will be discussed later . Although the kink effect leads to a higher drive current, it i s undesirable because it causes current overshoots, is difficult to mode l and to implement in circuit simulators, and prevents the use of CMO S SOI circuits for analog applications . Most of the floating body effects can
2 . Silicon Devices and Circuits
177
be suppressed or even eliminated by implementing a film contact, as wil l be discussed later . In addition, various technological modifications t o reduce floating body effects have been proposed (145—147) . The main idea is to apply an extra ion implantation by inert atoms (Ge, Ar, . . .) to create adjacent to the source (drain) junction lattice damage, whic h recombines the injected holes and therefore strongly reduces the curren t gain of the parasitic bipolar transistor . Another solution is the use of fully depleted devices (148) . The kin k effect is then suppressed because of the reduction of the electrical fiel d near the drain leading to a lower impact ionization probability and th e prevention of carrier accumulation in the film . Fully depleted device s have the additional benefits of larger drain saturation currents and superior subthreshold leakage . However, depending on the film thickness used, these devices may be prone to the parasitic bipolar transistor action leading to latch-up problems (149) . 2 .3 .4 . Alternative Device Concept s In addition to the large variety of technological options to improve th e electrical device performance, it is also possible to rely on desig n optimizations . The following sections address some design considerations that are important for the use of SOI circuits in cryogeni c applications .
2.3.4.1. Body Contacts For partially depleted devices the floating body effects can be avoide d by grounding the silicon film . However, the use of so-called body ties o r body contacts have a negative impact on the silicon estate, thereb y reducing the packing density. The typical loss of 15—25% in silicon are a per device can be reduced by using bottom body contacts, whereb y locally the silicon film makes contact with the silicon substrate (150) . Although these body ties result in a speed penalty due to the increase i n gate area and capacitance, the increased radiation hardness and th e potential for use in high-temperature applications such as automotiv e are benefits (151) . Whereas at room temperature the floating body effect s can be eliminated, this is only partially the case at cryogenic temperatures, as illustrated in Fig . 2 .55 for a 2 x 1-µm SOI nMOST operating a t 4 .2 K (152) . By grounding the film, the drain current is much flatter an d the hysteresis is suppressed . However, the kink effect is not avoided bu t rather increased . The reduction of the hysteresis and the suppression o f threshold voltage instabilities are related to the fact that a major part o f the multiplication-generated carriers is drained away by the contact and
E . A. Gutiérrez-D ., C . Claeys, and E . Simoe n
178 0 .-..
,–p Q
0 .01 0
float .
SQ 1 nMOST 20 µrnxi µm
VOS::5 V
0.00$ ` T=4 .2 K
" 4 V
3 V 2
0:0000
f
4MPdr#r 1
2
A
~
5
6
I V
3
4
Drain Voltage VDS (V)
0 .010 4C
0
~
coon,
SOI nMOST
,
0
20
6 V
~~.tnx! g.m
T=4 .2 K.
"e
s v 0 00e
w A... 0404
4
V
3
~,x
.e..«.
0
0,002 0 .000
VaS .:2 V
. 0
V
~
.-^~
1
2
3
4
Drain Voltage VDS
5
.
.s..
6
(V )
FIGURE 2.55. Output curves for a partially depleted SOI n-MOST at 4 .2 K with the body contact floating (a) or grounded (b) [after Simoen and Claeys (152)] .
thus not available for trapping or for charging the silicon film . The lower trapping probability will facilitate the forward biasing of the source—fil m junction and thereby enhancing the kink effect . In addition, one has t o take into account the high series resistance of the body contact a t cryogenic operation (153) . To some extent, this problem can be reduce d by implementing multiple or distributed film contacts at the expense of silicon area .
2 . Silicon Devices and Circuits
17 9
2 .3 .4 .2 . Twin-Gate Device s A very interesting design concept to avoid floating body effects is th e use of a so-called twin-gate structure (154) . As schematically illustrated in Fig . 2 .56, the twin-gate structure is realized by putting two commo n gate transistors in series . The middle reach-through n + region has a floating potential and serves to recombine the impact ionization generated holes . In fact, the structure consists of a master transistor TM with gate length LM and a slave transistor TS with gate length LS . Only the slave transistor will suffer from the floating body effects so that for sufficien t large LM / LS ratios the master transistor will have ideal output character istics . Not only the kink effect but also the parasitic bipolar effect are suppressed in the master transistor . This is illustrated in Fig . 2 .57, which shows the output characteristics of a single 1- and 2-,um transistor an d the twin-gate structure with a master of 1 pm and a slave of 2 µm an d with a master of 2 ,um and a slave of 1,um . It can clearly be seen that the latter structure is effective in suppressing the kink, in which case it ha s been made more pronounced by applying a negative back gate bias . From a design standpoint, the structure looks like a well-know n cascode MOS configuration . However, the basic operating principle i s different because the twin-gate essentially operates as a single transisto r according to the master—slave mode, whereas the cascode configuration operates like a tetrode and therefore requires a uniform voltage distribution over the two transistors . The twin structure is also very effective in suppressing the kink-related low-frequency noise (155), as discussed in
FIGURE 2 .56 . Schematic illustration of the twin-gate structure, together wit h the measurement configuration . The structure consists of a master (T M) and a slave (TS ) transistor in series, with a common source and gate [after Gao et al . (154)] .
180
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
~
;
r
S I n #s. k
.F
Twin, r ., . 2 .0
~;..~a ,;
4 [,t't,.>.'t` 'Twin., o,5
Li , ~
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/
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er°~^fi
,vy„w+.wa,,.,xa~u ~ ' -b.
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6?'~ w
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t•~'~ ~
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V
FIGURE 2 .57 . Comparison of the measured output characteristics for VGS = 3 V between twin MOSFETs with two different configuration of LM = 2 pm, LS = 1 pm (curve 3) and the case of an inverse twin with L M = 1 pm, LS = 2 pm (curve 4) . A negative back gate bias has been applied in order to make the kin k effect more pronounced and to assess the effectiveness of the kink suppressio n of the twin structure [after Gao et al . (154)] .
Chapter 3 . The practical applicability of the twin-gate concept fo r cryogenic applications has been demonstrated by studying the cryogenic performance of inverter structures (156) . 2 .3 .4.3. Gate-All-Around Device s Enhanced electrical device performance of thin film devices can b e achieved by using dual-gate devices with volume inversion, resulting in a significant improvement in the subthreshold swing, the transconductance, and the current drive capability (157) . The device is biased so tha t there is strong inversion through the entire silicon film . The curren t enhancement is much higher than expected due to the fact that there ar e two channels present. An optimized practical realization of the concep t is the so-called gate-all-around (GAA) structure, first proposed by Colinge et al . (158) (Fig . 2 .58) . The front and back gate oxides have th e same thickness and are of identical quality . For the device fabrication, only a few additional processing steps are needed compared to standar d SOI processing. After definition of the active areas, a cavity must b e etched so that the subsequent gate oxidation grows a thin oxide laye r around the resulting silicon bridge . The threshold voltage adjustment implantation is then followed by a low-pressure chemical vapour de -
2 . Silicon Devices and Circuits
18 1
FIGURE 2 .58 . Schematic illustration of the gate-all-around device for obtainin g volume inversion (158) .
position of polysilicon and patterning step . Both standard and GAA devices can be processed simultaneously . The superior performance of GAA devices is related to the higher transconductance and a subthreshold slope approaching the theoretica l limit of 60 mV/ decade at room temperature . The I ds – Vgf characteristic s for a 3 x 3-,um standard and GAA transistor are shown in Fig . 2 .59, clearly demonstrating the significantly improved subthreshold slope fo r the GAA device. Related to the subthreshold slope and coupled with th e volume inversion is the considerable reduction of the low-frequenc y
FIGURE 2.59 . Drain current in linear operation of a 30-nm, 3 x 3-µm GAA n-MOST compared with the drain current of standard SOI n-MOST of the sam e dimension [after Colinge et al . (158)] .
182
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
input referred noise (159) rendering these devices suitable for analo g applications . GAA devices show remarkable total dose hardness up t o the 30 Mrad level (160,161) . GAA devices also perform very well a t cryogenic temperatures down to liquid helium, although they migh t suffer from some voltage instability (162) . Somewhat unexpected is th e observation that the back gate has an impact on the GAA characteristics . This allows exploition of the previously mentioned MCCM effect .
2 .3 .5 . Deep Submicrometer Devices For ultra-thin film devices, quantization effects are not only importan t for the threshold voltage, but also may influence the transport propertie s in the silicon film, thereby modifying the transconductance . The trans conductance curve can exhibit oscillations and a step-like behavio r (117, 163, 164) . Although the scattering processes governing the carrie r mobility may cause oscillations, it has been postulated that local deviations in the film thickness are the underlying cause . These are relate d to the morphology roughness of the film—BOX interface . It should b e mentioned, however, that local fluctuations of the oxide charge at the to p BOX layer cannot be excluded . The anomalous transconductance behavior has been observed at both room and cryogenic temperatures . To model the mobility variations, one has to take into account that th e surface inversion layer can be larger than the silicon film thickness . To study the impact of quantum mechanical effects on the transpor t properties experimentally, silicon quantum wire structures have bee n fabricated (165—167) . The carrier confinement in the 2D electron gas i n the silicon film results in a splitting of the conduction band int o subbands . The filling of these subbands with electrons appears as a n oscillation in the current transport and associated transconductance . Th e potential change DF in the film can be modeled by the following equation (165) :
A O (vGf) -
h2 8m
~
t f2
[n 2 — (n — 1) 2 ]
(2 .107)
where h is the Planck's constant, m* is the effective electron mass i n silicon, and n is the quantum number for the different subbands . A typical transconductance curve for a 50-nm-wide GAA quantum wire fabricated on a SIMOX substrate is shown in Fig . 2 .60 for operation at 1 .5 K . The quantization of the drain current can be clearly observed a s local kinks . The oscillations remain present up to about 40 K and 20 mV source—drain voltage (165) .
2 . Silicon Devices and Circuits
70 60 50
183
~. Vsd..–.200 g V
f=14 .aH z .,. T.=1 ..5 K L=.2$.Lm pm
oVg -0 .7 V ~----.~~•+
C75" 40
C5
(9 30 20 10
—
0 .0
VT 1 .0
2 .0 Vg [V ]
3 .0
FIGURE 2.60 . Transconductance as a function of the gate voltage for a 50-nmwide silicon quantum wire GAA structure operating at 1 .5 K [after Morimoto et al. (167)] .
Figure 2 .61 illustrates the conductance fluctuations in a 200-nm-lon g and 100-nm-wide channel of an SOI MOSFET operating at 300 mK (168) . The spatial potential variations in the channel lead to the formation o f islands or quantum dots, the size of which determines the oscillatio n period of the conductance modulation . The spikes observed in Fig . 2 .61
~.Ox104 -
a 4 .Ox104 , ...
~
ca
'g 2 8 2.0004 -
0 .0 ,/ f8
1 .0
~
1 .2 Gate Voltage (v)
... . ..
t
1 ..4
FIGURE 2.61 . Transconductance as a function of the gate voltage for a 200-nmlong and 100-nm-wide SOI MOSFET at 300 mK [after Peters et al . (168)] .
184
E . A . Gutiérrez-D ., C . Claeys, and E. Simoe n
(e .g ., at Vgf = 1 .3 V) are caused by random telegraph signals in the drai n current with typical time constants from hundreds of microseconds t o tens of seconds (169) . Future scaling down of the device geometries will be limited b y physical constraints so that phenomena such as ballistic transport , tunneling, and quantum mechanical effects may control the devic e operation. Although 70-nm MOSFETs have already been fabricated, the 1997 Semiconductor Industry Association (170) road map is predictin g that in approximately the Year 2015 a 30-nm feature size will be revised . This implies that research into so-called nanoelectronics will become o f key importance . Whereas for a long time this research domain wa s reserved for III—V compounds, silicon-based devices are just around the corner . A particular class of devices gaining increasingly more interest i s the single electron transistors, based on the Coulomb blockade . Although currently processed mainly on bulk material, SOI substrates may provide some benefits . The operation of single electron transistors (SETs) is based on the fac t that the device capacitance is sufficiently small so that a single electro n leads to a detectable voltage change . These structures require a smal l silicon island separated from the source and drain electron reservoirs b y tunnel barriers and capacitively coupled to the gate electrode . The device performance strongly depends on the operating temperature . In general, the minimum operating temperature is given by
T « (q 2 /2kC)
(2 .108)
The Coulomb charging energy of a single electron must be larger tha n the energy of the thermal fluctuation kT. Therefore, the original SETs were operating at liquid helium temperature or below ; otherwise, the needed capacitance was too small, imposing difficulties from a fabrication standpoint. If the dielectric layer between the two capacitor plate s is sufficiently small, an electron can tunnel from one capacitor plate t o the other . A recent in-depth overview of the different theoretical an d experimental aspects of SETs was given by Smith (171) . For 77 K operation, it is required that the capacitance be strongly reduced (to a few aF) by, for example, using extremely small geometries, whic h imposes tremendous technological challenges . However, SETs successfully operating at 20 K have been reported (172) for devices processed b y using the so-called step edge cutoff (SECO) fabrication scheme, allowin g less stringent lithographic techniques to be used . A further optimization of these SECO SETs recently resulted in 77 K operation of SETs fabricated in a 0 .1-,um technology (173) . In principle, the operation of a SE T can be explained by studying the charging effects in the silicon cavity , which are also the basis of the MCCM effect . In this case, however, the
2 . Silicon Devices and Circuits
18 5
size of the cavity is so small that charging by a single electron has a measurable effect on the electrical performance of the structure . In th e 1980s most of the SETs were fabricated in III—V materials . A popular fabrication concept to study the physical aspects involved, such a s Coulomb blockade and quantum effects, is based on the split-gate desig n (174, 175) . The split gate can be either the upper or the lower level . Such a dual-gate concept has also been successfully applied to SOI structures (176) . The Coulomb blockade oscillations were demonstrated at 15 mK , in which case the observed 16 .4 mA periodicity allows the estimation o f an involved capacitance of about 13 aF . The development of single transistor memory cells provides a grea t potential for SETs to be used in the design of nonvolatile RAMs, fo r example, for mobile computer and communication applications (177) . The real breakthrough will of course depend on the required operatin g temperature, although there are strong indications that further improvements may eliminate the requirement for cryogenic operation . The feasibility of a room temperature SET memory, processed on a SO I substrate, has been demonstrated (178) . The operation is based on a narrow-channel transistor with 10-nm width, i .e ., smaller than the Debye screening length, and the use of a very small (7 x 7-nm) floating gate between the channel and the control gate . A single electron on th e floating gate will, even at room temperature, lead to a quantize d threshold voltage shift . 2 .3 .6 . Summary This section outlined the basic operating principles of the different type s of SOI transistors . Special attention was given to the potential for usin g SOI CMOS in cryogenic applications . SOI technologies are no longer restricted to niche markets but are gaining increasingly more interest fo r technologies with deep submicrometer feature size . It is expected that a real commercial use of high-volume products will be developed in the near future . Additionally, for future nanoelectronic applications, such a s single electron devices and quantum wires in silicon, the unique feature s of SOI devices may lead to a real breakthrough . Although the market o f commercial applications will increase, SOI also has a strong potential for cryogenic electronics .
2 .4 . THE BIPOLAR TRANSISTO R The bipolar transistor has been and is currently one of the leadin g devices that has pushed the evolution of high-speed communication
186
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen
systems . Bipolar technology evolved from the traditional bipolar structure (179) to the polysilicon emitter bipolar structure (180) and to the most advanced heterojunction bipolar transistor (HBT) (181) . This evolution has led to an impressive advancement in the high-speed communi cation systems, in which cutoff frequencies of 115 GHz (182), have been reached . The bipolar transistor has been combined with MOS transistor s in the BiCMOS technology (183) to obtain the best of both technologies : high speed from the bipolar transistors and low power consumption from MOS. For applications in which the operating temperature need s to be lowered to cryogenic temperatures, the MOS transistor behave s well, whereas the bipolar transistor suffers from freeze-out in the bas e which inhibits its use as a transistor . However, the bipolar transisto r which has a base made of a SiGe alloy, the HBT, does not suffer fro m freeze-out effects and is able to operate properly down to temperature s below 77K . In this section, the main figures-of-merit of the bipolar transistor will be presented and analyzed as a function of the operating temperature . The different bipolar technologies available today will also be presented, and their advantages and disadvantages as devices for cryogenic applications will be discussed . 2 .4 .1 . Bipolar Technologie s As in the case of MOS transistors, there exists a considerable variety o f technologies to fabricate bipolar transistors . However, we will restric t our discussion to the most representative ones, namely, the standar d bipolar transistor (SBT), the polysilicon emitter bipolar transistor (PEBT) , and the HBT . 2 .4.1 .1 .
The Standard Bipolar Transisto r
The SBT was first developed by Bardeen and Brattain (184) in 1948 . However, the structure first developed in 1948 was not of a practical us e for high-speed electronics because of the thick base dimensions . Thus, the development of solid-state impurity diffusion technology in 196 5 gave birth to the so-called planar bipolar transistor, which for practica l purposes we consider standard . The cross section of this SBT is shown in Fig . 2 .62 . The p-type base and n + -type emitter are implanted in such a wa y that the thickness of the base region, the region between the bottom o f the emitter and the top of the collector, is well controlled and kept short . By keeping a short base width, the speed of the transistor increases . The previously described technology has several limitations, including a
2 . Silicon Devices and Circuits
18 7
FIGURE 2 .62 . Cross section of a SBT fabricated with impurity implantation an d diffusion technology.
large parasitic capacitance and resistance and a relatively deep base junction that does not allow for high cutoff frequency fT . To overcome this problem, the PEBT is introduced .
2 .4 .1 .2. The Polysilicon Emitter Bipolar Transisto r The first PEBT was proposed in 1973 by Takagi et al (185) . They utilized a doped polysilicon layer as a diffusion source to form the emitter . Thi s layer also serves as a contact for the emitter . The structure looks like the one shown in Fig . 2 .63 . This structure has the advantages of reducin g parasitic components, reducing contact resistances, reducing size, an d increasing cutoff frequency, and it is less sensitive to temperatur e compared with the SBT . This structure is about one-third the size of th e standard planar bipolar transistor .
FIGURE 2.63 . A PEBT structure using the super-self-aligned technique .
188
E . A . Gutiérrez-D ., C . Claeys, and E . Simoe n
The electrical characteristics of a PEBT differ from those of a SBT in that the carrier transport takes place through the interfacial layer between the polysilicon and the monosilicon layers . A complete study an d technological description of the PEBT can be found in Kapoor an d Roulston (186) .
2 .4.1 .3 . The SiGe Heterojunction Bipolar Transistor The SiGe HBT is the only Si-based device with electrical characteristic s comparable to those of III—V-based devices . The SiGe HBT perform s much better than the standard bipolar and the PEBT, and it is als o compatible with existing Si technology . The HBT was first demonstrated in the late 1980s (187) . Actual SiGe HBT fabricated with selectivel y grown SiGe base (188) is shown in Fig . 2 .64 . Devices fabricated with thi s technology have reached fT frequencies in the range of 30 GHz (189) . An excellent review of the technological characteristics of SiGe HBTs can b e found in Luy and Russer (190) .
2 .4 .2. Electrical Performance In order to understand the differences in performance among these thre e technologies and their behavior as a function of temperature, it i s necessary to examine their operating principles .
FIGURE 2.64 . Cross section of a SiGe HBT fabricated with selectively grow n SiGe base.
2 . Silicon Devices and Circuits
189
2 .4.2 .1 . The Collector/Base Currents and the DC Gain hF E We consider npn transistors only . Thus, the collector le current of a standard bipolar transistor lc , (191), a PEBT J,p (192), and a SiGe HBT Ic h (193), are modeled by Ics
qD n n i
=
2 [
eVBE/Vt
_ 11
(2 .109 )
QBeff T4
Icp —
Cc
, e(RVBE —Egb/kT )
(2 .110 )
(\Pb T )
and Ich
qD n n iSiGe
2
,
QB eff
[
eVBE/vt —
1]
(2 .11 1 )
where D. is the diffusion constant for electrons in the base, n i is the Si intrinsic concentration, VBE is the emitter-base voltage, Vt is the thermal voltage, and QBeff is the integral of the base dopant inside the neutral base known as the Gummel number . This "effective" Gummel number which accounts for degeneracy and band gap narrowing effects i s modeled by (194) 2
QBeff
ni0 n ib
•
Na
L tanh (Z5b)
(2 .11 2 )
where n î0 2 is the equilibrium pn product in undoped silicon, n ib 2 is the intrinsic concentration in the base, L n is the diffusion length for electron s in the base, and Wb is the base width. The following parameters are used in Jcp : C c is a constant (195), p b (T) is the temperature-dependent sheet resistance of the base, which ac counts for the temperature dependence of the carrier mobility, and E gb is the band gap in the base . For the Ich current, the only difference is the nisiGe, which is the intrinsic carrier concentration of the SiGe layer, given by (196 )
n iStGe • 2 = n i Si 2
e(oEg/kT)
= n iSi 2
2 ~
F 1/2
Ev
k1, EF
e [(EF — Ev) — BGN /k T]
( 2 . 113)
where nisi is calculated following the Boltzman statistics, whereas n isiG e considers Fermi—Dirac statistics to account for band gap narrowing (BGN) occurring in the highly doped base of the HBT . The base currents JB for these three different bipolar devices are written as follows : For the SBT, if recombination in the neutral base a s well as in the emitter—base space charge layers is neglected, the bas e
190
E . A . Gu tiérrez-D ., C. Claeys, and E . Simoe n
current IBs is considered to be formed of pure injected holes into th e emitter:
Dp ni 2_ Ls
[e
Q Eeff
VBE/vt —
(2 .114 )
]
where QEeff is the Gummel number for electrons in the emitter, simila r to Eq . (2 .112) except that Na is replaced by Nd , D. by Dp, n ib by nie, Wb by We , and L n by L p . The base current for PEBTs, 'Bp, consists of tunneled holes into the emitter (192) : 'Bp =
kT
n1e2
27cmh*
Nde
e_1
(1
(gVBE/kT )
C hkT)
(2 .115 )
where
Ch =
(2ic5)
/2mh *
h
g xh
4 c~ )\/2mh*qxh 7
bh
h
(2 .116 )
(2.117 )
where, x h is the barrier height of the emitter—base potential barrier, and b is the thickness of the emitter—base interfacial oxide . The base current, IBh, for the SiGe HBT is given b y IBh
( D P n iSiGe2 )
QEef f
eVBE/vt , e — AEg/kT —
1 []
Under BE forward bias conditions, the DC current gain hFE can be defined for each of these devices . For the SBT, the current gain, hFEs, is given by h FEs=
DnNE
WE Dp NB WB
(2 .11 8 )
= (IC /IB )
(2 .119 )
where NE and NB are the doping concentration of the emitter and base , respectively. For the PEBTs the current gain, h FEP , is given by T° . 5
(1 — Chloe — (AEge — AEgb/kT)
h FEP = C e
(2 .120)
Pb
and for the SiGe HBTs, the current gain, hFEh, is given by
h FEh
(Dfl NE WE . e(AEg/kT ) Dp NN WB
(2 .121)
2 . Silicon Devices and Circuits
191
It can be readily seen that for achieving a high h FE in SBTs a high emitter-to-base doping ratio is needed, which implies a low base doping level . On the other hand, low emitter current crowding and low nois e require a low resistive base, which leads to slow switching devices tha t require a thin base . In the case of PEBTs, faster switching devices can be obtaine d because a thinner base can be obtained . At the same time the base current is reduced due to the presence of a potential barrier and a remnant native oxide layer in the EB interface . For the case of SiGe HBTs, the intrinsic concentration n isiGe plays an important role . For instance, a band gap difference AEg between the Si and SiGe systems of, for example, 200 mV, implies an increase of 2300 i n the ratio (nisi / iSiGe), which reflects a similar increase in the collecto r current, whereas the base current remains constant . In other words, the current gain of a SiGe HBT will be higher than that of a SBT by a facto r of e (AEglkT) . However, the advantage of the HBT resides not in the curren t gain but in the base that can be highly doped . This means that the base doping level can be much higher than the emitter doping level, where the high current gain is kept by the exponential factor . A high base doping level allows a reduction of the base resistance as well as the bas e thickness, which results in a short transit time and a high cutof f frequency . Now the question is how do these technologies behave as the temperature is lowered to the cryogenic regime . The answer is given in Fig. 2 .65 . The subscripts a and b in Fig . 2 .65 indicate two different EB interface oxide thicknesses for the PEBTs reported in Ashburn and Soerowirdj o (192) and Van Halen and Pulfrey (197), respectively . The subscripts 0 . 5 and 1 .0% indicate two different contents of C in the base of the SiGe HBTs as reported in Jayanarayanan et al . (198) . When lowering the operating temperature, the SBTs and PEBTs sho w a decrease in the current gain h FE due to freeze-out of the base . A theoretical extrapolation to 77 K would give a negligible value for hFE . The opposite behavior is observed for the SiGe HBTs . Because th e current gain hFE depends exponentially on the amount of Ge in the bas e divided by kT. The introduction of Ge into the Si base reduces the band gap by a AE g amount . Also, the temperature dependence of h FE depend s on the absolute value of AE g : The larger the AE g , the larger the increas e in h FE at low temperatures . However, the amount of Ge that can be introduced into Si is limited by the stability of the SiGe alloy . This constraint can be alleviated by introducing C into the SiGe alloy as proposed by Jayanarayanan et al . (198) . This is shown in Fig . 2 .66, whic h indicates the AE g dependence on the contents of Ge and C .
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
192 105
I
I
I
I
I
=
HBT~ .0 % PEBT b . :
_ ._~_~:__ - -
. .., â~10 3 _
, . .. . . . . HBT
100
,
_
0 .5%
PEBTa -
_
-°-
'
SB T
10 0
, ,
„
„ . , „ i 200 300 400 Temperature, T [K ]
100
►
►.
500
.
600
FIGURE 2.65. Current gain h FE as a function of temperature for standar d bipolar SBT, PEBT, and SiGe HBT transistors (with 0 .5 and 1 .0% of carbon in the base) . The experimental data have been replotted from Ashburn and Soerowirdj o (192), Van Halen and Pulfrey (197), and Jayanarayanan et al . (98) .
300 0 _
4
8
Ge fraction [% ]
12
16
20
24
28
32
~
0 .0 0 .50 1 .0
1 .5 2 .0 2 .5 3 .0 3 .5 4 . 0 C fraction [% ]
FIGURE 2.66 . Band gap shift for SiGe alloys as a function of C and Ge fractions [replotted from Jayanarayanan et al . (198)] .
2 . Silicon Devices and Circuits
19 3
200 2 .0 % C r-, N
-
150
C7
1 .5 % C 1 .0 % C
`
50
• 1
50
1•
,
1 100
• ~
1
1
1
150
1
1
1
1 200
1
1
1
1
250
1
1
1
1 300
1
1
1
350
Temperature, T [K ]
FIGURE 2 .67. Cutoff frequency f, as a function of temperature for Si SBT an d SiGeC HBTs with various percentages of C in the base [replotted fro m Jayanarayanan et al . (198)] .
Another figure-of-merit is the cutoff frequency fT' which is also a function of temperature . A straightforward implication of freeze-ou t effects in the base of SBTs and PEBTs is a drastic reduction of the fT a t cryogenic temperatures . The inclusion of C into the SiGe base reduce s both the emitter and the base transit times at low temperatures, whic h results in an enhancement of fT (Fig . 2 .67) . The enhancement of fT at cryogenic temperatures is obvious for C contents above 1 .0%, and it can reach a fT of 180 GHz at 77 K. The Early voltage VA has a temperature dependence similar to that of fT• The h FE , fT' and VA , depending on the application, can be traded by tailoring th e band gap guarding in the base region . 2 .4.3 . Summar y The fundamentals of the three main bipolar transistor structures an d their electrical performance as a function of temperature have bee n analyzed in this section . The best bipolar device in terms of speed i s the HBT, with its base made of a SiGe alloy . Thus, this band gapengineered Si-based technology provides better cost performance tha n compound semiconductor technologies while maintaining compatibility with BiCMOS processes .
194
E . A. Gutiérrez-D., C . Claeys, and E . Simoe n
On the other hand, in terms of cryogenic performance, the SiGe HB T is the only bipolar device capable of operating properly . If SiGe HBT ca n be combined with Si CMOS, then this combination will offer uniqu e advantages for cryogenic systems in which very high-speed systems , with low power-delay product will be able to be fabricated in a monolithic way .
2.5 . RADIATION DETECTORS A radiation detector can be defined as a transducer that creates an electronic signal in the presence of an optical signal, in which the electroni c signal is correlated to the optical power and wavelength of the optica l signal . A large variety of devices exist that detect an optical signal fro m soft X-ray to deep ultraviolet (UV), UV, visible, near infrared (IR) , medium IR, and the far IR wavelength range . These devices are used in a large variety of applications . The CCD is the most versatile among the optical detectors . The CCD is capable of detecting signals from 1 x 10 - 4 up to the 1 .1-µm wavelength range, with a quantum efficiency of 40% , high spatial resolution of up to 2048 x 2048 pixels, and a noise leve l below 7 e - rms. This gives the CCD a competitive edge over other U V imaging detectors (199) . In the visible range of the optical spectrum, from about 0 .38 to 0.77-µm wavelength range, the photodiode has become the most widely used photosensor as well as the most used device for solar conversio n in both terrestrial and space applications. Silicon photodiodes are particularly outstanding in applications requiring high accuracy . During the 1980s, high-quality silicon photodiodes were developed that had a high level of accuracy and precision in the visible range which exceeded tha t available from calibration against the radiometric standards and tech niques existing at that time (200) . This resulted in the creation of ne w calibration techniques for radiometric instrumentation and calibration standards (201) . Recently, radiometers based on planar silicon photo diodes have been shown to have calibration uncertainties on the orde r of + 0.0003 at 0 .855 and at 0 .442 ,im (202) . Further development of this kind of radiometer has shown an uncertainty smaller than 0 .0001 (203) . For the IR wavelength range detectors are used to detect, image, an d measure patterns of thermal heat radiation that many kind of object s emit . The PbS detector was the first IR detector and was developed in the early 1940s (204) . A decade later a wide variety of new materials were developed, giving rise to the next generation of IR sensors (205) and extending the spectral range to the 3- to 5-,um mid-IR range . Thes e materials included PbSe, PbTe, and InSb . The use of other materials,
2. Silicon Devices and Circuits
19 5
such as copper, zinc, and gold impurity levels in Ge, made possible the development of extrinsic photoconductors in the 8- to 14-µm long wavelengths IR spectrum . By the early 1960s, the semiconductor alloy s in III—V, IV—VI, and II—VI appeared . The appearance of these alloy s gave rise to band gap engineering, allowing for the possibility to tailo r the energy band gap for specific applications . The most representative alloy of that time was HgCdTe (206), which remains the most widely used of the tunable band gap materials . At the same time, the development of the IC fabrication techniques, especially photolithography mad e possible the fabrication of IR sensor arrays . Thus, linear array technolog y was applied to PbS, PbSe, InSb, and Hg-doped germanium detector s (207) . Because the activation energy of Hg—Ge is 0 .09 eV, it had to be cooled down to 25 K . The development of HgCdTe photoconductive detectors (208) allowed IR systems to operate at 80 K. Since then , due to the compactness and lightness of cryosystems, the HgCdT e linear arrays have been produced in high scale . When the HgCdTe linear arrays were being produced on a large scale for use in tactica l imaging systems, extrinsic silicon devices were being developed to largely replace extrinsic Ge in many applications in the 14- to 30µm IR wavelength range . Extrinsic silicon detectors can be made with significantly larger IR absorption coefficients than Ge in the 20-,um range (209) (Fig. 2 .68) . The intensive and extensive development of modern IC fabrication technology during the past 10 years has resulted in a strong impact o n
I
-
Ge:Au
_ //'--\
N
1012
* 10 A^
/
!,)(u
PbTe ,. . .
PbS
(77 K)
11
. ..,
-
_
-
101 0
Cc:Ca (4. .2 K)
_ ^
ti
(77 K)
HgCdTc
(77 K )
(4 .2 K)
Ge :Cu
~
~ ,.
(77 K )
=
_
- ,
[nSb (77 K ) ,~ -' ~i
~ Ge :Au . = _ ~`,., --~ -
I
(77 K)
Si :P
; .
.
(4 .2 K ) Ge :Zn (4.2 K )
.
PhSnTe (77 K)
10 9
1
10
, 100
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196
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the development of new types of silicon-based IR radiation detectors . This has provided the opportunity to integrate the detector with th e silicon signal processor on the same chip (210) . However, for far IR, Ge continues to be the dominant material in the production of detectors . Strained Ge detectors have extended the spectral response of IR detectors up to about 200 µm (211) . Under very low background radiation levels , there are dielectric relaxation effects in extrinsic devices, which make th e device less immune to the noise . These effects have been eliminated with the introduction of the so-called blocked impurity band detectors (BIBs) . These detectors are based on light detection in a thin, highly doped , sensitive layer . They feature less radiation sensitivity, increased spectra l coverage, less cross talk, and higher stability after irradiation tha n standard photoconductors . BIB detectors are ideal for the realization o f large arrays with far IR response down to 250 ,um . Si :P BIB detectors have also been successfully flown in the Kuyper aircraft observator y (212) . In the 1990s, Si-based detectors reappeared as a leading technology . Silicide Schottky barrier detectors (SBDs) are now widely used a s vacuum and UV detectors (213) . Further development of SBDs ha s resulted in an extension of the cutoff wavelength from the conventiona l 3- to 5-,um mid-IR to the 5 .7- to 22-µm range by incorporating a thin p + doping spike layer at the PtSi—silicon interface (214, 215) . Anothe r development in the IR range is the 1040 x 1040 IR charge sweep devic e imager based on PtSi Schottky barrier detectors (216) . Recently a VLSIcompatible, high-speed silicon photodetectors for optical data link applications has been proposed (217) . Following the trend in the development of radiation detectors, the evolution toward monolithic radiation detector systems is evident. As such, the potential of Si-based detectors is very promising. Because of the low-temperature operability of the CMO S technology, the CMOS-compatible radiation detectors seem to be th e natural candidates to occupy the leading position as cryodetectors . The purpose of the following sections is to describe the optical properties o f silicon at low temperature, give a review of the several Si-based radiation detectors for low-temperature operation, and outline the curren t trend and future perspectives for low-temperature optoelectronics .
2 .5.1 . Optical Properties and Extrinsic Detection Silicon is one of the most extensively used semiconductors in th e fabrication of radiation detectors for low-temperature operation . Most o f the observed optical, electrical, and thermal parameters of silicon, suc h as energy band gap, carrier mobility, and thermal conductivity, ar e available in analytical forms, based on either known theories or experimental data . However, in an attempt to discuss the optical properties o f Si as a function of temperature, we were not able to obtain from the
2 . Silicon Devices and Circuits
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literature a complete description of the temperature dependence of all the optical properties of Si . Therefore, we focus on the extrinsic photo conductivity of several impurity atoms in Si at 4.2 K and the absorption coefficient of Si . Many impurity elements produce energy levels in Si that allow Si t o be used as an IR detector . Some of these energy levels are below or abou t 0 .045 eV, including phosphorous (P) and boron (B), from either ban d edge which means the detector's spectral response can be extended t o 28 µm (Fig . 2 .69) . Another interesting feature of silicon is its high absorp tion coefficient a (Fig . 2 .70), which allows for the possibility of smalle r size detectors (218) . Extrinsic detectors are fabricated by the addition of impurity atom s into the Si host crystal . Thus, the properties of these detectors resul t more from the characteristics of the impurity atoms than from the hos t crystal. Therefore, the photosensivity of these detectors is called "extrinsic" detectivity. Impurity ionization energies in Si range from 0 .033 t o 0 .41 eV (Table 2 .1) . Therefore, the long-wavelength cutoff for conductivity can range from 3 to 28 ,um . This wavelength spectrum span o f sensitivity gives Si a versatility that has been one of the key factors i n their use as a IR detector during the past 20 years . Among the most use d detectors for the mid- and far IR spectral region are the stressed Ge :G a IR detectors (219) and the extrinsic Si :P mid- and far IR detector (220) . The stressed Ge :Ga photoconductors are the most sensitive low back ground currently available for the spectral region between 120 an d 200 µm . They have been used in the Infrared Space Observatory (221) . On the other hand, for the spectral range of about 2 = 20 ,um, Si :P has proven to be integratable and submicrometer CMOS compatible (220) . I n
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this approach the n-well of a submicrometer CMOS technology has bee n implemented as the photodetector . The spectral response of the stresse d Ge :Ga detectors operated at 4 K is shown in Fig . 2 .71 . The n-well detector connected to an n-MOS transistor was radiate d with a 2 = 0 .768 pm laser pulsed at a frequency f = 5 Mhz (Fig . 2.72) . The output voltage Vo as a function of time is shown in Fig . 2 .73 . The response time of this detector is on the order of 15 ns, and the dark-tolight current ratio is on the order of 5 x 10 6 . However, extrinsic Si photodetectors when placed in arrays have several drawbacks, such a s
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2 . Silicon Devices and Circuits
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FIGURE 2.72 . A 4 .2 K CMOS optical detector (220) . cross talk between closely spaced detectors, spatial nonuniformity of the optoelectrical response, "memory effects," and spurious current spikes . One way to circumvent these problems is by using BIB detector (222) . These detectors are based on light detection in a thin, highly doped, sensitive layer (Fig . 2 .74) . They feature less radiation sensitivity, large r spectral coverage for constant responsivity, less cross talk, and superio r uniformity of response over the detector area and from detector to detector. The BIB detector employs a thin undoped blocking layer (BL ) between a heavily doped infrared active layer (IRL) and a transparen t contact layer, which is formed in the BL by implantation of As . The structure lies on a silicon substrate . The IRL is doped with As .
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This structure makes possible the creation of avalanches in a 4-µm (W) high electric field region of the device in response to photo n absorption . This Si-based device is capable of detecting individua l photons in the 0 .4- to 28-,um wavelength range, with submicrosecond response to incident radiation, at T = 7 K . At a bias voltage of 5 V, th e gain M of this device is 2 x 10 4 . 2 .5 .2 .
Photodiodes
and Schottky Barrier Detector s
Basically there are two devices capable of detecting radiation from th e soft X-ray (1 x 10 - 4 ,um) to the UV (0 .33 pm) ; the SBD and the CCD. Both devices are capable of increasing their spectral response up to the IR range . However, here we focus on photodiodes and SBDs; the CCDs wil l be discussed later . Semiconductor photodiodes, originally designed for the visible spectral range, can also be used in the X-ray region . In the vacuum UV and sof t X-ray regions, however, the absorption lengths of all materials are ver y small, typically on the order of 20—200 nm. Therefore, semiconducto r detectors suffer from absorption losses in insensitive layers near the surface and thus have not been used . However, diffused and Schottky diodes have been shown to operate very well as soft X-ray and UV detectors (223 -225) . In the diffusion diode a depletion layer is formed between the p- an d n-doped layers (Fig . 2 .75a) . For the Schottky diode (Fig. 2 .75b) the depletio n layer is formed in the metal—semiconductor interface . Any photon absorbed in the semiconductor will produce man y electron—hole (e—h) pairs . When these e—h pairs are created in the depletion layer, they are swept by the electric field and collected as a n external photocurrent . In both detectors the radiation is mostly absorbe d in a "dead layer," which in the case of the diffusion diodes is composed
2 . Silicon Devices and Circuits
201
FIGURE 2.75. Device structure of diffusion and Schottky Si diodes . of SiO2 and part of the p-type material and has a thickness of 30–100 nm . For Schottky diodes, this layer consists of a thin metal film of abou t 10 nm . The absorption length in this spectral range is very small ; therefore, the response of these diodes is strongly reduced by th e absorption in the dead layer . The response of a radiation detector i s generally defined by its quantum efficiency r~(E) or by the responsivity s(E) . The quantum efficiency of a semiconductor photodiode is define d as the number of e—h pairs created by an incident photon of energy E, whereas the responsivity is the photocurrent per incident radiatio n power . Both n(E) and s(E) are related b y
s(E) = q where q is the electronic charge . Because the mean e–h pair energy w i s independent of the energy of the absorbed radiation (E » w) (225), the quantum efficiency of a perfect semiconductor detector should increas e linearly with the radiation energy, whereas the responsivity would be a constant, corresponding to the reciprocal of w . This behavior is modified by the absorption in the dead layer, which is most important at lo w energies, and by the penetration of photons through the depletio n regions at higher energies . The semiconductor diodes investigated b y Krumrey et al . (225) were commercially available photodiodes in which the glass or silica window were removed . The devices were tested in the photoamperic mode at a 2 = 0 .01 µm (E = 124 eV) . The stability of the photodiodes under ionizing radiation was measured . The experimental results are shown in Fig . 2.76 . The quantum efficiency decreases from it s initial value of = 27 to 10 at 400 s and to 8 at 1500 s. It is easily observed that these Si photodiodes show radiation-induced instabilitie s which would make them unsuitable for use as radiometric standards
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(226) . Results on the efficiency, stability, and spatial uniformity of a ne w class of Si photodiode have been reported by Canfield et al . (226) . The performance of this photodiode seems to be attractive for radiometric applications . These devices are N-on-p windowless photodiodes with a 1-cm 2 circular active area fabricated on <111> silicon wafers using P o r As diffusion . Figure 2 .77 shows the device structure . The active region oxide thickness is in the 20 to 250-A thickness range . This device wa s tested in the 3 .9- to 124-eV energy range (0 .318-0 .01 sum) . The measure d quantum efficiency of As- and P-doped photodiodes with two differen t oxide thicknesses is shown in Fig. 2 .78 . The oxide thickness is 77 A fo r P- and 44 A for As-doped devices . From these experimental data, one can see that the quantum efficiency for this photodiode nearly approache s the theoretical predicted slope of 3 .63 eV per e-h pair created (227, 228), regardless of whether the dopant is P or As . Near 10 eV the absorption of SiO 2 is at its maximum and efficiency differences between device s with different oxide thicknesses would be expected .
FIGURE 2.77. Device structure of the photodiode proposed by Krumrey et al. (225) .
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The efficiencies of several devices with different oxide thicknesses are shown in Fig . 2 .79 . The oscillations in efficiency suggest optical interference related to oxide thickness . Experimental results of these kinds o f detectors show a very good stability for oxide thicknesses thicker tha n 46 A . With careful processing and control of passivation layer thicknesses, predictable efficiencies and relative immunity to exposure dam age can be achieved with these detectors . The operation of SBDs is based on internal emission at the interfac e between a thin PtSi and a p—Si substrate . Conventionally, these device s are operated in the back-illumination mode . IR photons with energie s
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FIGURE 2.80 . Schematic diagram of a PtSi/p—Si Schottky barrier detector . less than the band gap of Si are transmitted through the substrate an d absorbed in the silicide film, where they generate the photocurrent . On the other hand, visible and UV photons, which have energy higher tha n the band gap, are absorbed in the Si . The absorption depth, whic h decreases rapidly with increasing photon energy, is approximately 5 p m at energy E = 1 .55 eV (2 = 0 .8 um) and reaches a value of approximatel y 0 .004 pm at E = 4 .428 eV (2 = 0.28 ,um) . Because the thickness of a typica l Si wafer is 400—500 pm and transport of photogenerated carriers towar d the silicide—Si Schottky barrier junction occurs primarily by diffusion , carrier collection is slow and inefficient . Furthermore, for the shorte r absorption lengths, especially in the blue and UV regions, a larg e fraction of the carriers generated in the Si can easily be lost by surfac e recombination . Consequently, UV/visible response of back-illuminate d detectors is generally too low to be of practical interest . Front-illuminated PtSi/p—Si SBDs exhibit excellent UV/visible photorespons e with little loss of IR response (229) . Front-illuminated detectors can b e useful for applications requiring multispectral imaging . The schematic diagram of a PtSi/p—Si SBD is shown in Fig . 2 .80 . This PtSi/p—Si SB D has been tested in a front-illuminated 160 x 244 element focal plane array integrated with a monolithic CCD readout circuitry (230) . This array was cooled to 77 K. The temporal UV, visible, and IR response of p-type detectors in both front- and back-illuminated operation has bee n measured for temperatures ranging from 10 to 80 K . The response is fas t enough for operation at video frame rates, except for back-illuminate d operation at temperatures of 30 K or below for values of 2 close to the S i absorption edge . The experimental results for the p-type detector operated in the front-illumination mode is given in Fig . 2 .81 . The kink observed in ii around 1 .0 eV in Fig. 2 .81 corresponds to the band gap of Si at 40 K. Note that ii decreases gradually with increasin g 2, exhibiting the wavelength dependence that is characteristic of interna l photoemission in a Schottky barrier . In the wavelength region beyond 1 .0 um the photoresponse is due to carriers generated by absorption in the PtSi film. The reduction in 17 for larger wavelengths is due to
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206
E. A . Gutiérrez-D ., C. Claeys, and E . Simoe n
FIGURE 2.82 . Pixel cross section of the 1040 x 1040 PtSi SBD (232) .
ground-based imaging, spectroscopic, and radiometric applications . Pro posed space applications include an X-ray imager on NASA's Advance d X-ray Astronomical Facility, a space telescope Imaging spectrometer, the solar optical telescope, and the comet rendezvous /asteroid flyby imaging subsystem . Despite the wide variety of applications for CCDs, ther e remain some drawbacks for their use . CCDs are very expensive ; a backside illuminated 2048 x 2048 CCD costs about $80,000, and CCD s with standard TV resolution range cost from $2000 to $10,000, depending on their performance and quality . However, what is most expensive in the use of CCDs are the auxiliary electronics and computers used t o make them work . CCD cameras and imagers generate a huge amount o f data . For example, a single 2048 x 2048 CCD image holds the same information as a 7-million-word book . This implies a very heavy data processing task, which requires expensive storage media. The high quantum efficiency performance of the CCDs has bee n possible because of the implementation of two techniques to control the backside surface potential: backside charging (233) and flash gate (234) . 4 Using either of these techniques, excellent photoresponse from 1 x 10 to 1 .1-,um wavelength range are obtained for soft X-ray to near IR . For front-illuminated CCD the transmittance of the signal contains bot h reflectance and significant absorbance components from the gate oxide structure . As a result of this absorption and scattering loss term in th e polysilicon, front-illuminated CCDs have poor quantum efficiency, especially in the blue and near UV spectral range . To overcome this problem, backside illumination has been implemented . In this technique,
2 . Silicon Devices and Circuits
207
the substrate of the CCD is etched away or thinned until only th e epitaxial silicon remains . In this way, it is possible to absorb inciden t photons directly into the silicon at the back surface of the CCD unimpeded by the polysilicon structure present at the front, resulting in a much higher quantum efficiency, especially in the blue and near U V spectral regions . One of the most widely used varieties of backside illuminated CCDs is the so-called flash gate . This approach requires tha t a substantial part of the bulk silicon be removed by an etching technique . Also, a growth of a passivating oxide layer on the backside is essential . However, this device shows an instability of the quantum efficienc y known as hysteresis due to trapping and emission of signal carriers i n the surface states at the Si/SiO 2 interface . This problem is worst for UV photons, which are absorbed almost immediately near the back surface . The solution to this problem lies in the growth of an oxide on the silicon back surface that can be negatively charged to negate the effect of the positively charged interface states . An additional key step for providin g good backside response in a CCD is to implement the method o f negatively charging the oxide (backside charging) . One approach is t o charge the oxide with UV photons . This has the effect of bending the energy bands upward into accumulation, driving signal electrons awa y from the Si / SiO 2 interface, thus eliminating the quantum efficienc y instability and providing 100% internal quantum efficiency. By floodin g the CCD back surface with intense UV light, electrons are excited to the conduction band of the Si O 2 , resulting in a negative charge on the oxide . Although very effective, this technique has the disadvantage of discharging over a period of time unless the CCD is held at temperatures below — 70°C . The flash gate technique is the most efficient among the othe r approaches used for CCDs. In this approach, a metal is deposited on th e backside of the CCD over the oxide (235, 236) . Because the work function of the metal is higher than that of the CCD, it permanently accumulate s the back surface with a negative charge and will then repel minorit y carriers (electrons) away from the back surface toward the desire d potential wells under the clock gates at the front of the device . Platinum has proven to be a good material for the flash gate because it is quit e stable . This flash gate process can optionally be followed by the application of an antireflection coating to further enhance the quantum efficiency of the CCD . The performance of the CCD, with the different approaches, is summarized in Fig . 2 .83 .
2.5.4. Amorphous Silicon-Based Photodetector s The performance of the InGaAsP / InP and GaAs-Al 1 _GaAs avalanch e photo detectors (APDs), used in the fiber optic communication
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wavelength range 0 .9 to 1 .55 pm (237, 238), is limited by the fact that i n InP the ionization coefficient ratio is close to unity over the entire rang e of the useful electric field range . The quantum efficiency of thes e separated absorption multiplication avalanche photodiodes (SAMAPDs ) is determined by the properties of the absorption layer and the hetero interface, whereas the multiplication and excess noise properties ar e determined by the avalanche multiplication process in the wide ban d gap semiconductor. In exporting the SAMAPD idea to silicon, two majo r facts should be considered : (i) The ionization coefficient ratio in Si is ver y different from unity and (ii) the absorption coefficient of amorphous S i is very large compared to its crystalline counterpart. For the absorption layer of the SAMAPD, amorphous silicon (a-Si) and its alloys (a-SiGe ) are a good option because they show at least one order of magnitud e higher absorption coefficient with respect to crystalline material . Additionally, amorphous materials have a very low deposition temperatur e (when PECVD is used) and do not contain any materials harmful to th e fabrication processing of the Si ICs . a-Si and a-SiGe alloys, used a s absorption layers in a SAMAPD structure, do not need to have smalle r band gap than the crystalline silicon, as in III—V-based APDs . Becaus e a-Si and its alloys have optical absorption coefficients larger tha n 10 4 cm' (for energies 0 .2 eV larger than the optical gap), only a 1-pmthick absorption layer is sufficient, which is two or three orders o f magnitude thinner than that needed in crystalline silicon . One of the important characteristics of amorphous materials is that materials o f arbitrary composition can be obtained . Alloying hydrogenated amor-
2 . Silicon Devices and Circuits
209
FIGURE 2.84 . Cross section of the a-SiGe SAMAPD (242) . phous silicon (a-Si :H) with carbon (239) or nitrogen (240) raises the band gap . Alloying a-Si :H with Ge or Sn lowers the band gap (241) . A cross section of the a-SiGe SAMAPD, fabricated in an n-type S i wafer (100), p = 3—5 0-cm of the INAOE 10-pm CMOS IC' s process, i s shown in Fig. 2 .84 . Only one extra implantation step is required t o prepare the substrate for the SAMAPD fabrication, and the IC's fabrication is not altered (242) . From the IR absorption spectrum of an 0 .8-pm a-SiGe layer we obtained values of the band gap Eg of 1 .72, 1 .33, and 1 .25 eV for x value s of 0 .0, 0 .33, and 0 .66, respectively, which correspond to 0 .720, 0 .933, an d 0 .992 pm wavelengths . As the Ge content is increased, the absorptio n coefficient also increases, suggesting that the higher the x value, the better the response of the material at higher wavelengths . However, the value of diffusion length determines the x value to be used in the absorption layer . If the thickness of the absorption layer is larger tha n the diffusion length of the material, there is a strong possibility that the photogenerated carriers will be lost in this layer before they reach th e multiplication region . An a-Sio .67Geo .33 :H,F alloy showed a diffusion length of 0 .08 pm and a lifetime of 79 .6 /is . From the point of view of process repeatability, a thickness of 0.08 pm can be easily obtained in the deposition system, and the risk of carrier recombination inside the absorption layer is therefore minimized . This is the main reason why the x = 0 .33 material wa s chosen as the absorption material . The measured dark current at a reverse bias voltage VD of — 20 V was 2 .22 nA and 2 .98 nA for a a-SiG e thickness of 0 .8 and 0 .065 pm, respectively . The on-wafer measurements gave a diode resistance R D of 25 .8 MQ and 4 .9 Gil at VD = — 20 and 0 V , respectively. The measured series resistance R S is 28 Q. The high frequency C—V characteristics were measured under dark conditions , giving a capacitance of 0 .5 pF at VD = — 20 V and 2 pF at VD = 0 V. A 100-mW-output laser, with a beam area of 0 .1256 cm 2 , was focused on the detector to measure the responsivity as a function of the wavelength . The results are shown in Fig . 2 .85 . The experimental results of the a-SiGe SAMAPD are compared to those of an MBE GaAs—Al 0 .4Ga0 .6 As super-
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Wavelength, X, [µm ] FIGURE 2 .85. Measured spectral response of the a-SiGe SAMAPD operated a t 300 K. Curves A and B correspond to the superlattice APD (242) .
lattice photodiode (SLPD) (238) . The responsivity R of the a-SiGe SAMAPD presented here is superior to that of the SLPD at wavelength s larger than 0.9 ,um. The S/N at B = 3.13 GHz (as calculated with SPICE) and VD = — 20 V is equal to 1819 .2, which ensures the operation of the device in optica l fiber communication systems . This device has been tested and proved to work very well in the 300 to 4 .2 K temperature range (243) . 2 .5 .5 . Summary The versatility of Si-based detectors is remarkable . We have seen tha t CCDs are capable of detecting radiation from the soft X-ray up to the IR spectral regime, and for all these applications CCDs can be operate d from 300 to 4.2 K. The camcorder systems are a very good example of a high-performance application of the CCDs in the visible (V) spectra l range . CCDs are also a very good option for radiometry, as has bee n demonstrated for the detection of vacuum UV and near UV signals . For the UV, V, and IR the photodiodes, and especially the SBDs, have bee n shown to be excellent candidates for integration as monolithic detectio n systems . New technology developments have made possible the extention of the spectral range of the SBDs down to the vacuum UV and u p to the mid-IR ranges . The SBDs are also capable of operating from room temperature to below 4 .2 K . A recent development of CMOS-compatible SAMAPD has opened the possibility of CMOS monolithic short-distanc e fiber optical telecommunication systems . This SAMAPD is based on a n amorphous Si :Ge device. This shows that not only crystalline Si but als o amorphous Si and its alloys with Ge can be used as high-speed IR
2 . Silicon Devices and Circuits
211
O
Uv —
0
I l00
I 200
1 300
Temperature, T [K] FIGURE 2.86 . Spectral application of Si-based photodetectors as a function o f temperature.
detectors . We have also tested this SAMAPD from 300 to 4 .2 K. For the far IR regime Si:P and Si :B extrinsic detectors have been shown to hav e an equivalent performance to that of the stressed Ge :Ga detectors near the 20-,um wavelength range . These Si-based extrinsic detectors operate at or below 4 .2 K. This review shows a trend toward the implementation of monolithi c Si-based technology. This is more clear for the IR spectral regime in which SBDs have been shown to be CMOS technology compatible . Thi s review can be summarized in Fig . 2.86, in which the different kinds o f detectors are shown in a wavelength 2 versus temperature T scheme . A review of the state of the art on silicon-based radiation detectors , their IC technology compatibility, and the optoelectronics properties o f silicon at low temperatures was presented . Future trends and perspectives of Si-based radiation detectors for low-temperature optoelectronics were also addressed .
2.6 . CIRCUITS The following sections summarize the most widespread applications an d published works on cryoelectronics, including CMOS, SOI, and SiGe HBT digital and analog circuits for specific applications such as readou t electronics for imager systems or nuclear instrumentation, digital micro-
212
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
processors such as the one used in the ETA cryocomputer, image r systems for IR detection, CCD arrays, IR SBD systems for night surveillance, and focal plane arrays for astronomy applications . This review on applications concludes with a summary in which future applications and trends are predicted based on the recent advancements in cryogenic SiGe technologies and hybrid semiconductor — superconductor systems .
2.6.1. CMOS Digital Circuits, Microprocessors, and Memorie s CMOS technology has been the most widely used for cryogenic applications due to its freeze-out immunity. For this reason, several attempt s have been made to integrate digital and analog circuits for cryogeni c operation . The first attempt was the testing at 77 K of the commerciall y available 16-bit DCJ11 microprocessor in 1986 by Colonna-R . and Deverell (244) . This 3-µm CMOS chip consists of two chips mounted i n individual ceramic packages in which both are surface mounted onto a 60-pin cofired ceramic hybrid . The first chip contains the primary execution data path, the memory management logic, the input/outpu t state sequencer, and the floating point and cache registers, whereas th e second chip contains the microprogram control store and sequencer . The results of this test are shown in Fig. 2 .87 . The instruction set diagnostic fI and the floating point diagnostic f F
FIGURE 2 .87. Experimental data (symbols) for the 16-bit DCJ11 micro processor. The solid lines represent fittings . The dashed lines represent percentage enhancement (244) © 1986 IEEE .
2 . Silicon Devices and Circuits
213
frequencies are shown in Fig . 2 .87 . Both frequencies increase when the CMOS microprocessor is cooled to 77 K . The average increase is fro m about 22 to 40 MHz, which represents an average percentage improve ment of 80% (see right axis of Fig . 2 .87) . The solid lines are fittings base d on the typical temperature dependence of the electrical parameters of the MOS transistor such as the threshold voltage and the transconductance . According to these results, 77 K is the best compromise in terms of cos t performance . Cooling below 77 K does not result in significant electrica l improvement, but the cost of the cooling system increases . As noted by Longsworth and Steyert (245), computers that require 1–400 W of refrigeration at 77 K can use refrigerators that are essentially the same as thos e that are in widespread use in small cryopumps . For systems dissipating less that 1 W at 77 K, a Joule–Thomson refrigerator is suggested . For 1 W to more than 100 W of power dissipation, a Gifford–McMahon cycl e refrigerator is suggested, whereas for systems requiring several hundre d watts of power dissipation, a Brayton cycle refrigerator can be a goo d choice . A prediction of cost C (in dollars) of the refrigeration system fo r computers in the 10- to 1000-W power range is approximately given b y
C = 750 •
Q0
.52
(2 .123 )
where Q is the power load in W at 77 K . In 1987, Hanamura et al. (246) demonstrated the operation of 1 .3-ym CMOS 8 x 8 bit multipliers at 77 and 4 .2 K They tested two types o f multipliers : full CMOS and pulsed pload logic (PPL) based . The results for the delay time per gate T g and the power dissipation P d at 10 MHz are shown in Fig . 2 .88 . The delay time per gate 2 g in both cases decrease s
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l
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ô
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Temperature, T (Kl
FIGURE 2 .88. Measured results for the 8 x 8 bit multipliers of Hanamura et al . (246) . The squares indicate the CMOS-type and the circles indicate the PPL-typ e delay time per gate T g and power consumption Pd (246) © 1987 IEEE .
214
E . A. Gutiérrez-D., C . Claeys, and E . Simoen ti
10000
PP L
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w
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100 150 200 Temperature, T [K]
1
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FIGURE 2 .89. Experimental energy consumption E d from Hanamura et al . (246) © 1987 IEEE .
as temperature is lowered . However, the power consumption in the PPL case increases at low temperatures . A better figure-of-merit is the energy consumption Ed or the product T mPd , where tm is the delay time of th e multiplier (Fig . 2 .89) . The delay time per gate ' rg reduces 52% at 77 K and 66% at 4 .2 K for the CMOS multiplier, whereas the energy consumptio n E d reduces 52% at 77 K and 68% at 4 .2 K. Also, Sun et al . (247) demonstrated a twofold improvement in bot h the speed and the power-delay product over room-temperature value , where a 0 .5-,um CMOS ring oscillator was used as a test vehicle . In 1988 , Deen et al . (248) reported experimental results on a commercial CMOS based microprocessor operated at 77 K . The maximum input frequenc y increased up to 32 MHz at 77 K compared to 19 MHz at 300 K . An example with a more complex system is the cryocooled ET A computer (249) . The ETA is a 10 GFLOP computer with 3M circuits, 4 Mbit SRAM, and 2 .3 Gbit of disk storage . Its CPU reliability was im proved by minimizing the number of interconnections and circuits . The CPU boards and the ICs were the only cooled parts, which resulted in a twofold speed improvement . The performance of this 77 K ETA computer was superior to that of similar room-temperature-operated super computers, such as the Cray X-MP, the Cyber 205, and the NEC SX-2 . The comparison was made by implementing the Los Alamos vecto r kernel benchmark, with an average performance, in megaflops, of 150 fo r the ETA, 55 for the Cyber 205, and 50 for the CRAY X-MP . This performance enhancement is due to the reduction of power consumption, heat dissipation, and speed increase at 77 K . Another interesting example is the cryogenic operation of Si DRAMs by Wyns and Anderson (250) . The 16-, 64-, and 256-kbit DRAMs fro m
2 . Silicon Devices and Circuits
21 5
different manufacturers were operated at low temperatures to investi gate their performance. It was observed that 89 K is the lowest temperature at which a 256-kbit DRAM can operate . Below this critica l temperature the sense circuits fail to operate properly . It was als o observed that below 240 K, the minimum refresh frequency is temperature independent but strongly voltage dependent. Above the typica l temperature value of 240 K, which can vary depending on the memory family, the Shockley—Hall—Read electron generation rate is the dominant mechanism . Below the typical temperature value the strong voltag e dependence results from band-to-band tunneling in the Si depletio n region under the memory capacitor . Another interesting result from thi s experiment is that the times between required refresh cycles are as lon g as 4 .6 days at 183 K . This suggests that DRAMs, when designed specifically for cryogenic operation, could operate properly at 77 K as stati c RAMs, thus giving the designer the chance to reduce the circuit complexity and the power dissipation . Experimental results on the numbe r of failures versus retention time are shown in Fig . 2 .90 . It is expected tha t with the advent of advanced DRAM and SRAM technologies, the result s at 77 K obtained from memory technologies from the 1980s will be outperformed . A detailed study of the voltage transfer characteristics of commercia l CMOS inverters for temperatures between 77 and 300 K, and for voltage s between 3 and 20 V, was presented by Deen (251) . In these experiments,
104 -
T=293 K T=273 K T=253 K T=233 K
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FIGURE 2.90 . Measured number of failures versus retention time for capacito r voltage Vcc = 5 V, with temperature as a parameter, for one-sixteenth of a 256-kbit NEC DRAM [replotted from Wyns and Anderson (250)] © 1989 IEEE .
216
E . A . Gutiérrez-D., C . Claeys, and E . Simoen
v ~~ tl
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Vinv
Input voltage, V in [V ]
FIGURE 2 .91 . The DC transfer characteristics of a CMOS inverter .
different commercial CMOS devices were used : RCA CD4007UBE, M C 14069UBE, and MC 74HCU04 . The DC transfer characteristics of a CMOS inverter are depicted in Fig. 2 .91 . The output high voltage is denoted by V oh , the output low voltage i s denoted by Vol , the input low voltage is denoted by Vil , and the inpu t high voltage is denoted by Vih . Thus, the low noise margin NM L and the high noise margin NM H are defined as follows :
NM L
— Vol 1
(2 .124 )
Voh — Vihl
(2 .125 )
= I Vi,
and
NM H
= I
The noise immunity NI is defined a s NI =
(NM H +NM L )
(2 .126)
where VDD is the supply voltage . The noise margin NI is a parameter related to the transfer characteristics of the inverter. This parameter defines the allowable noise voltage in the input of a gate so that th e output will not be affected . The threshold of the inverter Vin,, is define d at the Vin voltage, where Vo „t voltage is equal to VDD /2 . The experimental study presented by Deen (251) was later extende d to 4 .2 K and to submicrometer technologies by Gutiérrez-D . et al . (252) . The experimental results of these two works are shown in Fig . 2 .92 . For CMOS inverters, it is usually desirable to have the difference Vih —Vil close to zero or equivalently a high noise immunity NI . Both Deen and
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FIGURE 2 .92. Experimental results of the inverter threshold voltage and noise immunity NI for the inverters of Deen (251) (a) and Gutiérrez-D . et al. (252 ) (b) © 1989, 1992 IEEE .
Gutiérrez-D . et al . observed an increase in NI as temperature wa s lowered. The inverter threshold voltage also increased with the reduction of the temperature . The inverter of Gutiérrez-D. et al . (252 ) was made with a 0 .7-ym n-well CMOS technology (253), with TO = 15 nm, L. = L p = 0 .7 ,um, and Wn = Wp = 70 pm . In the 50—300 K range, the DC characteristics have the same behavior . It can be concluded that submicrometer CMOS inverters approach ideal behavior a t T = 50 K . For temperatures below 50 K, the combination of freeze-ou t and carrier multiplication degrades the DC characteristics and increase s the current consumption . However, the critical temperature at which the inverter performance is maximum may be lowered if the supply voltag e is reduced and the resistivity of the substrate and the well is optimized . Commercial 555 and 551 CMOS timer ICs were also evaluated fo r cryogenic use by Haruyama and Kirschman (254) . The general result is that these ICs are suitable for operation in the 300-80 K temperatur e range in a stable mode as R—C controlled oscillators . These ICs with stand repeated thermal cycles without their electrical characteristic s being noticeably altered . Thus, these CMOS IC timers are suitable for cryogenic applications requiring oscillation, timing, sequencing, an d pulse generation . The causes of the misfunctioning of CMOS digital circuits at temperatures below 77 K were identified by Gutiérrez-D . et al . (255) as substrate current due to carrier multiplication and freeze-out effects . As VLS I technology continues to develop, we must deal with problems such a s
218
E . A . Gutiérrez -D ., C . Claeys, and E. Simoen
carrier multiplication due to high-field impact ionization and self-heating (256) due to power dissipation . Moreover, the increased carrie r multiplication together with freeze-out, occurring at low ambient ternperatures, can have a major effect on the electrical performance o f submicrometer MOS transistors, which in turn affects the electrica l performance of circuits . At very low temperatures (below 50 K), many second-order parasitic effects, such as carrier multiplication, self-heating , freeze-out, and series resistance, which result from the use of LD D devices, combine to make the analysis and characterization of submicrometer MOS transistors very complex . The combination of these effects, obviously, affects the performance of cryogenic CMOS circuits . A n example of this is a 211 inverters chain ring oscillator (RO) fabricate d with the 0 .7-,um CMOS IMEC technology . The power consumption P an d the delay time per gate tg as a function of temperature of the RO biase d at different supply voltages are plotted in Fig . 2 .93 . All the plots show a plateau region in the 250—100 K range, an extended kink that goes fro m 100 to 50 K, and a second plateau from 30 to 4 .2 K. The first platea u region is attributed to the flattening of the current drive capability of th e MOS transistors, which is due to the series resistance effects . The extended kink is due to the soft freeze-out effect that combines with the generation of substrate currents to increase the substrate voltage an d reduce the threshold voltage . Finally, the second plateau region, in th e 30—4 .2 K range, is due to the combination of hard freeze-out that
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Temperature, T [K ] FIGURE 2.93. Experimental results of the power consumption P and the dela y time per gate t g as a function of temperature, with the supply voltage V DD as a parameter.
2. Silicon Devices and Circuits
21 9
increases the resistance of the substrate/well to values into the 10 g K2 range and of substrate currents that flow through the high-valu e substrate/well resistances R b . Thus, the product (R b • Ib ) clamps at a value near the source—substrate/well junction forward bias, whic h causes the P and 'cg parameters to also clamp at their constant values . The low-temperature effects cause a drastic reduction in the dela y time per gate, which results in an increase in the power consumption . The twofold reduction of ' cg at 4 .2 K compared to 300 K is compensate d by a twofold increase in P . In addition to the temperature dependence o f these two parameters, which is usually considered as a figure-of-meri t to evaluate the electrical performance of digital circuits, the temperatur e dependence of the product (P • 'c g ), which is equal to the consumed energy E d , serves much better as a universal figure-of-merit to compare the electrical performance of CMOS digital circuits at cryogenic temperatures. This consumption energy E d is plotted in Fig . 2 .94 . In general, the consumption of energy, as shown in Fig . 2 .94, reduce s as temperature is lowered, which is a good feature of cryogenic CMO S digital circuits . It is also observed from Fig . 2 .94 that the reduction of 'c g prevails over the increase of P, except in the extended kink (100—50 K) in which a noticeable bump is observed at high supply voltages becaus e the carrier multiplication effect is more pronounced at high suppl y voltages . The previous results call for an optimization of CMOS technologie s for cryogenic operation . This has already been done by Kakumu et al . (257), who theoretically and experimentally examined the tradeoff belb
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220
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
tween circuit performance and reliability for a 0 .3-,um CMOS technology at low-temperature operation . A simulator based on physics-base d models was used to determine power supply voltage and process / device parameters for proper low-temperature operation . The optimization procedure was demonstrated on a 0 .3-,um CMOS RO tested at 77 K. The measured delay time per stage is about 40 ps compared to 60 ps a t 300 K, which represents a 50% improvement in circuit performance . On the other hand, extremely low power-delay product, less than 1 fJ, wa s observed at 77 K with power supply voltage less than 1 V . Thus, thi s guideline optimization, combined with an advanced CMOS process , appears to offer extremely high speed and low energy consumption , which should be employed in future ULSI applications . Following the same trend of CMOS process optimization fo r cryogenic applications, a process modification for improved low-temperature CMOS performance was proposed by Hwang et al . (258) . TCAD (Technology Computer-Aided Design) tools are proposed to study an d optimize the room-temperature process for low-temperature operation . Room-temperature CMOS technologies, when operated at low tempera tures, only give a minimal performance improvement . However, by modifying the process flow, a two- or threefold increase in performanc e is possible . The TCAD tools proposed for this low-temperature proces s optimization are shown in Fig . 2 .95 . Process changes are first run through SUPREM (a device fabricatio n simulator) to obtain a new profile . MEDICI then imports the profile, producing the low-temperature optimized I—V characteristics . These I—V curves are then compared to the originals, and the measurement of th e circuit-level improvement is done with HSPICE . Optimization using these TCAD tools leads to modification of the threshold voltage implant s to reduce the high value of the threshold voltage at low temperature s and to modification of the LDD implant to reduce the high parasiti c
propose d process current RT process flow change
new LT process flow
SUPREM III I -D doping profile
lateral diffusio n
optimize HSPICE parameters circuit performance
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t
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parameter extraction
improved I-V curves
must match
FIGURE 2 .95. Schematic representation of the flow of TCAD tools for th e CMOS process optimization for low-temperature applications [after Hwang et al. (258)] .
2 . Silicon Devices and Circuits
221
resistance and increase reliability . With these modifications, delay improvements of up to 100% in ROs operated at 77 K with a supply voltag e of 2 .8 V can be obtained at 300 K .
2 .6.2 . CMOS Analog Circuits, Readout Electronics, and Detecto r Arrays Analog functions implemented with CMOS circuits are crucial fo r proper functioning of cryogenic preamplification stages . Most of the cryogenic systems are used to sense and process physical variables, suc h as light, IR radiation, magnetic fields, temperature radiation, and energ y radiation in general, that are analog signals by nature and thus requir e preamplification by an analog circuit, readout, and send out to a n analog-to-digital conversion system for further digital processing . Thi s circuit chain must be carefully designed in order to maximize th e impedance coupling and reduce spurious noise . One of the first attempts to establish a guideline for the design o f analog circuits for cryogenic applications was made by Fox and Jaege r in 1987 (259) . In this work simple scaling rules are used to predict th e 77 K performance of CMOS operational amplifiers . The basic CMOS op amp analyzed is shown in Fig. 2 .96 . The differential mode voltage gain of the first stage is Al =
gmp2 gdp2 ava + + 8an dn2z
(2 .127)
V DD
P4
P3
P5
V+
V-
Pl
Nl VSS
FIGURE 2 .96 . Diagram of the CMOS op amp studied by Fox and Jaeger (259 ) © 1987 IEEE .
222
E. A . Gutiérrez-D ., C. Claeys, and E . Simoen
and the gain of the second stage i s A2
=
g mn3
(2 .128 )
dp4 + gdn 3
The subscript d refers to output conductance and the subscript m to transconductance. The dominant pole wd is provided by the compensation capacitor Co . At frequencies above COd the open-loop gain reduces to unity at the frequency co, ~r =
(2 .128 )
(g mp2/ Co)
Both the conductance gd and transconductance gm increase as the ternperature is reduced . However, the rate of increase is also a function o f the bias conditions and the channel length . Figures 2.97—2.100 show the temperature dependence of the conductance g d and transconductance gm of an array of n-MOS transistors fabricated with a 0 .5-µm IMEC CMO S technology (260) . In Figs . 2 .97—2 .100, the rate of increase at lower temperatures i s always higher for longer transistors than for shorter ones . This is shown in Fig . 2.101, in which the 77 K values of gd and gm , normalized to 300 K, are plotted as a function of the channel length . The increase in gd and gm at 77 K with respect to 300 K is also a function of the bias condition . In general, the increase of g d and gm at 77 K is higher when the transistor s are operated in the linear region than in the saturation regime . Thi s
conductance g d (AN) @ 300 IC 2.73X10-3 1 .50X10-3
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FIGURE 2.97 . Normalized conductance gd (AId /Vd) versus temperature for an array of n-MOS transistors fabricated with a 0 .5-µm CMOS technology .
2 . Silicon Devices and Circuits
223
conductance gd (A/V) at 300 K 7 .50X10 -5 @ L=O .S µ m I .6OX 10" 5 @ L=1 .0 µ m
5 .03X I0-6 @ L=2 .0 µ m 1 .10X10-6 @ L=5 .0 p m 2 .50X 10-7 @ L=10 .0 pm
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pm
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L=1 .0 pm
0
100
50
150
200
300
250
Temperature, T [K]
Normalized conductance g d (AId /Vd) versus temperature for a n array of n-MOS transistors fabricated with a 0 .5-µm CMOS technology . Th e transistors were biased in the saturation regime ; VD = 3 .0 V, VG = 2 .0 V . Th e values at 300 K are shown in the inset . FIGURE 2 .98.
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♦ ♦♦♦ ♦ ♦
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l
1
L=I .O µ m 1 1 I 1 1 1 1 150 200
1
I
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250
1
I
300
Temperature, T [K ]
Normalized transconductance g m (AId /Vg) versus temperature for an array of n-MOS transistors fabricated with a 0 .5-µm CMOS technology. The transistors were biased in the linear regime ; V D = 0 .25 V. The values at 300 K are shown in the inset. FIGURE 2.99.
224
E . A . Guti érrez -D ., C . Claeys, and E. Simoe n 4.0 b4
Û .b
ô
3.5
_ I
I
_
L=10.0 p m
-
3 .0 = _
♦♦♦♦♦
L
2 .0
_ ~
•
g11= 1 .4 5 X 10- 3 (A/V), 2.0 p m g 11=7 .73 X 10- 4 (A/V ), 5.0 p m ♦ ♦
=A . AA A .,
.%
g 11=4 . 2 3 X 10- 4 ( A/V ), 10 .0 p m
• •
it,
_• ♦
♦
=
1 .0 –
Z
_
-
•
.5
O
1
till=2 .78X I0- 3 (A/V), 0.5 p m g11=2 .07 X 10- 3 (A/V ), 1 .0 p m
L=5.0 pm
2. 5
11 -_
11111111
1
L=0 .5 pm L=1 .0 Nm L=2 .0 }~m 1 1 1 1 0 .50 - I I , l I I l 1 I 100 150 0 50 _
I
,
,
_
_
-
1
►
,
(
200
I
1
►
,
1 1 250
I
300
Temperature, T [K ] FIGURE 2.100. Normalized transconductance gm (AId /V g) versus temperature for an array of n-MOS transistors fabricated with a 0 .5-µm CMOS technology . The transistors were biased in the saturation regime ; VD = 3.0 V. The values are 300 K are shown in the inset.
FIGURE 2 .101 . Normalized (77 K/300 K) conductance gd and transconductance gm versus channel length L for an array of n-MOS transistors . The subscripts lin and sat indicate linear and saturation regions, respectively .
2 . Silicon Devices and Circuits
22 5
temperature dependence is due to the different components of the carrier mobility, which have different temperature dependences . Thus , in the saturation regime the velocity saturation plays a key role, wherea s in the linear region components such as surface scattering and carrier-to carrier scattering are more important . At temperatures below 50 K anomalous behavior is observed in the conductance and sometimes i n the transconductance . This is due to the combination of three effects : the freeze-out, the drain threshold voltage (261), and generation of substrate currents (262) . The impact of these effects on the I - V characteristics o f MOS transistors at 4 .2 K is shown in Figs . 2.102 and 2 .103 . At low values of Vd the Id -Vd characteristics deviate from linear to a quasi-exponential behavior . This is due to the so-called "drain threshol d voltage" which is caused by a potential barrier at the edges of the gat e in the overlapping gate-to-source/drain regions . This quasi-exponential behavior causes the conductance g d to slightly increase at temperature s below 50 K . It is also important to note that this effect is channel lengt h dependent . As the channel length increases the I d -V d characteristic s suffer less of the drain threshold voltage . At high values of the Vd voltage, the combination of freeze-out and substrate current increases th e substrate voltage, thus reducing the threshold voltage and increasing the Id current and the conductance g, . The transition temperature at which freeze-out affects the electrica l performance of the MOS transistor is apparent in Fig . 2 .103 . From 50 K (continuous curve in Fig . 2 .103) upwards the substrate current lb gener ated by the MOS transistor flows through the substrate to the substrat e
14
111111111
1
I
quasi-exponentia l 1behavior due to the drain-threshol d voltage effect
I
1
1
~
I
V~, =4 V
-
3V
:–.
increase of the conductance due to the "kink" effect
o '/
0
0 .0
d
0 .50
1 .0
1 .5
l
1
1
i
1
1
1
2 .0
l I
2 .5
1
1 V I
1
L
1
3 .0
1
I
3 .5
Drain voltage, V d [V]
FIGURE 2.102. Experimental Id -Vd characteristics of a (W/L) = 10/0 .5 n-MOS transistor operated at 4 .2 K .
226
E . A . Gutiérrez-D ., C . Claeys, and E . Simoen 2.5
16 50 K
14
~
r--, 12
=
~
_
„
►—+
1
10 —
-
/
/
i
40 K 30 K
(n a
-
—_
2 .0 5r
6-1
1
,'
~,,
8
V
1
L V
4 — _
0 0 .0
;•.
. I; •
1!
~
0 .50>
~' ~•.~ .
~
,.
t~I/~
I
1 .0
.
_
._. l I 1" I 1 1 I 1 2 .0 3 .0 4 .0 Gate voltage, V g [V ] ~ I
~
~
~
}
1-
l
~,
0.0 5 .0
FIGURE 2 .103. Experimental Id —Vg characteristic of a (W/L) = 10/0 .5 n-MOS
transistor biased at Vd = 3 .0 V and operated at 4 .2 K . contact, causing a slight voltage drop through the substrate . At T = 40 K (short dashed curve in Fig. 2 .103), the top part of the lb current is cut off . The cutoff lb current is now flowing through the source–substrat e junction, which became forward biased due to the increase in the substrate voltage caused, by the flow of l b through a semifrozen high-resistive substrate . At 30 K (long dashed curve in Fig. 2 .103) the substrate is fully frozen and all the lb current flows through the source–substrate junction. The increase in the substrate voltage cause s the variation in the Id current, which also changes to conductance g d . Fox and Jaeger (259) proposed two ways to exploit low-temperatur e operation by using the same geometry as that of 300 K and b y reducing geometries . In both cases, the performance and geometry o f circuits are described in terms of the scale factors aµ and al . In the firs t case, a change of gm and gd at 77 K with respect to 300 K is given approximately b y and
gm177 K —
~ a µ al
gd177 K —
a
*
gm1300 K
I . gd1300 K
(2 .130 ) (2 .131 )
Because the gain of each stage is proportional to the (gm /gd ) ratio, the change in the DC open-loop gain Ao is given by
a
A
o177 K — () . AO I 3 ~ O K a
I
(2 .132)
2. Silicon Devices and Circuits
22 7
The slew rate depends on the capacity of transistors P 2 or N 2 to charge the C . capacitor, which is proportional to ai . The unity gain frequency co , at 77 K is given by W tI77K
= N,/ a µ aI
' Wt I300 K
(2 .133 )
The phase margin `l' m depends on the relation between co, and the lowes t frequency nondominant poles. The poles due to parasitic capacitance s increase by an amount between N/aµ a I and aI . Then, if a l < aµ , these poles may not increase in frequency as much as does co t , which implie s a degradation of qm at 77 K . However, as demonstrated for the channel and bias dependence of gm and gd, the bias can be adjusted to get a l > aµ for an improvement in 4m at 77 K. The second alternative to exploit low-temperature operation is t o reduce geometries at a constant performance . If the operating current s are kept constant and all the channel widths are reduced by a factor a µ , then a I ti 1, gm at 77 K will equal gm at 300 K, and gd at 77 K will equal g d at 300 K. Under these conditions the DC voltage gain and the power consumption remain unchanged . Then, as the areas of the parasiti c capacitances scale down with the channel width and the conductance s are unchanged, the nondominat poles scale up in frequency by a factor a µ . Therefore, the compensation capacitor C. can be reduced in area without degrading the phase margin, which results in an increase in th e slew rate . Fox and Jaeger (259) tested this model using a series o f measurements on op amps fabricated in an 8-,um Al-gate p-well CMOS process. The op amp shown in Fig . 2 .96 was biased at VDD = 5 V , Vss = — 5 V, with an external compensation capacitor C . = 54 pF. At 77 K the input stage transconductance G . increased by a factor of 2 .8 . These authors found discrepancies between the G . versus 'bias variation and the transconductance variation measured for the p-MOS transistors . They attributed this to a µ sensitivity to interface charge densities . However, a s discussed previously, these discrepancies can be attributed to the channel length and bias dependence of the temperature dependencies of gm and gd . The measured unity-gain frequency ft = (co t /2n) matched very well that calculated from ft = G m / (2itC°) . These results are shown in Fig . 2 .104 . The input-referred noise level (in decibels below 1 V rms / ./Hz ) measured at 77 K with 'bias = 400 ,uA is about 1 .5-2 dB lower than that at room temperature . The measured slew rate shows a nontemperaturedependence behavior . The overall voltage gain A . for this structure is given by the product of the gains of each of the two stages : A = °
G. 2 1 I3
gmn3 . 22Ibias
(2
.134
)
228
E . A . Gutiérrez-D ., C. Claeys, and E . Simoen N
2000-, 77 K
c,._,- 1500 — Û a) 4
1000 – _
-4
_
~
ân ~
calculated
_ -
300 K
-
500
FA _ measured
0
^ 1
1
0
1
1 1
1
1
1
100
1
1
1
200
1
1
l l l l l 1
1
300
1
1
400
Current bias, 'bias [µ
1
1
500
I
I I
I
I
1
600
1
1
1 700
A]
FIGURE 2 .104 . Unity-gain frequency f, versus 'bias at 300 and 77 K [replotte d from Fox and Jaeger (259)] © 1987 IEEE . where 2 1 = 0 .0143 V -1, 2 = 0 .022 V -1 , and G m , 13, and g. 3 are measured values . The measured overall DC voltage gain versus Ibias at 30 0 and 77 K is shown in Fig . 2 .105 . In a study by Schoeneberg et al. (263) the CMOS readout circuitry fo r a liquid argon calorimeter was optimized for 83 K operation . This chip, fabricated using n-well 2-µm CMOS technology, contains 16 analo g channels with switched-capacitor circuits for charge collection, storage , amplification, and averaging and correlated double-sampling circuits fo r
5000 0 0
40000 L
.• 8 aA a) bcdA
30000 _ 20000 ~~
O >
10000 =
–_
calculate d ~ , .
~
!
77 K
2
300 K O 0L~~~I~ „ ► I ► Ei) 400 500 600 0 100 200 300 Bias current, Ibias [µA ]
_700
FIGURE 2.105 . Measured and calculated voltage gain A. versus bias current 'bia s at 300 and 77 K [replotted from Jaeger (259) © 1987 IEEE .
2 . Silicon Devices and Circuits
22 9
noise reduction. This readout system is used for reading out the signal s from many capacitive sensors . These signals are generated by the secondary emission of an accelerator, in which the occurrence of thi s event depends on the collision and can occur only every 100 ns . The system and a trigger generator, an analog multiplexer, and digita l circuits for analog switching are operated at 83 K. Experimental results of this system operated at 77 K show a considerable reduction of whit e noise but a slight increase in flicker noise, suggesting that the S / N rati o of the system can be improved at cryogenic temperatures . It is als o shown in this experiment that the operation of high-performance CMO S analog circuits is feasible for readouts of capacitive detectors in the nanofarad range . Another interesting example of CMOS analog applications t o cryogenic systems is the ISOPHOT cryogenic readout electronics (264) . This Infrared Space Observatory is a project funded by the Europea n Space Agency (ESA) and will be used for astronomical satellite applications, in which the IR spectrum from 3 to 200 µm will be investigated . This instrument contains a cryogenically cooled telescope with focal plane instruments that allow imaging and photometric, spectroscopic , and polarometric observations . The specifications for this IRdetection system are very strong; fo r instance, a NEP of 10 - l ' W/ .3Hz, a dynamic range of 10 5 , a responsivity on the order of 1–10 A/W, a charge noise specification o f 100–1000 e -, a maximum detector current rate of 10' to 10 8 e - /s, and overall power dissipation per detector below 300 µW, are required . To eliminate the inherent problems related to low-temperature operation such as low response time, reduced output signal dynamic range , and charging of stray capacitances, Dierickx (264) proposed an integrating feedback amplifier (Fig . 2 .106) . The detector current is accumulated on the feedback capacitor C and the detector bias is kept constant at th e virtual ground level of the amplifier input-node . By resetting the ampli fier the 1/f noise and cryogenic drifts in the input MOS transistors ar e
rese t detector ti bias
1111
output to mux .
FIGURE 2.106 . Integrating feedback amplifier (264) .
230
E. A . Gutiérrez-D ., C . Claeys, and E. Simoen
partially alleviated . The power dissipation and the bandwidth of th e amplifier are both controlled by a current mirror stage . Two cascod e transistors are added to the basic amplifier scheme to further increase the amplifier gain and to keep the voltage over the transistors sufficient ly low to avoid excessive kink noise of the cryogenic amplifier . The charge integration capacitor is designed to have a minimum size and a minimal value. A sample and hold stage to synchronize the readout of the pixel s precedes the integrating stage . The system is calibrated by adding tw o supplementary inputs; one serves as a reference for the zero bias leve l ("dark" condition), and the second is connected to a 5 GSZ detector tha t emulates a resistor to determine the DC transfer function of the device . Most of the control pulses are generated on-chip . The system has a standby function that deactivates the clock generator and limits the current through the amplifier to reduce power dissipation . The experimental results of this initial experiment showed that requirements ar e met, and that CMOS analog circuitry is sufficiently reliable to operate a t 4 .2 K . The design has been recently optimized to be used in the ESA satellite FIRST (Far Infrared and Submillimeter Space Telescope) to be launched in 2005 (265) . This readout will be used for imaging signals i n the 100-ym to 1-mm wavelength range . This system will be operated a t 1 .6 K . Operation at this temperature requires a careful design . The modified readout circuit is shown in Fig. 2 .107. The Cac capacitor decouples the detector from the amplifier and cancels the variation of th e bias voltage over the detector . The feedback from the input to the direc t injection transistor is done with an AC-coupled amplifier . The photocur -
V DD
reset
rese t
outpu t signa l reset C ac zero bias
detecto r
uc OTA
Bias FIGURE 2 .107.
(265)] .
Modified direct-injection readout circuit [after Seijnaeve et al.
2 . Silicon Devices and Circuits
231 V
C~
MP2
1 Mpl
DD Mp 3
I
~--
MP 5 MP6 M P4
vo O MN3
MNI ~
FIGURE 2.108. Circuit scheme of the folded cascode amplifier [after Kleine e t al. (266)] © 1994 IEEE. rent is integrated on a capacitor C 1 . The variation and drift of the bia s voltage are very low . The main advantage of this scheme is that ful l integration on-chip is possible . A low-noise CMOS readout preamplifier operated at 4 .2 K has been reported by Kleine et al . (266) . This circuit is applied to a SQUID t o measure biomagnetic fields . It is a folded cascode amplifier with it s input attached directly to a low-impedance SQUID output . An equivalent noise voltage density of 0.3 nV .3Hz at 500 kHz at 4 .2 K has bee n measured . This preamplifier has proved to be essential in lowering th e costs of biomagnetic systems by simplifying the expensive shielding . Th e circuit diagram of the folded cascode amplifier is shown in Fig . 2 .108 . The magnitude of the input signal Vin is in the range of 100 ,uV and ha s a low linearity . Therefore, the preamplifier is in an open-loop configuration . Moreover, the folded cascode configuration prevents the circui t from displaying kink effects . The circuit is biased with an externa l current source I . The C 3 is an external capacitor (1 nF) used to ensure a common source operation of transistor MP4 . To achieve the required high-noise performance, the input transistor M P4 is made large (W/ L = 1000/2 ,um), and the resistive poly gate noise is reduced b y using a finger-like structure with 20 identical poly stripes .
E . A. Gutiérrez-D., C . Claeys, and E . Simoen
232 104
W
I
111111
1
111111
q
°
0 .1
1111111
1
1
1111111
10
1
1
1111111
1
1
1
1
.
IT1 1
°
1 1111
100
1000
1
1
11111 1
104
Frequency, f [KHz ]
Measured equivalent input noise voltage density at 4 .2 K for the amplifier of Fig . 2 .22 [replotted from Kleine et al . (266)] . FIGURE 2 .109.
The measured gain of the preamplifier, fabricated using a 1-gu m p-well CMOS technology, was 24 dB at 300 KHz with a power suppl y voltage of + 2 .5 V . The measured equivalent input noise density i s shown in Fig . 2 .109 . The 1/f is the dominant noise component and i s approximately threefold higher than its value at 300 K . The complete performance of the amplifier is characterized by a gain at 300 KHz o f 24 dB, an output swing of 400 mV, a bandwidth with a C L = 600 pF of 22-308 KHz, an output resistance of 3 k1, a power consumption of 9 mW , and a chip area of 0 .3 mm 2 . The 1/f noise can be reduced by using buried channel MOSFET s (267) in which implanted impurities in the channel, as opposed to tha t of the substrate, are biased to form the conducting channel away from the Si/SiO2 interface. In this way, noise sources other than the therma l and flicker noise are revealed, as is the 1/f 2 , which is attributed t o generation—recombination either in bulk silicon traps or in traps a t mid-band gap (268) . This 1 /f2 noise is largely dependent on gate an d substrate voltages, that with a careful choice of bias conditions, lead t o extremely low noise performance . The device discussed here was fabricated in a standard CCD process, in which the buried channel transis tor had a P implant of a dose of 8 x 10 11 ions / cm 2 at 180 keV tha t resulted in a channel junction depth of 1 .08 pm with a net surface donor concentration of 1 .5 x 1 0 16 cm - 3 . Thus, a deep buried channel is formed and the device behavior is studied in either the depletion or th e inversion mode by properly biasing the gate and bulk . The gate oxide
233
2 . Silicon Devices and Circuits
thickness is 50 nm, and the transistor has a square geometr y (10 x 10 µm2 ) . The drain voltage was kept at 5 V, the gate voltage wa s swept from 0 to — 8 V, and the bulk voltage was adjusted to maintain a constant drain current of 1 µA. Noise was measured, under these bia s conditions, over the frequency range of 1 Hz to 10 kHz . The measured o. s noise current at 1 Hz with Id = 0 .1,uA reduces from 20 to 0 .6 pA / Hz when the bulk-to-gate voltage Vbg changes from 0 to 4 .5 V . Kandiah and Whiting (268) conclude that a very low noise in a depletion-mod e MOSFET can be achieved only if the surface is inverted, which th e prominent G—R noise is totally suppressed . Thus, very low-frequency noise circuits are achievable in MOS technology . An experimental characterization of four different architectures o f CMOS amplifiers was presented by Daud et al . (269) . An n-channel input two-stage Miller amplifier (NDV), a p-channel input two-stage operational transconductance amplifier (POTA), an n-channel folded cascod e two-stage amplifier (NDC), and a low-power version of the NDC wit h input stage in weak inversion (DCL) were characterized at 300, 77, an d 4 .2 K . The four architectures are shown in Figs . 2 .110 and Fig . 2 .111 . Th e experimental results of these configurations operated at 300 and 4 .2 K ar e shown in Table 2 .3 . Another interesting application is the neural network requiring hig h speed and intensive image processing capability, which inherently re quires a fully parallel hardware embodiment . Recognition of targets in a few seconds is one of the specifications that must be met using a 64 x 6 4 pixel IR image sensor mated to a 3D stack (cube) of 64 neural networ k ICs along each of the edges . Daud et al . (269) propose the "cube" t o operate at 90 K with a signal processing speed lower than 250 ns an d approximately 2 W of power dissipation . Special designs of analo g neuron and synapse, implemented in VLSI, are presented which bear ou t
vss 'a
vss b
FIGURE 2 .110 . Architecture of the NDV (a) and POTA (b) amplifiers .
E . A . Gutiérrez-D ., C . Claeys, and E. Simoen
234
13 1M—I
El
j
I I
M13
b
M3
14
1:
M4
M7 ~
M6
5 14
Vou t
V ou t 8
I 6
M5
M 15
VD D
V DD M 10 M8 M 16 C f 34 10 M2 I- 2 12 E2 1 17 •
M9
M 12
I
15
1
v ss a FIGURE 2 .111 .
b
Architecture of the NDC (a) and DCL (b) amplifiers .
high-speed response at room temperature with synapse—neuron signa l propagation times lower than 150 ns . In order to increase the size of th e VLSI networks, die stacking is used to form a cube constructed fro m many thinned die that occupy the same footprint as a single die . In this case, a 64 x 64 image sensor is mated to a stack of 64 neural networks . The idea of this proposal is shown in Fig . 2 .112 . The demonstration of high-speed, low-power neuron and synapse circuits enables the realization of a 3D neural network architecture for high-speed pattern recognition. Power dissipation estimated with circuit simulation is expecte d to be less than 30 mW for each neural network IC . The neural ICs wit h
Table 2 .3 Measured Results for T = 4 .2 K and T = 300 K T =300K
T =4 .2 K
Parameter
NDV
POTA NDC
DCL
NDV
POTA NDC
DC L
fT (kHz)
100
100
3800
100
360
130
322
52
lb (µA)
25
50
20
50
11
25
21
40
VB (V)
±7
±5
±5
±5
±3
±3
±5.9
±5
A0, (dB)
42
60
66
42
36
42
43
28
C~ (pF)
10
10
0
10
22
22
0
100
v 1f (1 kHz) [nV /Hz ° 5 1
71
71
45
158
56
40
P(mW) lowest
0.18
0.2
0 .5
1 .2
0 .15
6.4
16
1 .0
2. Silicon Devices and Circuits
235
FIGURE 2.112 . The 3D cube architecture (a) and the circuit diagram of a variable sigmoidal neuron (b) (269) .
64 inputs, up to 64 hidden units, and six outputs are designed fo r stacking in a 64-chip cube, resulting in more than 1 trillion connection s per second potential. This very high processing power system allows th e spatiotemporal recognition of both point and resolved objects in a constrained time . These researchers anticipate stackings of up to 1024 ICs, mated to a 1024 x 1024 imager systems . Among the imager systems, the most widely used in the field o f cryoelectronics are the IR focal plane arrays . As mentioned previously, these are mated to silicon readout circuitry. This hybrid configuration is the most convenient for high-performance applications, in which the
236
E . A . Guti érrez -D ., C . Claeys, and E . Simoe n
Table 2 .4 Predicted Characteristics of the HAWAII-2 IR FPA Parameter
Minimum
Format
2048 x 2048
Pixel pitch
Off-chip temporal nois e suppressio n
µm
128 pin
Die size
Units Pixels
18
Chip package (optional)
Input circuit
Maximum
ZIF PG A
u 39 x 39
mm2
Direct detector integration correlated double sampling, Fowle r sampling 8-tap video averaging
Spatial noise suppression Supply voltage Integration capacitance Charge capacity at 0 .5 V
5 20
35
0 .102
0.105
Input offset nonuniformity Dynamic range Output taps
Conversion gain (Sv)
10 -15 F
<5 > 0 .8
1
4
32
Data rate per output tap Read noise
V
mV p—p 10 3
2 <3 ti 3 .5
10 6 e
MHz
<9
e7
µV /e
detector array and the circuit can be optimized in an independent way . It is important to note that although the materials used to fabricate th e detectors are HgCdTe, InSb, Si :Ga, Si :Ge, or doped silicon, the circuit that reads the signal from them is always silicon based . The most widely used is the submicrometer CMOS applied to IR astronomy . The most advanced approach is the HAWAII-2 2048 x 2048 CMO S FPA currently being developed by Rockwell Science Center (270) . This has four independent 1024 x 1024 quadrants combined with a 0 .8-,um CMOS circuitry . The expected characteristics of HAWAII-2 CMOS FP A are shown in Table 2 .4. Twelve 2048 x 2048 CMOS readouts will b e fabricated in a 200-mm wafer, in which each readout will be an array o f MOSFET switches comprising cascaded source follower stages that ar e separated by MOSFET switches . The signal voltage from each pixel in the array is read through the first stage source follower consisting of a pixel-based driver MOSFET and a current source FET shared among the
2 . Silicon Devices and Circuits
237
1024 elements in each column . The whole chip will be packaged using the zero insertion force pin grid array . This design anticipates about 4 . 2 million pixels, a read noise after correlated double sampling lower tha n 10 e -, a dark current at 78 K lower than 0 .1 e - Is, and a broadban d quantum efficiency larger than 50% from 0 .85 to 2 .5 ,um .
2 .6 .3 . SiGe HBT Circuits Among the SiGe-based technologies, the emitter-coupled logic bipola r technology is one of the most used for fast digital applications . The propagation delay time 'rd is the main figure-of-merit that determines th e switching speed. Increasing the cutoff frequency fT of the transistor only gives a slight reduction of T d . However, a reduction of the base resistanc e R B results in a significant reduction of T d , both of which are possible with SiGe-based bipolar technology. The first experimental examples of thi s performance improvement are those reported by Harame et al . (271) , who noted delay times of 18 .9 ps from ring oscillators fabricated wit h SiGe HBTs . A remarkable feature of SiGe HBTs is that their low bas e resistance makes it unnecessary to scale them down to submicrometer emitter widths . For instance, a gate delay of 15 ps can be obtained wit h a 1-µm SiGe HBT technology (272) compared with 20 ps of a 0 .25-µ m BJT technology (273) . The SiGe HBT technology has been modified so that two bases ca n be added, providing the chance to independently control the transisto r current, and thus forming a single-transistor NAND gate for operatio n at 77 K (274) . Low noise amplification is another potential application for SiG e HBTs . The high-frequency noise is determined by the base emitte r capacitance CBE , the base resistance RB , and the base transit time T B of the bipolar transistor . In the case of the SiGe HBTs, these parameters ca n technologically be made very small, which leads to low noise data . Fo r instance, unpassivated mesa structures used in a 9 .6-GHz hybrid dielectric resonator oscillator (275) showed — 85 dB noise at 100 KHz of f carrier . This noise level is comparable to that of III—V devices . Furthermore, the SiGe HBT has been used in very high-performance analo g applications, such as the 1 .0 Gs/s 12-bit digital-to-analog converter (276) . The most recent progress and future prospects for the cryogenic operation of SiGe technologies have been reviewed by Cressler (277) , who mentioned that the SiGe HBT technology can be successfull y manufactured on 200-mm wafers with integration levels, performance , reliability, and yield that will make it useful for realizing commercial RF and microwave integrated circuits in the 1- to 20-GHz domain . Here, the
238
E. A . Gu tiérrez-D ., C. Claeys, and E . Simoen
integration of conventional Si CMOS and BiCMOS with SiGe HBT technology is anticipated to offer considerable leverage for cryo applications because of the superior cryogenic properties of both SiGe HBT an d CMOS/BiCMOS technologies . It is also anticipated that SiGe HBT / BiCMOS technology will be required to implement "system-on-a-chip " for the emerging wireless market, and that the extension of the combination of technologies to the cryogenic environment should naturally follow . Jayanarayanan et al. (278) also reviewed the potential of silicongermanium—carbon HBTs for cryogenic application . Simulation results of the strain-compensated SiGeC HBT are presented in the 300—77 K temperature range, where the limitation on the amount of Ge that can b e introduced into the Si lattice can be alleviated by introducing C into the SiGe alloy . Due to the smaller lattice constant of C, very little amount s of C suffice for giving a free-strain material that offers the same devic e possibilities as SiGe . It is shown through simulations that the curren t gain and cutoff frequency for a graded-base SiGeC HBT increase substantially with cooling, yielding very high-performance transistors a t
77 K. Regarding the possible applications of SiGe HBTs for cryogeni c instruments, the radiation hardness can be a restriction for space-borne instruments such as space telescopes . However, studies on the effects o f neutron irradiation on the cryogenic performance of UHV / CVD SiG e HBTs (279), show that SiGe HBTs exposed to 1 MeV neutrons at doses ranging from 10 11 to 10 15 n / cm 2 at 300 K, and characterized over the temperature range of 300 to 8 .4 K, are sufficiently robust to bear such an irradiation without affecting their electrical performance . Further studies on the static and dynamic characteristics of SiG e HBTs operated in the 300—50 K temperature range were performed b y Aniel et al . (280) . The unity current gain frequency fT' which is extrapolated from the — 6 dB/octave roll-off of h 21 , and the maximum frequenc y frnax' which is the 0 dB frequency of the maximum available power gain , increase 75% (fT = 52 GHz at 50 K) and 30% (fmax = 68 GHz at 50 K) with respect to 300 K .
2.6 .4 .
SOI Circuits
It has been difficult to prepare SOI technology for commercialization , especially because of the high defect density, which is the major obstacl e for mass production . However, in 1998 IBM announced that it woul d produce the first SOI-based circuits (281) . IBM has prototyped micro processors, 4 MB SRAMs, and phase-locked loop circuits on SOI wafers .
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2 .6 .5. Summary The electrical performance as a function of temperature of CMOS digita l and analog circuits was reviewed. Digital circuits, such as microprocessors and multiplexers, work well at 77 and 4 .2 K, with an enhancemen t of about 1 .7 in frequency response at 77 K compared to room temperature. CMOS analog circuits works well down to 4 .2 K as preamplifier s for SQUIDs . DRAMs were observed to work to 89 K (a 256 Kb DRAM), wit h failures of the sense circuit . However, it is expected that with new technologies the results at 77 K obtained in the 1980s will be improved . Moreover, for the CMOS technologies designed for cryogenic operation , it is expected that additional improvement will be obtained for bot h digital and analog circuits. Among the bipolar-based circuits, only those fabricated with SiG e HBTs are appropriate for cryogenic application . The SiGe HBT technology is ready for mass production in 200-mm wafers for commercial RF applications in the 1- to 20-GHz range . This technology, combined with CMOS (BiCMOS), is anticipated to offer considerable leverage fo r cryogenic applications because of the superior cryogenic properties o f both SiGe HBT and CMOS / BiCMOS technologies .
2 .7 . CONCLUSION S This chapter discussed the most important and widely used Si-base d technologies, from the device level to the circuit level . Thus, the electrica l performance of MOS transistors was reviewed as a function of temperature . The review was based on two of the most popular models used b y IC designers . The predicted results were compared to experimental data , and discrepancies were discussed based on physical properties . W e discussed the future of deep submicrometer MOSFETs for cryogeni c operation . Following the trend of the CMOS evolution, we conclude that by th e end of the Year 2000 gigaintegrated CMOS systems, with more than 10 9 transistors on chip operated at frequencies above 1 GHz, will be available, and that deep submicrometer and nano MOSFETs indicate a promising future for cryogenic applications . SOI MOS transistors were also reviewed, including the basic operatin g principles and the different structures . It is expected that commercial us e of high-volume products will become feasible in the near future, indicated by research at IBM . SOI also has a strong potential for cryogeni c applications, in which it can be applied for hard-radiation systems .
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Bipolar technology was also discussed in this chapter . The different topologies of bipolar transistors were reviewed, and we concluded tha t the only bipolar transistor appropriate for cryogenic applications is th e SiGe HBT, which shows a remarkable performance at temperatures as low as 77 K . The SiGe HBT can be combined with CMOS to exploit th e cryogenic benefits of both technologies . In addition to transistors, radiation detectors were also analyzed a s possible prospects for cryogenic applications . The versatility of Si-base d photodetectors is remarkable; they are able to cover the spectral rang e from soft X-ray up to mid-IR, passing through the visible range . They are also able to operate at room temperature to 4 .2 K with excellen t electrooptical performance. Among these photodetectors, the CCDs, photodiodes, and SBDs are the most versatile . They cover the soft X-ray to the IR wavelength range and work well in the 300-4 .2 K temperature range. Furthermore, there is a trend toward the implementation of monolithic Si-based technology detectors . This is more clear fo r the IR spectral region, for which SBDs have been shown to be CMO S compatible . In the field of circuits applications, CMOS technology has bee n shown to be ready for digital and analog application for temperatures a s low as 4.2 K. The SiGe HBT is a good candidate for RF and wireless applications in the 1- to 20-GHz range . This technology combined wit h CMOS (BiCMOS) is anticipated to offer considerable leverage fo r cryogenic applications because of the superior cryogenic properties o f both SiGe HBT and CMOS/BiCMOS technologies .
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