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Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs
Solid State Electronics 159 (2019) 83–89
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Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs
T
Bruna Cardoso Paza, , Mikaël Casséb, Sylvain Barraudb, Gilles Reimboldb, Maud Vinetb, Olivier Faynotb, Marcelo Antonio Pavanelloa ⁎
a b
Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France
ARTICLE INFO
ABSTRACT
Keywords: SiGe SGOI Strain Nanowire Low temperature Quantum transport Analog parameters
This work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasiplanar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20 nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor.
1. Introduction Multiple gate transistors have been proposed to improve the electrostatic integrity and therefore reduce undesirable short channel effects (SCE) occurrence in aggressively scaled MOSFETs [1,2]. Since the electrostatic coupling increases when scaling down transistors crosssection dimensions, i.e. fin width (WFIN) and fin height (HFIN), advanced scaled triple gate transistors have shown to be promising structures for future technological nodes [3,4]. Recently, Ω-shaped MOSFETs with both HFIN and WFIN with similar dimensions, in the order of 10–15 nm, have been referred in literature as nanowires (NWs) [5–8]. Nanowires have shown to promote high charge control on the channel region, reduced SCE and great scalability, which leads to excellent electrical properties for both digital and analog applications [5,9–12]. Moreover, due to their nanometer-size channel, quantum transport can be evidenced in aggressively scaled nanowires at low temperatures [13,14]. In order to accomplish ITRS requests for higher drive current [15], different alternative technologies have been under study and integrated in the fabrication process of nanowires to increase carriers mobility, ⁎
Corresponding author. E-mail address: [email protected] (B.C. Paz).
https://doi.org/10.1016/j.sse.2019.03.041
Available online 19 March 2019 0038-1101/ © 2019 Elsevier Ltd. All rights reserved.
such as strain engineering [16]. Strained nanowires have shown to be a promising alternative to allow the continuity of the CMOS roadmap and attracted the interest of both scientific community and semiconductor industry [8,16]. Compressively strained SiGe material has been widely investigated in multiple gate structures, showing high drain current for p-MOSFETs thanks to hole mobility enhancement [17,18]. However, no reports in literature present a complete study of SiGe-on-insulator nanowires operation under cryogenic temperatures with evidences of quantum transport. It is important to mention that cryogenic electronics are of high interest for several applications, such as in the spatial industry, medical diagnostics and cooled systems, where not only digital circuits are required, but also mixed analog-digital ones. In this work we present the performance and transport of p-MOSFET SGOI NWs operating from room temperature down to cryogenic temperatures. Digital parameters, transconductance (gm) oscillations and effective mobility (µeff) are analyzed down to 5.2 K as a function of fin width. Results are compared to unstrained p-MOSFET Silicon-On-Insulator (SOI) NWs. Analog parameters are also investigated for the narrowest available SGOI NW down to 10 K.
Solid State Electronics 159 (2019) 83–89
B.C. Paz, et al.
The paper is organized as follows: Section 2 details the devices characteristics of the studied p-MOSFET SGOI NWs. Section 3 presents the obtained results and discussion on the low temperature influence over basic MOSFET electrical parameters (Section 3.1), quantum confinement evidences (Section 3.2), transport (Section 3.3) and analog performance (Section 3.4). Finally, Section 4 points out the main conclusions of this work. 2. Devices characteristics The Ω-gate [1 1 0]-oriented SGOI NWs have been fabricated at CEALETI with buried oxide thickness (tBOX) of 145 nm, Si0.7Ge0.3 channel with thickness of 13 nm, Si0.7Ge0.3:B raised source and drain and channel length (L) of 10 µm. The gate stack is composed by HfSiON/TiN leading to an effective oxide thickness (EOT) of 1.4 nm. Devices with WFIN = 10 µm (quasi-planar structure) have a single fin while narrower transistors are multiple finger structures of 50 fins. The channel of wide SGOI devices (typically WFIN > 240 nm) is under compressive biaxial strain corresponding to ∼2.1 GPa. Strain relaxation occurs on the SiGe stripe edges for narrower transistors, converting the biaxial stress into uniaxial compressive stress along [1 1 0] direction [18]. Unstrained SOI NWs used for comparison present similar gate stack, tBOX, L and number of fins as the studied SGOI NWs. Besides, SOI NWs present Si source and drain and thickness of Si channel equal to 11 nm. Further fabrication details of both NWs structures can be found in [6,18,19]. 3. Results and discussion
Fig. 2. Absolute threshold voltage as a function of temperature for p-NWs SGOI (a) and SOI (b) with different WFIN at VDS = −40 mV. Threshold voltage dependence on temperature has been extracted from linear regression of data points and is indicated for each device.
3.1. Basic MOSFET electrical parameters Fig. 1 presents drain current (IDS) normalized by the effective channel width (Weff calculated from the approximation for triple gate transistors: WFIN + 2HFIN) as a function of gate to source voltage (VGS) in both linear (a) and logarithmic (b) scales, at low drain bias (VDS = −40 mV). Results compare uniaxially strained SGOI to unstrained SOI NWs with WFIN = 20 nm at room and cryogenic temperatures (300 K and 10 K). It is observed higher IDS/Weff at low temperature and also for SGOI NW in comparison to SOI NW due to expected holes mobility increase. Fig. 1b highlights the subthreshold regime, where steeper slope is found at 10 K and threshold voltage (VTH) mismatches between SGOI and SOI transistors can be noted. No clear step-like behavior (oscillations) related to quantum effects are observed for IDS/Weff at 10 K.
Fig. 2 presents VTH as a function of T for SGOI (a) and SOI (b) NWs with several values of WFIN (from 15 nm to 10 µm), extracted from the second derivative method at VDS = −40 mV. As expected from results shown in Fig. 1, Fig. 2 shows lower |VTH| for SGOI devices in comparison to SOI ones independently of WFIN due to lower band gap for SiGe and valence band offsets [20]. Comparing SGOI to SOI devices, the |VTH| difference between both strained and unstrained technologies reduces with WFIN decrease due to stress relaxation, which means that |VTH| is lower for biaxial stress (WFIN = 10 µm) in comparison to uniaxial stress. Fig. 2a shows that |VTH| of SGOI devices with WFIN = 10 µm and 15 nm varies 150 mV and 80 mV at 300 K and 10 K, respectively. Fig. 2b shows smaller |VTH| variation with WFIN reduction for unstrained SOI NWs, smaller than 30 mV while reducing WFIN from 10 µm to 15 nm. Linear regression of data points has been used to extract the threshold voltage dependence on temperature (ΔVTH/ΔT) for each device in Fig. 2. Higher ΔVTH/ΔT is observed for wider NWs in comparison to narrow ones because of increased surface potential variation with temperature, as previously discussed in literature for FinFETs [21]. Results show that ΔVTH/ΔT decreases from 0.78 mV/K to 0.53 mV/K for SGOI NWs with WFIN ranging from 10 µm to 15 nm. For SOI NWs, ΔVTH/ΔT decreases from 0.67 mV/K to 0.47 mV/K for the same range of WFIN. The slightly higher values extracted for SGOI nanowires can be related to their slightly thicker SiGe channel (13 nm) in comparison to the Si channel (11 nm) of the SOI NWs. Fig. 3 presents the subthreshold slope (S) as a function of T for pNWs SGOI with different WFIN at VDS = −40 mV. The S theoretical limit (k × T × ln(10)/q, where k is the Boltzmann constant and q is the electron charge) is also indicated in Fig. 3. It is observed that all devices (including the quasi-planar structure) present S results close to the theoretical limit, following linear temperature dependence from 300 K
Fig. 1. Normalized drain current as function of gate voltage in linear (a) and logarithmic (b) scales for p-NWs SGOI and SOI with WFIN = 20 nm, at VDS = −40 mV and T = 10 K and 300 K. 84
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Fig. 3. Subthreshold slope as a function of temperature for p-NWs SGOI with different WFIN. Dashed line indicates the theoretical limit for S calculated by k × T × ln(10)/q.
down to 100 K. For temperatures smaller than 100 K, the extracted S values starts diverging from the theoretical limit, becoming higher for lower temperatures, which is associated to the increase in the body factor thanks to higher effective trap density under cryogenic operation [22]. Fig. 5. Normalized transconductance as a function of gate voltage of p-NWs SGOI (a) and SOI (b), varying WFIN for T = 10 K, at VDS = −40 mV.
3.2. Evidence of quantum confinement effects
4.3 meV. Fig. 5 presents gm normalized by WFIN as a function of VGS for SGOI (a) and SOI (b) NWs with different WFIN at T = 10 K and VDS = −40 mV. Transconductance oscillations are mainly observed for WFIN = 20 nm for SGOI NWs (smooth oscillations are also seen around VGS = −0.7 V for WFIN = 40 nm). On the other hand, the unstrained NWs with WFIN up to 80 nm still presents clear gm oscillations. Less pronounced transconductance oscillations for strained SGOI NWs could be related to the reduction of inter-subband scattering, which is also one of the responsible for holes mobility enhancement due to strain [23,24]. Besides, it is important to remember that SOI NWs are about 2 nm thinner than the SGOI ones, which should favor energy subbands formation. Fig. 6 presents gm oscillations in details as a function of VGS for SGOI NW with WFIN = 20 nm at 5.2 K. Results are normalized by VDS and presented at VDS = −10 mV, −50 mV and −100 mV. At VDS = −10 mV, 4 distinguished peaks are observed, where the numbered dashed lines indicate VGS positions of gm minima before the subsequent peak. The differences between VGS for each gm minima of each oscillation are found to be 0.12 V and 0.08 V, also indicated in Fig. 6. From the extracted differences of VGS for each gm minima and Eq. (1) [25,26], experimental ΔE are estimated around 15 meV and 10 meV, much lower than the thermal energy (φt = 0.45 meV at 5.2 K). Fig. 6 also shows VDS influence over gm oscillations. When q × VDS is much higher than ΔE, oscillations can no longer be observed, as it is possible to note for VDS higher than −50 mV.
Fig. 4 presents transconductance (gm) results normalized by Weff as a function of VGS for p-NWs SGOI (a) and SOI (b) with WFIN = 20 nm at VDS = −40 mV and temperatures of 10 K, 100 K and 300 K. The same yaxis scale for both SGOI and SOI evidences higher transconductance results for compressively strained p-NWs. Although no oscillations were observed in IDS characteristics in Fig. 1, Fig. 4 shows some transconductance peaks (also often referred as oscillations in literature) at 50 K and mainly at 10 K for both SGOI and SOI NWs. These oscillations indicate holes confinement in two directions (across fin height and width), formation of energy subbands and one-dimensional density of states (1D DoS) [13]. As VGS increases, the energy subbands are filled and oscillations appear related to mobility degradation due to intersubband scattering [13]. If the thermal energy (φt = k × T) is much higher than energy difference between subbands (ΔE), the oscillations cannot be observed. Since the oscillations are seen below 50 K (φt = 4.3 meV), subband energy spacing should be higher than
E=
h¯ 2COX VGS 2m*q
(1)
where COX is the gate capacitance per unit area, ħ is the normalized Planck constant, m* is the effective electron mass and q is the electron charge. Fig. 7 presents gate to channel capacitance normalized by Weff as a function of VGS for quasi-planar (a) and narrow (b) SGOI NWs, varying temperature. In Fig. 7a, quasi-planar transistor shows conventional C-V
Fig. 4. Normalized transconductance as a function of gate voltage of p-NWs SGOI (a) and SOI (b) with WFIN = 20 nm, varying temperature from 300 K down to 10 K, at VDS = −40 mV. 85
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Fig. 6. Normalized transconductance as a function of gate voltage of p-NW SGOI with WFIN = 20 nm, at 5.2 K and VDS = −10 mV, −50 mV and −100 mV. Dotted lines and numbers indicate VGS position of gm minimum values for each oscillation.
Fig. 8. Effective mobility as a function of inversion charge density of p-NW SGOI with WFIN = 20 nm at 5.2 K and VDS = −10 mV and −40 mV.
Fig. 7. Normalized gate to channel capacitance as a function of gate voltage for p-NWs SGOI with WFIN = 10 µm (a) and WFIN = 20 nm (b), varying temperature.
Fig. 9. Effective mobility as a function of inversion charge density for p-NWs SOI with WFIN = 20 nm (a) and WFIN = 10 µm (b), varying T from 300 K down to 10 K, at VDS = −40 mV.
behavior with shift to the right indicating |VTH| increase with temperature reduction and same maximum results related to COX for all T. On the other hand, Fig. 7b shows step-like behavior for C-V results of SGOI NW with WFIN = 20 nm at low temperature. At 5.2 K, clear CGC oscillation related to 1D DoS is observed and two plateaus can be distinguished. As previously investigated in [27], CGC oscillations mainly appear due to semiconductor capacitance change related to subbands occupation, once it is proportional to the density of states and equal to the derivative of the charge in the channel with respect to the surface potential. Moreover, CGC oscillations can slightly arise due to the dark space capacitance, related to quantum confinement [27].
Fig. 9 shows µeff as a function of Ninv for SOI NWs with WFIN = 20 nm (a) and WFIN = 10 µm, varying temperature from 300 K down to 10 K, at VDS = −40 mV. Different from the narrow SGOI in Fig. 8, Fig. 9a shows smooth mobility oscillations around the maximum mobility (µmax) for narrow SOI transistor at T = 20 K and 10 K. From Fig. 5, it is noticed that SOI NW gm oscillations are more perceptible in comparison to the SGOI NW since the differences among the amplitudes of the oscillations are higher, which explains why it is possible to observe µeff oscillation at VDS = −40 mV for the SOI NW. For T > 150 K, the SOI NW with WFIN = 20 nm presents higher effective mobility in comparison to the quasi-planar transistor. The opposite behavior is verified for T ≤ 100 K, indicating that narrow SOI nanowire presents stronger surface roughness mobility (µsr) contribution. Fig. 10 µeff as a function of Ninv for SGOI and SOI NWs with WFIN = 20 nm (a) and quasi-planar SGOI NW (b), varying T, at VDS = −40 mV. Fig. 10a shows an improvement in SGOI NW in comparison to unstrained one due to higher mobility in uniaxial compressively strained Si0.7Ge0.3. Mobility increase for SGOI NW with WFIN = 20 nm reaches 61% and 86% at 300 K and 10 K, respectively. As Fig. 10a and b presents the same y-axis scale, it is possible to observe that narrow SGOI device presents µeff
3.3. Transport parameters Fig. 8 presents µeff as a function of inversion charge density (Ninv) for SGOI NW with WFIN = 20 nm at T = 5.2 K and VDS = −10 mV and −40 mV. Results have been extracted through split C-V method. Dashed lines indicate Ninv values correspondent to VGS where gm oscillations are observed in Fig. 6. At VDS = −10 mV, very smooth µeff oscillations arise. Although quantum transport is still evidenced in gm curves at VDS = −40 mV, as indicated in Fig. 5, effective mobility oscillations disappear at this VDS value. 86
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Fig. 10. Effective mobility as a function of inversion charge density for p-NWs SGOI and SOI with WFIN = 20 nm (a) and SGOI with WFIN = 10 µm (b), varying T from 300 K down to 10 K, at VDS = −40 mV.
Fig. 12. Maximum mobility as a function of temperature for p-NWs SGOI and SOI with different WFIN at VDS = −40 mV.
respect to WFIN = 40 nm, which may be due to significant corner effects that have been evidenced in scaled triple gate NWs [31]. Fig. 12 presents µmax as a function of T for SGOI and SOI with different WFIN at VDS = −40 mV. For all devices, µmax is approximately constant below 100 K because surface roughness limited contribution dominates at these low temperatures [32]. In agreement with results shown in Fig. 9 and Fig. 10, Fig. 12 shows that the SOI NW with WFIN = 20 nm presents lower µSR than quasi-planar SOI device, probably due to poorer lateral interface quality [33]. Therefore their curves (indicated by open symbols) cross around 100 K. For the SGOI transistors, µmax keeps the same trend down to 10 K, which means that narrow SGOI nanowires exhibit higher µSR in comparison to quasiplanar SGOI transistor. According to the following expression, valid at high Ninv [32],
improvement over the quasi-planar SGOI transistor at room temperature and also at cryogenic operation (T = 10 K). Fig. 11 shows µeff as a function of WFIN for different temperatures at Ninv = 0.8 × 1013 cm−2 for SOI and SGOI NWs at VDS = −40 mV. Comparing the SOI NW with WFIN = 20 nm to WFIN = 10 µm, the effective mobility increases 18% at 300 K, due to hole mobility enhancement in (1 1 0)-oriented sidewalls in comparison to (1 0 0) inversion surface. The effect of biaxial-to-uniaxial relaxation on effective mobility can be observed in the SGOI NWs ranging from WFIN = 10 µm to WFIN = 100 nm, where enhanced µeff for uniaxial compressive strain obtained for WFIN = 100 nm is in agreement with previous results in literature [28]. For uniaxial compressive strained SGOI NWs (WFIN ≤ 100 nm), effective mobility shows almost no dependence with WFIN down to 40 nm. Although better hole mobility is expected for SiGe (1 1 0)//[1 1 0] sidewall in comparison to SiGe(1 0 0)//[1 1 0] one [29], uniaxial compressed SiGe(1 0 0)//[1 1 0] presents higher strain effect [30]. Those opposite effects for WFIN influence over µeff seem to be competing against each other and, as a result, µeff is approximately constant for SGOI NWs with WFIN ≤ 100 nm. For the narrowest dimension (WFIN = 20 nm), a mobility degradation of 17% is obtained in
1 1 1 = + µeff µph µsr
(2)
Phonon-limited mobility contribution (µph) can be estimated by subtracting µeff−1 measured at a given T ≥ 100 K from µeff−1 at 10 K, because µeff ≈ µsr at 10 K and µsr does not depend on temperature. Fig. 13 shows estimated results for µph as a function of T for narrow and quasi-planar SGOI and SOI NWs at VDS = −40 mV. With both xand y-axis in logarithmic scales, phonon mobility results show good T−γ dependence, where γ is defined as the temperature dependence coefficient [32]. Extracting γ from the linear regression of the data points (dashed lines), it is observed that both SOI and SGOI technologies present similar temperature dependence coefficient, 2.0 and 1.9 for SGOI and SOI with WFIN = 10 µm and 3.1 and 3.3 for SGOI and SOI with WFIN = 20 nm, showing slight effect of alloy scattering and strain on phonon limited mobility [34]. 3.4. Analog performance Fig. 14 presents gm/IDS as a function of IDS/(Weff/L) for SGOI NWs with WFIN = 20 nm and 10 µm, from 300 K to 10 K, at VDS = −0.9 V. Weak, moderate and strong inversion regimes are indicated. Different from previous results displayed for low drain bias, oscillations related to quantum transport should not interfere in the analysis of analog performance of devices operating in saturation, at high VDS, since q × VDS is much higher than energy difference between subbands. Fig. 14 shows that gm/IDS in weak inversion is close to 1/φt for T ≥ 100 K, which means that the body factor is close to 1. Below 100 K, gm/IDS results are much lower than 1/φt, as expected from Fig. 3a,
Fig. 11. Effective mobility extracted at Ninv = 0.8 × 1013 cm−2 and VDS = −40 mV as a function of fin width for several p-NWs SGOI and SOI varying T from 300 K down to 10 K. 87
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Fig. 15. Transconductance (left axis) and output conductance (right axis) as a function of temperature for p-NW SGOI with WFIN = 20 nm, at VDS = −0.9 V and VGT = −200 mV and −400 mV.
Fig. 13. Phonon-limited mobility as a function of temperature for p-NWs SGOI and SOI with WFIN = 20 nm and 10 µm, at VDS = −40 mV. Dashed lines indicate linear regression of data points. Extracted values for phonon-limited mobility dependence on temperature are indicated for each device.
Fig. 16. Intrinsic voltage gain (left axis) and Early voltage (right axis) as a function of temperature for p-NW SGOI with WFIN = 20 nm, at VDS = −0.9 V and VGT = −200 mV and −400 mV. Fig. 14. Transconductance over drain current as a function of normalized drain current for p-NWs SGOI with WFIN = 20 nm and 10 µm, varying T, at VDS = −0.9 V.
From gm and gD results of Fig. 15, the intrinsic voltage gain (AV) has been calculated by gm/gD and plotted in Fig. 16 as a function of T at VDS = −0.9 V and VGT = −200 mV and −400 mV. The Early voltage (VEA = IDS/gD) is also displayed. Since gm and gD temperature dependence is mainly determined by the mobility behavior, by calculating the ratio between the two parameters, a small temperature influence is verified over AV, which decreases up to 10% and 8% for VGT = −200 mV and −400 mV, respectively, considering the entire studied T range. Intrinsic voltage gain decrease with T decrease is related to the stronger gD degradation in comparison to gm improvement (i.e. increase). Therefore, both AV and VEA follow the 1/gD behavior with temperature. Similar trends have been evidenced in literature for unstrained and strained n-type nanowires [36].
where the subthreshold slope already shows divergence from the theoretical limit due to higher trap density effect. Moreover, narrow SGOI NW shows higher gm/IDS in comparison to quasi-planar transistor because of better electrostatic coupling and body factor closer to 1. Fig. 15 shows gm and output conductance (gD = ∂IDS/∂VDS) as a function of T for narrow SGOI with WFIN = 20 nm at VDS = −0.9 V and two different gate voltage overdrives (VGT = VGS − VTH). It is important to mention that VGT = −200 mV and −400 mV correspond to bias conditions where the effective mobility is close to its maximum. From the shape of both gm and gD in Fig. 15, one can note that their behavior follow the µmax dependence on temperature described in Fig. 12, where there is an increase of the parameters with T reduction down to 100 K, then gm and gD are approximately constant down to 10 K. Since IDS is proportional to µeff, gm and gD are also proportional to µeff. Moreover, gm is directly proportional to VGT and gD to VGT2, which explains the stronger influence of |VGT| increase in gD increase. The stronger gD degradation (i.e. increase) in comparison to gm increase with temperature reduction can be related to the worsening of the channel length modulation effect [35] at low temperature, once the depletion at the drain may increase, reducing the effective channel length.
4. Conclusions The temperature reduction influence on the performance of long channel Si07Ge03-On-Insulator nanowires has been presented and compared to unstrained Silicon-On-Insulator nanowires, both with variable fin widths. Larger threshold voltage variation with temperature was observed in wider nanowires. For strained SiGe and unstrained Si NWs with 15 nm of fin width, ΔVTH/ΔT of 0.53 mV/K and 0.47 mV/K were obtained. Long channel studied strained nanowires present subthreshold slope close to the theoretical limit for temperatures down to 100 K whereas for lower temperatures the subthreshold slope degrades 88
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due to interface trap density. At 5.2 K the subthreshold slope of SGOI NW with WFIN = 20 nm reaches 15 mV/dec, which represents a degradation of 14.5 times with respect to the theoretical limit. Quantum transport has been evidenced for SGOI NWs varying WFIN, VDS and temperature. Clear transconductance oscillations were observed for 20 nm-wide SGOI NW up to 50 K at VDS = −40 mV and at 5.2 K up to VDS = −50 mV. Clearer step-like behavior for gm was observed decreasing temperature, fin width and drain voltage. Gate to channel capacitance oscillations were also noted due to subbands formation below 50 K for WFIN = 20 nm, where two different plateaus can be distinguished. Low field mobility enhancement due to SiGe channel material remains as high as 86% at 10 K, comparing SGOI to SOI nanowires with WFIN of 20 nm. Temperature dependence coefficients for phonon mobility contribution of 3.1 and 3.3 were obtained for SGOI and SOI NWs with WFIN = 20 nm. Analog performance of narrow SGOI NW operating in saturation regime and cryogenic temperatures has been also evaluated. Transconductance and output conductance variation with temperature follow similar behavior as maximum mobility temperature dependence, where surface roughness mobility contribution prevails below 100 K and keep both gm and gD constant. Intrinsic voltage gain slightly decreases (up to 10%) with temperature reduction, following 1/gD trend. At 10 K and VGT = −200 mV, SGOI NW with WFIN = 20 nm presents an intrinsic voltage gain of 62 dB.
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Acknowledgements Acknowledgments to IBM/STMicroelectronics/Leti Joint Development Alliance, CNPq and FAPESP process 2015/10491-7. References [1] Colinge JP. Multiple-gate SOI MOSFETs. Solid State Electron Jun. 2004;48(6):897–905. [2] Colinge JP. FinFETs and other multi-gate transistors. Springer; 2008. [3] Colinge JP, Gao MH, Romano-Rodriguez A, Maes H, Claeys C. Silicon-on-insulator ‘gate-all-around device. International technical digest electron devices meeting, 1990. IEDM ’90. 1990. p. 595–8. [4] Kuhn KJ. Considerations for Ultimate CMOS Scaling. IEEE Trans Electron Dev 2012;59(7):1813–28. [5] Coquand R, et al. Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width. 2012 13th international conference on ultimate integration on silicon (ULIS). 2012. p. 37–40. [6] Barraud S, et al. Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm. IEEE Electron Dev Lett 2012;33(11):1526–8. [7] Bangsaruntip S, et al. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling. 2009 IEEE international electron devices meeting (IEDM). 2009. p. 1–4. [8] Coquand R, et al. Strain-induced performance enhancement of tri-gate and omegagate nanowire FETs scaled down to 10nm Width. 2012 symposium on VLSI technology (VLSIT). 2012. p. 13–4. [9] Pan C, et al. Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node. IEEE Trans Electron Dev 2015;62(10):3125–32. [10] Smith JA, et al. Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications. 2017 47th European Solid-state device research conference (ESSDERC). 2017. p. 188–91. [11] Deshpande V, et al. Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities. 2012 Proceedings of the European solid-state device research conference (ESSDERC). 2012. p. 121–4.
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Solid State Electronics journal homepage: www.elsevier.com/locate/sse
Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs
T
Bruna Cardoso Paza, , Mikaël Casséb, Sylvain Barraudb, Gilles Reimboldb, Maud Vinetb, Olivier Faynotb, Marcelo Antonio Pavanelloa ⁎
a b
Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France
ARTICLE INFO
ABSTRACT
Keywords: SiGe SGOI Strain Nanowire Low temperature Quantum transport Analog parameters
This work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasiplanar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20 nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor.
1. Introduction Multiple gate transistors have been proposed to improve the electrostatic integrity and therefore reduce undesirable short channel effects (SCE) occurrence in aggressively scaled MOSFETs [1,2]. Since the electrostatic coupling increases when scaling down transistors crosssection dimensions, i.e. fin width (WFIN) and fin height (HFIN), advanced scaled triple gate transistors have shown to be promising structures for future technological nodes [3,4]. Recently, Ω-shaped MOSFETs with both HFIN and WFIN with similar dimensions, in the order of 10–15 nm, have been referred in literature as nanowires (NWs) [5–8]. Nanowires have shown to promote high charge control on the channel region, reduced SCE and great scalability, which leads to excellent electrical properties for both digital and analog applications [5,9–12]. Moreover, due to their nanometer-size channel, quantum transport can be evidenced in aggressively scaled nanowires at low temperatures [13,14]. In order to accomplish ITRS requests for higher drive current [15], different alternative technologies have been under study and integrated in the fabrication process of nanowires to increase carriers mobility, ⁎
Corresponding author. E-mail address: [email protected] (B.C. Paz).
https://doi.org/10.1016/j.sse.2019.03.041
Available online 19 March 2019 0038-1101/ © 2019 Elsevier Ltd. All rights reserved.
such as strain engineering [16]. Strained nanowires have shown to be a promising alternative to allow the continuity of the CMOS roadmap and attracted the interest of both scientific community and semiconductor industry [8,16]. Compressively strained SiGe material has been widely investigated in multiple gate structures, showing high drain current for p-MOSFETs thanks to hole mobility enhancement [17,18]. However, no reports in literature present a complete study of SiGe-on-insulator nanowires operation under cryogenic temperatures with evidences of quantum transport. It is important to mention that cryogenic electronics are of high interest for several applications, such as in the spatial industry, medical diagnostics and cooled systems, where not only digital circuits are required, but also mixed analog-digital ones. In this work we present the performance and transport of p-MOSFET SGOI NWs operating from room temperature down to cryogenic temperatures. Digital parameters, transconductance (gm) oscillations and effective mobility (µeff) are analyzed down to 5.2 K as a function of fin width. Results are compared to unstrained p-MOSFET Silicon-On-Insulator (SOI) NWs. Analog parameters are also investigated for the narrowest available SGOI NW down to 10 K.
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The paper is organized as follows: Section 2 details the devices characteristics of the studied p-MOSFET SGOI NWs. Section 3 presents the obtained results and discussion on the low temperature influence over basic MOSFET electrical parameters (Section 3.1), quantum confinement evidences (Section 3.2), transport (Section 3.3) and analog performance (Section 3.4). Finally, Section 4 points out the main conclusions of this work. 2. Devices characteristics The Ω-gate [1 1 0]-oriented SGOI NWs have been fabricated at CEALETI with buried oxide thickness (tBOX) of 145 nm, Si0.7Ge0.3 channel with thickness of 13 nm, Si0.7Ge0.3:B raised source and drain and channel length (L) of 10 µm. The gate stack is composed by HfSiON/TiN leading to an effective oxide thickness (EOT) of 1.4 nm. Devices with WFIN = 10 µm (quasi-planar structure) have a single fin while narrower transistors are multiple finger structures of 50 fins. The channel of wide SGOI devices (typically WFIN > 240 nm) is under compressive biaxial strain corresponding to ∼2.1 GPa. Strain relaxation occurs on the SiGe stripe edges for narrower transistors, converting the biaxial stress into uniaxial compressive stress along [1 1 0] direction [18]. Unstrained SOI NWs used for comparison present similar gate stack, tBOX, L and number of fins as the studied SGOI NWs. Besides, SOI NWs present Si source and drain and thickness of Si channel equal to 11 nm. Further fabrication details of both NWs structures can be found in [6,18,19]. 3. Results and discussion
Fig. 2. Absolute threshold voltage as a function of temperature for p-NWs SGOI (a) and SOI (b) with different WFIN at VDS = −40 mV. Threshold voltage dependence on temperature has been extracted from linear regression of data points and is indicated for each device.
3.1. Basic MOSFET electrical parameters Fig. 1 presents drain current (IDS) normalized by the effective channel width (Weff calculated from the approximation for triple gate transistors: WFIN + 2HFIN) as a function of gate to source voltage (VGS) in both linear (a) and logarithmic (b) scales, at low drain bias (VDS = −40 mV). Results compare uniaxially strained SGOI to unstrained SOI NWs with WFIN = 20 nm at room and cryogenic temperatures (300 K and 10 K). It is observed higher IDS/Weff at low temperature and also for SGOI NW in comparison to SOI NW due to expected holes mobility increase. Fig. 1b highlights the subthreshold regime, where steeper slope is found at 10 K and threshold voltage (VTH) mismatches between SGOI and SOI transistors can be noted. No clear step-like behavior (oscillations) related to quantum effects are observed for IDS/Weff at 10 K.
Fig. 2 presents VTH as a function of T for SGOI (a) and SOI (b) NWs with several values of WFIN (from 15 nm to 10 µm), extracted from the second derivative method at VDS = −40 mV. As expected from results shown in Fig. 1, Fig. 2 shows lower |VTH| for SGOI devices in comparison to SOI ones independently of WFIN due to lower band gap for SiGe and valence band offsets [20]. Comparing SGOI to SOI devices, the |VTH| difference between both strained and unstrained technologies reduces with WFIN decrease due to stress relaxation, which means that |VTH| is lower for biaxial stress (WFIN = 10 µm) in comparison to uniaxial stress. Fig. 2a shows that |VTH| of SGOI devices with WFIN = 10 µm and 15 nm varies 150 mV and 80 mV at 300 K and 10 K, respectively. Fig. 2b shows smaller |VTH| variation with WFIN reduction for unstrained SOI NWs, smaller than 30 mV while reducing WFIN from 10 µm to 15 nm. Linear regression of data points has been used to extract the threshold voltage dependence on temperature (ΔVTH/ΔT) for each device in Fig. 2. Higher ΔVTH/ΔT is observed for wider NWs in comparison to narrow ones because of increased surface potential variation with temperature, as previously discussed in literature for FinFETs [21]. Results show that ΔVTH/ΔT decreases from 0.78 mV/K to 0.53 mV/K for SGOI NWs with WFIN ranging from 10 µm to 15 nm. For SOI NWs, ΔVTH/ΔT decreases from 0.67 mV/K to 0.47 mV/K for the same range of WFIN. The slightly higher values extracted for SGOI nanowires can be related to their slightly thicker SiGe channel (13 nm) in comparison to the Si channel (11 nm) of the SOI NWs. Fig. 3 presents the subthreshold slope (S) as a function of T for pNWs SGOI with different WFIN at VDS = −40 mV. The S theoretical limit (k × T × ln(10)/q, where k is the Boltzmann constant and q is the electron charge) is also indicated in Fig. 3. It is observed that all devices (including the quasi-planar structure) present S results close to the theoretical limit, following linear temperature dependence from 300 K
Fig. 1. Normalized drain current as function of gate voltage in linear (a) and logarithmic (b) scales for p-NWs SGOI and SOI with WFIN = 20 nm, at VDS = −40 mV and T = 10 K and 300 K. 84
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Fig. 3. Subthreshold slope as a function of temperature for p-NWs SGOI with different WFIN. Dashed line indicates the theoretical limit for S calculated by k × T × ln(10)/q.
down to 100 K. For temperatures smaller than 100 K, the extracted S values starts diverging from the theoretical limit, becoming higher for lower temperatures, which is associated to the increase in the body factor thanks to higher effective trap density under cryogenic operation [22]. Fig. 5. Normalized transconductance as a function of gate voltage of p-NWs SGOI (a) and SOI (b), varying WFIN for T = 10 K, at VDS = −40 mV.
3.2. Evidence of quantum confinement effects
4.3 meV. Fig. 5 presents gm normalized by WFIN as a function of VGS for SGOI (a) and SOI (b) NWs with different WFIN at T = 10 K and VDS = −40 mV. Transconductance oscillations are mainly observed for WFIN = 20 nm for SGOI NWs (smooth oscillations are also seen around VGS = −0.7 V for WFIN = 40 nm). On the other hand, the unstrained NWs with WFIN up to 80 nm still presents clear gm oscillations. Less pronounced transconductance oscillations for strained SGOI NWs could be related to the reduction of inter-subband scattering, which is also one of the responsible for holes mobility enhancement due to strain [23,24]. Besides, it is important to remember that SOI NWs are about 2 nm thinner than the SGOI ones, which should favor energy subbands formation. Fig. 6 presents gm oscillations in details as a function of VGS for SGOI NW with WFIN = 20 nm at 5.2 K. Results are normalized by VDS and presented at VDS = −10 mV, −50 mV and −100 mV. At VDS = −10 mV, 4 distinguished peaks are observed, where the numbered dashed lines indicate VGS positions of gm minima before the subsequent peak. The differences between VGS for each gm minima of each oscillation are found to be 0.12 V and 0.08 V, also indicated in Fig. 6. From the extracted differences of VGS for each gm minima and Eq. (1) [25,26], experimental ΔE are estimated around 15 meV and 10 meV, much lower than the thermal energy (φt = 0.45 meV at 5.2 K). Fig. 6 also shows VDS influence over gm oscillations. When q × VDS is much higher than ΔE, oscillations can no longer be observed, as it is possible to note for VDS higher than −50 mV.
Fig. 4 presents transconductance (gm) results normalized by Weff as a function of VGS for p-NWs SGOI (a) and SOI (b) with WFIN = 20 nm at VDS = −40 mV and temperatures of 10 K, 100 K and 300 K. The same yaxis scale for both SGOI and SOI evidences higher transconductance results for compressively strained p-NWs. Although no oscillations were observed in IDS characteristics in Fig. 1, Fig. 4 shows some transconductance peaks (also often referred as oscillations in literature) at 50 K and mainly at 10 K for both SGOI and SOI NWs. These oscillations indicate holes confinement in two directions (across fin height and width), formation of energy subbands and one-dimensional density of states (1D DoS) [13]. As VGS increases, the energy subbands are filled and oscillations appear related to mobility degradation due to intersubband scattering [13]. If the thermal energy (φt = k × T) is much higher than energy difference between subbands (ΔE), the oscillations cannot be observed. Since the oscillations are seen below 50 K (φt = 4.3 meV), subband energy spacing should be higher than
E=
h¯ 2COX VGS 2m*q
(1)
where COX is the gate capacitance per unit area, ħ is the normalized Planck constant, m* is the effective electron mass and q is the electron charge. Fig. 7 presents gate to channel capacitance normalized by Weff as a function of VGS for quasi-planar (a) and narrow (b) SGOI NWs, varying temperature. In Fig. 7a, quasi-planar transistor shows conventional C-V
Fig. 4. Normalized transconductance as a function of gate voltage of p-NWs SGOI (a) and SOI (b) with WFIN = 20 nm, varying temperature from 300 K down to 10 K, at VDS = −40 mV. 85
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Fig. 6. Normalized transconductance as a function of gate voltage of p-NW SGOI with WFIN = 20 nm, at 5.2 K and VDS = −10 mV, −50 mV and −100 mV. Dotted lines and numbers indicate VGS position of gm minimum values for each oscillation.
Fig. 8. Effective mobility as a function of inversion charge density of p-NW SGOI with WFIN = 20 nm at 5.2 K and VDS = −10 mV and −40 mV.
Fig. 7. Normalized gate to channel capacitance as a function of gate voltage for p-NWs SGOI with WFIN = 10 µm (a) and WFIN = 20 nm (b), varying temperature.
Fig. 9. Effective mobility as a function of inversion charge density for p-NWs SOI with WFIN = 20 nm (a) and WFIN = 10 µm (b), varying T from 300 K down to 10 K, at VDS = −40 mV.
behavior with shift to the right indicating |VTH| increase with temperature reduction and same maximum results related to COX for all T. On the other hand, Fig. 7b shows step-like behavior for C-V results of SGOI NW with WFIN = 20 nm at low temperature. At 5.2 K, clear CGC oscillation related to 1D DoS is observed and two plateaus can be distinguished. As previously investigated in [27], CGC oscillations mainly appear due to semiconductor capacitance change related to subbands occupation, once it is proportional to the density of states and equal to the derivative of the charge in the channel with respect to the surface potential. Moreover, CGC oscillations can slightly arise due to the dark space capacitance, related to quantum confinement [27].
Fig. 9 shows µeff as a function of Ninv for SOI NWs with WFIN = 20 nm (a) and WFIN = 10 µm, varying temperature from 300 K down to 10 K, at VDS = −40 mV. Different from the narrow SGOI in Fig. 8, Fig. 9a shows smooth mobility oscillations around the maximum mobility (µmax) for narrow SOI transistor at T = 20 K and 10 K. From Fig. 5, it is noticed that SOI NW gm oscillations are more perceptible in comparison to the SGOI NW since the differences among the amplitudes of the oscillations are higher, which explains why it is possible to observe µeff oscillation at VDS = −40 mV for the SOI NW. For T > 150 K, the SOI NW with WFIN = 20 nm presents higher effective mobility in comparison to the quasi-planar transistor. The opposite behavior is verified for T ≤ 100 K, indicating that narrow SOI nanowire presents stronger surface roughness mobility (µsr) contribution. Fig. 10 µeff as a function of Ninv for SGOI and SOI NWs with WFIN = 20 nm (a) and quasi-planar SGOI NW (b), varying T, at VDS = −40 mV. Fig. 10a shows an improvement in SGOI NW in comparison to unstrained one due to higher mobility in uniaxial compressively strained Si0.7Ge0.3. Mobility increase for SGOI NW with WFIN = 20 nm reaches 61% and 86% at 300 K and 10 K, respectively. As Fig. 10a and b presents the same y-axis scale, it is possible to observe that narrow SGOI device presents µeff
3.3. Transport parameters Fig. 8 presents µeff as a function of inversion charge density (Ninv) for SGOI NW with WFIN = 20 nm at T = 5.2 K and VDS = −10 mV and −40 mV. Results have been extracted through split C-V method. Dashed lines indicate Ninv values correspondent to VGS where gm oscillations are observed in Fig. 6. At VDS = −10 mV, very smooth µeff oscillations arise. Although quantum transport is still evidenced in gm curves at VDS = −40 mV, as indicated in Fig. 5, effective mobility oscillations disappear at this VDS value. 86
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Fig. 10. Effective mobility as a function of inversion charge density for p-NWs SGOI and SOI with WFIN = 20 nm (a) and SGOI with WFIN = 10 µm (b), varying T from 300 K down to 10 K, at VDS = −40 mV.
Fig. 12. Maximum mobility as a function of temperature for p-NWs SGOI and SOI with different WFIN at VDS = −40 mV.
respect to WFIN = 40 nm, which may be due to significant corner effects that have been evidenced in scaled triple gate NWs [31]. Fig. 12 presents µmax as a function of T for SGOI and SOI with different WFIN at VDS = −40 mV. For all devices, µmax is approximately constant below 100 K because surface roughness limited contribution dominates at these low temperatures [32]. In agreement with results shown in Fig. 9 and Fig. 10, Fig. 12 shows that the SOI NW with WFIN = 20 nm presents lower µSR than quasi-planar SOI device, probably due to poorer lateral interface quality [33]. Therefore their curves (indicated by open symbols) cross around 100 K. For the SGOI transistors, µmax keeps the same trend down to 10 K, which means that narrow SGOI nanowires exhibit higher µSR in comparison to quasiplanar SGOI transistor. According to the following expression, valid at high Ninv [32],
improvement over the quasi-planar SGOI transistor at room temperature and also at cryogenic operation (T = 10 K). Fig. 11 shows µeff as a function of WFIN for different temperatures at Ninv = 0.8 × 1013 cm−2 for SOI and SGOI NWs at VDS = −40 mV. Comparing the SOI NW with WFIN = 20 nm to WFIN = 10 µm, the effective mobility increases 18% at 300 K, due to hole mobility enhancement in (1 1 0)-oriented sidewalls in comparison to (1 0 0) inversion surface. The effect of biaxial-to-uniaxial relaxation on effective mobility can be observed in the SGOI NWs ranging from WFIN = 10 µm to WFIN = 100 nm, where enhanced µeff for uniaxial compressive strain obtained for WFIN = 100 nm is in agreement with previous results in literature [28]. For uniaxial compressive strained SGOI NWs (WFIN ≤ 100 nm), effective mobility shows almost no dependence with WFIN down to 40 nm. Although better hole mobility is expected for SiGe (1 1 0)//[1 1 0] sidewall in comparison to SiGe(1 0 0)//[1 1 0] one [29], uniaxial compressed SiGe(1 0 0)//[1 1 0] presents higher strain effect [30]. Those opposite effects for WFIN influence over µeff seem to be competing against each other and, as a result, µeff is approximately constant for SGOI NWs with WFIN ≤ 100 nm. For the narrowest dimension (WFIN = 20 nm), a mobility degradation of 17% is obtained in
1 1 1 = + µeff µph µsr
(2)
Phonon-limited mobility contribution (µph) can be estimated by subtracting µeff−1 measured at a given T ≥ 100 K from µeff−1 at 10 K, because µeff ≈ µsr at 10 K and µsr does not depend on temperature. Fig. 13 shows estimated results for µph as a function of T for narrow and quasi-planar SGOI and SOI NWs at VDS = −40 mV. With both xand y-axis in logarithmic scales, phonon mobility results show good T−γ dependence, where γ is defined as the temperature dependence coefficient [32]. Extracting γ from the linear regression of the data points (dashed lines), it is observed that both SOI and SGOI technologies present similar temperature dependence coefficient, 2.0 and 1.9 for SGOI and SOI with WFIN = 10 µm and 3.1 and 3.3 for SGOI and SOI with WFIN = 20 nm, showing slight effect of alloy scattering and strain on phonon limited mobility [34]. 3.4. Analog performance Fig. 14 presents gm/IDS as a function of IDS/(Weff/L) for SGOI NWs with WFIN = 20 nm and 10 µm, from 300 K to 10 K, at VDS = −0.9 V. Weak, moderate and strong inversion regimes are indicated. Different from previous results displayed for low drain bias, oscillations related to quantum transport should not interfere in the analysis of analog performance of devices operating in saturation, at high VDS, since q × VDS is much higher than energy difference between subbands. Fig. 14 shows that gm/IDS in weak inversion is close to 1/φt for T ≥ 100 K, which means that the body factor is close to 1. Below 100 K, gm/IDS results are much lower than 1/φt, as expected from Fig. 3a,
Fig. 11. Effective mobility extracted at Ninv = 0.8 × 1013 cm−2 and VDS = −40 mV as a function of fin width for several p-NWs SGOI and SOI varying T from 300 K down to 10 K. 87
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Fig. 15. Transconductance (left axis) and output conductance (right axis) as a function of temperature for p-NW SGOI with WFIN = 20 nm, at VDS = −0.9 V and VGT = −200 mV and −400 mV.
Fig. 13. Phonon-limited mobility as a function of temperature for p-NWs SGOI and SOI with WFIN = 20 nm and 10 µm, at VDS = −40 mV. Dashed lines indicate linear regression of data points. Extracted values for phonon-limited mobility dependence on temperature are indicated for each device.
Fig. 16. Intrinsic voltage gain (left axis) and Early voltage (right axis) as a function of temperature for p-NW SGOI with WFIN = 20 nm, at VDS = −0.9 V and VGT = −200 mV and −400 mV. Fig. 14. Transconductance over drain current as a function of normalized drain current for p-NWs SGOI with WFIN = 20 nm and 10 µm, varying T, at VDS = −0.9 V.
From gm and gD results of Fig. 15, the intrinsic voltage gain (AV) has been calculated by gm/gD and plotted in Fig. 16 as a function of T at VDS = −0.9 V and VGT = −200 mV and −400 mV. The Early voltage (VEA = IDS/gD) is also displayed. Since gm and gD temperature dependence is mainly determined by the mobility behavior, by calculating the ratio between the two parameters, a small temperature influence is verified over AV, which decreases up to 10% and 8% for VGT = −200 mV and −400 mV, respectively, considering the entire studied T range. Intrinsic voltage gain decrease with T decrease is related to the stronger gD degradation in comparison to gm improvement (i.e. increase). Therefore, both AV and VEA follow the 1/gD behavior with temperature. Similar trends have been evidenced in literature for unstrained and strained n-type nanowires [36].
where the subthreshold slope already shows divergence from the theoretical limit due to higher trap density effect. Moreover, narrow SGOI NW shows higher gm/IDS in comparison to quasi-planar transistor because of better electrostatic coupling and body factor closer to 1. Fig. 15 shows gm and output conductance (gD = ∂IDS/∂VDS) as a function of T for narrow SGOI with WFIN = 20 nm at VDS = −0.9 V and two different gate voltage overdrives (VGT = VGS − VTH). It is important to mention that VGT = −200 mV and −400 mV correspond to bias conditions where the effective mobility is close to its maximum. From the shape of both gm and gD in Fig. 15, one can note that their behavior follow the µmax dependence on temperature described in Fig. 12, where there is an increase of the parameters with T reduction down to 100 K, then gm and gD are approximately constant down to 10 K. Since IDS is proportional to µeff, gm and gD are also proportional to µeff. Moreover, gm is directly proportional to VGT and gD to VGT2, which explains the stronger influence of |VGT| increase in gD increase. The stronger gD degradation (i.e. increase) in comparison to gm increase with temperature reduction can be related to the worsening of the channel length modulation effect [35] at low temperature, once the depletion at the drain may increase, reducing the effective channel length.
4. Conclusions The temperature reduction influence on the performance of long channel Si07Ge03-On-Insulator nanowires has been presented and compared to unstrained Silicon-On-Insulator nanowires, both with variable fin widths. Larger threshold voltage variation with temperature was observed in wider nanowires. For strained SiGe and unstrained Si NWs with 15 nm of fin width, ΔVTH/ΔT of 0.53 mV/K and 0.47 mV/K were obtained. Long channel studied strained nanowires present subthreshold slope close to the theoretical limit for temperatures down to 100 K whereas for lower temperatures the subthreshold slope degrades 88
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due to interface trap density. At 5.2 K the subthreshold slope of SGOI NW with WFIN = 20 nm reaches 15 mV/dec, which represents a degradation of 14.5 times with respect to the theoretical limit. Quantum transport has been evidenced for SGOI NWs varying WFIN, VDS and temperature. Clear transconductance oscillations were observed for 20 nm-wide SGOI NW up to 50 K at VDS = −40 mV and at 5.2 K up to VDS = −50 mV. Clearer step-like behavior for gm was observed decreasing temperature, fin width and drain voltage. Gate to channel capacitance oscillations were also noted due to subbands formation below 50 K for WFIN = 20 nm, where two different plateaus can be distinguished. Low field mobility enhancement due to SiGe channel material remains as high as 86% at 10 K, comparing SGOI to SOI nanowires with WFIN of 20 nm. Temperature dependence coefficients for phonon mobility contribution of 3.1 and 3.3 were obtained for SGOI and SOI NWs with WFIN = 20 nm. Analog performance of narrow SGOI NW operating in saturation regime and cryogenic temperatures has been also evaluated. Transconductance and output conductance variation with temperature follow similar behavior as maximum mobility temperature dependence, where surface roughness mobility contribution prevails below 100 K and keep both gm and gD constant. Intrinsic voltage gain slightly decreases (up to 10%) with temperature reduction, following 1/gD trend. At 10 K and VGT = −200 mV, SGOI NW with WFIN = 20 nm presents an intrinsic voltage gain of 62 dB.
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