Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

Solid-State Electronics 84 (2013) 46–52

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Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs M. Koyama a,d,⇑, M. Cassé a, R. Coquand a,b,c, S. Barraud a, C. Vizioz a, C. Comboroure a, P. Perreau a, V. Maffini-Alvaro a, C. Tabone a, L. Tosti a, S. Barnola a, V. Delaye a, F. Aussenac a, G. Ghibaudo b, H. Iwai d G. Reimbold a a

CEA LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France IMEP-LAHC, MINATEC, INPG, 3 Parvis Louis Neel, 38016 Grenoble Cedex 1, France STMicroelectronics, 850 rue J. Monnet, 38926 Crolles, France d Frontier Research Center, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8502, Japan b c

a r t i c l e

i n f o

Article history: Available online 13 March 2013 Keywords: Si nanowire MOSFETs Tri-gate Omega-gate Carrier transport Uniaxial stress

a b s t r a c t We report an experimental study of the carrier transport in [1 1 0]-oriented long channel tri-gate (TG) and omega-gate (XG) silicon nanowire (SiNW) transistors cross-section down to 11 nm  10 nm. Electron and hole mobilities have been measured down to 20 K to evaluate the contribution from the dominant scattering mechanisms. We have studied and discussed the influence of channel shape, channel width and strain effect on carrier mobility. In particular, we have shown that the transport properties are mainly driven by the relative contribution of the different inversion surfaces, without noticeable differences between TG and XGNWs. We have also demonstrated the effectiveness of an additional uniaxial tensile strain in NMOS NWs down to 10 nm width. Ó 2013 Elsevier Ltd. All rights reserved.

1. Introduction Multigate transistors are strongly attractive for future CMOS technology nodes, due to their good immunity to short channel effects (subthreshold slope degradation and drain induced barrier lowering), and better electrostatic control. They offer advantages for both geometry downscaling and power consumption. These innovative 3-dimensional structures thus allow the continuing enhancement of devices performance [1]. In this context silicon nanowire (SiNW) MOSFETs have been demonstrated with remarkable performance [2,3]. The reduced dimensions of the cross-section of NW below 20 nm can lead to the confinement of carriers and change the transport properties of inversion carriers in NW devices [4,5]. Moreover the side-wall planes, with (1 1 0) crystallographic orientation, may also contribute to the total carrier mobility and modify the drain current [6]. These two effects can be the origin of complicated carrier transport properties. In addition, stress engineering is also expected to further improve the device performance [5,7]. The combination of stress and NW architecture appears as a promising solution to scale further CMOS technology. However, the understanding of carrier transport in both NMOS and PMOS SiNWs, with

⇑ Corresponding author at: CEA LETI, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. E-mail address: [email protected] (M. Koyama). 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2013.02.024

additional uniaxial strain along the channel direction, is not trivial and need experimental and theoretical investigation. In this work, we present an experimental study of the carrier transport in rectangular (tri-gate) and semi-circular (omega-gate) SiNW MOSFETs. In particular, we have focused our study on the influence of the cross-section shape, width dimensions, and the effect of a strong uniaxial tensile strain. Carrier mobility has been measured on NMOS and PMOS NW transistors down to low temperature (20 K). We have evaluated the influence of three dominant scattering mechanisms, i.e. phonon, surface roughness and Coulomb scatterings, and studied how these contributions change from wide planar to NW structure. 2. Devices and measurements Si NWs were fabricated using the top-down approach by optical lithography followed by a resist trimming process [3,8]. [1 1 0]-Oriented tri-gate (TG) and omega-gate (XG) NWs were fabricated on (1 0 0) unstrained and strained SOI (SOI and sSOI) wafers, with 10 nm Si thickness. For the NW fabrication undoped SOI wafers were used to obtain undoped channel. The conduction in TGNWs occurs in both (1 0 0) top and (1 1 0) side-wall surfaces. XGNW was formed with additional H2 annealing (indicated in Fig. 1). Strained NWs are obtained from sSOI substrate with a 1.4 GPa biaxial tensile stress. After etching, the biaxial strain reduces to a uniaxial tensile strain along the [1 1 0] channel direction, due to

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M. Koyama et al. / Solid-State Electronics 84 (2013) 46–52

W

W Structure of NW

H

H

10nm

10nm

SOI sSOI (σ = 1.4GPa)

2000

Omega-gate

H = 11 nm W = 10, 30 nm

H = 10 nm W = 23 nm

H = 10.5 nm W = 16, 36 nm

H = 8.4 nm W = 33 nm

Effective Mobility (cm2/Vs)

Tri-gate

10µm-wide FET 1800 Coulomb scattering 1600 Surface Phonon 1400 roughness scattering scattering 1200 Low 1000 800

Temperature

600

T=20K

400

T=150K

200

T=300K

High

0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

L = 10 μm, array of 50 channels

13

-2

Ninv (×10 cm ) Fig. 1. Channel dimensions (height H and top-view width W) of SiNW MOSFETs and cross-sectional TEM images of the channel of TG (left) and XG (right) SiNW MOSFETs.

3

(a)

1400

Id /Wtot (µA/µm)

10

Vd=0.9V

Tri-gate Ω-gate

Vd=0.9V 0

Vd=40mV Vd=40mV

10

-3

W=10nm H=11nm

10

-6

10

-9

-1.5

-1.0

-0.5

W=23nm H=10nm

0.0

0.5

1.0

Effective Mobility (cm2/Vs)

10

Fig. 3. Schematic exhibiting the three dominant scattering mechanisms which limits carrier mobility of MOSFET and the temperature dependent mobility behavior from 300 K to 20 K on 10 lm-wide FET.

1.5

1000

T=20K

800 600 400 200

T=300K 13

-2

Ninv (×10 cm )

(b) SOI-TG sSOI-TG

0

600

Vd=0.9V

Vd=40mV Vd=40mV

10

-3

10

-6

10

-9

-1.5

Vt shift

sSOI-TG W=16nm H=10.5nm

-1.0

-0.5

0.0

0.5

1.0

1.5

Vg (V) Fig. 2. Id–Vg characteristics on N- and P-type SiNW MOSFETs, comparing (a) unstrained TG and XGNWs and (b) unstrained- and strained-TGNWs.

lateral relaxation [3]. N- and P-type FET structures with varied widths were fabricated, from 10 lm (wide FET) down to 10 nm (NW FET). The high-j/metal gate stack consists in 2.3 nm CVD HfSiON, 5 nm ALD TiN covered with 50 nm poly-Si. The total EOT varies from 12.5 Å for wide and TGNW FETs to 15 Å for XGNW FET, as a probable consequence of the H2 anneal. We focused our study to long channel transistors with channel length L = 10 lm. Measurements were done on the NWs with 50

Effective Mobility (cm2/Vs)

Id /Wtot (µA/µm)

TGNW (W=10nm) Wide (W=10µm)

3

Vd=0.9V

10

(a) NMOS

0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Vg (V) 10

1200

(b) PMOS 500

TGNW (W=10nm) Wide FET (W=10µm)

400 300

T=50K

200 100 0 0.0

T=300K 0.2

0.4

0.6 13

0.8

1.0

1.2

-2

Ninv (×10 cm ) Fig. 4. Effective mobility extracted as a function of Ninv on SOI TGNW and wide FETs at different temperatures (from 300 K down to 20 K) for (a) NMOS and (b) PMOS. The channel width is 10 nm and 10 lm for TGNW and wide transistors respectively.

channels in parallel in order to extract carrier mobility using the conventional split C–V technique [9]. In the following the NW width and height are defined as top-view width W and H (which is equal to the silicon film thickness tsi), as illustrated in Fig. 1. Effective mobility measurements have also been performed at low temperature, with temperature varying from 300 K down to 20 K.

M. Koyama et al. / Solid-State Electronics 84 (2013) 46–52

600 µtop 500 (a) NMOS µside-wall 400 µSi(110) 300 T=300K 200 100 TGNW (W=10nm) 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 300 µtop 250 (b) PMOS µside-wall 200 µSi(110) 150 100 50 TGNW (W=30nm) T=300K 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2

1600

Effective Mobility (cm2/Vs)

Effective Mobility (cm2/Vs)

48

(a) NMOS

1400

ΩGNW (W=23nm) TGNW (W=30nm)

1200 1000 800

T=20K

600 400 200

T=300K

0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 13

-2

Ninv (×10 cm )

13

Ninv (×10 cm-2 ) Fig. 5. Extraction of the (1 0 0) top and (1 1 0) side-wall mobility contributions at 300 K in unstrained TGNW FETs (ltop and lside-wall, see text for details) as a function of Ninv on (a) NMOS with width of 10 nm and (b) PMOS with width of 30 nm. The mobility of Si(1 1 0) wide MOSFET lSi(110) measured at 300 K is also shown as a reference.

Effective Mobility (cm2/Vs)

1400 1200

~µC

(a) NMOS TGNW (W=10nm)

1000

~µSR_top

800

(b) PMOS

700

ΩGNW (W=23nm) TGNW (W=30nm)

600 500 400

T=20K

300 200 100 0 0.0

T=300K 0.2

0.4

0.6 13

600 400

µtop µside-wall

200

~µSR_side-wall T=50K

13

-2

Ninv (×10 cm ) 800 700

~µC

600

(b) PMOS TGNW (W=10nm)

500 400

~µSR_side-wall

300 200

µtop ~µSR_top µside-wall T=50K

100 0 0.0

0.8

1.0

1.2

-2

Ninv (×10 cm )

0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Effective Mobility (cm2/Vs)

Effective Mobility (cm2/Vs)

800

0.2

0.4

0.6 13

0.8

1.0

-2

Ninv (×10 cm ) Fig. 6. Extraction of ltop and lside-wall contributions at 50 K in unstrained TGNW FETs as a function of Ninv on (a) NMOS and (b) PMOS with width of 10 nm.

3. Results and discussion Fig. 2 shows drain current (Id) vs. gate voltage (Vg) characteristics in N- and P-type NW MOSFETs with 10 lm-long channels. In Fig. 2a no significant difference are observed between TG and XG

Fig. 7. Effective mobility as a function of Ninv extracted at different temperatures for SOI TG and XGNW (a) NMOS and (b) PMOS. The channel width is 30 nm and 23 nm for TG and XGNWs respectively.

with similar dimensions. Uniaxial tensile strain provides an ON current enhancement (+83%) with a shift of the threshold voltage Vt for TG NMOS in Fig. 2b. Subthreshold slopes on the NWs are 70 mV/dec and thereby well behaved Id–Vg characteristics can be confirmed. A well known schematic showing the three dominant scattering mechanisms which limit carrier mobility of MOSFET is shown in Fig. 3. Mobility limited by phonon scattering (PS) depends on temperature more keenly than others. PS disappears at low temperature, and below 77 K, the mobility is only limited by Coulomb scattering (CS) at low inversion carrier density (Ninv) and surface roughness scattering (SRS) at higher Ninv [10,11]. Fig. 3 provides the mobility extracted on 10 lm-wide FET as an illustration of these scattering mechanisms. Effective carrier mobility (leff) has been systematically measured as a function of temperature, from room temperature down to 20 K, for all our transistors. Fig. 4 shows the electron and hole mobilities extracted as a function of inversion carrier density Ninv for SOI TGNW and wide FETs. For NWs, leff was obtained through Cgc measurement which takes into account inversion carrier density in the whole structure, including side-walls and top surface. In NMOS case, the effective mobility of TGNW is degraded compared to wide FET in the whole range of Ninv. On the other hand, the hole mobility in TGNW is improved in medium–high Ninv region. In particular, the degradation in NMOS is larger at low temperature and high Ninv (above 0.4  1013 cm2). Moreover, the maximum peak mobility lmax appears at lower Ninv for NMOS TGNW (lmax  650 cm2/V s at Ninv  0.2  1013 cm2 and T = 100 K) compared to wide FETs (lmax  800 cm2/V s at

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M. Koyama et al. / Solid-State Electronics 84 (2013) 46–52

µeff (cm /Vs) @ High Ninv

500 Tri-gate 400

+70% 300

2

2

µeff (cm /Vs) @ High Ninv

(a) NMOS

200

sSOI +55%

100 0.01

SOI 0.1

1

500

Ω-gate

400

+65%

300

+50%

200

sSOI SOI

100 0.01

10

0.1

1

10

Wtop (µm)

Wtop (µm)

Tri-gate

µeff (cm /Vs) @ High Ninv

140

sSOI SOI

120 100

-30%

2

2

µeff (cm /Vs) @ High Ninv

(b) PMOS

80 60 0.01

0.1

1

140

Ω-gate

sSOI SOI

120

-25% 100 80 60 0.01

10

Wtop (µm)

0.1

1

10

Wtop (µm)

Fig. 8. Effective mobility leff as a function of channel width Wtop for SOI and sSOI TG and XGNW (a) NMOS and (b) PMOS at 300 K. The mobility was extracted at high inversion carrier density, Ninv = 1013 cm2 for both type TGNWs. In XGNW, the mobility was extracted at Ninv = 0.9  1013 cm2 for NMOS and Ninv = 0.8  1013 cm2 for PMOS.

(a)

Strain (transport //[110]) no strain biaxial tensile uniaxial tensile // [110]

(b)

NMOS PMOS (100) (110) (100) (110) 0 0 + + -/= ++ ++ --

lateral strain relaxation [110] s-Si

[110]

BOX BoX

Fig. 9. (a) Table summarizing the effect of the stress on carrier transport along [1 1 0], for various stress configurations of interest here (mainly established from piezoresistive coefficients and results given in Refs. [12,14–21]. (b) Schematics of the lateral strain relaxation occurring in NWs.

Ninv  0.6  1013 cm2 and T = 100 K). On the other hand, there is no shift of the maximum mobility in PMOS case. The mobility improvement for PMOS and mobility degradation for NMOS is in good agreement with the increasing contribution of the (1 1 0)-oriented sidewalls as the transistor width is reduced down to NW [8]. Indeed, the hole mobility in (1 1 0)/[1 1 0] channel is higher than the one in (1 0 0)/[1 1 0] channel [11]. In contrast, the electron mobility is degraded in (1 1 0)/[1 1 0] channel. In the following we discuss the contribution of the top and sidewall surfaces on TGNW mobility (lTG), using the total mobility expressed as [6,8]:

lTG ¼

W 2H lð100Þ þ lð110Þ 2H þ W top 2H þ W sidewall

ð1Þ

where ltop and lside-wall are the mobility corresponding to each surface orientation ((1 0 0) for top surface and (1 1 0) for side-walls). Using this equation and making the reliable assumption that the (1 0 0)-oriented top mobility ltop is given by the 10 lm-wide FETs, we can de-correlate the mobility contributions of the top and the side-walls for both N- and P-type TGNWs. The extracted contributions as a function of Ninv at 300 K are shown in Fig. 5. Side-wall mobility of both NMOS and PMOS is in good agreement with the referential mobility of Si(1 1 0) wide FET, showing that the transport properties of TGNWs in strong inversion are mainly governed by the independent inversion surfaces. The extracted contributions at 50 K are plotted in Fig. 6. For NMOS, the SRS contribution in NW is drastically increased due to the side-wall contribution, in good agreement with data reported for (1 1 0)/[1 1 0] electrons in literature [11,12]. Furthermore, the maximum mobility peak in NW is shifted to lower Ninv, and could indicate a reduced CS contribution for the side-wall. For PMOS the SR-limited mobility in side-wall is slightly enhanced, leading to better mobility at high Ninv for NW compared to the wide (1 0 0) FET. Similarly to NMOS, (1 1 0) side- walls for PMOS also show lower CS contribution. In Fig. 7 we compare the electron and hole mobilities as a function of Ninv for SOI TG and XG NW FETs with similar width. For PMOS the mobility of XGNW and TGNW are very similar in the whole range of Ninv and temperature, with a slightly higher mobility at low Ninv for XGNW. On the other hand, differences appear for NMOS at low temperature: the mobility is higher for XGNW at low

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M. Koyama et al. / Solid-State Electronics 84 (2013) 46–52

(a) NMOS 3000

µeff (cm /Vs) @ High Ninv

3000

Unstrained

~µSR_wide 1000

1000

~µSR_NW Ω-gate

2

Tri-gate 100

~µSR_NW

W=33nm W=10µm

W=16nm W=10µm

300

100

20

Ω-gate

Tri-gate

W=23nm W=10µm

W=10nm W=10µm

Strained

~µSR_wide

100

20

300

100

Temperature (K)

Temperature (K)

(b) PMOS 500

µeff (cm /Vs) @ High Ninv

500

Unstrained

~µSR_NW ~µSR_wide

2

100

~µSR_NW Ω-gate

Tri-gate

100

W=33nm W=10µm

W=36nm W=10µm

300

100

20

Ω-gate

Tri-gate

W=23nm W=10µm

W=30nm W=10µm

50

Strained

~µSR_wide

50

100

20

300

Temperature (K)

Temperature (K)

Fig. 10. Effective mobility leff extracted at high Ninv as a function of temperature in SOI and sSOI (a) NMOS and (b) PMOS. The mobility was extracted at Ninv = 0.8  1013 cm2 for NMOS and Ninv = 0.7  1013 cm2 for PMOS.

3000

1000

( b) P MOS

1000

2

µmax (cm /Vs)

(a) NMOS SOI: γ ~ 0.94 sSOI: γ ~ 0.63

100

SOI: γ ~ 0.98 sSOI: γ ~ 1.25

SOI-TGNW (W=10nm) sSOI-TGNW (W=16nm) 20

300

100

100

SOI-TGNW (W=30nm) sSOI-TGNW (W=36nm) 20

Temperature (K)

(c)

100

300

Temperature (K) NMOS

Values of power law exponent γ

PMOS

SOI

sSOI

SOI

sSOI

Tri-gate

Wide (10µm)

0.95

0.64

1.00

1.18

w/o H2 anneal

NW

0.94

0.63

0.98

1.25

Ω-gate Ω

Wide (10µm)

1.05

0.69

1.03

1.07

with H2 anneal

NW

1.05

0.41

1.12

1.13

Fig. 11. Maximum mobility lmax extracted as a function of temperature in SOI and sSOI (a) NMOS and (b) PMOS TGNWs. (c) Values of the power law exponent c of the temperature dependence of leff extracted at maximum mobility lmax  Tc for all devices studied.

Ninv, while it is deteriorated at high Ninv region. A different surface roughness due to circular shape can be distinguished at 20 K. However, these results show that the shape of the NWs (rectangular vs. semi-circular) has only a little influence on carrier transport for dimension as small as 10 nm  10 nm, especially for PMOS and at 300 K. The (1 1 0)-oriented surface can still be distinguished even in the semi-circular geometry of XGNW. The difference at low Ninv

could indicate a lower CS contribution in the case of XGNWs, due to the H2 anneal process, in contrast with previous work [13]. It also confirms the change of CS contribution from H2 anneal process even in 10 lm-wide FETs. In the following, we discuss the effect of an additional uniaxial tensile strain on transport properties. Fig. 8 shows the effective mobility extracted at high inversion carrier density as a function

M. Koyama et al. / Solid-State Electronics 84 (2013) 46–52

of channel width for all SOI and sSOI transistors. For SOI transistors, the behavior is well explained by the contribution of top and side-wall mobility and the surface orientation dependence of the mobility (see table in Fig. 9a). The Si(1 1 0) side-walls are beneficial to hole transport parallel to [1 1 0], while Si(1 0 0) top surface is advantageous to electron transport. Therefore, for NMOS the mobility is degraded as top surface area decreases, i.e. as the width W decreases. On the other hand, the mobility is increased in PMOS as side-wall contribution increases. The hole mobility enhancement and the electron mobility degradation as W decreases is similar for TG and XG NWs as already noticed. For sSOI devices the effect of strain for different surface orientations and stress conditions (biaxial vs. uniaxial) has to be taken into account to understand our results. Moreover as the width decreases, the tensile biaxial stress in wide transistor (1 0 0) plane changes to a uniaxial stress along the [1 1 0] channel direction originating from lateral strain relaxation (Fig. 9b). Physical and electrical characterizations have shown that full lateral relaxation occurs in our NWs for W below roughly 50 nm [3]. Thus, a uniaxial tensile strain along [1 1 0] direction is expected to enhance electron mobility in both (1 0 0) (top surface) and (1 1 0) (side-wall) planes. The enhancement results from the strain induced repopulation of the 2-fold valleys with lighter conduction mass, and from the suppression of intervalley phonon scattering between the 2-fold (D2) and 4-fold valleys (D4) [12,21–23]. The latter contribution can be expressed as follows [22]:

1

sphonon

51

improved for strained devices. Electron mobility is degraded on narrowest width in both SOI and sSOI FETs without correlation to channel shape, in agreement with a dominant (1 1 0) surface orientation for NWs. For PMOS the mobility improvement of wide FETs and the degradation of NWs in sSOI FETs are observed in the whole temperature range. The hole mobility is degraded by SRS on uniaxial strained NWs in contrast to the improvement in biaxial strained wide FETs. Finally, Fig. 11 shows the values of the power law exponent, c, of the temperature dependent maximum mobility (lmax  Tc) extracted for all FETs studied. Above 77 K, the slope of the temperature dependent mobility is driven by PS, especially at moderate Ninv (typically around lmax). For SOI or sSOI, the values do not differ significantly for each structure: wide, TG or XGNW FETs. On the other hand, the temperature dependence changes significantly when comparing unstrained (SOI) and strained (sSOI) devices, especially for NMOS. These results are in good agreement with the temperature coefficient values which are similar for (1 0 0) and (1 1 0) planes [11]. They also indicate that the temperature dependence of phonon-limited electron and hole mobilities is mainly governed by the strain down to NW width of 10 nm. Moreover, no significant difference in the temperature dependence of leff can be observed between TG and XG NWs, revealing again no significant influence of cross-sectional shape and width dimensions. 4. Conclusion

/ DE

ð2Þ

where sphonon is relaxation time due to intervalley phonon scattering and DE is the energy splitting between the D2 and D4 valleys of the Si conduction band. The scattering rate decreases as the energy splitting enlarges due to the applied tensile stress for NMOS. The mobility is clearly degraded as the width is narrowed in both SOI and sSOI NMOS originating from increase of the (1 1 0) side-wall contribution. However, it is worth noting that the electron mobility of strained NMOS devices is still enhanced for a given width, showing the efficiency of a uniaxial strain in NW, with up to +55% gain in leff for W = 10 nm. We noticed that both TG and XGNW exhibit roughly the same mobility improvement for the same width. These results are in qualitative agreement with the piezoresistance measurements performed on corresponding NWs, giving pL = 545  1012 Pa1 and pL = + 280  1012 Pa1 for the longitudinal piezoresistive coefficients of respectively NMOS and PMOS TG [24]. The obtained mobility enhancement in TG and XG is almost similar, thus suggesting that the strain relaxation is the same in both geometries. It also indicates that piezoresistive properties are nearly identical in TG and XGNWs despite the more complex inversion surface orientations of XGNW. On the contrary, hole mobility is degraded by a tensile uniaxial stress along the channel especially for (1 0 0) top surface [14]. In (1 1 0) side-wall surface the better mobility in unstrained case is counterbalanced by the detrimental effect of a uniaxial tensile strain. As a result, as the width is decreased the total hole mobility in sSOI NWs is no more improved as compared to wide transistors, and remain roughly constant with W variation. Again TG and XGNW exhibit roughly the same mobility for a given width, in agreement with NMOS results. Next, the effective mobility extracted at a constant high Ninv (resp. 0.7 and 0.8  1013 cm2 for PMOS and NMOS) has been plotted as a function of temperature, for SOI and sSOI FETs (Fig. 10). Below 100 K, the phonon contribution becomes negligible, and the mobility at high Ninv saturates, as a consequence of the dominant SR limited contribution. TG and XGNWs also exhibit the same mobility behavior in both NMOS and PMOS case. For NMOS phonon-limited mobility at high temperature (above 100 K) is

We have carefully studied the carrier transport in strained and unstrained NWs with the channel along Si[1 1 0] direction and rectangular (TG) and rounded (XG) cross-section shape. We found that: (i) the transport properties in TGNW with Si(1 0 0) top and Si(1 1 0) side-wall surfaces are well described by the separate contribution of inversion surfaces, for rectangular sections as small as 10 nm  10 nm; (ii) XGNW mainly exhibits the same mobility behavior as TGNW, despite a more complex geometry with multiple surface orientations, for top view width down to 23 nm; (iii) Lower Coulomb scattering is observed in XGNW, as possible consequence of the H2 anneal process; (iv) Additional tensile uniaxial strain obtained from sSOI starting substrate is effective in NMOS NWs, independently of the NW geometry, and can thus be exploited to enhance NMOS performances in NW devices. Acknowledgement This work has been carried out in the frame of the ST/IBM/LETI joint program. References [1] Ferain I, Colinge CA, Colinge J-P. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 2011;479:310–6. [2] Saitoh M, Nakabayashi Y, Itokawa H, Murano M, Mizushima I, Uchida K, et al. Short-channel performance and mobility analysis of <1 1 0>- and <1 0 0>oriented tri-gate nanowire MOSFETs with raised source/drain extensions. Symp VLSI Tech Dig 2010:169–70. [3] Coquand R, Cassé M, Barraud S, Leroux P, Cooper D, Vizioz C, et al. Straininduced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10 nm width. Symp VLSI Tech Dig 2012:13–4. [4] Gnani E, Reggiani S, Rudan M, Baccarani G. Effects of the band-structure modification in silicon nanowires with small diameters. Proc ESSDERC 2006:170–3. [5] Baykan MO, Thompson SE, Nishida T. Strain effects on three-dimensional, twodimensional, and one-dimensional silicon logic devices: predicting the future of strained silicon. J Appl Phys 2010;108:093716. [6] Chen J, Saraya T, Miyaji K, Shimizu K, Hiramoto T. Experimental study of mobility in [1 1 0]- and [1 0 0]-directed multiple silicon nanowire GAA MOSFETs on (1 0 0) SOI. Symp VLSI Tech Dig 2008:32–3. [7] Liu CW, Maikap S, Yu C-Y. Mobility-enhancement technologies. IEEE circ dev mag 2005;21:21–36.

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