Newsfile Digital neurochip A high-speed digital neurochip, with an arithmetic speed more than 100 times faster than conventional systems has been developed by Toshiba. It uses advanced application specific integrated circuit (ASIC) technology, by which the optimization, learning and other arithmetic characteristics of the neurocomputer can be processed most rapidly. The company plans to commercialize the neurochip for incorporation in an engineering workstation in two to three years. This neurochip uses complementary metal oxide semiconductor (CMOS) technology with a line width of 1/Jm. Two pseudo neurons are accommodated in a single chip, while the memory requiring a large chip area is mounted outside so the chip can be miniaturized. To enable rapid processing, the chip incorporates four specialpurpose computing circuits for addition, multiplication, decimal point transfer and absolute value calculation, while the chips are designed to work at high speeds through parallel processing. An arithmetic board mounting a maximum of 64 of these chips on a printed circuit board can perform 1200 million neurocalculations s-1, and achieves processing speeds about 1000 times faster than a conventional computer using neurocalculation programs. The neurocomputer can be applied, for example, to the recognition of handwriting. Whereas several dozen hours were required for learning by conventional computers, this can be achieved in tens of seconds. The computer is also usable for recognizing images and audio sounds, for LSI design and for system optimization by apportioning tasks to parallel processing computers. Information processing in the human brain is by an analogue system, but at present digital type devices and system technologies are widely used, so the technical team introduced the completely digital system for m a s s production.
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Manufacture of neurocomputers will shift to the analogue type in the future, but it is predicted the digital type will remain in wide use for the next three to four years. (Toshiba Corporation, Public Communications Office, 1-1-1, Shibaura, Minato-ku, Tokyo 105, Japan. Tel: +81-3-34572100; Fax: +81-3-3456-4776)
Self-learning MISFET using thin film ferroelectric Prof. H Ishihara of The Precision and Intelligence Laboratory, Tokyo Institute of Technology, has devised a MISFET (metal insulator semiconductor field effect transistor) with a self-learning function like the synapse bonding of neuron cells. It has the same structure as an ordinary MOSFET but a ferroelectric thin film is used as the gate insulation film. The ferroelectric material exhibits spontaneous polarization. Lead titanate, in particular, has a learning function, with electric charge accumulating gradually, making current passage easier when a voltage is applied repeatedly. A transistor using this ferroelectric material, when a positive voltage pulse is applied to the gate, forms an inversion layer at the channel, so the FET will be switched ON. At the same time, polarization will occur inside the ferroelectric film, which will be retained after the voltage pulse is zero. By applying the pulse several times, a stationary conductive layer will be formed on the semiconductor surface, and will remain ON even after the gate voltage has been removed. Also, when a reverse voltage is applied to the gate, the transistor will be returned to the original state. In a biological neural network, multiple signals are input into the neurons via synapse bonding, and signals are output when the sum of these signals exceeds a certain level. By applying the new transistor, it will be possible to fabricate an electronic circuit with a learning function setting the threshold value (signal sum) appropriately that generates the switched-ON state. (The Precision and Intelligence Laboratory, Tokyo
Institute of Technology, 4259, Nagatsuta-cho, Midori-ku, Yokohama City, Kanagawa PreL 227, Japan. Tel: +81-45-922-1111; Fax: +81-45-921-
0898)
Low voltage digital logic A complete line of low voltage (3.3 V) digital logic devices has been announced by National Semiconductor. The low voltage quiet (LVQ) family is targeted at batteryoperated computers and comprises 19 devices ranging from gates, multiplexers and flip-flops (medium scale integration circuits) to octal transceivers. It addresses the four major concerns of the batten/operated computing marketplace: low power, low noise, low profile small footprint packaging and low price. Typical 5 V notebook computers consume 8 W of power, half of which is taken up by the motherboard. By converting to 3.3 V, the motherboard will consume approximately half this amount of power. The LVQ follows the recommendations of the JEDEC committee, JC-16, which is in the process of establishing a low voltage regulated standard. Most current generation notebook computers are being designed to operate from regulated 3.3 V power. Noise, in the form of electromagnetic interference, can affect product casing, time-to-market and size. Helping designers build products that generate less EMI means faster approvals, giving a real time-to-market advantage. The range uses the QSOP (quarter size outline package) package, which offers size and cooling advantages over SOIC and SSOP. National Semiconductor's 20-lead, 25 Mil pitch QSOP package occupies 61% less board space than a 20-lead SOIC. The lower profile allows better thermal conductivity, which increases product reliability. It also allows more room for adding daughter boards to the main motherboard. (National Semiconductor, Industriestrasse 10, D-8080 FrJsternfeldbruck, Germany. Fax: 08141 103515)
Microprocessors and Microsystems