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Low-voltage ZnO thin-film transistors operating at 2.0 V gated with mesoporous SiO2 dielectric processed at room-temperature
ARTICLE IN PRESS Physica E 42 (2009) 154–157
Contents lists available at ScienceDirect
Physica E journal homepage: www.elsevier.com/locate/physe
Low-voltage ZnO thin-film transistors operating at 2.0 V gated with mesoporous SiO2 dielectric processed at room-temperature Y. Hu a,b, A.X. Lu a, L.P. Wang a, H.C. Yu a, Q. Wan a,b, a b
Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education, Hunan University, Changsha 410082, People’s Republic of China State Key Laboratory of Silicon Materials, Zhejiang University, Hangzhou 310027, People’s Republic of China
a r t i c l e in f o
a b s t r a c t
Article history: Received 5 August 2009 Received in revised form 27 September 2009 Accepted 29 September 2009 Available online 4 October 2009
Low-voltage thin-film transistors (TFTs) with ZnO nanocrystal channel layers and mesoporous SiO2 gate dielectric are fabricated on glass substrates at room-temperature. The resulting n-type TFTs operate at a low voltage of 2.0 V. The equivalent field-effect electron mobility, current on/off ratio and subthreshold voltage swing is estimated to be 28.8 cm2 V 1 s 1, 3 106 and 84 mV/decade, respectively. The possible mechanism for low-voltage operation is discussed based on the electric double layer effect. Such roomtemperature-processed low-voltage TFTs are very promising for low-power macroelectronics on temperature-sensitive substrates. & 2009 Elsevier B.V. All rights reserved.
PACS: 61.72.uj 73.23.-b 85.30.TV Keywords: Low-voltage thin-film transistors ZnO nanocrystal Mesoporous SiO2 dielectric Electric double layer
High-performance thin-film transistors (TFTs) are fundamental building blocks for next generation macroelectronics [1,2]. TFTs with wide band-gap oxide semiconductors channels have attracted much attention over last several years because of their high field-effect mobilities, large-area fabrication and low processing temperature [3,4]. Among multifarious metal-oxide semiconductors, ZnO is one of the most promising materials as the channel layer for TFTs, not only because of the eminent semiconductor characteristics, but also partly on account of Znbased minerals enriched on earth and potentially lower cost [5–7]. The field-effect mobility was reported to be 25 cm2/V s in a polycrystalline channel layer [8,9] and as high as 70 cm2/V s in a single-crystalline channel layer [10]. At the same time, large operation voltages are often required for ZnO-based TFTs operation because commonly used SiO2 gate dielectrics provide weak capacitive coupling between the gate electrode and the semiconductor channel. TFTs capable of low-voltage operation are required to reduce the power consumption of next generation electronic devices driven by microelectronic components such as inverters, ring Corresponding author at: Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education, Hunan University, Changsha 410082, People’s Republic of China. Tel.: + 86 73188823407; fax: + 86 73188822137. E-mail address: [email protected] (Q. Wan).
1386-9477/$ - see front matter & 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.physe.2009.09.019
oscillators and backplane circuits for mobile displays [11]. A root idea for low-voltage operation is that gate insulator should have high capacitance and that increase in the capacitance is always linked to high dielectric constant (k) or thin thickness of the dielectric [12]. For example, ZnO TFTs operating at 3.0 V was demonstrated using polymer/high-k oxide double layer as the gate dielectric [13]. Another interesting approach in achieving low-voltage operation is using ion gel or ionic liquids as gate dielectrics [14,15]. For example, organic single-crystal transistors gated by ionic liquids operating at 1.0 V were demonstrated due to the huge electric double layers (EDLs) capacitance [14]. Here, we report on an alternative approach to achieve low-voltage amorphous ZnO TFTs operating at 2.0 V. Mesoporous SiO2 films containing protons were used as the gate dielectrics, and the ZnO TFTs exhibited high-performance n-type transistor characteristics with a high saturation field-effect mobility of 28.8 cm2/V s. The current on/off ratio and subthreshold swing were found to be 3 106 and 84 mV/decade, respectively. ZnO TFTs were fabricated on glass substrates with a bottomgate and top-contact source and drain electrodes. At first, ITO bottom-gate electrode film with a thickness of 200 nm was deposited on glass substrates by radio frequency (rf) sputtering at room-temperature (RT) with a fixed rf power of 100 W. The working pressure was 0.5 Pa in pure Ar ambient. Then SiO2 gate dielectric layer was deposited on ITO films by plasma-enhanced
ARTICLE IN PRESS Y. Hu et al. / Physica E 42 (2009) 154–157
chemical vapor deposition (PECVD) at RT using SiH4 and O2 as the reactive gas. For cross-section scanning electron microscopy (SEM) characterization, SiO2 films were also deposited on ITO/Si substrates. After SiO2 dielectric layer deposition, 50 nm ZnO channel layer was deposited via rf sputtering at RT with an rf power of 100 W in Ar/O2 mixed atmosphere. At last, aluminum source/drain electrodes with a thickness of 100 nm were deposited by vacuum electron-beam evaporation through a nickel shadow mask. The channel length and width-to-length ratio of the TFTs is 80 mm and 5:1, respectively. The crystal structure of the ZnO films deposited at roomtemperature was analyzed by X-ray diffraction (XRD) measurements using CuKa line. The surface morphology of ZnO films and cross-section morphology of SiO2 dielectric were analyzed by SEM (Hitachi S-4800). The electrical characterization of the ZnO films was tested by Hall Effect analyzer (HMS-3000). The electrical characteristics of the ZnO TFTs were measured in air ambient using a microprobe station connected to a semiconductor parameter analyzer (Model Keithley 4200 SCS). The capacitancefrequency (C-f) characterization of dielectric was performed by Agilent 4294A precision impedance analyzer. Fig. 1(a) shows a schematic picture of the ZnO TFTs on glass substrates. Here we should emphasize that all processes including SiO2 gate dielectric deposition were performed at roomtemperature. Thus, our technology is very promising for flexible electronics on temperature-sensitive substrates. Fig. 1(b) shows the XRD pattern of the room-temperature-deposited ZnO film. Diffraction peaks corresponding to the (1 0 0) and (11 0)
Fig. 1. (a) The schematic picture of the fabricated ZnO thin-film transistor (TFT) on glass substrates. (b) X-ray diffraction (XRD) pattern of the ZnO channel films. Inset: the SEM image of the ZnO thin film deposited at room-temperature. Scale bar: 100 nm.
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orientations of wurtzite ZnO were observed. The peaks are very weak because of the thickness of the ZnO film is 50 nm. Inset in Fig. 1(b) is a top-view SEM image of the ZnO film. A smooth and compact surface with high-density nanoclusters was observed. The resistivity, carrier concentration and hall mobility of the ZnO film are measured to be 7.32 102 O cm 1, 2.78 1014 cm 3 and 31.8 cm2/V s, respectively, by Hall Effect measurement. Fig. 2(a) shows a cross-section SEM image of the as-deposited SiO2 films. The thickness of the SiO2 films was found to be about 5.0 mm. Furthermore, mesoporous structure with nanocolumn arrays was observed. In our experiment, SiO2 deposition is a spontaneous reaction because SiH4 and O2 were used as the reactive gases, and the RF electric field between two capacitor electrodes is of great help for nanocolumn arrays formation. Fig. 2(b) shows the output characteristics (Vds–Ids) of the ZnO TFTs with mesoporous SiO2 dielectric. The devices exhibit typical ntype transistor characteristics under low operating voltage of 1.5 V. The drain current Ids increases linearly with increase in drain voltage Vds at low Vds, and saturates at higher Vds. Moreover, drain current Ids increases quickly as the gate voltage Vgs continuously increases from 0.5 to 1.5 V. A saturation current of 550 mA is obtained at the bias condition Vgs =1.5 V and Vds =1.5 V.
Fig. 2. (a) The cross-section SEM image of the mesoporous SiO2 dielectric film deposited on ITO/Si substrates at room-temperature. (b) The output characteristics of ZnO TFT.
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101
Cox (µF/cm2)
100
10-1 Al electrode Mesoporous SiO2
10-2
ITO Glass
10
-3
102
103 Frequency (Hz)
104
Fig. 4. Frequency dependence of the gate specific capacitance of mesoporous SiO2 dielectric (40 Hz to 10 kHz). Inset show the structure for capacitance measurement.
Fig.p 3.ffiffiffiffiffi(a) ffi The transfer characteristics [log(Ids) vs. Vgs for Vds = 1.5 V] of the ZnO TFT. (b) Ids vs. Vgs curve of the ZnO TFT at Vds = 1.5 V.
Fig. 3(a) shows the transfer characteristics for Vds at 1.5 V of the ZnO TFTs in the saturation region. The curve [log(Ids) vs. Vgs] indicates an off-state current is as low as 0.18 nA. The drain current on/off ratio, calculated from the drain current at maximum and minimum values, is estimated to be about 3 106, and the subthreshold swing S (S= dVgs/log|Ids|) is found to be as low as 84 mV/decade. A clear anticlockwise hysteresis is observed and the threshold voltage shift (DVth) is found to be ) and saturation mobility about 0.12 V. The threshold voltage (V pthffiffiffiffiffi (msat) are extracted from the plot ( Ids vs. Vgs), as shown by Fig. 3(b). The threshold voltage is found to be as low as 0.4 V, which indicates ZnO TFT is operated as an enhanced-type mode. And the saturation mobility (msat) is calculated by Ids = WCoxmsat(Vgs Vth)2/2L, where Cox is the capacitance per unit area of the gate dielectric, W (400 mm) and L (80 mm) are channel width and length, respectively. If the physical thickness (d= 5.0 mm) of the SiO2 was used for Cox calculation based on Cox = e0e/d, where e = 2.0 is the dielectric constant for porous SiO2 dielectric [16]. A saturation field-effect mobility value as high as 3.76 105 cm2/V s would be obtained. Obviously, this ultrahigh mobility value is unreasonable. The gate specific capacitance of mesoporous SiO2 dielectric was measured using MIM structure which consisted of a 200 nm ITO layer, a 5.0 mm SiO2 dielectric and a 100 nm Al thin film, as shown by the inset of Fig. 4. As shown in
Fig. 5. Schematic picture of the operation mechanism of the ZnO TFTs. (a) When mobile protons are accumulated at the SiO2 dielectric/channel interface, TFT is switched on under low gate voltage. (b) When mobile protons are accumulated at the SiO2 dielectric/gate electrode interface, TFT is switched off.
Fig. 4. The gate specific capacitance increases with decrease in frequency from 10 KHz to 40 Hz, and reach a maximum value of 1.88 mF/cm2 at 40 Hz. Based on Cox = e0e/d, the equivalent dielectric thickness is estimated to be 0.94 nm, which is in agreement with the reported thickness of the electric double layer (1.0 nm) [17]. In fact, proton transport in SiO2 for silicon-on-insulator type memory application was previously demonstrated [18]. Fig. 5 illustrates the possible low-voltage operation principle of the ZnO TFTs. As shown in Fig. 5(a), under positive gate bias voltage, mobile protons in mesoporous SiO2 insulator are transported to the interface between gate dielectric and channel layer. Then, high-density electrons will be induced in the active channel layer
ARTICLE IN PRESS Y. Hu et al. / Physica E 42 (2009) 154–157
near this interface, which is similar to the case of organic electric double layer transistors. When a negative gate voltage is applied, as shown in Fig. 5(b), mobile protons are attracted to the gate electrode/SiO2 interface. The ZnO channel would be switched off since the physical thickness of the dielectric is 5 mm and the gating effect of the positive protons near gate electrode can be ignored. The possible proton transport in SiO2 dielectric operation mechanism is in good agreement with the hysteresis curve that is shown in Fig. 3(a). The hysteresis in the two curves was measured due to the presence of the protons either at the gate electrode/ oxide interface or oxide/semiconductor channel. Due to the huge electric double layer gate specific capacitance, the operating voltage can be reduced to only 2.0 V, which is similar to organic transistors gated by electrolyte-gate dielectrics. According to the measured gate specific capacitance (1.88 mF/cm2) of mesoporous SiO2 dielectric at 40 Hz, then an equivalent field mobility value of 69.4 cm2/V s was estimated. Here we should point out that in the case of small channel ratios, the effective channel width is not equivalent to the geometrical channel width but is extended somewhat because of the fringing electric field at the ends of the electrodes, which can lead to the overestimation of the field-effect mobility. The field-effect mobility of undefined TFTs became overestimated by about 241% at the small geometrical channel ratio of about 5 [19]. So the reasonable mobility is estimated to be 28.8 cm2/V s, which is close to the measured mobility value by Hall Effect. In summary, low-voltage ZnO thin-film transistors operating at 2.0 V gated with mesoporous SiO2 gate dielectric were fabricated on glass substrate at room-temperature. The equivalent fieldeffect mobility, current on/off ratio and subthreshold voltage swing were estimated to be 28.8 cm2/V s, 3 106 and 84 mV/ decade, respectively. These devices had potential application for lower-power, portable electronics. At the same time, all roomtemperature processing of the TFTs demonstrated the compatibility with flexible polymeric substrates.
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Acknowledgements This work was supported by the National Natural Science Foundation of China (10874042), Program for New Century Excellent Talents in University (NCET-06-0699), Hunan Provincial Natural Science Foundation of China (07jj107), and a Foundation for the Author of National Excellent Doctoral Dissertation of People’s Republic of China (200752). References [1] A. Sazonov, D. Striakhilev, C.H. Lee, A. Nathan, Proc. IEEE 93 (2005) 1420. [2] R.A. Street, Adv. Mater. 21 (2009) 1. [3] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, H. Hosono, Nature 432 (2004) 488. [4] A. Suresh, P. Wellenius, A. Dhawan, J. Muth, Appl. Phys. Lett. 90 (2007) 123512. [5] R.L. Hoffman, B.J. Norris, J.F. Wager, Appl. Phys. Lett. 82 (2003) 733. [6] D.C. Look, J. Electron. Mater. 35 (2006) 1299. [7] U. Ozgur, Y.I. Alivov, C. Liu, A. Teke, M.A. Reshchikov, S. Dogan, V. Avrutin, S.J. Cho, K. Morkoc, J. Appl. Phys. 98 (2005) 41301. [8] R.L. Hoffman, J. Appl. Phys. 95 (2004) 5813. [9] E.M.C. Fortunato, P.M.C. Barquinha, A.C.M.B.G. Pimentel, A.M.F. Gonvalves, A.J.S. Marques, R.F.P. Martins, L.M.N. Pereira, Appl. Phys. Lett. 85 (2004) 2541. [10] T.I. Suzuki, A. Ohtomo, A. Tsukazaki, F. Sato, J. Nishii, H. Ohno, M. Kawasaki, Adv. Mater. 16 (2004) 1887. [11] J.B. Kim, C.F. Hernandez, W.J. Potscavage, X.H. Zhang, B. Kippelen, Appl. Phys. Lett. 94 (2009) 142107. [12] I.D. Kim, M.H. Lim, K. Kang, H.G. Kim, S.Y. Choi, Appl. Phys. Lett. 89 (2006) 022905. [13] K. Lee, J.H. Kim, S. Im, C.S. Kim, H.K. Baik, Appl. Phys. Lett. 89 (2006) 133507. [14] S. Ono, S. Seki, R. Hirahara, Y. Tominari, J. Takeya, Appl. Phys. Lett. 92 (2008) 103313. [15] J.H. Cho, J. Lee, Y. He, B.S. Kim, T.P. Lodge, C.D. Frisbie, Adv. Mater. 20 (2008) 686. [16] C. Murray, C. Flannery, I. Streiter, S.E. Schulz, M.R. Baklanov, K.P. Mogilnikov, C. Himcinschi, M. Friedrich, D.R.T. Zahn, T. Gessner, Microelectron. Eng. 60 (2002) 133. [17] J. Takeya, K. Yamada, K. Hara, K. Shigeto, K. Tsukagoshi, S. Ikehata, Y. Aoyagi, Appl. Phys. Lett. 88 (2006) 112102. [18] K. Vanheusden, W.L. Warren, R.A.B. Devine, D.M. Fleetwood, J.R. Schwank, M.R. Shaneyfelt, P.S. Winokur, Z.J. Lemnios, Nature 386 (1997) 587. [19] K. Okamura, D. Nikolova, N. Mechau, H. Hahn, Appl. Phys. Lett. 94 (2009) 183503.
Contents lists available at ScienceDirect
Physica E journal homepage: www.elsevier.com/locate/physe
Low-voltage ZnO thin-film transistors operating at 2.0 V gated with mesoporous SiO2 dielectric processed at room-temperature Y. Hu a,b, A.X. Lu a, L.P. Wang a, H.C. Yu a, Q. Wan a,b, a b
Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education, Hunan University, Changsha 410082, People’s Republic of China State Key Laboratory of Silicon Materials, Zhejiang University, Hangzhou 310027, People’s Republic of China
a r t i c l e in f o
a b s t r a c t
Article history: Received 5 August 2009 Received in revised form 27 September 2009 Accepted 29 September 2009 Available online 4 October 2009
Low-voltage thin-film transistors (TFTs) with ZnO nanocrystal channel layers and mesoporous SiO2 gate dielectric are fabricated on glass substrates at room-temperature. The resulting n-type TFTs operate at a low voltage of 2.0 V. The equivalent field-effect electron mobility, current on/off ratio and subthreshold voltage swing is estimated to be 28.8 cm2 V 1 s 1, 3 106 and 84 mV/decade, respectively. The possible mechanism for low-voltage operation is discussed based on the electric double layer effect. Such roomtemperature-processed low-voltage TFTs are very promising for low-power macroelectronics on temperature-sensitive substrates. & 2009 Elsevier B.V. All rights reserved.
PACS: 61.72.uj 73.23.-b 85.30.TV Keywords: Low-voltage thin-film transistors ZnO nanocrystal Mesoporous SiO2 dielectric Electric double layer
High-performance thin-film transistors (TFTs) are fundamental building blocks for next generation macroelectronics [1,2]. TFTs with wide band-gap oxide semiconductors channels have attracted much attention over last several years because of their high field-effect mobilities, large-area fabrication and low processing temperature [3,4]. Among multifarious metal-oxide semiconductors, ZnO is one of the most promising materials as the channel layer for TFTs, not only because of the eminent semiconductor characteristics, but also partly on account of Znbased minerals enriched on earth and potentially lower cost [5–7]. The field-effect mobility was reported to be 25 cm2/V s in a polycrystalline channel layer [8,9] and as high as 70 cm2/V s in a single-crystalline channel layer [10]. At the same time, large operation voltages are often required for ZnO-based TFTs operation because commonly used SiO2 gate dielectrics provide weak capacitive coupling between the gate electrode and the semiconductor channel. TFTs capable of low-voltage operation are required to reduce the power consumption of next generation electronic devices driven by microelectronic components such as inverters, ring Corresponding author at: Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education, Hunan University, Changsha 410082, People’s Republic of China. Tel.: + 86 73188823407; fax: + 86 73188822137. E-mail address: [email protected] (Q. Wan).
1386-9477/$ - see front matter & 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.physe.2009.09.019
oscillators and backplane circuits for mobile displays [11]. A root idea for low-voltage operation is that gate insulator should have high capacitance and that increase in the capacitance is always linked to high dielectric constant (k) or thin thickness of the dielectric [12]. For example, ZnO TFTs operating at 3.0 V was demonstrated using polymer/high-k oxide double layer as the gate dielectric [13]. Another interesting approach in achieving low-voltage operation is using ion gel or ionic liquids as gate dielectrics [14,15]. For example, organic single-crystal transistors gated by ionic liquids operating at 1.0 V were demonstrated due to the huge electric double layers (EDLs) capacitance [14]. Here, we report on an alternative approach to achieve low-voltage amorphous ZnO TFTs operating at 2.0 V. Mesoporous SiO2 films containing protons were used as the gate dielectrics, and the ZnO TFTs exhibited high-performance n-type transistor characteristics with a high saturation field-effect mobility of 28.8 cm2/V s. The current on/off ratio and subthreshold swing were found to be 3 106 and 84 mV/decade, respectively. ZnO TFTs were fabricated on glass substrates with a bottomgate and top-contact source and drain electrodes. At first, ITO bottom-gate electrode film with a thickness of 200 nm was deposited on glass substrates by radio frequency (rf) sputtering at room-temperature (RT) with a fixed rf power of 100 W. The working pressure was 0.5 Pa in pure Ar ambient. Then SiO2 gate dielectric layer was deposited on ITO films by plasma-enhanced
ARTICLE IN PRESS Y. Hu et al. / Physica E 42 (2009) 154–157
chemical vapor deposition (PECVD) at RT using SiH4 and O2 as the reactive gas. For cross-section scanning electron microscopy (SEM) characterization, SiO2 films were also deposited on ITO/Si substrates. After SiO2 dielectric layer deposition, 50 nm ZnO channel layer was deposited via rf sputtering at RT with an rf power of 100 W in Ar/O2 mixed atmosphere. At last, aluminum source/drain electrodes with a thickness of 100 nm were deposited by vacuum electron-beam evaporation through a nickel shadow mask. The channel length and width-to-length ratio of the TFTs is 80 mm and 5:1, respectively. The crystal structure of the ZnO films deposited at roomtemperature was analyzed by X-ray diffraction (XRD) measurements using CuKa line. The surface morphology of ZnO films and cross-section morphology of SiO2 dielectric were analyzed by SEM (Hitachi S-4800). The electrical characterization of the ZnO films was tested by Hall Effect analyzer (HMS-3000). The electrical characteristics of the ZnO TFTs were measured in air ambient using a microprobe station connected to a semiconductor parameter analyzer (Model Keithley 4200 SCS). The capacitancefrequency (C-f) characterization of dielectric was performed by Agilent 4294A precision impedance analyzer. Fig. 1(a) shows a schematic picture of the ZnO TFTs on glass substrates. Here we should emphasize that all processes including SiO2 gate dielectric deposition were performed at roomtemperature. Thus, our technology is very promising for flexible electronics on temperature-sensitive substrates. Fig. 1(b) shows the XRD pattern of the room-temperature-deposited ZnO film. Diffraction peaks corresponding to the (1 0 0) and (11 0)
Fig. 1. (a) The schematic picture of the fabricated ZnO thin-film transistor (TFT) on glass substrates. (b) X-ray diffraction (XRD) pattern of the ZnO channel films. Inset: the SEM image of the ZnO thin film deposited at room-temperature. Scale bar: 100 nm.
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orientations of wurtzite ZnO were observed. The peaks are very weak because of the thickness of the ZnO film is 50 nm. Inset in Fig. 1(b) is a top-view SEM image of the ZnO film. A smooth and compact surface with high-density nanoclusters was observed. The resistivity, carrier concentration and hall mobility of the ZnO film are measured to be 7.32 102 O cm 1, 2.78 1014 cm 3 and 31.8 cm2/V s, respectively, by Hall Effect measurement. Fig. 2(a) shows a cross-section SEM image of the as-deposited SiO2 films. The thickness of the SiO2 films was found to be about 5.0 mm. Furthermore, mesoporous structure with nanocolumn arrays was observed. In our experiment, SiO2 deposition is a spontaneous reaction because SiH4 and O2 were used as the reactive gases, and the RF electric field between two capacitor electrodes is of great help for nanocolumn arrays formation. Fig. 2(b) shows the output characteristics (Vds–Ids) of the ZnO TFTs with mesoporous SiO2 dielectric. The devices exhibit typical ntype transistor characteristics under low operating voltage of 1.5 V. The drain current Ids increases linearly with increase in drain voltage Vds at low Vds, and saturates at higher Vds. Moreover, drain current Ids increases quickly as the gate voltage Vgs continuously increases from 0.5 to 1.5 V. A saturation current of 550 mA is obtained at the bias condition Vgs =1.5 V and Vds =1.5 V.
Fig. 2. (a) The cross-section SEM image of the mesoporous SiO2 dielectric film deposited on ITO/Si substrates at room-temperature. (b) The output characteristics of ZnO TFT.
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101
Cox (µF/cm2)
100
10-1 Al electrode Mesoporous SiO2
10-2
ITO Glass
10
-3
102
103 Frequency (Hz)
104
Fig. 4. Frequency dependence of the gate specific capacitance of mesoporous SiO2 dielectric (40 Hz to 10 kHz). Inset show the structure for capacitance measurement.
Fig.p 3.ffiffiffiffiffi(a) ffi The transfer characteristics [log(Ids) vs. Vgs for Vds = 1.5 V] of the ZnO TFT. (b) Ids vs. Vgs curve of the ZnO TFT at Vds = 1.5 V.
Fig. 3(a) shows the transfer characteristics for Vds at 1.5 V of the ZnO TFTs in the saturation region. The curve [log(Ids) vs. Vgs] indicates an off-state current is as low as 0.18 nA. The drain current on/off ratio, calculated from the drain current at maximum and minimum values, is estimated to be about 3 106, and the subthreshold swing S (S= dVgs/log|Ids|) is found to be as low as 84 mV/decade. A clear anticlockwise hysteresis is observed and the threshold voltage shift (DVth) is found to be ) and saturation mobility about 0.12 V. The threshold voltage (V pthffiffiffiffiffi (msat) are extracted from the plot ( Ids vs. Vgs), as shown by Fig. 3(b). The threshold voltage is found to be as low as 0.4 V, which indicates ZnO TFT is operated as an enhanced-type mode. And the saturation mobility (msat) is calculated by Ids = WCoxmsat(Vgs Vth)2/2L, where Cox is the capacitance per unit area of the gate dielectric, W (400 mm) and L (80 mm) are channel width and length, respectively. If the physical thickness (d= 5.0 mm) of the SiO2 was used for Cox calculation based on Cox = e0e/d, where e = 2.0 is the dielectric constant for porous SiO2 dielectric [16]. A saturation field-effect mobility value as high as 3.76 105 cm2/V s would be obtained. Obviously, this ultrahigh mobility value is unreasonable. The gate specific capacitance of mesoporous SiO2 dielectric was measured using MIM structure which consisted of a 200 nm ITO layer, a 5.0 mm SiO2 dielectric and a 100 nm Al thin film, as shown by the inset of Fig. 4. As shown in
Fig. 5. Schematic picture of the operation mechanism of the ZnO TFTs. (a) When mobile protons are accumulated at the SiO2 dielectric/channel interface, TFT is switched on under low gate voltage. (b) When mobile protons are accumulated at the SiO2 dielectric/gate electrode interface, TFT is switched off.
Fig. 4. The gate specific capacitance increases with decrease in frequency from 10 KHz to 40 Hz, and reach a maximum value of 1.88 mF/cm2 at 40 Hz. Based on Cox = e0e/d, the equivalent dielectric thickness is estimated to be 0.94 nm, which is in agreement with the reported thickness of the electric double layer (1.0 nm) [17]. In fact, proton transport in SiO2 for silicon-on-insulator type memory application was previously demonstrated [18]. Fig. 5 illustrates the possible low-voltage operation principle of the ZnO TFTs. As shown in Fig. 5(a), under positive gate bias voltage, mobile protons in mesoporous SiO2 insulator are transported to the interface between gate dielectric and channel layer. Then, high-density electrons will be induced in the active channel layer
ARTICLE IN PRESS Y. Hu et al. / Physica E 42 (2009) 154–157
near this interface, which is similar to the case of organic electric double layer transistors. When a negative gate voltage is applied, as shown in Fig. 5(b), mobile protons are attracted to the gate electrode/SiO2 interface. The ZnO channel would be switched off since the physical thickness of the dielectric is 5 mm and the gating effect of the positive protons near gate electrode can be ignored. The possible proton transport in SiO2 dielectric operation mechanism is in good agreement with the hysteresis curve that is shown in Fig. 3(a). The hysteresis in the two curves was measured due to the presence of the protons either at the gate electrode/ oxide interface or oxide/semiconductor channel. Due to the huge electric double layer gate specific capacitance, the operating voltage can be reduced to only 2.0 V, which is similar to organic transistors gated by electrolyte-gate dielectrics. According to the measured gate specific capacitance (1.88 mF/cm2) of mesoporous SiO2 dielectric at 40 Hz, then an equivalent field mobility value of 69.4 cm2/V s was estimated. Here we should point out that in the case of small channel ratios, the effective channel width is not equivalent to the geometrical channel width but is extended somewhat because of the fringing electric field at the ends of the electrodes, which can lead to the overestimation of the field-effect mobility. The field-effect mobility of undefined TFTs became overestimated by about 241% at the small geometrical channel ratio of about 5 [19]. So the reasonable mobility is estimated to be 28.8 cm2/V s, which is close to the measured mobility value by Hall Effect. In summary, low-voltage ZnO thin-film transistors operating at 2.0 V gated with mesoporous SiO2 gate dielectric were fabricated on glass substrate at room-temperature. The equivalent fieldeffect mobility, current on/off ratio and subthreshold voltage swing were estimated to be 28.8 cm2/V s, 3 106 and 84 mV/ decade, respectively. These devices had potential application for lower-power, portable electronics. At the same time, all roomtemperature processing of the TFTs demonstrated the compatibility with flexible polymeric substrates.
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