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MBE-grown SiGe base HBT with polysilicon-emitter and TiSi2 base ohmic layer
Solid-State Hecwonics Vol. 39. No. 1I. pp. 1643-1648, 1996 Copyright CI 1996 Elsevier Science Ltd Printed in Great Britain. All rights reserved PII: SOO38-1101(96)00087-1 0038-I 101/96 Sl5.00 + 0.00
Pergamon
MBE-GROWN POLYSILICON-EMITTER
SiGe BASE HBT WITH AND TiSiz BASE OHMIC
B. R. RYUM Electronics
and Telecommunications
Research
and T.-H.
Institute Korea
(ETRI).
LAYER
HAN Yusong.
P.O. Box 106, Taejon
31X-600,
(Receiced 27 July 1995; in revised form 22 April 1996)
Abstract-Using
Si/SiGe heteroepitaxy grown by solid-sources (SS) molecular beam epitaxy (MBE) on LOCOS-patterned wafers, an n-pn Si/SiGe/Si heterojunction bipolar transistor (HBT) which is isolated by a polysilicon-filled trench has been fabricated. Unlike other SiGe HBTs using a metallic salicide process, in this proposed device a titanium disilicide (TiSiz) base electrode layer is formed by deposition and patterning of an amorphous TiSi2, (x = gO.9) layer on the SiGe base layer using selective wet etching. In view of a lower thermal budget furnace annealing at 840°C has only been applied for the drive-in and activation of arsenic (As) implanted in the polysilicon-emitter. The Si/SiossGea ,JSi n-pn HBT with a 1 x 4 pm’ mask size emitter typically shows a common-emitter current gain of 118, an Early voltage in the range of 150-170 V, a breakdown voltage BV,,, of 7.8 V, a unity current gain frequencyfr of 20 GHz, and a maximum oscillation frequency fm.., of 15GHz. Considering the theoretical limit offr vs BV,,, the performance of our device is near the limit and demonstrates a potential for high frequency analog IC applications. Copyright I~J 1996 Elsevier Science Ltd
1. INTRODUCTION
Due to their potential in the field of high speed analog and digital IC applications, heterojunction bipolar transistors (HBTs) have drawn a lot of attention. The narrow bandgap base allows the benefits of higher current gain (/?), lower base resistance with a moderate current gain and higher cut-off frequency (fr) together with maximum oscillation frequency tfmaX)[l,2] to be obtained. In addition bandgap grading in the base introduces a quasi-electric field to accelerate the electrons injected from the emitter and thereby results in a reduction of the base transit time as well as an enhancement of fr for all injection levels[3,4]. Particularly for SiGe/Si heterostructures, bandgap reduction of SiGe occurs by increase of the Ge composition and strain[5,6]. Since the conduction band offset of about 0.02 eV is nearly constant for the entire Ge composition, while most of the bandgap difference between Si and Si,.,Ge, occurs in the valence band[7], bandgap alignment of the elastically strained Si,.,Ge, to the cubic Si is also more suitable for the HBT. In the last few years dramatic developments of the epitaxial SiGe base HBT to exploit the bandgap engineering have been achieved through a rapid progress in epitaxial growth technologies such as ultra-high vacuum chemical vapor deposition (UHVCVD)[8], molecular beam epitaxy (MBE)[9, lo] and limited reaction processes (LRP)-CVD[ 111. Unlike the fabrication process and structure of the afore-mentioned HBTs[&l 11, the motivation of this
paper is to fabricate an IC-compatible polysiliconemitter SiGe base HBT with more simple process integration, especially by using solid-source (SS) MBE-grown Si/SiGe heteroepitaxy on LOCOS-patterned wafers[ 12,131. In addition in this proposed device the TiSiz layer with a lower sheet resistance than the boron-doped polysilicon layer is used as an ohmic base contact to reduce the extrinsic base resistance. Since a conventional TiSiz formation process combining sputtering of Ti on Si with post-annealing does result not only in the loss of Si but also in an agglomeration at the TiSiJSi interface[l4], in the case of SiGe HBT with a TiSQ SiGe(base)/Si(collector) structure, a shorted base and collector due to penetration of TiSiz through the thin SiGe base layer in the vicinity of the LOCOS bird’s beak is quite probable. Unlike the other Si/SiGe HBTs using a metallic salicide process[ 15,161, in our device amorphous TiSiz,, layer is deposited on the entire SiGe layer by sputtering a composite TiSi2, target, which is next patterned by wet etch. The surface of the locally exposed SiGe underlayer was as clean as that of a bare wafer. Phase transition of a-TiS&, to C54-TiSiz with lower resistivity is achieved simultaneously during thermal annealing to drive-in and activate the dopant in the polysilicon-emitter. Penetration of titanium disilicide is also reduced by using a-TiS&, layer. Therefore our device has been subjected to only one low temperature furnace annealing after the growth of the Si/SiGe layer, which is desirable for thermal stability of the strained SiGe layer. In addition owing to this simplified base electrode
1643
B. R. Ryum and T.-H. Han
1644
formation process, the fabrication of our SiGe base HBT becomes very simple and sufficiently reproducible to be applied in IC fabrication. 2. DEVICE FABRICATION
Fabrication process of the proposed n-p-n Si/SiGe HBT is shown in Fig. 1. In Fig. l(a). after forming a buried collector with a resistivity of 2 x lo-’ R cm by arsenic implantation into a p-type Si(100)
Single-crystai!ine SilSiCe
I
’
Amorphous(or Poly)-SiiSiGe
P+ POlY
(a)
I
’ P+PolY (b) TiSiz
\
n+ poly
p- Si substrate P+ POlY (c)
Fig. 1. Schematic cross section of our n-p-n Si:SiGe:‘Si HBT: (a) after trench isolation, LOCOS formation. collector sink formation, growth of an Si:‘SiGe layer by SSMBE; (b) after BF: ion implantation into extrinsic base deposition of a-TiSi:, and etching, oxide deposition and patterning oxide/a-TiSi:&iGe/Si multilayer on LOCOS oxide; and (c) after polysilicon deposition, As ion implantation and polysilicon-emitter definition.
substrate with a resistivity of 18-22 f2 cm, a 0.65 pm thick in-situ phosphorous-doped collector layer with a resistivity of 0.2 R cm was deposited. Then a polysilicon-filled trench was formed for device isolation by the following steps; forming a pad oxide, depositing a low temperature oxide (LTO) and a nitride. forming a trench by etching the LTO, the nitride, the pad oxide and exposed silicon, forming an oxide side wall in the trench, filling a boron-doped polysilicon in the trench and chemical-mechanical polishing of the polysilicon down to the nitride surface. After the LOCOS process, a collector sink was formed by phosphorous implantation. After a [4/1]H2SOJiH201 treatment and a dilute HF dip, prebaking at 850-C was performed to remove the native oxide on silicon. Then, a 30 nm thick SiGe base layer with a boron concentration of 5 x 10’” crnmTand a constant Ge mole fraction of 0.15 was grown at 650’ C by SSMBE (RIBER45). In order to suppress not only the tunneling conduction at the emitter-base (E-B) junction[8] but also the parasitic potential barrier effect resulting from boron outdiffusion from the SiGe base layer to adjacent Si layer[l7,18]. a 30 nm thick undoped Si layer and a 20 nm thick SiGe layer with the same Ge mole fraction as that in the SiGe base layer were deposited on the top and the bottom of the SiGe base layer, respectively. In Fig. l(b), after BF2 implantation with a dose of 6 x 10” cm-’ and an energy of 30 keV for the base ohmic contact, a 100 nm thick amorphous TiSi? b layer was deposited by sputtering a hot-pressured TiSila composite target. After a dilute BHF etching of the a-TiSi:, layer within the active device region, the opened surface of the undoped Si layer was found to be clean by SEM and residual titanium species were not detected by SIMS. Depositing an oxide and patterning the multilayer(oxide/a-TiSi2,/Si/SiGe) on the field oxide completely defined the a-TiS& base electrode. Then an emitter window was opened by etching the oxide, as shown in Fig. l(b). In Fig. l(c), a polysilicon layer was deposited by low-pressure (LP) CVD, arsenic ion was implanted and the polysilicon layer was patterned by RIE. After passivating the device by an oxide layer, for the drive-in and activation of the arsenic ions in the polysilicon layer, the device was annealed at 84O~C for 20 mins. In the meantime. the phase of the a-TiSi, h base electrode was changed to the C54 phase with a resistivity of about 20 PR cm. Finally. contact windows were opened. and a 0.05 pm-1 pm thick TiW/AI- 1%Si bilayer was deposited and then patterned. 3. RESULTS
AND DISCUSSIONS
Final SIMS profiles of the intrinsic device region under the emitter and the extrinsic region where BF2 ions were implanted are shown in Figs 2(a) and (b). respectively. As can be seen in Fig. 2(a). the E-B
MBE-grown
SiGe base HBT
20 18 16
1645
C-B junction location almost coincides with the SiGe-Si metallurgical junction location. Peak concentration of arsenic in the polysilicon-emitter is shown to be approximately 1 x lo?’ cm--‘. In Fig. 2(b), the titanium is shown to be confined within the SiGe base layer of the BFz-implanted extrinsic base region and hence it is confirmed that penetration of the titanium disilicide through the base into the collector is avoided. Peak concentration of boron in the extrinsic base region is observed to be approximately 2 x 10zOcm-“. For the polysilicon-emitter layer. the calculated resistivity from the measured spread resistance of 4OOQ is 1.1 x lo-‘R cm. The measured ohmic resistance of the polysilicon-emitter with a 1 x 4 pm’ contact area is 5 R t_ 10%. Therefore the contact resistivity is 2 x 10-Q cm? and the resistivity is 1 x 10-9 cm, which agrees well with the resistivity value of ASR measurement. In addition the measured sheet resistance of the polysilicon-emitter layer is 200 Q/n t_ 12%. For the BFz-implanted extrinsic base layer, the calculated resistivity and boron concentration from the measured spread resistance of 400 R are 1.2 x 10-Q cm and 1.2 x 10’“cm-3, respectively. Therefore, arsenic ions in the polysilicon-emitter and boron ions in the extrinsic base are incompletely activated by the furnace annealing at 84O’C for 20 mins. The measured sheet resistance of the TiSi, base electrode on the single-crystalline Si/SiGe layer is 2.6 n/a + 12% while it is 7. I Cl/ f 15% on the polycrystalline Si/SiGe layer on the field oxide. This difference is thought to be due to the agglomeration of the TiSiz layer, depending on the underlayer morphology, but the TiSiz layer still gives a much lower resistance value than the typical value of -200 Q/n for a doped polysilicon layer by boron-nitride (BN) sourcing. In order to investigate the thermal stability of the SiGe layer, a DXRD analysis for the SiGe base on the Si collector after completion of the device fabrication was performed (post-annealed sample) and compared with that of an as-grown sample, as
i3-Tcidi, 2
c
I3epth(rricron) (4
ll
rd 7
104
......._.... y ..
; Id
3
P
IO'
I
10'40.0
0.1
I
I
0.2
*
I
0.3
I
I
0.4
I
100
0.5
Fig. ?. Final SIMS profile of our n-pn SiossGeoIs HBT after completion of device fabrication: (a) intrinsic device region under the polysilicon-emitter; and (b) extrinsic base region under the TiSiz base ohmic layer.
junction depth is observed to be approximately 20 nm and the base thickness is about 6.5 nm. Since the phosphorous concentration in the collector is below the detectable limit of SIMS, a calculated concentration from spread resistance measurement is presented instead. At the collector-base (C-B) junction, boron diffusion from the SiGe base to the Si collector is suppressed to be negligible so that the
Pflw smealing /
Fig. 3. X-ray diffraction data showing thermal stability of the SiOxsGeo ,S base layer for the as-grown and the thermally annealed samples.
1646
B. R. Ryum and T.-H.
Fig. 4. XTEM of the intrinsic device area of our SioasGeo 15 HBT after device fabrication being completed. Absence of misfit dislocation is confirmed.
Han
‘%O
0.2 0.4 0.6 I I 0.8 I , 1.0 I , 1.2 E33se-Errittervd~(v)
presented in Fig. 3. For the as-grown and the post-annealed samples, the SiGe peaks, relative to the silicon peak, locate at - 1612 and - 1640 s, the peak heights are 19.6 and 18.5 countrate (=2 s) and the FWHM of the SiGe layer are 13.8 and 9.5 arcs, respectively. Consequently due to the growth of the Si/SiGe layer, the SiGe layer still remains unrelaxed after the highest annealing step (furnace annealing at 840’C for 20 mins) for the E-B junction formation and the absence of a misfit dislocation at the Si-SiGe interface is also confirmed by the XTEM photograph in Fig. 4. As for the electrical performance of the n-p-n Si/Si085Ge, ,JSi HBT with a 1 x 4 pm’ emitter area, from a Gummel plot in Fig. 5 the ideality factor of the collector current (I,-) and the base current (ZB) is shown to be 1.01 and 1.6, respectively. Based on the measured increasing E-B reverse leakage current with increasing the emitter area and the exponential dependence of the leakage current on the reverse E-B bias voltage, the nonideality of ZBis presumably due to the tunneling conduction at the E-B junctior@] resulting from the somewhat thin Si spacer. In addition the zero variation of Zc and Is with C-B reverse bias voltage Ifcs at low E-B forward bias voltage ( VBE)indicates absence of the punch-through effect. A plot of current gain (p) vs Zc is presented in Fig. 6. At Ic being equal to 1.2 mA and I’cB equal to 0 V, p peaks at 102 and also slightly increases up to 118 at Ic equal to 2 mA and V,, equal to 2 V. It has been reported for Si/SiGe/Si n-pn HBTs that boron diffusion from the SiGe layer to the adjacent Si, resulting in the non-coincidence of the Si/SiGe metallurgical junction with the electrical pn junction, introduces the parasitic potential barrier on the conduction band at the Si/SiGe heterojunctions and thus b[ 171 and ZrJ183 will vary with varying Vcs.
Fig. 5. Ic and IS vs E-B forward bias voltage ( VBE)(at Vca being equal to 0 and 2 V) for an Sio 8sGea ,S HBT with an emitter mask size of 1 x 4 pm’.
Noticeably, in our device variation of b with varying I’c, is negligible. In addition the measured Is of our Si/SiGe HBT is nearly constant over V. until impact ionization takes place (see Fig. 7), as typically observed in Si base homojunction bipolar transistors. Therefore, this result indicates that the effect of the parasitic potential barrier is insignificant in our device. From a plot of Zc vs collector-emitter voltage (V,,) in Fig. 8, a high Early voltage in the range of 150-170 V is obtained by linearly extrapolating the plot. It is presumably due to an abrupt boron profile
100.. 10”
10-S
10-l
10”
10”
Collector Current (A) Fig. 6. Common-emitter current gain fi vs IC (at V~S being equal to 0 and 2 V) for an SerGea ,S HBT.
MBE-grown
0.6
,
,
,
,
SiGe base HBT
,
40
‘.*. ‘,*. .,‘~
0.5 35
-
0.4 30.
0.3 -
-
0.2 0.1
B
4
3 :
ii3
0.0
25,
2015
-0.1 -
d
-0.2 -
. . . . ..
,
.,‘.
*.*.
‘.‘. ‘,I. ‘.,‘.J
n
-ti
l
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. . ..._@
..~* *. ., ‘% *.‘%
s -
1647
-30
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-25 -
:; : ‘. ‘,-. ‘.A .. *i :i *‘a,;
8 -20 * 3
l
lA
:
-15
l\‘. +J
10-
c.$l. fr = 2OGHz -“+I.5
1.0
1.5
2.0
2.5
(V,+O.6) Fig. 7. Nearly constant
3.0
3.5
5.
f&&= 15GHz
:t,_.
Fig. 9. AC characteristics of an SioasGea 15HBT showingfr and fmrx at P’CEbeing equal to 6.5 V and IC being equal to 1.8 mA.
15 GHz, respectively, at equal to 6.5 V, which is at the peak of fr in theoretical limit of peakfr fr of 20 GHz with BV,,, Si/SiGe HBT is thought
Ic equal to 1.8 mA and VcE consistent with the Zc value Fig. 10. Referring to the vs BV,,,[21], the maximum being equal to 7.8 V of our to be nearly the limit.
4. CONCLUSION
Using an SSMBE-grown Si/SiGe layer on a LOCOS-patterned wafer and a TiSiz layer as a base
1.5
h 1.0
E 8 &I 0.5
8
0.0
/
2
4
6
8
Collector - Einitter Voltage( V) Fig. 8. ICVCE characteristics
- 10
Vce for an SiossGeo Is
of suppressing the boron outdiffusion by the low thermal-budget and a higher boron concentration than the collector doping concentration as well. Breakdown voltages BVceo, BVEBo and BVcso are measured to be 7.8, 3.9 and 9.2 V at a reverse leakage current of 1.0, 3.9 and 3.3 nA, respectively. After de-embedding the pad parasitic of our device in the same manner as that shown in Refs [19.20], a plot of the common-emitter current gain hzI and the unilateral power gain vs frequency in Fig. 9 was obtained and a plot of fr vs Zc is also presented in Fig. 10. Extrapolating each plot in Fig. 9 by a - 20 dB/dec line gives an fTand anfman of 20 GHz and
8
E n”
lR
IS with varying HBT.
in the SiGe base, as a result
B
-35
of an SiorsGeoIs HBT.
Cdlector au-rent (mA) Fig. 10. f4, plot of an SiossGeo 15 HBT.
1648
B. R. Ryum and T.-H. Han
electrode, a low thermal-budget polysilicon-emitter SiGe-base HBT with a non-self-aligned emitter-base has been fabricated. Fabrication process is simple and reproducible so that our device can be applied to integrated circuits (ICs). The performance of our device optimized with respect to the trade-off between fr and BV,,, demonstrates a potential in analog IC applications such as microwave amplifiers and radio frequency (RF) front-end components.
REFERENCES
1. H. Kriimer, Proc. IRE 45, 1535 (1957). 2. B. R. Ryum and I. M. Abdel-Motaleb. Solid-State Elecrron. 33, 869 (1990). 3. B. R. Ryum and I. M. Abdel-Motaleb, IEEE BCTM. p. 199 (i990). 4. B. R. Rvum and I. M. Abdel-Motaleb, Solid-State Electron.-34, 1125 (1991). 5. R. Braunstein et al., Phys. Reo. 109, 695 (1958). 6. B. V. Lang et al.. Appl. Phys. Lett. 41, 1333 (1985).
7. R. People and J. C. Bean, Appl. Phys. Leff. 48, 538 (1986). 8. E. F. Crabbe et al., 5lst DRC (1993). 9. A. Gruhle, H. Kibbel. U. Erben and E. Kasper, 51sr DRC (1993). 10. F. Sato et al.. IEDM, p. 397 (1992). 11. T. I. Kamins et al.. IEDM, p. 647 (1989). 12. B. R. Ryum, T.-H. Han and S.-C. Lee, 24th ESSDERC, p. 59 (1994). 13. A. Schuppen et al.. 24th ESSDERC, p. 469 (1994). 14. T. D. Nolon and R. Sinclair, J. Appl. Phys. 53, 6219 (1982). 15. M. Ugajin ei al., BCTM, p. 26 (1992). 16. E. F. Crabbe et al., IEEE Electron. Device. Lett. 14,478 (1993). 17. E. J. Prinz et al.. IEEE Electron. Decice Lett. 12, 42 (1991). 18. S. Kim, B. R. Ryum. S. Kang and W. Kim, So/id-State Electron. 37, 517 (1994). 19. S. Lee, B. R. Ryum, O.-J. Kwon and J.-H. Lee, Electron. Lett. 29. 1797 (1993). 20. S. Lee, B. R. Ryum and S: Kang, IEEE Trans. Electron. Devices ED-41, 233 (1994). 21. E. 0. Johnson. R. C. A. Rep. 26, 163 (1965).
Pergamon
MBE-GROWN POLYSILICON-EMITTER
SiGe BASE HBT WITH AND TiSiz BASE OHMIC
B. R. RYUM Electronics
and Telecommunications
Research
and T.-H.
Institute Korea
(ETRI).
LAYER
HAN Yusong.
P.O. Box 106, Taejon
31X-600,
(Receiced 27 July 1995; in revised form 22 April 1996)
Abstract-Using
Si/SiGe heteroepitaxy grown by solid-sources (SS) molecular beam epitaxy (MBE) on LOCOS-patterned wafers, an n-pn Si/SiGe/Si heterojunction bipolar transistor (HBT) which is isolated by a polysilicon-filled trench has been fabricated. Unlike other SiGe HBTs using a metallic salicide process, in this proposed device a titanium disilicide (TiSiz) base electrode layer is formed by deposition and patterning of an amorphous TiSi2, (x = gO.9) layer on the SiGe base layer using selective wet etching. In view of a lower thermal budget furnace annealing at 840°C has only been applied for the drive-in and activation of arsenic (As) implanted in the polysilicon-emitter. The Si/SiossGea ,JSi n-pn HBT with a 1 x 4 pm’ mask size emitter typically shows a common-emitter current gain of 118, an Early voltage in the range of 150-170 V, a breakdown voltage BV,,, of 7.8 V, a unity current gain frequencyfr of 20 GHz, and a maximum oscillation frequency fm.., of 15GHz. Considering the theoretical limit offr vs BV,,, the performance of our device is near the limit and demonstrates a potential for high frequency analog IC applications. Copyright I~J 1996 Elsevier Science Ltd
1. INTRODUCTION
Due to their potential in the field of high speed analog and digital IC applications, heterojunction bipolar transistors (HBTs) have drawn a lot of attention. The narrow bandgap base allows the benefits of higher current gain (/?), lower base resistance with a moderate current gain and higher cut-off frequency (fr) together with maximum oscillation frequency tfmaX)[l,2] to be obtained. In addition bandgap grading in the base introduces a quasi-electric field to accelerate the electrons injected from the emitter and thereby results in a reduction of the base transit time as well as an enhancement of fr for all injection levels[3,4]. Particularly for SiGe/Si heterostructures, bandgap reduction of SiGe occurs by increase of the Ge composition and strain[5,6]. Since the conduction band offset of about 0.02 eV is nearly constant for the entire Ge composition, while most of the bandgap difference between Si and Si,.,Ge, occurs in the valence band[7], bandgap alignment of the elastically strained Si,.,Ge, to the cubic Si is also more suitable for the HBT. In the last few years dramatic developments of the epitaxial SiGe base HBT to exploit the bandgap engineering have been achieved through a rapid progress in epitaxial growth technologies such as ultra-high vacuum chemical vapor deposition (UHVCVD)[8], molecular beam epitaxy (MBE)[9, lo] and limited reaction processes (LRP)-CVD[ 111. Unlike the fabrication process and structure of the afore-mentioned HBTs[&l 11, the motivation of this
paper is to fabricate an IC-compatible polysiliconemitter SiGe base HBT with more simple process integration, especially by using solid-source (SS) MBE-grown Si/SiGe heteroepitaxy on LOCOS-patterned wafers[ 12,131. In addition in this proposed device the TiSiz layer with a lower sheet resistance than the boron-doped polysilicon layer is used as an ohmic base contact to reduce the extrinsic base resistance. Since a conventional TiSiz formation process combining sputtering of Ti on Si with post-annealing does result not only in the loss of Si but also in an agglomeration at the TiSiJSi interface[l4], in the case of SiGe HBT with a TiSQ SiGe(base)/Si(collector) structure, a shorted base and collector due to penetration of TiSiz through the thin SiGe base layer in the vicinity of the LOCOS bird’s beak is quite probable. Unlike the other Si/SiGe HBTs using a metallic salicide process[ 15,161, in our device amorphous TiSiz,, layer is deposited on the entire SiGe layer by sputtering a composite TiSi2, target, which is next patterned by wet etch. The surface of the locally exposed SiGe underlayer was as clean as that of a bare wafer. Phase transition of a-TiS&, to C54-TiSiz with lower resistivity is achieved simultaneously during thermal annealing to drive-in and activate the dopant in the polysilicon-emitter. Penetration of titanium disilicide is also reduced by using a-TiS&, layer. Therefore our device has been subjected to only one low temperature furnace annealing after the growth of the Si/SiGe layer, which is desirable for thermal stability of the strained SiGe layer. In addition owing to this simplified base electrode
1643
B. R. Ryum and T.-H. Han
1644
formation process, the fabrication of our SiGe base HBT becomes very simple and sufficiently reproducible to be applied in IC fabrication. 2. DEVICE FABRICATION
Fabrication process of the proposed n-p-n Si/SiGe HBT is shown in Fig. 1. In Fig. l(a). after forming a buried collector with a resistivity of 2 x lo-’ R cm by arsenic implantation into a p-type Si(100)
Single-crystai!ine SilSiCe
I
’
Amorphous(or Poly)-SiiSiGe
P+ POlY
(a)
I
’ P+PolY (b) TiSiz
\
n+ poly
p- Si substrate P+ POlY (c)
Fig. 1. Schematic cross section of our n-p-n Si:SiGe:‘Si HBT: (a) after trench isolation, LOCOS formation. collector sink formation, growth of an Si:‘SiGe layer by SSMBE; (b) after BF: ion implantation into extrinsic base deposition of a-TiSi:, and etching, oxide deposition and patterning oxide/a-TiSi:&iGe/Si multilayer on LOCOS oxide; and (c) after polysilicon deposition, As ion implantation and polysilicon-emitter definition.
substrate with a resistivity of 18-22 f2 cm, a 0.65 pm thick in-situ phosphorous-doped collector layer with a resistivity of 0.2 R cm was deposited. Then a polysilicon-filled trench was formed for device isolation by the following steps; forming a pad oxide, depositing a low temperature oxide (LTO) and a nitride. forming a trench by etching the LTO, the nitride, the pad oxide and exposed silicon, forming an oxide side wall in the trench, filling a boron-doped polysilicon in the trench and chemical-mechanical polishing of the polysilicon down to the nitride surface. After the LOCOS process, a collector sink was formed by phosphorous implantation. After a [4/1]H2SOJiH201 treatment and a dilute HF dip, prebaking at 850-C was performed to remove the native oxide on silicon. Then, a 30 nm thick SiGe base layer with a boron concentration of 5 x 10’” crnmTand a constant Ge mole fraction of 0.15 was grown at 650’ C by SSMBE (RIBER45). In order to suppress not only the tunneling conduction at the emitter-base (E-B) junction[8] but also the parasitic potential barrier effect resulting from boron outdiffusion from the SiGe base layer to adjacent Si layer[l7,18]. a 30 nm thick undoped Si layer and a 20 nm thick SiGe layer with the same Ge mole fraction as that in the SiGe base layer were deposited on the top and the bottom of the SiGe base layer, respectively. In Fig. l(b), after BF2 implantation with a dose of 6 x 10” cm-’ and an energy of 30 keV for the base ohmic contact, a 100 nm thick amorphous TiSi? b layer was deposited by sputtering a hot-pressured TiSila composite target. After a dilute BHF etching of the a-TiSi:, layer within the active device region, the opened surface of the undoped Si layer was found to be clean by SEM and residual titanium species were not detected by SIMS. Depositing an oxide and patterning the multilayer(oxide/a-TiSi2,/Si/SiGe) on the field oxide completely defined the a-TiS& base electrode. Then an emitter window was opened by etching the oxide, as shown in Fig. l(b). In Fig. l(c), a polysilicon layer was deposited by low-pressure (LP) CVD, arsenic ion was implanted and the polysilicon layer was patterned by RIE. After passivating the device by an oxide layer, for the drive-in and activation of the arsenic ions in the polysilicon layer, the device was annealed at 84O~C for 20 mins. In the meantime. the phase of the a-TiSi, h base electrode was changed to the C54 phase with a resistivity of about 20 PR cm. Finally. contact windows were opened. and a 0.05 pm-1 pm thick TiW/AI- 1%Si bilayer was deposited and then patterned. 3. RESULTS
AND DISCUSSIONS
Final SIMS profiles of the intrinsic device region under the emitter and the extrinsic region where BF2 ions were implanted are shown in Figs 2(a) and (b). respectively. As can be seen in Fig. 2(a). the E-B
MBE-grown
SiGe base HBT
20 18 16
1645
C-B junction location almost coincides with the SiGe-Si metallurgical junction location. Peak concentration of arsenic in the polysilicon-emitter is shown to be approximately 1 x lo?’ cm--‘. In Fig. 2(b), the titanium is shown to be confined within the SiGe base layer of the BFz-implanted extrinsic base region and hence it is confirmed that penetration of the titanium disilicide through the base into the collector is avoided. Peak concentration of boron in the extrinsic base region is observed to be approximately 2 x 10zOcm-“. For the polysilicon-emitter layer. the calculated resistivity from the measured spread resistance of 4OOQ is 1.1 x lo-‘R cm. The measured ohmic resistance of the polysilicon-emitter with a 1 x 4 pm’ contact area is 5 R t_ 10%. Therefore the contact resistivity is 2 x 10-Q cm? and the resistivity is 1 x 10-9 cm, which agrees well with the resistivity value of ASR measurement. In addition the measured sheet resistance of the polysilicon-emitter layer is 200 Q/n t_ 12%. For the BFz-implanted extrinsic base layer, the calculated resistivity and boron concentration from the measured spread resistance of 400 R are 1.2 x 10-Q cm and 1.2 x 10’“cm-3, respectively. Therefore, arsenic ions in the polysilicon-emitter and boron ions in the extrinsic base are incompletely activated by the furnace annealing at 84O’C for 20 mins. The measured sheet resistance of the TiSi, base electrode on the single-crystalline Si/SiGe layer is 2.6 n/a + 12% while it is 7. I Cl/ f 15% on the polycrystalline Si/SiGe layer on the field oxide. This difference is thought to be due to the agglomeration of the TiSiz layer, depending on the underlayer morphology, but the TiSiz layer still gives a much lower resistance value than the typical value of -200 Q/n for a doped polysilicon layer by boron-nitride (BN) sourcing. In order to investigate the thermal stability of the SiGe layer, a DXRD analysis for the SiGe base on the Si collector after completion of the device fabrication was performed (post-annealed sample) and compared with that of an as-grown sample, as
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0.1
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I
0.2
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I
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Fig. ?. Final SIMS profile of our n-pn SiossGeoIs HBT after completion of device fabrication: (a) intrinsic device region under the polysilicon-emitter; and (b) extrinsic base region under the TiSiz base ohmic layer.
junction depth is observed to be approximately 20 nm and the base thickness is about 6.5 nm. Since the phosphorous concentration in the collector is below the detectable limit of SIMS, a calculated concentration from spread resistance measurement is presented instead. At the collector-base (C-B) junction, boron diffusion from the SiGe base to the Si collector is suppressed to be negligible so that the
Pflw smealing /
Fig. 3. X-ray diffraction data showing thermal stability of the SiOxsGeo ,S base layer for the as-grown and the thermally annealed samples.
1646
B. R. Ryum and T.-H.
Fig. 4. XTEM of the intrinsic device area of our SioasGeo 15 HBT after device fabrication being completed. Absence of misfit dislocation is confirmed.
Han
‘%O
0.2 0.4 0.6 I I 0.8 I , 1.0 I , 1.2 E33se-Errittervd~(v)
presented in Fig. 3. For the as-grown and the post-annealed samples, the SiGe peaks, relative to the silicon peak, locate at - 1612 and - 1640 s, the peak heights are 19.6 and 18.5 countrate (=2 s) and the FWHM of the SiGe layer are 13.8 and 9.5 arcs, respectively. Consequently due to the growth of the Si/SiGe layer, the SiGe layer still remains unrelaxed after the highest annealing step (furnace annealing at 840’C for 20 mins) for the E-B junction formation and the absence of a misfit dislocation at the Si-SiGe interface is also confirmed by the XTEM photograph in Fig. 4. As for the electrical performance of the n-p-n Si/Si085Ge, ,JSi HBT with a 1 x 4 pm’ emitter area, from a Gummel plot in Fig. 5 the ideality factor of the collector current (I,-) and the base current (ZB) is shown to be 1.01 and 1.6, respectively. Based on the measured increasing E-B reverse leakage current with increasing the emitter area and the exponential dependence of the leakage current on the reverse E-B bias voltage, the nonideality of ZBis presumably due to the tunneling conduction at the E-B junctior@] resulting from the somewhat thin Si spacer. In addition the zero variation of Zc and Is with C-B reverse bias voltage Ifcs at low E-B forward bias voltage ( VBE)indicates absence of the punch-through effect. A plot of current gain (p) vs Zc is presented in Fig. 6. At Ic being equal to 1.2 mA and I’cB equal to 0 V, p peaks at 102 and also slightly increases up to 118 at Ic equal to 2 mA and V,, equal to 2 V. It has been reported for Si/SiGe/Si n-pn HBTs that boron diffusion from the SiGe layer to the adjacent Si, resulting in the non-coincidence of the Si/SiGe metallurgical junction with the electrical pn junction, introduces the parasitic potential barrier on the conduction band at the Si/SiGe heterojunctions and thus b[ 171 and ZrJ183 will vary with varying Vcs.
Fig. 5. Ic and IS vs E-B forward bias voltage ( VBE)(at Vca being equal to 0 and 2 V) for an Sio 8sGea ,S HBT with an emitter mask size of 1 x 4 pm’.
Noticeably, in our device variation of b with varying I’c, is negligible. In addition the measured Is of our Si/SiGe HBT is nearly constant over V. until impact ionization takes place (see Fig. 7), as typically observed in Si base homojunction bipolar transistors. Therefore, this result indicates that the effect of the parasitic potential barrier is insignificant in our device. From a plot of Zc vs collector-emitter voltage (V,,) in Fig. 8, a high Early voltage in the range of 150-170 V is obtained by linearly extrapolating the plot. It is presumably due to an abrupt boron profile
100.. 10”
10-S
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10”
10”
Collector Current (A) Fig. 6. Common-emitter current gain fi vs IC (at V~S being equal to 0 and 2 V) for an SerGea ,S HBT.
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,
,
,
,
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1.5
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5.
f&&= 15GHz
:t,_.
Fig. 9. AC characteristics of an SioasGea 15HBT showingfr and fmrx at P’CEbeing equal to 6.5 V and IC being equal to 1.8 mA.
15 GHz, respectively, at equal to 6.5 V, which is at the peak of fr in theoretical limit of peakfr fr of 20 GHz with BV,,, Si/SiGe HBT is thought
Ic equal to 1.8 mA and VcE consistent with the Zc value Fig. 10. Referring to the vs BV,,,[21], the maximum being equal to 7.8 V of our to be nearly the limit.
4. CONCLUSION
Using an SSMBE-grown Si/SiGe layer on a LOCOS-patterned wafer and a TiSiz layer as a base
1.5
h 1.0
E 8 &I 0.5
8
0.0
/
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4
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8
Collector - Einitter Voltage( V) Fig. 8. ICVCE characteristics
- 10
Vce for an SiossGeo Is
of suppressing the boron outdiffusion by the low thermal-budget and a higher boron concentration than the collector doping concentration as well. Breakdown voltages BVceo, BVEBo and BVcso are measured to be 7.8, 3.9 and 9.2 V at a reverse leakage current of 1.0, 3.9 and 3.3 nA, respectively. After de-embedding the pad parasitic of our device in the same manner as that shown in Refs [19.20], a plot of the common-emitter current gain hzI and the unilateral power gain vs frequency in Fig. 9 was obtained and a plot of fr vs Zc is also presented in Fig. 10. Extrapolating each plot in Fig. 9 by a - 20 dB/dec line gives an fTand anfman of 20 GHz and
8
E n”
lR
IS with varying HBT.
in the SiGe base, as a result
B
-35
of an SiorsGeoIs HBT.
Cdlector au-rent (mA) Fig. 10. f4, plot of an SiossGeo 15 HBT.
1648
B. R. Ryum and T.-H. Han
electrode, a low thermal-budget polysilicon-emitter SiGe-base HBT with a non-self-aligned emitter-base has been fabricated. Fabrication process is simple and reproducible so that our device can be applied to integrated circuits (ICs). The performance of our device optimized with respect to the trade-off between fr and BV,,, demonstrates a potential in analog IC applications such as microwave amplifiers and radio frequency (RF) front-end components.
REFERENCES
1. H. Kriimer, Proc. IRE 45, 1535 (1957). 2. B. R. Ryum and I. M. Abdel-Motaleb. Solid-State Elecrron. 33, 869 (1990). 3. B. R. Ryum and I. M. Abdel-Motaleb, IEEE BCTM. p. 199 (i990). 4. B. R. Rvum and I. M. Abdel-Motaleb, Solid-State Electron.-34, 1125 (1991). 5. R. Braunstein et al., Phys. Reo. 109, 695 (1958). 6. B. V. Lang et al.. Appl. Phys. Lett. 41, 1333 (1985).
7. R. People and J. C. Bean, Appl. Phys. Leff. 48, 538 (1986). 8. E. F. Crabbe et al., 5lst DRC (1993). 9. A. Gruhle, H. Kibbel. U. Erben and E. Kasper, 51sr DRC (1993). 10. F. Sato et al.. IEDM, p. 397 (1992). 11. T. I. Kamins et al.. IEDM, p. 647 (1989). 12. B. R. Ryum, T.-H. Han and S.-C. Lee, 24th ESSDERC, p. 59 (1994). 13. A. Schuppen et al.. 24th ESSDERC, p. 469 (1994). 14. T. D. Nolon and R. Sinclair, J. Appl. Phys. 53, 6219 (1982). 15. M. Ugajin ei al., BCTM, p. 26 (1992). 16. E. F. Crabbe et al., IEEE Electron. Device. Lett. 14,478 (1993). 17. E. J. Prinz et al.. IEEE Electron. Decice Lett. 12, 42 (1991). 18. S. Kim, B. R. Ryum. S. Kang and W. Kim, So/id-State Electron. 37, 517 (1994). 19. S. Lee, B. R. Ryum, O.-J. Kwon and J.-H. Lee, Electron. Lett. 29. 1797 (1993). 20. S. Lee, B. R. Ryum and S: Kang, IEEE Trans. Electron. Devices ED-41, 233 (1994). 21. E. 0. Johnson. R. C. A. Rep. 26, 163 (1965).