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MCT heteroepitaxial 4 × 288 FPA
Infrared Physics & Technology 45 (2004) 13–23 www.elsevier.com/locate/infrared
MCT heteroepitaxial 4 288 FPA V.V. Vasilyev a, A.G. Klimenko a, I.V. Marchishin a, V.N. Ovsyuk a, N.Ch. Talipov a, T.I. ZaharÕyash a, A.G. Golenkov b, Yu.P. Derkach b, V.P. Reva b, F.F. Sizov b,*, V.V. Zabudsky b a
b
Institute of Semiconductor Physics, 630090 Novosibirsk, Russia Institute of Semiconductor Physics, 03028, Nauki Av., 41, Kiev, Ukraine Received 29 August 2002
Abstract 4 288 heteroepitaxial mercury–cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28 25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (0 1 3) GaAs substrates with CdZnTe buffer layers and had cutoff wavelength kco 11:8 0:15 lm at T ¼ 78 K. To decrease the surface influence of carrier recombination processes the compositionally dependent layers with increase of Cd content both toward the surface and HgCdTe/CdZnTe boundary interface were grown. Silicon readouts with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure, to qualify readout integrated circuits on wafer level at T ¼ 300 K, was worked out. The silicon readouts for 4 288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4 288 MCT n–p-junctions, the detectivity for several tested 4 288 arrays was within Dk ffi 9 1010 –1:8 1011 cm Hz1=2 /W for background temperature Tb ¼ 295 K. 2003 Elsevier B.V. All rights reserved. Keywords: MBE technology; MCT arrays; CCD readouts; Detectivity
1. Introduction Today high-performance IR imaging systems typically include hybrid focal plane arrays (FPAs) cooled down to cryogenic temperatures with readout integration circuits (ROICs) in the focal plane. The IR FPA hybrid technology is wide*
Corresponding author. Tel.: +380-44-2656296; fax: +38044-2658342. E-mail address: [email protected] (F.F. Sizov).
spread since it permits the parameters of detectors and the silicon ROICs coupled to the detector array to be optimized separately [1]. The major IR FPA hybrid technology uses MCT photovoltaic detector chips and silicon CCD or CMOS chips [1,2]. At present, MCT-based FPA detectors for IR imaging applications in 3–5 and 8–12 lm wavelength regions occupy a central position in development and manufacture of IR systems operating at high frame rates and low integration time.
1350-4495/$ - see front matter 2003 Elsevier B.V. All rights reserved. doi:10.1016/S1350-4495(03)00138-5
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Medium- and long-wavelength infrared (MWIR and LWIR) HgCdTe photodiodes and arrays have the most suitable parameters for IR applications [3–5]. MCT moderately cooled arrays remain the most sensitive small pitch FPAs among others (e.g., QWIP (both AlGaAs QWIPs and GaInSb strain layer superlattices), doped silicon detectors, uncooled microbolometer arrays, InSb photodiodes, Schottky-barrier detectors, etc.) in LWIR and MWIR regions. The MBE growth procedure of MCT layers on alternative (not CdZnTe) substrates is successfully used for SWIR and MWIR layers for large area arrays [4,6,7]. For LWIR applications up to wavelength k 12 lm the growth of MCT layers for large area LWIR arrays as a rule is realized on CdZnTe substrates [4]. The growth of large area MCT layers on alternative substrates was less successful [8,9] because of insufficient quality of the diodes and their parameters homogeneity to be used with ROICs. Here is shown that MBE procedure can be applied for obtaining high impedance large area heteroepitaxial LWIR MCT arrays with sufficiently high detectivities for different applications and cutoff wavelength up to kco 12:0 lm at T ¼ 78 K.
2. Growth procedure The MBE MCT growth technology on (0 1 3) gallium arsenide substrates was used with intermediate CdZnTe layer which allows one to achieve significant decrease of the CdHgTe material cost for the large format IR FPAs. The advantages of MBE technology at creating the epitaxial layers seem to be the most adaptable for production of large square MCT arrays [10–12]. The equipment was designed and manufactured for industrial production of the MBE grown epitaxial MCT layers on different substrates with an automatic system to control the technological process parameters and the layer quality in situ [13]. This system can precisely maintain the growth condition processes of the buffer layers on GaAs substrate and MCT films. Using an automatic ellipsometer allows to change the layer composition
on thickness with high accuracy, correcting the molecular sources temperature. HgCdTe smooth surface epitaxial layers were grown on 2 in. (0 1 3) GaAs substrates with an intermediate CdZnTe buffer layer. The growth temperature was within T ¼ 180–190 C for MCT layers and within T ¼ 240–300 C for the buffer layers. During the growth process the composition of layers was controlled by a built-in ellipsometer. The feedback of built-in ellipsometer with temperature control of the component sources allowed to keep up the composition non-uniformity over 1 cm2 area better than Dx ¼ 0:001. The limiting process of MCT surface formation layers by MBE growth is the dissociation process of diatomic Te molecules [14]. Dissociation is favored at the surfaces with high step densities and this is the reason why for MCT layers growth technology on the alternative substrates the (1 1 2) or (0 1 3) substrate orientations are used. Dissociation is favored when absorbed Te2 molecules are surrounded by metal atoms. At low temperature growth conditions (T 6 190 C) and at high densities of Hg atoms absorbed at the surface with high step densities, the effective growth of layers can be realized and it is possible to obtain smooth MCT surfaces almost without pronounced faceting [15] and small densities of V-defects. The use of (0 1 3) substrates permits to widen the interval of growth conditions (Hg vapor pressure, growth rate, substrate temperature) at which the films with low defect densities can be obtained. At temperature increase the density of absorbed Hg atoms and the fraction of surface, at which dissociation of Te2 molecules takes place, decrease. At high temperatures dissociation of Te2 molecules will take place only at some places of the surface, where enough Hg atoms are situated. In such places the growth will be preferable. In this temperature range above T 190 C the normal layer growth will be complicated and material precipitation takes place with some kind of relief. Te clusters are generating and it was shown that excess of Te leads to increase of V-defects density [16]. The as-grown layers were of n-type conductivity (electron concentration n77 2 1015 cm3 , electron mobility l77 105 cm2 /V s) requiring annealing to convert the conductivity type in order
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to use boron implantation for fabricating nþ –pdiodes to be used with n-channel CCD readouts. The dislocations density in these MCT films was about ND 105 cm2 . The as-grown MCT layers have electron concentration about 1015 cm3 in dependence of growth temperature conditions. This can be the reason of anti-site Te [17], interstitial metal atoms [18], vacancies in telluride sublattice [18], and impurity atoms, first of all in this case gallium as GaAs substrates are used. The results of calculations of anti-site Te equilibrium concentration have shown that these equilibrium concentrations are too small (by several orders) at these temperatures to explain the electron concentration of N 1015 cm3 [15,16]. Another reason for this rather high electron concentration may be the influence of Ga doping as GaAs substrates are used. The results of electrically active Ga concentration calculations at equilibrium conditions have shown that Ga solubility at growth temperatures of MBE method is too low (NGa 108 –1010 cm3 ) and cannot explain observable phone electron concentrations. At growth temperatures typical, e.g. for liquid phase or vapor phase methods (T 450 C), the Ga solubility increases to NGa 1016 –1017 cm3 and it can lead to increase of electron concentration in the layers grown on GaAs substrates. It seems that Ga cannot be a primary donor impurity in MBE MCT layers grown on GaAs substrates, as, e.g., for such MBE grown layers on (1 1 2) silicon substrates the electron concentration is of the same order as for layers grown on GaAs substrates [15]. Electron concentrations observed in MCT layers can be explained by an anti-site non-equilibrium Te capture model. Super-saturation conditions increase the probability formation of the defect configurations in the layers. With temperature increase super-saturation decreases and there the anti-site Te concentration (which is a donor type defect in MCT layers) should decrease [16]. It was observed that the measured temperature dependence of electron concentrations in as-grown MCT layers qualitatively agrees with the tendencies of nonequilibrium Te capture data and electron concentrations in MCT layers [16] (electron concentration decreases as the substrate temperature increases).
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After approximately 200 h of annealing process at T 230 C the n-type HgCdTe layers were converted to p-type conductivity layers. In the samples annealed the hole concentration p and mobility lp values of the films at T ¼ 77 K were p77 ð5–10Þ 1015 cm3 and l77 ð300–400Þ cm2 /V s, respectively. Analyzing the dark current transport mechanisms and their reverse bias dependences [15,19] it was concluded that these values of hole concentrations are the most suitable for MCT LWIR nþ –p-diodes operation. To decrease the surface recombination processes influence in MCT layers they were grown with x value increased to surface composition [13]. Schematic cross-section of these layers is shown in Fig. 1a. Structures used for arrays manufacturing have wide gap regions of d 0:5–1.0 lm thickness with composition x 0:55 near the surface, while in the layers bulk the composition value was within x ¼ 0:219–0.220. The total thickness of heteroepitaxial layers was within 10–12 lm. The example of the heteroepitaxial layer profile in situ measured and controlled by high speed ellipsometer is shown in Fig. 1b. The epitaxial Hg1x Cdx Te (x 0:2) films grown on Cd1y Zny Te (y 0:04) single crystal substrates are lattice-matched to them and have sufficiently high crystal perfection, which is mainly determined by the substrates quality. This is the base to design the IR arrays operating at background limited performance (BLIP) conditions. But Cd1y Zny Te single crystal substrates are cost limited in area which limits their use for manufacturing large size arrays. Using sapphire (see, e.g., [4,6]) or silicon (see, e.g., [7,11]) substrates allows one to grow large area MCT epitaxial layers, suitable for manufacturing large format arrays in 3–5 micron IR region. It was shown (see, e.g., [13,20]) that gallium arsenide substrates can be used for growth of large area epitaxial layers applicable for manufacturing of high quality IR detectors. Still, the structure perfection of these layers is poorer compared to the analoguous ones grown on CdZnTe substrates. Nevertheless here it is shown that MCT heteroepitaxial layers grown by MBE are suitable for manufacturing of large area arrays for 8–12 lm wavelength range with characteristics of acceptable quality.
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growth procedure on 2–3 in. GaAs wafer level. This equipment still can be used for epitaxial MCT material growth on different substrates with an automatic system controlling the technological process parameters and the layer quality in situ [21]. This system provides precise maintaining conditions of the buffer layer and MCT film growth process on GaAs substrates. Automatic ellipsometer used allows to control the thickness changes of layer composition and to maintain it constant with high accuracy, correcting the molecular sources temperature.
3. Diode properties In the grown and annealed p-type HgCdTe MBE epitaxial layers the 4 288 focal plane arrays with 56 43 lm pitch and 28 25 lm n–p-type photodiodes were manufactured similar to the procedure described in [22]. The photodiodes were obtained by boron implantation with particle energies within E 50–120 keV. The topology of the 4 288 array is shown in Fig. 2. Fig. 1. (a) Transverse section of multilayer MCT heterostructure. Right-hand side: change of the band gap for different layers. (b) MCT heteroepitaxial layer profile grown by MBE technology controlled by high-speed ellipsometer.
One of the most important parameters of MCT layers is the composition uniformity across the film area. For FPA operating in the 8–12 lm spectral range the composition changes should not exceed the value Dx < 0:001 across the array area, which, e.g., for a 256 256 array with pitch of 40 lm is about 10 mm. To provide the chemical and the thickness uniformity of epitaxial MCT layers across the wafer diameter there were designed special molecular sources with practically constant (during long time processes) molecular flows. To know the subsequent changes of flows at decreasing the materials in crucibles it was possible to correct the sources temperature for maintaining stable molecular flows [20]. MBE equipment was designed and manufactured with possibility to control the MCT layer
Fig. 2. Topology of 4 288 array.
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Dark currents at V 100–150 mV reverse bias chosen for the hybridization procedure diodes in the arrays with kco 11:8 0:15 lm as a rule did not exceed the values of Id 10–15 nA and the zero bias resistant-area product R0 A for them was within the values R0 A 15–20 X cm2 . The average R0 A values for array elements within the wafer were R0 A 6 X cm2 . For such reverse biases the main contribution to the nþ –p-junction dark current manufactured in MBE grown heterostructures with concentrations of p-type layers within p77 ð5–10Þ 1015 cm3 is from diffusion, generation–recombination (G–R) and trap assisted tunneling processes [19]. In Fig. 3 the typical reverse bias dark current, differential resistance dependencies, and also re-
Fig. 3. (a) Typical dependencies of dark current and dynamic resistance for one of the MCT MBE-grown diodes (kco ¼ 11:8 lm) versus bias voltage; (b) typical relative response of three photodiodes from different parts of 4 288 photodiode array.
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sponsivity spectra of the diodes from different parts of one of the arrays with kco 11:8 lm versus IR wavelength at an operating temperature T ¼ 78 K are presented. One can see rather good photoresponse homogeneity spectra for such MBE, grown on GaAs (0 1 3) substrates, HgCdTe diodes.
4. CCD silicon readouts The primary function of a readout device for IR array is to provide an IR detector charge to voltage conversion, integration of the electrons generated in a photodetector, permission to perform some preliminary treatment of the signals (e.g., skimming, partitioning, amplification and time multiplexing of signals) from the detectors in the array [23], to a much smaller number of outputs from, as a rule, cold zone. In the case of a multiraw linear array, used in scanning mode, time delay and integration (TDI) function should be included to improve the performance of the array. Of course, IR readout electronics should not limit the performance of the detector in the array. Present IR FPAs for 8–12 lm spectral region are facing the problem of large charge integration implying a large charge integration capacitor (because of large background flux at T P 300 K). Thus, the background signal suppression should be used and this function must be performed in a short time compared with a total integration time. The performance requirements for IR FPAs are highly varied with respect to wavelength region, background photon flux, operating temperature, dynamic range, noise, readout rate, power dissipation, detector bias, and some other parameters. The performance of the IR FPAs is also to a large extent determined by the charge stored in the input stage of the signal processor. There are several possible main types of architecture and circuit approaches for readout electronics (see, e.g., [1,2,23,24]). Here were chosen CCD-type circuits because of the possibility to realize the lower level of noise, compared to CMOS-type circuits in spite of the need to use for circuits manufacturing the specific production line. Though the integration possibilities are less than those of CMOC lines, the design rules 2.0 lm used
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here were enough to get all the functions needed in producing ROICs with pitch of approximately 45 lm in PV arrays for which they were designed and manufactured. Another reason for the CCD approach is connected with the best possible solution for improved performance when the TDI concept is used and more flexibility of operating conditions due to the higher number of external biases and clocks required (see, e.g., [2]). For CCD readout devices manufacturing here was used a standard silicon process with two polysilicon gate levels and one metal level, which combines n-channel MOS transistors on the same wafer. The four-inch boron-doped p-type h1 0 0i Si wafers with resistivity of 10–20 X cm were taken for the process. The circuits under consideration consist of MOS transistors with gates from first and second polysilicon level and CCD cells with buried and semi-buried channels. The direct injection transistors are designed as MOS-transistors with induced channel with first polysilicon level gates. The under-gate dielectric is a thermally grown SiO2 layer with the thickness of about 400 and threshold voltage of approximately 0.3 V. A To achieve the suppression of the useless currents prior to CCD multiplexing, several possible solutions exist. Among them are: reduction of the incoming photon flux by narrowing spectral band and field of view (FOV) of the detector; reduction of integration time (at the price of lower signalto-noise ratio); oversampling (multiple detector signal read out during one sampling); design various circuits (subframe readout, DC level subtraction, antiblooming, charge partitioning, charge skimming, in-pixel current memory cell, which enables PV direct current suppression), etc. Here among the available solutions to achieve background suppression in CCD ROICs were chosen [25] the classical charge skimming and partitioning functions, when only a part of charge according to the background is subtracted from the integrated charge packet or a fraction of the integrated charge is transferred to CCD, respectively. 4.1. Unit cell electronics Unit cell electronics is the most important part of the readout device and should provide perfect
bias control, high linearity and low noise performance. There exist several possible solutions [1,23,24]. Among them to satisfy the requirements of FPA with PV HgCdTe detectors for operation at relatively large backgrounds there were chosen the unit cells with direct injection (DI) to improve the coupling between PV detector and CCD signal processor. The scattering values of threshold voltages of the input transistors were within DV ¼ 7 mV, and the nonlinearity of transmission characteristics was less than 2%. Special procedure to control these parameters at T ¼ 300 K at wafer level was developed. Here the multiplexers were designed according to CCD technology with buried channel. To simplify the external control circuits the CCD cell with asymmetric potential well is used (with two or one and a half phase control). The storage charge region is created by phosphorus ion implantation into the under-the-gate region from polysilicon first level. To fabricate the barrier regions under the gates from polysilicon second level there is used second boron implantation, which compensates the part of introduced phosphorus. The resulting depth of the potential well for information charge storage is about 5 V, and the multiplexer charge capacity Q is about Q 2:4 pC. 4.2. TDI function Displacement register of TDI with four inputs of information charge is also designed as CCD cells with asymmetrical potential well. To increase its charge capacity there is used the technology of ‘‘semi-buried’’ channel, which differs compared to buried channel with the potential at the barrier gate. In the case of ‘‘semi-buried’’ channel the charge capacity regions under the first polysilicon level are manufactured by phosphorus ion implantation at the same time with manufacturing the capacity regions in multiplexer, and in the barrier region there is executed the addition boron implantation, that increases the depth of the potential well up to U 8 V. The charge capacity of the TDI register output bit is about 2.4 pC per channel at an output signal voltage of U ffi 5 V. With partitioning mode included it is about 6.4 pC for unit cell, and it is about 10.0 pC with skimming
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Fig. 4. An example of CCD cell operation with four stages TDI function.
and partitioning modes switched on both for fourand two-phases clock pulses CCD ROICs. The example of CCD cell operation with four stage TDI function is shown in Fig. 4 for ROIC driven with four phase clock pulses. Here are shown the signal amplitudes from one, from the sum of two, three, and four diodes, respectively. 4.3. Charge skimming and partitioning modes Different operation modes of the CCD readout circuit are shown in Fig. 5 schematically. High intensity of background radiation and long integration time (particularly in the case of PV detector low R0 A product value for long wavelength applications and large background fluxes) can lead to the overflow of accumulation capacity. In this case it is necessary to use the skimming mode or partitioning mode, or skimming and partitioning modes simultaneously according to the userÕs requirements. To maintain this feature of the readout device here several elements are added into the input circuits. There are skimming/partitioning gate G1, CCD transfer control gate G2, capacity C2 (see Fig. 5), skimming/antiblooming transistor for extraction of the charge excess. The electrodes C1, C2, G1, and G2 are pointed out only in Fig. 5a. The voltages UC1, FPS, UC2, and F0 at corresponding electrodes C1, C2, G1, and G2 are shown also in Fig. 5. When skimming mode is applied, a constant portion of charge according to the background
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flux is subtracted from the integrated charge packet. In this case a constant voltage is applied to skimming gate G1. The value of this voltage is lower than the voltages applied to gates C1 and C2. In the case of using partitioning mode only a fraction of the integrated charge is transferred to the CCD, the partitioning ratios can be changed according to the userÕs requirements. In partitioning mode electrodes C1 and C2 are connected together and direct voltage of some level is applied to them (in Fig. 5c it is a voltage V 4 V practically used here). The pulse voltages are applied to partitioning gate G1, CCD control gate G2 and extraction transistor gate (not shown here). At integration time period T the accumulation of signal charge takes place into capacitor C1 and C2. During the integration processes to partitioning electrode G1 is applied the high potential, which provides free charge flow from one capacitor to another and also equalizing these capacitance potentials. Then the channel between them is switched off and full signal charge is divided between two capacities proportionally to their values (both information and noise charges). If one applies to electrode C2 the direct potential lower than to electrode C1, an amplitude Ups of pulse Fps equals direct potential C2, it is possible for part of the input charge to be subtracted and another part of charge to be divided proportionally to capacities C1 and C2. This is a skimming/partitioning mode. Applying skimming and partitioning modes leads to noise enhancement of the FPA but allows to enhance its dynamic range, e.g., to extend the application range of FPA to higher background temperatures, higher FPA operating temperatures, and longer cutoff wavelength regions. The additional noise that this technique provides, depends much on the gate noise potential and at well stabilized direct voltage (noise potential lower than 100 lm) it does not exceed 1–2% compared to other noises [25].
5. Linear array manufacturing At the diode array manufacturing one of the primary problems is the problem of producing of
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Fig. 5. Different operating modes of the input circuit of the CCD silicon readout. (a) Operating mode without skimming and partition. 1––accumulation of the input charge; 2––insertion of the charge into 16-bit CCD multiplexor. (b) Operating mode without skimming and partition. Integration time is regulated by voltage at FPS gate. 1––accumulation of the input charge; 2––restriction of the accumulation time by voltage at FPS gate; 3 – insertion of the charge into 16-bit CCD multiplexor. (c) Operating mode with partition. 1––accumulation of the input charge; 2––charge partitioning; 3––insertion of the partitioned charge into 16-bit CCD multiplexor and removing of the excess charge (to drain). (d) Operating mode with skimming and partition. 1––accumulation of the input charge; 2–– charge skimming and partitioning; 3––insertion of the partitioned charge into 16-bit CCD multiplexor and removing of the excess charge (to drain).
passivation layers to MBE MCT layers with high characteristics at the semiconductor-dielectric
boundary. MCT surface coating should satisfy at least the following requirements:
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• low temperature of formation (less than 100 C); • low built-in charge surface density (6 1010 cm2 ); • good adhesion quality which is stable at different technological processes; • time and thermal treatment stability. As the basic dielectric coating, which satisfies the above mentioned requirements, here was chosen the low temperature deposited silicon dioxide (deposition temperature T 100 C). But low temperature deposited SiO2 actively interact with atmosphere moisture. It leads to accumulation of positive charge up to values of about 1012 cm2 during several weeks. Therefore, one cannot use this type of dielectric for MCT as the only one passivation layer. For elimination of the possible atmosphere moisture influence here was used the additional dielectric layer, which is silicon nitride, that was formed at temperature T 60 C by plasma-chemical reaction deposition procedure over the silicon dioxide layer. Assembling of 4 288 arrays, which include the photodiode linear arrays and silicon CCD readout circuits, was carried out by the method of cold welding (at room temperature) process of twolayer indium bumps preliminary deposited through two different photomasks at different technological conditions on photodiode arrays and silicon ROICs. The truncated pyramidal In bumps height was about 12 ¼ 6 + 6 lm (two layers of indium characterized relatively small indium grains in bottom layer) with ground dimensions about 17–20 lm, and about 12 lm at the top. With such type of In bumps during the hybridization process, when the tops of In bumps at diode array and silicon circuit are touching each other, the plastic yielding and cold welding take place at the top layers of In bumps. The bottom layers of In bumps are practically not deformed, as the pressure arising at upper layers is not sufficient to overcome the breaking point of lower In bump layers. The use of two-layer In bump technology allows to reduce pressure to MCT surface during the hybridization process. In such a procedure the pressure used during the hybridization process does not exceed 0.3 kg/mm2 on the MCT surface, which is about five times lower than the critical one for MCT
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diodes degradation beginning (Pcrit ¼ 1:7 kg/mm2 at T ¼ 20 C [26]).
6. FPA properties Because of the TDI function from four photosensitive diodes in the chain the output information from 288 channels is formed from 1152 sensitive elements. The output 288 information signals are grouped by 18 channels and were brought out by 16 analog outputs at maximum frequency of 2 MHz. Some back-side illuminated arrays properties were investigated at T ¼ 78 K. 4 288 FPA detectivities with skimming mode included at integration time sint ¼ 6 ls at T ¼ 78 K, and background temperature Tb ¼ 295 K were in the range of Dk ffi 9 1010 –1.8 1011 cm Hz1=2 / W for several arrays tested. The sensitivity histogram of one of the arrays with Dk ¼ 1:81 1011 is shown in Fig. 6. In this array the number of defect elements (the value of detectivity Dk is less than 2.5 1010 cm Hz1=2 /W) was equal to 9 pixels with no dead elements. The presence of defect elements and relatively large standard sensitivity and Dk deviations are connected to local microinhomogeneities presented in these MBE fims grown on
Fig. 6. Channels sensitivity (4 pixels in each channel) histogram for one of the MCT LWIR 4 288 arrays manufactured on GaAs substrate. Sensitivity mean value is equal to 2.87 107 V/ W, sensitivity standard deviation is equal to 27.1%, TBB ¼ 500 K, 2h1 ¼ 64, 2h2 ¼ 32.
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Table 1 Some parameters of one of the 4 288 TDI LWIR MCT array Parameter
Measured value
Sensitivity max wavelength, lm Cutoff wavelength, lm Mean sensitivity, V/W Sensitivity standard deviation, % Mean detectivity, Dk , cm Hz1=2 W1 Dk standard deviation, % Number of defect elements, pixels
9.95 0.15 11.80 0.15 2.87 107 27.1 1.81 1011 31.5 9
Acknowledgements The authors are very grateful to Yu.G. Sidorov and S.A. Dvoretski for supplying the MCT layers on GaAs substrates.
GaAs substrates. Some parameters of one of these arrays are presented in Table 1. The sensitivity Sk data were used for detectivity Dk evaluation according to the expression [27]: Dk ¼
Sk 1=2 1=2 A ðDf Þ ; Vn
arrays was not rather good (standard deviation about 30%), the detectivities obtained are high enough to be used in different IR instrumentation.
ð1Þ
where Vn is the noise level (in this case at the FPA output), A is the pixel area, and Df is the frequency bandwidth, which in case of TDI mode is equal to ð2sint Þ1 , where sint is the integration time. Because of the large field of view of the testing system (cold shield plane angle in horizontal plane is 2h1 ¼ 64 and in vertical plane 2h2 ¼ 32) and lack of the short wavelength filter the integration time used did not exceed sint ¼ 6 ls, though in the systems used it can be regulated in wide range in dependence of background fluxes and the signal level.
7. Conclusions MCT 4 288 heteroepitaxial linear diode arrays for LWIR applications with CCD silicon readouts were designed, manufactured and tested. MBE grown MCT heteroepitaxial layers on (0 1 3) GaAs substrates used in these hybrid arrays have cutoff wavelength kco 11:8 lm at T ¼ 78 K. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bump technology. With skimming mode used for 4 288 MCT n–pjunctions, the detectivity was Dk ffi (0.9–1.8) 1011 cm Hz1=2 /W at background temperature Tb ¼ 295 K. In spite of the fact that homogeneity of the
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Technical Fundamentals of HgCdTe Molecular Beam Epitaxy, Matrix Photodetector Arrays for Infrared Region, Nauka, Novosibirsk, 2001 (Chapter 2, in Russian). M.A. Berding, M. van Schilfgaarde, A.T. Paxton, A. Sher, J. Vac. Sci. Technol. 8 (1990) 1103. C.G. Morgan-Pond, R. Raghavan, Phys. Rev. B 31 (1985) 6616. J.V. Gumeniuk-Sichevskaja, F.F. Sizov, V.N. Ovsyuk, V.V. Vasilyev, D.G. Esaev, Fizika i Technika Poluprovodnikov 35 (2001) 835 (in Russian) [English Ed.: Semiconductors 35 (2001) N7]. V.S. Varavin, S.A. Dvoretsky, V.I. Liberman, N.N. Mikhailov, Yu.G. Sidorov, Thin Solid Films 267 (1995) 121. V.S. Varavin, S.A. Dvoretsky, V.I. Liberman, N.N. Mikhailov, Yu.G. Sidorov, J. Cryst. Growth 159 (1996) 1161. V.V. Vasilyev, D.G. Esaev, A.G. Klimenko, A.I. Kozlov, A.I. Krymsky, I.V. Martchisin, V.N. Ovsyuk, L.N. Ro-
[23]
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[25] [26]
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mashko, A.O. Suslyakov, N.K. Talipov, V.V. Voinov, T.I. Zahariash, Yu.G. Sidorov, V.S. Varavin, S.A. Dvoretski, N.N. Mikhailov, Proc. SPIE 3061 (1997) 956. J.L. Vampola, in: W.D. Rogatto (Ed.), Electro-Optical Components, SPIE Opt. Eng. Press, Bellingham, 1993 (Chapter 5). L.J. Kozlowski, W.F. Kosonocky, in: M. Boss, W. Van Stryland, D.R. Williams, W.L. Wolfe (Eds.), Handbook of Optics, McGraw-Hill, New York, 1995. F.F. Sizov, Yu.P. Derkach, V.P. Reva, Yu.G. Kononenko, Optoelectronics Review 7 (1999) 327. V.N. Ovsyuk, V.V. Vasilyev, N.Ch. Talipov, L.N. Romashko, A.I. Kozlov, A.G. Klimenko, I.V. Marchishin, in: S.P. Sinitsa (Ed.), MCT Layer Photodetector Arrays for Infrared Region, Matrix Photodetector Arrays for Infrared Region, Nauka, Novosibirsk, 2001 (Chapter 3, in Russian). R.J. Keyes (Ed.), Optical and Infrared Detectors, SpringerVerlag, Berlin–Heidelberg, 1980.
MCT heteroepitaxial 4 288 FPA V.V. Vasilyev a, A.G. Klimenko a, I.V. Marchishin a, V.N. Ovsyuk a, N.Ch. Talipov a, T.I. ZaharÕyash a, A.G. Golenkov b, Yu.P. Derkach b, V.P. Reva b, F.F. Sizov b,*, V.V. Zabudsky b a
b
Institute of Semiconductor Physics, 630090 Novosibirsk, Russia Institute of Semiconductor Physics, 03028, Nauki Av., 41, Kiev, Ukraine Received 29 August 2002
Abstract 4 288 heteroepitaxial mercury–cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28 25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (0 1 3) GaAs substrates with CdZnTe buffer layers and had cutoff wavelength kco 11:8 0:15 lm at T ¼ 78 K. To decrease the surface influence of carrier recombination processes the compositionally dependent layers with increase of Cd content both toward the surface and HgCdTe/CdZnTe boundary interface were grown. Silicon readouts with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure, to qualify readout integrated circuits on wafer level at T ¼ 300 K, was worked out. The silicon readouts for 4 288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4 288 MCT n–p-junctions, the detectivity for several tested 4 288 arrays was within Dk ffi 9 1010 –1:8 1011 cm Hz1=2 /W for background temperature Tb ¼ 295 K. 2003 Elsevier B.V. All rights reserved. Keywords: MBE technology; MCT arrays; CCD readouts; Detectivity
1. Introduction Today high-performance IR imaging systems typically include hybrid focal plane arrays (FPAs) cooled down to cryogenic temperatures with readout integration circuits (ROICs) in the focal plane. The IR FPA hybrid technology is wide*
Corresponding author. Tel.: +380-44-2656296; fax: +38044-2658342. E-mail address: [email protected] (F.F. Sizov).
spread since it permits the parameters of detectors and the silicon ROICs coupled to the detector array to be optimized separately [1]. The major IR FPA hybrid technology uses MCT photovoltaic detector chips and silicon CCD or CMOS chips [1,2]. At present, MCT-based FPA detectors for IR imaging applications in 3–5 and 8–12 lm wavelength regions occupy a central position in development and manufacture of IR systems operating at high frame rates and low integration time.
1350-4495/$ - see front matter 2003 Elsevier B.V. All rights reserved. doi:10.1016/S1350-4495(03)00138-5
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Medium- and long-wavelength infrared (MWIR and LWIR) HgCdTe photodiodes and arrays have the most suitable parameters for IR applications [3–5]. MCT moderately cooled arrays remain the most sensitive small pitch FPAs among others (e.g., QWIP (both AlGaAs QWIPs and GaInSb strain layer superlattices), doped silicon detectors, uncooled microbolometer arrays, InSb photodiodes, Schottky-barrier detectors, etc.) in LWIR and MWIR regions. The MBE growth procedure of MCT layers on alternative (not CdZnTe) substrates is successfully used for SWIR and MWIR layers for large area arrays [4,6,7]. For LWIR applications up to wavelength k 12 lm the growth of MCT layers for large area LWIR arrays as a rule is realized on CdZnTe substrates [4]. The growth of large area MCT layers on alternative substrates was less successful [8,9] because of insufficient quality of the diodes and their parameters homogeneity to be used with ROICs. Here is shown that MBE procedure can be applied for obtaining high impedance large area heteroepitaxial LWIR MCT arrays with sufficiently high detectivities for different applications and cutoff wavelength up to kco 12:0 lm at T ¼ 78 K.
2. Growth procedure The MBE MCT growth technology on (0 1 3) gallium arsenide substrates was used with intermediate CdZnTe layer which allows one to achieve significant decrease of the CdHgTe material cost for the large format IR FPAs. The advantages of MBE technology at creating the epitaxial layers seem to be the most adaptable for production of large square MCT arrays [10–12]. The equipment was designed and manufactured for industrial production of the MBE grown epitaxial MCT layers on different substrates with an automatic system to control the technological process parameters and the layer quality in situ [13]. This system can precisely maintain the growth condition processes of the buffer layers on GaAs substrate and MCT films. Using an automatic ellipsometer allows to change the layer composition
on thickness with high accuracy, correcting the molecular sources temperature. HgCdTe smooth surface epitaxial layers were grown on 2 in. (0 1 3) GaAs substrates with an intermediate CdZnTe buffer layer. The growth temperature was within T ¼ 180–190 C for MCT layers and within T ¼ 240–300 C for the buffer layers. During the growth process the composition of layers was controlled by a built-in ellipsometer. The feedback of built-in ellipsometer with temperature control of the component sources allowed to keep up the composition non-uniformity over 1 cm2 area better than Dx ¼ 0:001. The limiting process of MCT surface formation layers by MBE growth is the dissociation process of diatomic Te molecules [14]. Dissociation is favored at the surfaces with high step densities and this is the reason why for MCT layers growth technology on the alternative substrates the (1 1 2) or (0 1 3) substrate orientations are used. Dissociation is favored when absorbed Te2 molecules are surrounded by metal atoms. At low temperature growth conditions (T 6 190 C) and at high densities of Hg atoms absorbed at the surface with high step densities, the effective growth of layers can be realized and it is possible to obtain smooth MCT surfaces almost without pronounced faceting [15] and small densities of V-defects. The use of (0 1 3) substrates permits to widen the interval of growth conditions (Hg vapor pressure, growth rate, substrate temperature) at which the films with low defect densities can be obtained. At temperature increase the density of absorbed Hg atoms and the fraction of surface, at which dissociation of Te2 molecules takes place, decrease. At high temperatures dissociation of Te2 molecules will take place only at some places of the surface, where enough Hg atoms are situated. In such places the growth will be preferable. In this temperature range above T 190 C the normal layer growth will be complicated and material precipitation takes place with some kind of relief. Te clusters are generating and it was shown that excess of Te leads to increase of V-defects density [16]. The as-grown layers were of n-type conductivity (electron concentration n77 2 1015 cm3 , electron mobility l77 105 cm2 /V s) requiring annealing to convert the conductivity type in order
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to use boron implantation for fabricating nþ –pdiodes to be used with n-channel CCD readouts. The dislocations density in these MCT films was about ND 105 cm2 . The as-grown MCT layers have electron concentration about 1015 cm3 in dependence of growth temperature conditions. This can be the reason of anti-site Te [17], interstitial metal atoms [18], vacancies in telluride sublattice [18], and impurity atoms, first of all in this case gallium as GaAs substrates are used. The results of calculations of anti-site Te equilibrium concentration have shown that these equilibrium concentrations are too small (by several orders) at these temperatures to explain the electron concentration of N 1015 cm3 [15,16]. Another reason for this rather high electron concentration may be the influence of Ga doping as GaAs substrates are used. The results of electrically active Ga concentration calculations at equilibrium conditions have shown that Ga solubility at growth temperatures of MBE method is too low (NGa 108 –1010 cm3 ) and cannot explain observable phone electron concentrations. At growth temperatures typical, e.g. for liquid phase or vapor phase methods (T 450 C), the Ga solubility increases to NGa 1016 –1017 cm3 and it can lead to increase of electron concentration in the layers grown on GaAs substrates. It seems that Ga cannot be a primary donor impurity in MBE MCT layers grown on GaAs substrates, as, e.g., for such MBE grown layers on (1 1 2) silicon substrates the electron concentration is of the same order as for layers grown on GaAs substrates [15]. Electron concentrations observed in MCT layers can be explained by an anti-site non-equilibrium Te capture model. Super-saturation conditions increase the probability formation of the defect configurations in the layers. With temperature increase super-saturation decreases and there the anti-site Te concentration (which is a donor type defect in MCT layers) should decrease [16]. It was observed that the measured temperature dependence of electron concentrations in as-grown MCT layers qualitatively agrees with the tendencies of nonequilibrium Te capture data and electron concentrations in MCT layers [16] (electron concentration decreases as the substrate temperature increases).
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After approximately 200 h of annealing process at T 230 C the n-type HgCdTe layers were converted to p-type conductivity layers. In the samples annealed the hole concentration p and mobility lp values of the films at T ¼ 77 K were p77 ð5–10Þ 1015 cm3 and l77 ð300–400Þ cm2 /V s, respectively. Analyzing the dark current transport mechanisms and their reverse bias dependences [15,19] it was concluded that these values of hole concentrations are the most suitable for MCT LWIR nþ –p-diodes operation. To decrease the surface recombination processes influence in MCT layers they were grown with x value increased to surface composition [13]. Schematic cross-section of these layers is shown in Fig. 1a. Structures used for arrays manufacturing have wide gap regions of d 0:5–1.0 lm thickness with composition x 0:55 near the surface, while in the layers bulk the composition value was within x ¼ 0:219–0.220. The total thickness of heteroepitaxial layers was within 10–12 lm. The example of the heteroepitaxial layer profile in situ measured and controlled by high speed ellipsometer is shown in Fig. 1b. The epitaxial Hg1x Cdx Te (x 0:2) films grown on Cd1y Zny Te (y 0:04) single crystal substrates are lattice-matched to them and have sufficiently high crystal perfection, which is mainly determined by the substrates quality. This is the base to design the IR arrays operating at background limited performance (BLIP) conditions. But Cd1y Zny Te single crystal substrates are cost limited in area which limits their use for manufacturing large size arrays. Using sapphire (see, e.g., [4,6]) or silicon (see, e.g., [7,11]) substrates allows one to grow large area MCT epitaxial layers, suitable for manufacturing large format arrays in 3–5 micron IR region. It was shown (see, e.g., [13,20]) that gallium arsenide substrates can be used for growth of large area epitaxial layers applicable for manufacturing of high quality IR detectors. Still, the structure perfection of these layers is poorer compared to the analoguous ones grown on CdZnTe substrates. Nevertheless here it is shown that MCT heteroepitaxial layers grown by MBE are suitable for manufacturing of large area arrays for 8–12 lm wavelength range with characteristics of acceptable quality.
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growth procedure on 2–3 in. GaAs wafer level. This equipment still can be used for epitaxial MCT material growth on different substrates with an automatic system controlling the technological process parameters and the layer quality in situ [21]. This system provides precise maintaining conditions of the buffer layer and MCT film growth process on GaAs substrates. Automatic ellipsometer used allows to control the thickness changes of layer composition and to maintain it constant with high accuracy, correcting the molecular sources temperature.
3. Diode properties In the grown and annealed p-type HgCdTe MBE epitaxial layers the 4 288 focal plane arrays with 56 43 lm pitch and 28 25 lm n–p-type photodiodes were manufactured similar to the procedure described in [22]. The photodiodes were obtained by boron implantation with particle energies within E 50–120 keV. The topology of the 4 288 array is shown in Fig. 2. Fig. 1. (a) Transverse section of multilayer MCT heterostructure. Right-hand side: change of the band gap for different layers. (b) MCT heteroepitaxial layer profile grown by MBE technology controlled by high-speed ellipsometer.
One of the most important parameters of MCT layers is the composition uniformity across the film area. For FPA operating in the 8–12 lm spectral range the composition changes should not exceed the value Dx < 0:001 across the array area, which, e.g., for a 256 256 array with pitch of 40 lm is about 10 mm. To provide the chemical and the thickness uniformity of epitaxial MCT layers across the wafer diameter there were designed special molecular sources with practically constant (during long time processes) molecular flows. To know the subsequent changes of flows at decreasing the materials in crucibles it was possible to correct the sources temperature for maintaining stable molecular flows [20]. MBE equipment was designed and manufactured with possibility to control the MCT layer
Fig. 2. Topology of 4 288 array.
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Dark currents at V 100–150 mV reverse bias chosen for the hybridization procedure diodes in the arrays with kco 11:8 0:15 lm as a rule did not exceed the values of Id 10–15 nA and the zero bias resistant-area product R0 A for them was within the values R0 A 15–20 X cm2 . The average R0 A values for array elements within the wafer were R0 A 6 X cm2 . For such reverse biases the main contribution to the nþ –p-junction dark current manufactured in MBE grown heterostructures with concentrations of p-type layers within p77 ð5–10Þ 1015 cm3 is from diffusion, generation–recombination (G–R) and trap assisted tunneling processes [19]. In Fig. 3 the typical reverse bias dark current, differential resistance dependencies, and also re-
Fig. 3. (a) Typical dependencies of dark current and dynamic resistance for one of the MCT MBE-grown diodes (kco ¼ 11:8 lm) versus bias voltage; (b) typical relative response of three photodiodes from different parts of 4 288 photodiode array.
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sponsivity spectra of the diodes from different parts of one of the arrays with kco 11:8 lm versus IR wavelength at an operating temperature T ¼ 78 K are presented. One can see rather good photoresponse homogeneity spectra for such MBE, grown on GaAs (0 1 3) substrates, HgCdTe diodes.
4. CCD silicon readouts The primary function of a readout device for IR array is to provide an IR detector charge to voltage conversion, integration of the electrons generated in a photodetector, permission to perform some preliminary treatment of the signals (e.g., skimming, partitioning, amplification and time multiplexing of signals) from the detectors in the array [23], to a much smaller number of outputs from, as a rule, cold zone. In the case of a multiraw linear array, used in scanning mode, time delay and integration (TDI) function should be included to improve the performance of the array. Of course, IR readout electronics should not limit the performance of the detector in the array. Present IR FPAs for 8–12 lm spectral region are facing the problem of large charge integration implying a large charge integration capacitor (because of large background flux at T P 300 K). Thus, the background signal suppression should be used and this function must be performed in a short time compared with a total integration time. The performance requirements for IR FPAs are highly varied with respect to wavelength region, background photon flux, operating temperature, dynamic range, noise, readout rate, power dissipation, detector bias, and some other parameters. The performance of the IR FPAs is also to a large extent determined by the charge stored in the input stage of the signal processor. There are several possible main types of architecture and circuit approaches for readout electronics (see, e.g., [1,2,23,24]). Here were chosen CCD-type circuits because of the possibility to realize the lower level of noise, compared to CMOS-type circuits in spite of the need to use for circuits manufacturing the specific production line. Though the integration possibilities are less than those of CMOC lines, the design rules 2.0 lm used
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here were enough to get all the functions needed in producing ROICs with pitch of approximately 45 lm in PV arrays for which they were designed and manufactured. Another reason for the CCD approach is connected with the best possible solution for improved performance when the TDI concept is used and more flexibility of operating conditions due to the higher number of external biases and clocks required (see, e.g., [2]). For CCD readout devices manufacturing here was used a standard silicon process with two polysilicon gate levels and one metal level, which combines n-channel MOS transistors on the same wafer. The four-inch boron-doped p-type h1 0 0i Si wafers with resistivity of 10–20 X cm were taken for the process. The circuits under consideration consist of MOS transistors with gates from first and second polysilicon level and CCD cells with buried and semi-buried channels. The direct injection transistors are designed as MOS-transistors with induced channel with first polysilicon level gates. The under-gate dielectric is a thermally grown SiO2 layer with the thickness of about 400 and threshold voltage of approximately 0.3 V. A To achieve the suppression of the useless currents prior to CCD multiplexing, several possible solutions exist. Among them are: reduction of the incoming photon flux by narrowing spectral band and field of view (FOV) of the detector; reduction of integration time (at the price of lower signalto-noise ratio); oversampling (multiple detector signal read out during one sampling); design various circuits (subframe readout, DC level subtraction, antiblooming, charge partitioning, charge skimming, in-pixel current memory cell, which enables PV direct current suppression), etc. Here among the available solutions to achieve background suppression in CCD ROICs were chosen [25] the classical charge skimming and partitioning functions, when only a part of charge according to the background is subtracted from the integrated charge packet or a fraction of the integrated charge is transferred to CCD, respectively. 4.1. Unit cell electronics Unit cell electronics is the most important part of the readout device and should provide perfect
bias control, high linearity and low noise performance. There exist several possible solutions [1,23,24]. Among them to satisfy the requirements of FPA with PV HgCdTe detectors for operation at relatively large backgrounds there were chosen the unit cells with direct injection (DI) to improve the coupling between PV detector and CCD signal processor. The scattering values of threshold voltages of the input transistors were within DV ¼ 7 mV, and the nonlinearity of transmission characteristics was less than 2%. Special procedure to control these parameters at T ¼ 300 K at wafer level was developed. Here the multiplexers were designed according to CCD technology with buried channel. To simplify the external control circuits the CCD cell with asymmetric potential well is used (with two or one and a half phase control). The storage charge region is created by phosphorus ion implantation into the under-the-gate region from polysilicon first level. To fabricate the barrier regions under the gates from polysilicon second level there is used second boron implantation, which compensates the part of introduced phosphorus. The resulting depth of the potential well for information charge storage is about 5 V, and the multiplexer charge capacity Q is about Q 2:4 pC. 4.2. TDI function Displacement register of TDI with four inputs of information charge is also designed as CCD cells with asymmetrical potential well. To increase its charge capacity there is used the technology of ‘‘semi-buried’’ channel, which differs compared to buried channel with the potential at the barrier gate. In the case of ‘‘semi-buried’’ channel the charge capacity regions under the first polysilicon level are manufactured by phosphorus ion implantation at the same time with manufacturing the capacity regions in multiplexer, and in the barrier region there is executed the addition boron implantation, that increases the depth of the potential well up to U 8 V. The charge capacity of the TDI register output bit is about 2.4 pC per channel at an output signal voltage of U ffi 5 V. With partitioning mode included it is about 6.4 pC for unit cell, and it is about 10.0 pC with skimming
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Fig. 4. An example of CCD cell operation with four stages TDI function.
and partitioning modes switched on both for fourand two-phases clock pulses CCD ROICs. The example of CCD cell operation with four stage TDI function is shown in Fig. 4 for ROIC driven with four phase clock pulses. Here are shown the signal amplitudes from one, from the sum of two, three, and four diodes, respectively. 4.3. Charge skimming and partitioning modes Different operation modes of the CCD readout circuit are shown in Fig. 5 schematically. High intensity of background radiation and long integration time (particularly in the case of PV detector low R0 A product value for long wavelength applications and large background fluxes) can lead to the overflow of accumulation capacity. In this case it is necessary to use the skimming mode or partitioning mode, or skimming and partitioning modes simultaneously according to the userÕs requirements. To maintain this feature of the readout device here several elements are added into the input circuits. There are skimming/partitioning gate G1, CCD transfer control gate G2, capacity C2 (see Fig. 5), skimming/antiblooming transistor for extraction of the charge excess. The electrodes C1, C2, G1, and G2 are pointed out only in Fig. 5a. The voltages UC1, FPS, UC2, and F0 at corresponding electrodes C1, C2, G1, and G2 are shown also in Fig. 5. When skimming mode is applied, a constant portion of charge according to the background
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flux is subtracted from the integrated charge packet. In this case a constant voltage is applied to skimming gate G1. The value of this voltage is lower than the voltages applied to gates C1 and C2. In the case of using partitioning mode only a fraction of the integrated charge is transferred to the CCD, the partitioning ratios can be changed according to the userÕs requirements. In partitioning mode electrodes C1 and C2 are connected together and direct voltage of some level is applied to them (in Fig. 5c it is a voltage V 4 V practically used here). The pulse voltages are applied to partitioning gate G1, CCD control gate G2 and extraction transistor gate (not shown here). At integration time period T the accumulation of signal charge takes place into capacitor C1 and C2. During the integration processes to partitioning electrode G1 is applied the high potential, which provides free charge flow from one capacitor to another and also equalizing these capacitance potentials. Then the channel between them is switched off and full signal charge is divided between two capacities proportionally to their values (both information and noise charges). If one applies to electrode C2 the direct potential lower than to electrode C1, an amplitude Ups of pulse Fps equals direct potential C2, it is possible for part of the input charge to be subtracted and another part of charge to be divided proportionally to capacities C1 and C2. This is a skimming/partitioning mode. Applying skimming and partitioning modes leads to noise enhancement of the FPA but allows to enhance its dynamic range, e.g., to extend the application range of FPA to higher background temperatures, higher FPA operating temperatures, and longer cutoff wavelength regions. The additional noise that this technique provides, depends much on the gate noise potential and at well stabilized direct voltage (noise potential lower than 100 lm) it does not exceed 1–2% compared to other noises [25].
5. Linear array manufacturing At the diode array manufacturing one of the primary problems is the problem of producing of
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Fig. 5. Different operating modes of the input circuit of the CCD silicon readout. (a) Operating mode without skimming and partition. 1––accumulation of the input charge; 2––insertion of the charge into 16-bit CCD multiplexor. (b) Operating mode without skimming and partition. Integration time is regulated by voltage at FPS gate. 1––accumulation of the input charge; 2––restriction of the accumulation time by voltage at FPS gate; 3 – insertion of the charge into 16-bit CCD multiplexor. (c) Operating mode with partition. 1––accumulation of the input charge; 2––charge partitioning; 3––insertion of the partitioned charge into 16-bit CCD multiplexor and removing of the excess charge (to drain). (d) Operating mode with skimming and partition. 1––accumulation of the input charge; 2–– charge skimming and partitioning; 3––insertion of the partitioned charge into 16-bit CCD multiplexor and removing of the excess charge (to drain).
passivation layers to MBE MCT layers with high characteristics at the semiconductor-dielectric
boundary. MCT surface coating should satisfy at least the following requirements:
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• low temperature of formation (less than 100 C); • low built-in charge surface density (6 1010 cm2 ); • good adhesion quality which is stable at different technological processes; • time and thermal treatment stability. As the basic dielectric coating, which satisfies the above mentioned requirements, here was chosen the low temperature deposited silicon dioxide (deposition temperature T 100 C). But low temperature deposited SiO2 actively interact with atmosphere moisture. It leads to accumulation of positive charge up to values of about 1012 cm2 during several weeks. Therefore, one cannot use this type of dielectric for MCT as the only one passivation layer. For elimination of the possible atmosphere moisture influence here was used the additional dielectric layer, which is silicon nitride, that was formed at temperature T 60 C by plasma-chemical reaction deposition procedure over the silicon dioxide layer. Assembling of 4 288 arrays, which include the photodiode linear arrays and silicon CCD readout circuits, was carried out by the method of cold welding (at room temperature) process of twolayer indium bumps preliminary deposited through two different photomasks at different technological conditions on photodiode arrays and silicon ROICs. The truncated pyramidal In bumps height was about 12 ¼ 6 + 6 lm (two layers of indium characterized relatively small indium grains in bottom layer) with ground dimensions about 17–20 lm, and about 12 lm at the top. With such type of In bumps during the hybridization process, when the tops of In bumps at diode array and silicon circuit are touching each other, the plastic yielding and cold welding take place at the top layers of In bumps. The bottom layers of In bumps are practically not deformed, as the pressure arising at upper layers is not sufficient to overcome the breaking point of lower In bump layers. The use of two-layer In bump technology allows to reduce pressure to MCT surface during the hybridization process. In such a procedure the pressure used during the hybridization process does not exceed 0.3 kg/mm2 on the MCT surface, which is about five times lower than the critical one for MCT
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diodes degradation beginning (Pcrit ¼ 1:7 kg/mm2 at T ¼ 20 C [26]).
6. FPA properties Because of the TDI function from four photosensitive diodes in the chain the output information from 288 channels is formed from 1152 sensitive elements. The output 288 information signals are grouped by 18 channels and were brought out by 16 analog outputs at maximum frequency of 2 MHz. Some back-side illuminated arrays properties were investigated at T ¼ 78 K. 4 288 FPA detectivities with skimming mode included at integration time sint ¼ 6 ls at T ¼ 78 K, and background temperature Tb ¼ 295 K were in the range of Dk ffi 9 1010 –1.8 1011 cm Hz1=2 / W for several arrays tested. The sensitivity histogram of one of the arrays with Dk ¼ 1:81 1011 is shown in Fig. 6. In this array the number of defect elements (the value of detectivity Dk is less than 2.5 1010 cm Hz1=2 /W) was equal to 9 pixels with no dead elements. The presence of defect elements and relatively large standard sensitivity and Dk deviations are connected to local microinhomogeneities presented in these MBE fims grown on
Fig. 6. Channels sensitivity (4 pixels in each channel) histogram for one of the MCT LWIR 4 288 arrays manufactured on GaAs substrate. Sensitivity mean value is equal to 2.87 107 V/ W, sensitivity standard deviation is equal to 27.1%, TBB ¼ 500 K, 2h1 ¼ 64, 2h2 ¼ 32.
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Table 1 Some parameters of one of the 4 288 TDI LWIR MCT array Parameter
Measured value
Sensitivity max wavelength, lm Cutoff wavelength, lm Mean sensitivity, V/W Sensitivity standard deviation, % Mean detectivity, Dk , cm Hz1=2 W1 Dk standard deviation, % Number of defect elements, pixels
9.95 0.15 11.80 0.15 2.87 107 27.1 1.81 1011 31.5 9
Acknowledgements The authors are very grateful to Yu.G. Sidorov and S.A. Dvoretski for supplying the MCT layers on GaAs substrates.
GaAs substrates. Some parameters of one of these arrays are presented in Table 1. The sensitivity Sk data were used for detectivity Dk evaluation according to the expression [27]: Dk ¼
Sk 1=2 1=2 A ðDf Þ ; Vn
arrays was not rather good (standard deviation about 30%), the detectivities obtained are high enough to be used in different IR instrumentation.
ð1Þ
where Vn is the noise level (in this case at the FPA output), A is the pixel area, and Df is the frequency bandwidth, which in case of TDI mode is equal to ð2sint Þ1 , where sint is the integration time. Because of the large field of view of the testing system (cold shield plane angle in horizontal plane is 2h1 ¼ 64 and in vertical plane 2h2 ¼ 32) and lack of the short wavelength filter the integration time used did not exceed sint ¼ 6 ls, though in the systems used it can be regulated in wide range in dependence of background fluxes and the signal level.
7. Conclusions MCT 4 288 heteroepitaxial linear diode arrays for LWIR applications with CCD silicon readouts were designed, manufactured and tested. MBE grown MCT heteroepitaxial layers on (0 1 3) GaAs substrates used in these hybrid arrays have cutoff wavelength kco 11:8 lm at T ¼ 78 K. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bump technology. With skimming mode used for 4 288 MCT n–pjunctions, the detectivity was Dk ffi (0.9–1.8) 1011 cm Hz1=2 /W at background temperature Tb ¼ 295 K. In spite of the fact that homogeneity of the
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