- Email: [email protected]
Metallization in microelectronics
Thin Solid Films. 45 (1977) 69 84 ~ Elsevier Sequoia S.A., Lausanne--Printed in the Netherlands
69
METALLIZAT1ON IN M I C R O E L E C T R O N I C S * P. B. GHATE, J. C. BLAIR AND C. R. FULLER Semicomhwtor Research anti Engineering Laboratories, Texas Instruments, Inc., Dallas, Texas 75222 (U.S.A.) (Received March 31, 1977: accepted April 8, 1977)
Continued improvements in the design and fabrication of semiconductor devices have led to the introduction of medium and large scale integration of microcircuits. These advances have placed severe demands on metallization techniques, requiring metal contacts to shallow junction devices and definition of metal interconnections that are closely spaced and of a narrow pattern. Aluminum is the most widely used metal in microelectronics for providing the necessary contacts and interconnections. The contact resistance of the Si-A1 interface is sensitive to surface preparation, the vacuum ambience of the AI film deposition and contact sintering. Controlled contaminations, such as H:O, CO and 0 2, have been introduced during the AI film deposition in order to determine their effects on AI/Si contacts. Extensive studies have shown the interdependence of the film deposition parameters, the physical properties of the A1 films and the dominant failure mechanisms, such as electromigration, that limit the reliability of integrated circuit interconnections. For high speed very shallow emitter-base junction devices, A1 in silicon contact windows can penetrate to the junction during sintering and can cause leakage. Solutions to this problem include the use of A1 + Si films, PtSi contacts with a barrier layer (e.g. Ti : W) and AI or Au conductors. Metallization must be suited to all the device processing steps beginning with contact sintering, device packaging, testing and also the operating conditions. Highly complex large scale integrated circuits require multilevel interconnections. A two-level metallization scheme (Al/insulator/Al) and its application are presented. Future trends in metallization processing are also discussed.
I. INTRODUCTION
Microelectronics covers a broad spectrum of devices from discrete diodes and transistors to the most complex integrated circuits. Metallization requirements are so diverse that no unique metailization solution satisfies all the requirements 1-6. The metallization process must be suited to the device performance requirements (ohmic and Schottky contacts), the operating temperature range, the packing density (narrow lead widths and smaller spacings between leads), the packaging *.Paper presented at the International Conference on Metallurgical Coatings, San Francisco, California, U.S.A., March 28-April 1, 1977.
70
P.B. GHATE, J. C. BLAIR, C. R. FULLER
(bonding to Au or Al wires, gang bonding to Au bumps, plastic packages, hermetic packages with glass sealing operations), the reliability (long mean time to failure (MTF) under normal operating conditions with failure rates of 0.1 to 0.2 per million device hours) and cost effectiveness. Continued improvements in circuit design and fabrication led to medium scale integration (MSI) and large scale integration (LSI) of microcircuits. Higher device packing density, higher speed and reduced bar size have been the primary driving forces in this evolution. The progress achieved in the complexity and packing density of LSI circuits over the last 10 years can be seen from the photographs of typical circuits shown in Fig. I. These advances have placed severe demands on
1970
1976
1976
1977
Fig. 1. MOS technology progress.
metallization techniques, requiring metal contacts to shallow junction devices and the definition of closely spaced narrow metal patterns for interconnections. In this paper the discussion will be restricted to metal film interconnections used in silicon planar technology for integrated circuit (IC) fabrication. Aluminum is the most widely used metal for contacts and interconnections in both bipolar and MOS ICs 6' ~. It has a high conductivity, and the films can be vacuum deposited to within 5-10 ~ of the bulk resistivity (2.7 laf2 cm). AI forms low resistive contacts with p- and n-type silicon. The contact resistance of the Si-AI interface has been examined as a function of the silicon surface preparation, controlled contamination (such as H20, 02 and CO) during AI film deposition and contact sintering 8. For high speed very shallow emitter base junction devices, AI penetration in silicon contact windows during sintering can extend to the junction and can cause leakage. Solutions of this problem
METALLIZATIONIN MICROELECTRONICS
71
include the use of A I + S i films 9' l o or PtSi contacts ~1 with a barrier metal (such as T i : W and Mo) and AI or Au conductors 12.13 PtSi layers are formed by sintering vacuum-deposited Pt films on Si contacts in N 2 or air ambience. The effect of sintering ambience on the composition of PtSi layers has been examined by Auger spectroscopy and ion profiling ~4-~ 7. The reliability of aluminum film interconnections depends on the physical properties of the films as they are to be found on finished devices 18-22. Transmission electron micrographs are presented to show that the final aluminum film microstructure depends on the initial film microstructure 22 even after a 15 min, 450°C anneal in N 2. Highly complex circuits require multilevel interconnections 23-25. A two-level metallization scheme (Al/insulator/Al) and its application will be presented. Optical patterning technology is reaching the practical limit for defining narrow interconnections (0.1 mil or 2.5 ~m). With the advances made in electron beam patterning 26-28 and X-ray lithography 29, devices with micron and submicron geometries are feasible, and metallization techniques need to be developed to meet these requirements. 2. METAL--SEMICONDUCTORCONTACTS
Metal-semiconductor contacts are an integral part of the overall interconnection system in ICs. The behavior of electrical contacts (ohmic or rectifying) depends on the silicon surface concentration, the surface cleanliness and the metal-silicon interface reactions. Many metals such as Al, Cr, Ag, Ti, Pt, Pd, Mo, W; HI', Ta and Ni have been examined for forming metal-silicon contacts. A m o n g the metals investigated for contacts, aluminum is the most widely used because it forms low resistive contacts to both p- and n-type silicon and also meets the interconnection requirements. In practice, Si/Al contacts are effected by sintering at temperatures in the 400-550 °C range, forming Al + Si alloy at the interface. High resistive Si/A1 contacts (or poor contacts) are not uncommon in IC manufacturing. Poor metallurgical reaction at the Si-Al interface either due to surface contamination or due to poor metal deposition technique is considered to be the primary cause of this problem. Recently, the influences of (a) surface contamination (or impurities) due either to pre-metallization clean-ups or to residual gas levels in vacuum metal deposition systems and of (b) contact sintering temperatures and ambients on the formation of the Si/A1 contact have been investigated a. Test structures were fabricated on silicon substrates (n-type l0 15 ~) cm 2, I I 1 orientation) processed through boron base and emitter diffusions 2a. The base and emitter diffusion corresponded to surface concentrations of (3-4) x l0 is cm -a and ( 4 - 6 ) x l020 cm - a respectively. After base and emitter windows were opened, the slices were pre-evaporation cleaned in 3 parts of H2SO 4 and 4 parts H 2 0 2 and then rinsed in running deionized water for 15 min. The slices were then dipped in Bell II etchant for a period of 0-10 s, were rinsed in deionized water and were dried for l0 min in refluxing isopropyl alcohol vapor. Prior to the Al deposition, known residual gas contaminants such as H 2 0 , 0 2 and CO were admitted to the vacuum chamber (1.33 x 10-5 Pa (1 x l 0-7 Torr) base pressure) by a controlled leak valve up to a partial pressure of 6.7 x l0 -5 Pa (5 × 10 -v Tort) which was monitored with a U T I 100C mass analyzer. The Si/A1 contacts were
72
P.B. GHATE, J. C. BLAIR, C. R. FULLER
AI L
E
A
k._
~
-"
AI S, iNTERFACE
EQUATIONS
V23
1 ~1
Vl4 I =3Rs
3.
Re=
(
3R s
2Rc"l"3Rs 1
2
J
,I $I
4
V23- V14 2 I CURRENT IN
CURRENT OUT
Fig. 2. A contact resistance test pattern.
effected by sintering at 4 0 0 - 5 5 0 °C in an N 2 ambience. F i g u r e 2 shows a typical test structure. Several h u n d r e d test structures with c o n t a c t areas o f 4.9 x 10 6 cm 2 (0.2 mil x 3.8 rail) were m u l t i p r o b e d . A specific c o n t a c t resistance o f the o r d e r o f (1-2) x 10- 6 ~ cm 2 was o b s e r v e d for all e m i t t e r regions in the 15 22 ~ / [ ] range (see T a b l e I). N o systematic c o r r e l a t i o n between the c o n t a c t resistance a n d the residual gas c o n t a m i n a n t was found. It was c o n c l u d e d that the surface p r e p a r a t i o n a n d c o n c e n t r a t i o n s o f a d d e d c o n t a m i n a n t s in the c h a m b e r at a base pressure o f 1.33 x l0 -5 Pa (I x 10 7 T o r r ) had a l r e a d y affected the silicon surface, f o r m i n g an "'interfacial layer". F u r t h e r a d d i t i o n o f H 2 0 , 0 2 a n d C O to a pressure o f 1.33 x 10 -5 Pa (1 x 10 v T o r r ) exerted no m e a s u r a b l e influence on the g r o w t h o f this interracial layer. Even if the interracial layer thickness increased p r i o r to AI metal deposition, it did not affect the c o n t a c t resistance adversely 8. TABLE l SPECIFIC CONTACT RESISTANCE DATA
Interlace
Si/Al Si/Al Si/AI+Si Si/PtSi
Controlled contaminants
Partialpressure/ Totalpressure
Specific contact
None H20, O2, CO None None
/3 x 10 -7 Torr 7 × 1 0 ~/2×10 6Torr /1.6×10 6Torr
1 1.3 0.3 1.3 I 1.3 0.5
resistance
(10 6 ~ cm 2)
Thecontactareais4.9 x 10 6cmZ(0.2mil × 3.8mil);~hesheet resistivityoftheemittcrrcgionisabout 15 22
n/E3.
METALLIZATION IN MICROELECTRON1CS
73
For most devices, the processing of the Si/A1 contacts with AI-Si alloy formation at the interface is not a serious problem. It must be noted that there is a natural SiO z layer 1-3 nm thick on the silicon prior to metal deposition. Aluminum in a diffusion-controlled reaction reduces the silicon dioxide, forming aluminum oxide. A sintering operation of short duration at elevated temperatures reduces this oxide uniformly at the contact window, leading to uniform AI + Si formation; with a lower temperature and longer duration sintering, A1 penetrates deeply into the silicon at discontinuities in the oxide layer instead of reducing the SiO z layer to permit uniform AI-Si formation. Silicon from the contact windows diffuses into the aluminum films along grain boundaries to satisfy the solid solubility of Si in AI, and precipitates on cooling. Aluminum, in turn, diffuses into the silicon contacts. This alloy penetration is a function of sintering temperature, time and crystal perfection. A wide A1 lead covering smaller contact windows can lead to deep alloy penetration and junction shorting. For devices with shallow emitter-base junctions ( < 1 p.m), alloy penetration can cause junction shorting. Alloy penetration can be impeded by the use ofAl + Si films for interconnections 9' 10 Alternatively, the AI films can be separated from the Si by a barrier metal (such as T i : W ) 12. Electrical contacts to the silicon are readily achieved with PtSi layers ~ The Pt films are vacuum deposited onto silicon substrates and are sintered at temperatures ranging from 400 to 600 °C. The formation of PtSi has been studied by several workers 14-17, and some understanding of the effects of sintering ambience on PtSi formation has been gained with the aid of Auger electron spectroscopy (AES) and ion profiling. PtSi layers are formed by the diffusion of Si into Pt films. Pt and Si atoms react with each other to form PtESi and then PtSi. When hot slices are pulled into room air, Si atoms present on the PtSi surface react to form S i O 2 ( o r PtSiO4). It is this oxide layer that protects the PtSi from dissolution during subsequent platinum stripping in aqua regia ~4. The PtSi layer thickness can vary as a function of the Pt thickness, the Si surface treatment prior to the Pt deposition and the sintering ambience. If the native oxide on the silicon surface is not removed either by dipping the substrate in HF solution or by in situ sputter etching in vacuum prior to Pt deposition, Si diffusion into Pt films is impeded by this oxide layer. Thinner non-stoichiometric PtSi films can result. The PtSi layers formed by sintering in inert (N2) and oxidizing (air) ambients (525 °C, 15 min) have been examined. Depth profiles for Pt, Si, O, N and C were developed using peak-to-peak heights of the Auger transition and sputtering times. In order to compare the Pt and O concentration versus depth into these PtSi layers, the ratios of the peak-to-peak heights of Pt : Si and O: Si were developed and are shown in Fig. 3. It can readily be seen that oxygen is present throughout the PtSi layer (Fig. 3(a)) when it is formed in an oxidizing (air) ambience. The presence of e x c e s s S i O 2 in PtSi layers has been found to affect devices adversely. Figure 3(b) shows the confinement of the SiO 2 layer to the surface of PtSi, thereby permitting a control of the PtSi layer in normal processing. PtSi contacts have been found to be satisfactory for junction depths of less than 1 p.m. The interface resistance of the Si/PtSi contacts has been determined with the test structures described earlier. The specific contact resistance for typical surface concentrations in the emitter regions is of the order of 5 × l 0- 7 D c m 2.
74
P. B. GHATt', J. ('. BLAIR, ('. R. FUI.I.IIR
.fw/~/"'X\~
1. \
1 Pt + Si
/"
,
"
, f'%~-
O5 -/
(a) o o
1L0
1+5
~0
D
1.! ',,+
P| ,. Si
•
•
10 0 5i
"'" . . . . . . . 0
(b)
",L
;2
0, DEPTH ~SPUTTERING TI&~E IN ~,~IN )
Fig. 3. The A u g e r peak-to-peak height ratio vs. the sputtering time for samples annealed in (a) air and (b) N 2. 3. SINGLE-LEVEL INTERCONNECTIONS
Any metallization system for IC interconnections must satisfy certain minimum requirements : (i) it should make good ohmic contacts to both p- and n-type silicon ; (ii) it should be adaptable to practical methods of deposition to provide low resistive interconnection paths (p < 3-10 gfl cm); (iii) it should be adherent to both silicon and silicon dioxide; (iv) it should be patternable in chemicals not reactive with photoresist, silicon and silicon dioxide; (v) it should be compatible with bonding techniques; and (vi) it should be reliable under normal operating conditions. A large number of single metal, bimetal and trimetal combinations have been explored for interconnections, e.g. single metal bimetal trimetal
A1, Cr, W etc. Cr-Ag, Cr-Au, M o - A u , Ti: W - A u etc. T i - P t - A u , T i - P d - A u , C r - A g - A u etc.
For reasons previously stated A1 is the most widely used metal system 6"7' however, bimetal and trimetal sandwiches with Au as the main conductor are also used for interconnections 1z, 13. Au films have poor adhesion to SiO z. Hence in such metallization systems refractory metals such as Mo, T i : W or Ti-Pt provide the necessary adhesion to the SiO 2 and act as a barrier layer between the silicon and gold films. Metal systems other than AI and Au as primary conductors have been used in special applications ; however, these two metals satisfy most microelectronic interconnection needs.
METALLIZATION 1N MICROELECTRONICS
75
Aluminum films are vacuum deposited by several techniques including (i) filament evaporation, (ii) flash evaporation, (iii) induction heating, (iv) electron beam heating, (v) sputtering etc. Electron beam and induction heating tend to dominate the deposition technology because of their ability to deposit high purity Al films to within 5 - l 0 % of the bulk resistivity (p = 2.7 lift cm) at reasonable rates with minimum device damage (MOS devices are sensitive to deposition techniques). Two areas of major interest are (i) metal coverage on Si-SiO 2 steps at the contact windows and (ii) establishing low resistive A1-Si contacts. Step coverage depends on the oxide profiles to be covered, the deposition equipment and the deposition parameters 3°'3~. Substrate heating and some form of slice rotation are highly desirable in order to improve step coverage. Oxide profiles with nearly vertical or reverse slopes are major causes of discontinuity in metal leads after either the metal deposition or metal patterning. A 2 0 - 1 0 0 ~ thinning of the metal film is observed at these oxide steps. Many techniques including novel slice rotation and appropriate biasing of the substrates during sputter deposition of the films have been employed to solve this problem 25. However, the use of a gently sloped oxide profile appears to be the best pragmatic solution to this step coverage problem. The reliability of interconnections depends on the physical and electrical properties of the films as they are to be found on the finished devices (end product). AI films are subjected to several temperature excursions during lead patterning, ohmic contact bake, final assembly and packaging. Microstructure is the single most important film property that undergoes changes due to device processing 4"23. In Fig. 4, we present transmission electron micrographs of AI-I films (deposited on unheated substrates) and AI-II films (substrates held at 200°C during film deposition) before and after a 450°C, 15 min anneal in N 2. These films were deposited at 2 nm s- 1 by electron beam evaporation under nominal v a c u u m ( 1 0 - 6 Torr (1.33 x 10 -4 Pa)). The films were thinned for the transmission studies from their original thickness of 0.85 lam. AI-I films have a smaller grain size than AI-II films. Also microstructural inhomogeneities in AI-I are greater subsequent to anneal than those in AI-II samples. In Fig. 5, transmission electron micrographs of sputter-deposited and thermally evaporated gold films before and after a 450°C, 24 h anneal in air are presented. The average grain size of the Au films prior to anneal is of the order of 0.2 lam. We note that the 450 °C, 24 h anneal does not change the microstructure of the sputtered Au films a2, but that the average grain size of the evaporated Au films increases from 0.2 ~tm to 1.1 ~tm with this anneal. The resistivity of the sputtered Au films was 4.1 ~tl) cm and that of the annealed evaporated Au films was close to the bulk value (2.4 ~tfl cm). Reliability studies on microelectronic circuits have led to the identification of "electromigration-induced failures in thin film conductors" as one of the failure modes. Mass migration under the influence of a direct current is called electro-. migration. Atomic flux (or vacancy flux) is related to current density in the framework of a model proposed by Huntington and Grone 33, and is given by NiD
jj = ~ - Z
,
epj
76
P.B. GHATE, J. C. BLAIR, C. R. FULLER
(a)
(b)
(c)
~d)
Fig. 4. M i c r o g r a p h s o f A l - l a n d A l - l l film> bcforc and after a 15 min anncal at 450 C : ( a ) Al-lbcl\)rc anneal; (b) AI-I after anneal; (c) AI-II before anneal; (d) AI-I! after anneal. The scale bar is 1 jam.
whereji is the flux of metal ions, N i the local density of ions, D ( = D o exp( - Q/k T) ) the diffusion coefficient, Z*e the effective charge on the ion,./the current density and p the film resistivity. The above expression, though developed for a bulk specimen, is assumed to be valid for films where grain boundary diffusion dominates over ion migration. A non-vanishing divergence of the atomic flux (vacancy flux in the opposite direction) leads to void formation. Temperature gradients and structural inhomogeneities (an abrupt change in grain size, a triple point of grain boundaries, a precipitate) are primary causes leading to non-vanishing divergences of vacancy
METALLIZATIONIN MICROELECTRONI('S
77
(a)
(b)
(c)
(d)
Fig. 5. Micrographs of sputtered and evaporated Au films before and after a 24 h anneal at 450 :C: (a) sputtered Au, before anneal; (b) sputtered Au, after anneal; (c) evaporated Au, before anneal; (d) evaporated Au, after anneal. The scale bar is 0.1 I.tm. flux a n d the resulting void f o r m a t i o n . These voids g r o w to develop open lead failures. Expressions have been d e v e l o p e d for the M T F o f film c o n d u c t o r s subjected to high current stress: MTF =
Aj-" exp(Q/k T)
where A is a p a r a m e t e r d e p e n d i n g on the s a m p l e g e o m e t r y a n d the physical characteristics o f film a n d substrate, j is the c u r r e n t density, n an exponent, Q the
78
1,. B. GHATE, J. ('. BLAIR, C. R. FULLER
activation energy, k Boltzmann's constant and T the average temperature of the conductor. For AI conductors the reported values of Q and n lie in the ranges 0.6+0.2 eV and 1 7 respectively. The M T F has been observed to improve with increase in grain size if the variance of the grain size is held constant. The M T F decreases with increasing variance of the grain size distribution if the grain size is held constant. The grain size distribution is important because an abrupt change in grain size between one interconnection region and another leads to vacancy flux divergence. If the grain size is of the order of the lead width, a single grain boundary can span the lead width and can be a location for void formation and an open lead failure. Grain size differences at particular lead locations also provide sites for void growth. Experience suggests that structurally homogeneous films are desirable with increasingly smaller geometry interconnections (2-6 lam). Furthermore, optimization of the grain size with respect to lead width needs to be considered. Gold film resistors 6.5 lam in width, 0.8 lam in thickness and 1125 ~tm in length were subjected to high current stress in 150 ~'C air ambience. MTF data as a function of current density j are presented in Fig. 6. We note that the M T F is longer for evaporated Au films with larger grain size than for sputtered films with a small grain size. In the same figure the M T F data for AI conductors are presented for comparison. In certain applications where high current density requirements exist, Au film interconnections are preferred.
lOO( 50(
=. loc
\
5o
O
I
1.5
2!0
Z.15
3.1
315
4.10
5
CURRENT DENSITY (106 A/cm21
Fig. 6. The M T F vs. current density for Au and AI film resistors: curve 1, evaporated Au films ( M o - A u ) ; curve 2, annealed sputtered Au films (Ti : W - A u ) ; curve 3, unannealed sputtered Au films (Ti : W - A u ) ; curve 4, large grain AI films with protective coating (r.f. silane SiO2, silane SiO2).
4.
TWO-LEVEL INTERCONNECTIONS
Improvements in the design and fabrication of complex MSI and LSI circuits require the use of multilevel (at least two) interconnections to achieve higher
79
METALLIZATION IN MICROELECTRONICS
T !
|lldl
I,q
V
~|
.--__..q
L
Fig. 7. The impact of two-levelinterconnections on a 256-bit TTL RAM.
packing density and speeds and a reduced bar size. The impact of two-level interconnections on the design and performance of an MSI circuit is shown in Fig. 7. Some metal-insulator combinations employed to achieve multilevel interconnections are: (a) AI/SiO2/AI 3"23-2L34, (b) AI/AI2Oa/A1 35-37, (c) M o Au-Mo/SiOz/Mo-Au and (d) T i W - A u - T i W / S i O 2 / T i W - A u 13. Aluminum and gold films provide the desired low resistive interconnections, and SiO2 o r A l x O 3 provide the necessary insulation between layers. The primary components of a two-level interconnection system are (a) crossovers (a second-level lead crossing the first-level lead separated by an insulator (SiO2) layer) and (b) vias (locations'for level-to-level contact through a hole in the insulator). The topography of the oxide layer covering first-level leads (e.g. reentrant folds developed over vertical edges of first-level leads) has been a major factor affecting the integrity of crossovers because of poor metal coverage on these oxide steps. The anodic two-level A1/AI2OCAI system, which produces an almost flat topography for the second-level metal, was introduced to solve the crossover problem. In the fabrication of etched two-level interconnections, the desirability of sloped first-level leads to generate smooth oxide contours for second-level metal coverage has been well recognized. Hillock formation on the first-level leads has also been a major concern in fabrication of interlevel short free crossovers. Poor photoresist coverage over hillocks can permit insulator removal near the hillocks
80
P. B. GHATE, J. C. BLAIR, C. R. FULLER
during via etching, providing a shorting path between levels at crossovers. Hillock formation results from mass migration due to compressive stresses acting on the film when it is heated for photoresist operation, contact sintcring, insulator deposition etc. Hillock density can be minimized by use of large grain films. The addition of impurities such as Cu to A1 suppresses hillock growth and increases electromigration resistance 21. Copper-doped AI films can be deposited by several techniques : flash evaporation, dual electron guns or filaments, magnetron sputtering etc. We have found that copper concentration control is readily maintained by depositing from an r.f. induction-heated source. A1 + C u films with 1-2 at. o~ of Cu at 3 3.5 la~ cm resistivity are readily obtained. The thickness of first-level metal leads is dictated by the current density and the metal coverage requirements on oxide steps at contact windows. An AI film 1-1.2 ~tm thick is used for first-level leads. Insulator films considerably thicker than the first-level leads have been suggested to ensure insulator integrity between levels. Thicker insulator films pose internal stress-cracking problems. This problem can be eliminated by the use of thinner A1 + Cu film conductors without loss of reliability. Sloped first-level leads, realized by optimizing photoresist and etching operations, provide the desired insulator profiles for second-level coverage on steps. Several dielectrics such as sputtered quartz, chemically vapor-deposited silicon dioxide, anodic oxide, silicon nitride, polyimide and a combination of sputtered and chemically vapor-deposited oxides have been explored for multilevel insulators. Dielectric selection for multilevels is governed by several factors such as pinhole density, coverage at metal edges, internal stresses, via etching, reliability etc. For most applications chemically vapor-deposited SiO 2 provides satisfactory insulation for multilevel interconnections. The etching of vias in insulators is a critical step. Proper process controls must be established to achieve a reproducible process. An AI A1 interface resistance of the order of 10-v ~ cm 2 is observed in clean vias. Incomplete removal of oxide in vias produces very high interface resistance (about 10 -2 ~ cm2), resulting in nonfunctional integrated circuits. Sputter etching of vias prior to second-level metal deposition appears to be one of the solutions that overcome the high resistance via problem. Continuity of the second-level leads is no longer a problem with smooth oxide contours over the edges of sloped first-level leads. Test structures 23 consisting of long via chains and a number of crossovers (serpentine metal patterns crossing over each other) are used to optimize two-level interconnection processes and to determine interconnection yields. The results of such experiments are useful in developing the circuit design layout rules. In Fig. 8, scanning electron micrographs of vias and crossovers for an A I + C u / S i O z / A I system are presented. A metallization process scheme useful for LSI can be as follows : PtSi/Ti : W-Al + Cu/SiO2/Al where PtSi forms the ohmic and Schottky contacts, T i : W acts as a barrier layer, A1 + Cu acts as a first-level conductor, SiO z serves the purpose of an interlevel insulator and AI acts as a second-level conductor. Such a metallization process has been applied in the fabrication of two-level interconnections on LSI circuits.
Fig. 8. Two-level interconnections on an IC: (A) circuit; (B) crossover; (C) via; (D) via cross section.
O~
z a
©
Q -4
O r~ r" rrl
7~
Z
-]
U"
-] >
82
P. B. G H A T E , J. ( ' . B L A I R , ( ' . R. F U L L E R
5,
BONDING
AND ASSEMBLY
Major advances are being witnessed in the chip bonding technology. Thc bonding of gold wires to A1 pads one step at a time is being replaced by automated wire bonding. The reliability of gold ball bonds attached to AI pads has been problematical because of Au-AI intcrmetallic formation 38. Beam lead processing eliminates this problem by attaching gold beams to gold pads on 1Cs. Competitive cost pressures have led to the development of "'gang bonding" 3 9 . 4 0 . Here gold or copper bumps are formed on a passivated slice at the bond pad locations. A barrier metal such as Ti, Pt, Cr, Cr + Ag etc. is deposited on the A1 pads of conventionally metallized ICs and gold or Cu bumps (10 25 lam in height) are formed. Chips on these slices are separated and carried on an adhesive tape together with a tape of tin-plated copper leads for fluxless contact soldering by.a gang lead bonder in a single step. The gang bonding process promises high yield and high throughput. The reliability of lead attachment to bumps will depend strongly on the effectiveness of the barrier layer between the gold bumps and the aluminum pads. The adhesion of these bumps to chips will be one of the parameters that will determine the MTF oflCs. Metallization processes for interconnections need to be compatible with advanced bonding techniques. 6.
FUTURE
TRENDS IN METALLIZATION
The increasing demand for high performance (speed) and high density (large number of components, e.g. diodes, transistors, resistors and capacitors) LSI circuits is being met by new device dcvelopment, circuit designs and by continuous shrinkage of geometrical dimensions. Metal interconnections for some LSI circuits
0.6 0.4 fOPTICAL
-- 3OO
IMAGING
2OO
0.
150
loo ~
0.
6O ~ N E_BEAM.r. / / " " X-RAYS
3O
z ~ 1 ~
z0.0,
4K
MEMORY
20 15
0. 01 '
'
'
' I~70.
'
'
'
'
1475'
i
i
]~BO
i
i
i
YEAR
F i g . 9. The trend in bar size and minimum geometry for complex 1Cs.
I
METALLIZATION IN MICROELECTRONICS
83
occupy a significant (almost 50 ~ ) portion of the bar area. Longer interconnection paths contribute to signal propagation delays, lowering the circuit speed. Multilevel interconnections aid in the reduction of bar size and in improving the circuit performance. Figure 9 shows the trend in the reduction of linewidths and spacings over the past 10 years. Optical patterning techniques are reaching their physical limits as linewidths and spacings are approaching the wavelength of light that is used for photoresist exposure. Practical limits in today's IC manufacturing environment appear to be 0.1 mil (2.5 lam) lines and spaces. The trend in increasing the device packing density by reduction of linewidths and spacings will continue through developments in electron beam technology and X-ray lithography for patterning submicron geometries 26-29. Use of electron beam (or X-ray) patterning for LSI circuit fabrication will require re-evaluation of present metallization practices. The formation of thousands of small metal-silicon contacts will be a challenging problem. The specific contact resistance for typical base surface concentrations is of the order of 10-5 f~ cm 2. The contact resistance for a 1 lam 2 contact may be as high as 1 k~. This interface resistance will depend on the silicon surface preparation. The metal-silicon reaction at the interface will be highly sensitive to the impurities and the oxide layers formed in the contacts prior to metal deposition. Characterization techniques capable of characterizing the surfaces in these small contact areas must provide the understanding necessary to optimize the processes. It appears that the current densities in these submicron wide IC interconnections will be of the order of 1 x 10 6 A cm -z (the conventional LSI circuit current density is 2 x 105 A c m - z maximum). Small grain size films desirable for submicron lead definition offer a large number of grain boundary diffusion paths for electromigration. Reliability studies on small grain metal film interconnections will be needed to set current density design limits. Microstructure control of metal films by deposition process optimization will be a key factor in fabricating reliable interconnections. Other parameters that need to be controlled are metal coverage on oxide steps, film thickness uniformity and surface roughness (hillock formation). Stringent process controls will be needed in metal removal steps. Dry processing such as sputter etching, ion milling and plasma processing may provide a better control in metal removal than the conventiorial wet etching process' does. Finally, it must be noted that metallization is only a part of the IC fabrication process, and it has to be compatible with the rest of the IC processing. Furthermore, metallization is one of the last critical steps to be performed in LSI circuit fabrication, and considerable cost has already been incurred in slice processing prior to this step. It is highly desirable to establish well-characterized metallization processes. ACKNOWLEDGMENTS
It is a pleasure to acknowledge the technical support by Willie McCandless, Howard Schindler, Robbie Skinner and Naomi White. We wish to thank Art Wilson for helpful discussions on patterning and Gary McGuire for the Auger analysis.
84
P. B. GHATE, J. ('. BI,AIR, ('. R. FULLER
REFERENCES
1 J.A. Cunningham, Solid-State Electron., 8 (1965) 735. 2 M.P. Lepselter, Bell Syst. Tech. J., 45 (1966) 233. 3 H. Sello, in B. Schwartz (ed.), Ohmic Contacts to Semieomh~ctors, The Electrochemical Society Softbound Symposium Scries, New York, 1969, p. 277. 4 J.C. Blair and P. B. Ghate, Weseon Teeh. Papers, 5, Wcscon, Los Angeles, Calif., 1971, Session 2, paper 1. 5 R . W . Wilson and L. E. Terry, Weseon Teeh. Papers, 5, Wescon, Los Angeles. Calif., 197 I, Session 2. paper 2. 6 G.L. Schnable and R. S. Keen, Proc. IEEE, 56 (1969) 1570 : IEEE Trans. Electron Devices, 16 (1969) 322. 7 A.J. Learn, J. Eleetroehem. Sot., 123 (1976) 894. 8 J.C. Blair and P. B. Ghatc, J. Vae. Sei. Technol., 14 (1977) 79. 9 P . A . T o t t a a n d R . P. Sopher, I B M J . Res. Dev, 13(1969) 226. 10 G.J. V a n G u r p , Appl. Phys. Lett.,19(1971)476:J. Appl. Phys.,44(1973) 2040. t 1 M . P . Lepselter and J. M. Andrews. in B. Schwartz (ed.), Ohmic Contacts to Semieonductor,~, The Electrochemical Society Softbound Symposium Series, New York, 1969, p. 159. 12 U.S. Patent No. 3,833,842 (March 9, 1976), to J. A. C u n n i n g h a m and C. R. Fuller. 13 J. A. Cunningham, W. R. Gardner and S. J. Wood, in B. Schwartz (ed.), Ohmic Contacts to Semiconductors, The Electrochemical Society Softbound Symposium Series, New York, 1969, p. 299. 14 J . M . Morabito and M. J. Rand, Thin Solid Films, 22 (1974) 293. 15 S. D a n y l u k a n d G . E. McGuire, J. Appl. Phys.,45(1974) 5141. 16 T.J. Kingzett and C. A. Ladas. J. Eleetroehem. Soe., 122 (1975) t 729. 17 R.J. Blattner, C. A. Evans, Jr., S. S. Lau, J. W. Mayer and B. M. Ullrich, J. Electrochem. Sot., 122 (1975) 1732. 18 J . R . Black, IEEE Trans. Electron Devices, 16 (1969) 338. 19 J.A. Blech and E. S. Meieran, Proe. 8th Annu. S)'mp. on Reliability Physics, IEEE, New York, 1970, p. 243. 20 J.C. Blair, P.B. G h a t e a n d C . T. Haywood. Appl. Phys. Lett.,17(1970)281. 21 F . M . D'Heurle and R. Rosenberg, Ph3w. Thin Films, 7 (1973)257 310. 22 L. Braun, Microeleetron. Reliab., 13 (1974) 215 228. 23 P.B. Ghate, Failure mechanism studies in multilevel metallization systems, Rome Air Development Center, Air Foree Systems Command, Gr!ffiss Air Force. New York, Final Teeh. Rep. R A D C TR-71186, September 1971 24 C.J. Santaro and D. L. Tolliver. Proe. IEEE, 59 ( 1971 ) 1403. 25 J.L. Vossen, G. L. Schanble and W. Kern, J. Vac. Sci. Teehnol., 11 (1974) 60. 26 G.L. Varnell, D. F. Spicer, A. C. Roger and R~ D. Holland, Extemled Abstr. Electroehem. Sot., 74 1 (218) (1974) 510. 27 E.I. Gordon and D. R. Herriott, IEEE Trans. Electron Deviees, 22 (1975) 371. 28 F . F . Fang, M. Hatzakis and C. H. Ting, J. Vac. Sei. Technol., 10 (1973) 1082. 29 S.E. Bernacki and H. 1. Smith. 1EEE Trans. Electron Devices, 22 (1975) 421. 30 1. A. Blech, Thin Solid Films, 6 (1970) 113. 31 T. Yanagawa and I. Takekoshi, IEEE Trans. Electron Devices, 11 (1970) 964. 32 J.C. Blair, C. R. Fuller, P. B. Ghate and C. T. Haywood, J. Appl. Phys., 43 (1972) 307. 33 H.B. Huntington and A. R. Grone, J. Phys. Chem. Solids, 20 (1961) 76, 34 P.B. Ghate, W. R. Gardner and D. L. Crosthwait, 1EEE Trans. Reliab., 22 (1973) 186. 35 M. Tsunemitsu and M. Shiba. IEEE Int. Electron Device Meeting, October 1969, IEEE, New York, 1969, Abstract 18.4. 36 W. R. McMahon, 1EEE Int. Electron Device Meeting, October 1970, IEEE, New York, 1970, Abstract 7.1. 37 G . C . Schwartz and V. Platter. J. Eleetroehem. Sot., 122 (1975) 1508. 38 E. Philofsky, Solid-State Electron., 13 (1970) t 39 I. 39 J. Lymann, Electronics, 48 (26) (1975) 61. 40 T. Angelucci, Sr., Solid State Technol., 19 (7) (1976) 2 I.
69
METALLIZAT1ON IN M I C R O E L E C T R O N I C S * P. B. GHATE, J. C. BLAIR AND C. R. FULLER Semicomhwtor Research anti Engineering Laboratories, Texas Instruments, Inc., Dallas, Texas 75222 (U.S.A.) (Received March 31, 1977: accepted April 8, 1977)
Continued improvements in the design and fabrication of semiconductor devices have led to the introduction of medium and large scale integration of microcircuits. These advances have placed severe demands on metallization techniques, requiring metal contacts to shallow junction devices and definition of metal interconnections that are closely spaced and of a narrow pattern. Aluminum is the most widely used metal in microelectronics for providing the necessary contacts and interconnections. The contact resistance of the Si-A1 interface is sensitive to surface preparation, the vacuum ambience of the AI film deposition and contact sintering. Controlled contaminations, such as H:O, CO and 0 2, have been introduced during the AI film deposition in order to determine their effects on AI/Si contacts. Extensive studies have shown the interdependence of the film deposition parameters, the physical properties of the A1 films and the dominant failure mechanisms, such as electromigration, that limit the reliability of integrated circuit interconnections. For high speed very shallow emitter-base junction devices, A1 in silicon contact windows can penetrate to the junction during sintering and can cause leakage. Solutions to this problem include the use of A1 + Si films, PtSi contacts with a barrier layer (e.g. Ti : W) and AI or Au conductors. Metallization must be suited to all the device processing steps beginning with contact sintering, device packaging, testing and also the operating conditions. Highly complex large scale integrated circuits require multilevel interconnections. A two-level metallization scheme (Al/insulator/Al) and its application are presented. Future trends in metallization processing are also discussed.
I. INTRODUCTION
Microelectronics covers a broad spectrum of devices from discrete diodes and transistors to the most complex integrated circuits. Metallization requirements are so diverse that no unique metailization solution satisfies all the requirements 1-6. The metallization process must be suited to the device performance requirements (ohmic and Schottky contacts), the operating temperature range, the packing density (narrow lead widths and smaller spacings between leads), the packaging *.Paper presented at the International Conference on Metallurgical Coatings, San Francisco, California, U.S.A., March 28-April 1, 1977.
70
P.B. GHATE, J. C. BLAIR, C. R. FULLER
(bonding to Au or Al wires, gang bonding to Au bumps, plastic packages, hermetic packages with glass sealing operations), the reliability (long mean time to failure (MTF) under normal operating conditions with failure rates of 0.1 to 0.2 per million device hours) and cost effectiveness. Continued improvements in circuit design and fabrication led to medium scale integration (MSI) and large scale integration (LSI) of microcircuits. Higher device packing density, higher speed and reduced bar size have been the primary driving forces in this evolution. The progress achieved in the complexity and packing density of LSI circuits over the last 10 years can be seen from the photographs of typical circuits shown in Fig. I. These advances have placed severe demands on
1970
1976
1976
1977
Fig. 1. MOS technology progress.
metallization techniques, requiring metal contacts to shallow junction devices and the definition of closely spaced narrow metal patterns for interconnections. In this paper the discussion will be restricted to metal film interconnections used in silicon planar technology for integrated circuit (IC) fabrication. Aluminum is the most widely used metal for contacts and interconnections in both bipolar and MOS ICs 6' ~. It has a high conductivity, and the films can be vacuum deposited to within 5-10 ~ of the bulk resistivity (2.7 laf2 cm). AI forms low resistive contacts with p- and n-type silicon. The contact resistance of the Si-AI interface has been examined as a function of the silicon surface preparation, controlled contamination (such as H20, 02 and CO) during AI film deposition and contact sintering 8. For high speed very shallow emitter base junction devices, AI penetration in silicon contact windows during sintering can extend to the junction and can cause leakage. Solutions of this problem
METALLIZATIONIN MICROELECTRONICS
71
include the use of A I + S i films 9' l o or PtSi contacts ~1 with a barrier metal (such as T i : W and Mo) and AI or Au conductors 12.13 PtSi layers are formed by sintering vacuum-deposited Pt films on Si contacts in N 2 or air ambience. The effect of sintering ambience on the composition of PtSi layers has been examined by Auger spectroscopy and ion profiling ~4-~ 7. The reliability of aluminum film interconnections depends on the physical properties of the films as they are to be found on finished devices 18-22. Transmission electron micrographs are presented to show that the final aluminum film microstructure depends on the initial film microstructure 22 even after a 15 min, 450°C anneal in N 2. Highly complex circuits require multilevel interconnections 23-25. A two-level metallization scheme (Al/insulator/Al) and its application will be presented. Optical patterning technology is reaching the practical limit for defining narrow interconnections (0.1 mil or 2.5 ~m). With the advances made in electron beam patterning 26-28 and X-ray lithography 29, devices with micron and submicron geometries are feasible, and metallization techniques need to be developed to meet these requirements. 2. METAL--SEMICONDUCTORCONTACTS
Metal-semiconductor contacts are an integral part of the overall interconnection system in ICs. The behavior of electrical contacts (ohmic or rectifying) depends on the silicon surface concentration, the surface cleanliness and the metal-silicon interface reactions. Many metals such as Al, Cr, Ag, Ti, Pt, Pd, Mo, W; HI', Ta and Ni have been examined for forming metal-silicon contacts. A m o n g the metals investigated for contacts, aluminum is the most widely used because it forms low resistive contacts to both p- and n-type silicon and also meets the interconnection requirements. In practice, Si/Al contacts are effected by sintering at temperatures in the 400-550 °C range, forming Al + Si alloy at the interface. High resistive Si/A1 contacts (or poor contacts) are not uncommon in IC manufacturing. Poor metallurgical reaction at the Si-Al interface either due to surface contamination or due to poor metal deposition technique is considered to be the primary cause of this problem. Recently, the influences of (a) surface contamination (or impurities) due either to pre-metallization clean-ups or to residual gas levels in vacuum metal deposition systems and of (b) contact sintering temperatures and ambients on the formation of the Si/A1 contact have been investigated a. Test structures were fabricated on silicon substrates (n-type l0 15 ~) cm 2, I I 1 orientation) processed through boron base and emitter diffusions 2a. The base and emitter diffusion corresponded to surface concentrations of (3-4) x l0 is cm -a and ( 4 - 6 ) x l020 cm - a respectively. After base and emitter windows were opened, the slices were pre-evaporation cleaned in 3 parts of H2SO 4 and 4 parts H 2 0 2 and then rinsed in running deionized water for 15 min. The slices were then dipped in Bell II etchant for a period of 0-10 s, were rinsed in deionized water and were dried for l0 min in refluxing isopropyl alcohol vapor. Prior to the Al deposition, known residual gas contaminants such as H 2 0 , 0 2 and CO were admitted to the vacuum chamber (1.33 x 10-5 Pa (1 x l 0-7 Torr) base pressure) by a controlled leak valve up to a partial pressure of 6.7 x l0 -5 Pa (5 × 10 -v Tort) which was monitored with a U T I 100C mass analyzer. The Si/A1 contacts were
72
P.B. GHATE, J. C. BLAIR, C. R. FULLER
AI L
E
A
k._
~
-"
AI S, iNTERFACE
EQUATIONS
V23
1 ~1
Vl4 I =3Rs
3.
Re=
(
3R s
2Rc"l"3Rs 1
2
J
,I $I
4
V23- V14 2 I CURRENT IN
CURRENT OUT
Fig. 2. A contact resistance test pattern.
effected by sintering at 4 0 0 - 5 5 0 °C in an N 2 ambience. F i g u r e 2 shows a typical test structure. Several h u n d r e d test structures with c o n t a c t areas o f 4.9 x 10 6 cm 2 (0.2 mil x 3.8 rail) were m u l t i p r o b e d . A specific c o n t a c t resistance o f the o r d e r o f (1-2) x 10- 6 ~ cm 2 was o b s e r v e d for all e m i t t e r regions in the 15 22 ~ / [ ] range (see T a b l e I). N o systematic c o r r e l a t i o n between the c o n t a c t resistance a n d the residual gas c o n t a m i n a n t was found. It was c o n c l u d e d that the surface p r e p a r a t i o n a n d c o n c e n t r a t i o n s o f a d d e d c o n t a m i n a n t s in the c h a m b e r at a base pressure o f 1.33 x l0 -5 Pa (I x 10 7 T o r r ) had a l r e a d y affected the silicon surface, f o r m i n g an "'interfacial layer". F u r t h e r a d d i t i o n o f H 2 0 , 0 2 a n d C O to a pressure o f 1.33 x 10 -5 Pa (1 x 10 v T o r r ) exerted no m e a s u r a b l e influence on the g r o w t h o f this interracial layer. Even if the interracial layer thickness increased p r i o r to AI metal deposition, it did not affect the c o n t a c t resistance adversely 8. TABLE l SPECIFIC CONTACT RESISTANCE DATA
Interlace
Si/Al Si/Al Si/AI+Si Si/PtSi
Controlled contaminants
Partialpressure/ Totalpressure
Specific contact
None H20, O2, CO None None
/3 x 10 -7 Torr 7 × 1 0 ~/2×10 6Torr /1.6×10 6Torr
1 1.3 0.3 1.3 I 1.3 0.5
resistance
(10 6 ~ cm 2)
Thecontactareais4.9 x 10 6cmZ(0.2mil × 3.8mil);~hesheet resistivityoftheemittcrrcgionisabout 15 22
n/E3.
METALLIZATION IN MICROELECTRON1CS
73
For most devices, the processing of the Si/A1 contacts with AI-Si alloy formation at the interface is not a serious problem. It must be noted that there is a natural SiO z layer 1-3 nm thick on the silicon prior to metal deposition. Aluminum in a diffusion-controlled reaction reduces the silicon dioxide, forming aluminum oxide. A sintering operation of short duration at elevated temperatures reduces this oxide uniformly at the contact window, leading to uniform AI + Si formation; with a lower temperature and longer duration sintering, A1 penetrates deeply into the silicon at discontinuities in the oxide layer instead of reducing the SiO z layer to permit uniform AI-Si formation. Silicon from the contact windows diffuses into the aluminum films along grain boundaries to satisfy the solid solubility of Si in AI, and precipitates on cooling. Aluminum, in turn, diffuses into the silicon contacts. This alloy penetration is a function of sintering temperature, time and crystal perfection. A wide A1 lead covering smaller contact windows can lead to deep alloy penetration and junction shorting. For devices with shallow emitter-base junctions ( < 1 p.m), alloy penetration can cause junction shorting. Alloy penetration can be impeded by the use ofAl + Si films for interconnections 9' 10 Alternatively, the AI films can be separated from the Si by a barrier metal (such as T i : W ) 12. Electrical contacts to the silicon are readily achieved with PtSi layers ~ The Pt films are vacuum deposited onto silicon substrates and are sintered at temperatures ranging from 400 to 600 °C. The formation of PtSi has been studied by several workers 14-17, and some understanding of the effects of sintering ambience on PtSi formation has been gained with the aid of Auger electron spectroscopy (AES) and ion profiling. PtSi layers are formed by the diffusion of Si into Pt films. Pt and Si atoms react with each other to form PtESi and then PtSi. When hot slices are pulled into room air, Si atoms present on the PtSi surface react to form S i O 2 ( o r PtSiO4). It is this oxide layer that protects the PtSi from dissolution during subsequent platinum stripping in aqua regia ~4. The PtSi layer thickness can vary as a function of the Pt thickness, the Si surface treatment prior to the Pt deposition and the sintering ambience. If the native oxide on the silicon surface is not removed either by dipping the substrate in HF solution or by in situ sputter etching in vacuum prior to Pt deposition, Si diffusion into Pt films is impeded by this oxide layer. Thinner non-stoichiometric PtSi films can result. The PtSi layers formed by sintering in inert (N2) and oxidizing (air) ambients (525 °C, 15 min) have been examined. Depth profiles for Pt, Si, O, N and C were developed using peak-to-peak heights of the Auger transition and sputtering times. In order to compare the Pt and O concentration versus depth into these PtSi layers, the ratios of the peak-to-peak heights of Pt : Si and O: Si were developed and are shown in Fig. 3. It can readily be seen that oxygen is present throughout the PtSi layer (Fig. 3(a)) when it is formed in an oxidizing (air) ambience. The presence of e x c e s s S i O 2 in PtSi layers has been found to affect devices adversely. Figure 3(b) shows the confinement of the SiO 2 layer to the surface of PtSi, thereby permitting a control of the PtSi layer in normal processing. PtSi contacts have been found to be satisfactory for junction depths of less than 1 p.m. The interface resistance of the Si/PtSi contacts has been determined with the test structures described earlier. The specific contact resistance for typical surface concentrations in the emitter regions is of the order of 5 × l 0- 7 D c m 2.
74
P. B. GHATt', J. ('. BLAIR, ('. R. FUI.I.IIR
.fw/~/"'X\~
1. \
1 Pt + Si
/"
,
"
, f'%~-
O5 -/
(a) o o
1L0
1+5
~0
D
1.! ',,+
P| ,. Si
•
•
10 0 5i
"'" . . . . . . . 0
(b)
",L
;2
0, DEPTH ~SPUTTERING TI&~E IN ~,~IN )
Fig. 3. The A u g e r peak-to-peak height ratio vs. the sputtering time for samples annealed in (a) air and (b) N 2. 3. SINGLE-LEVEL INTERCONNECTIONS
Any metallization system for IC interconnections must satisfy certain minimum requirements : (i) it should make good ohmic contacts to both p- and n-type silicon ; (ii) it should be adaptable to practical methods of deposition to provide low resistive interconnection paths (p < 3-10 gfl cm); (iii) it should be adherent to both silicon and silicon dioxide; (iv) it should be patternable in chemicals not reactive with photoresist, silicon and silicon dioxide; (v) it should be compatible with bonding techniques; and (vi) it should be reliable under normal operating conditions. A large number of single metal, bimetal and trimetal combinations have been explored for interconnections, e.g. single metal bimetal trimetal
A1, Cr, W etc. Cr-Ag, Cr-Au, M o - A u , Ti: W - A u etc. T i - P t - A u , T i - P d - A u , C r - A g - A u etc.
For reasons previously stated A1 is the most widely used metal system 6"7' however, bimetal and trimetal sandwiches with Au as the main conductor are also used for interconnections 1z, 13. Au films have poor adhesion to SiO z. Hence in such metallization systems refractory metals such as Mo, T i : W or Ti-Pt provide the necessary adhesion to the SiO 2 and act as a barrier layer between the silicon and gold films. Metal systems other than AI and Au as primary conductors have been used in special applications ; however, these two metals satisfy most microelectronic interconnection needs.
METALLIZATION 1N MICROELECTRONICS
75
Aluminum films are vacuum deposited by several techniques including (i) filament evaporation, (ii) flash evaporation, (iii) induction heating, (iv) electron beam heating, (v) sputtering etc. Electron beam and induction heating tend to dominate the deposition technology because of their ability to deposit high purity Al films to within 5 - l 0 % of the bulk resistivity (p = 2.7 lift cm) at reasonable rates with minimum device damage (MOS devices are sensitive to deposition techniques). Two areas of major interest are (i) metal coverage on Si-SiO 2 steps at the contact windows and (ii) establishing low resistive A1-Si contacts. Step coverage depends on the oxide profiles to be covered, the deposition equipment and the deposition parameters 3°'3~. Substrate heating and some form of slice rotation are highly desirable in order to improve step coverage. Oxide profiles with nearly vertical or reverse slopes are major causes of discontinuity in metal leads after either the metal deposition or metal patterning. A 2 0 - 1 0 0 ~ thinning of the metal film is observed at these oxide steps. Many techniques including novel slice rotation and appropriate biasing of the substrates during sputter deposition of the films have been employed to solve this problem 25. However, the use of a gently sloped oxide profile appears to be the best pragmatic solution to this step coverage problem. The reliability of interconnections depends on the physical and electrical properties of the films as they are to be found on the finished devices (end product). AI films are subjected to several temperature excursions during lead patterning, ohmic contact bake, final assembly and packaging. Microstructure is the single most important film property that undergoes changes due to device processing 4"23. In Fig. 4, we present transmission electron micrographs of AI-I films (deposited on unheated substrates) and AI-II films (substrates held at 200°C during film deposition) before and after a 450°C, 15 min anneal in N 2. These films were deposited at 2 nm s- 1 by electron beam evaporation under nominal v a c u u m ( 1 0 - 6 Torr (1.33 x 10 -4 Pa)). The films were thinned for the transmission studies from their original thickness of 0.85 lam. AI-I films have a smaller grain size than AI-II films. Also microstructural inhomogeneities in AI-I are greater subsequent to anneal than those in AI-II samples. In Fig. 5, transmission electron micrographs of sputter-deposited and thermally evaporated gold films before and after a 450°C, 24 h anneal in air are presented. The average grain size of the Au films prior to anneal is of the order of 0.2 lam. We note that the 450 °C, 24 h anneal does not change the microstructure of the sputtered Au films a2, but that the average grain size of the evaporated Au films increases from 0.2 ~tm to 1.1 ~tm with this anneal. The resistivity of the sputtered Au films was 4.1 ~tl) cm and that of the annealed evaporated Au films was close to the bulk value (2.4 ~tfl cm). Reliability studies on microelectronic circuits have led to the identification of "electromigration-induced failures in thin film conductors" as one of the failure modes. Mass migration under the influence of a direct current is called electro-. migration. Atomic flux (or vacancy flux) is related to current density in the framework of a model proposed by Huntington and Grone 33, and is given by NiD
jj = ~ - Z
,
epj
76
P.B. GHATE, J. C. BLAIR, C. R. FULLER
(a)
(b)
(c)
~d)
Fig. 4. M i c r o g r a p h s o f A l - l a n d A l - l l film> bcforc and after a 15 min anncal at 450 C : ( a ) Al-lbcl\)rc anneal; (b) AI-I after anneal; (c) AI-II before anneal; (d) AI-I! after anneal. The scale bar is 1 jam.
whereji is the flux of metal ions, N i the local density of ions, D ( = D o exp( - Q/k T) ) the diffusion coefficient, Z*e the effective charge on the ion,./the current density and p the film resistivity. The above expression, though developed for a bulk specimen, is assumed to be valid for films where grain boundary diffusion dominates over ion migration. A non-vanishing divergence of the atomic flux (vacancy flux in the opposite direction) leads to void formation. Temperature gradients and structural inhomogeneities (an abrupt change in grain size, a triple point of grain boundaries, a precipitate) are primary causes leading to non-vanishing divergences of vacancy
METALLIZATIONIN MICROELECTRONI('S
77
(a)
(b)
(c)
(d)
Fig. 5. Micrographs of sputtered and evaporated Au films before and after a 24 h anneal at 450 :C: (a) sputtered Au, before anneal; (b) sputtered Au, after anneal; (c) evaporated Au, before anneal; (d) evaporated Au, after anneal. The scale bar is 0.1 I.tm. flux a n d the resulting void f o r m a t i o n . These voids g r o w to develop open lead failures. Expressions have been d e v e l o p e d for the M T F o f film c o n d u c t o r s subjected to high current stress: MTF =
Aj-" exp(Q/k T)
where A is a p a r a m e t e r d e p e n d i n g on the s a m p l e g e o m e t r y a n d the physical characteristics o f film a n d substrate, j is the c u r r e n t density, n an exponent, Q the
78
1,. B. GHATE, J. ('. BLAIR, C. R. FULLER
activation energy, k Boltzmann's constant and T the average temperature of the conductor. For AI conductors the reported values of Q and n lie in the ranges 0.6+0.2 eV and 1 7 respectively. The M T F has been observed to improve with increase in grain size if the variance of the grain size is held constant. The M T F decreases with increasing variance of the grain size distribution if the grain size is held constant. The grain size distribution is important because an abrupt change in grain size between one interconnection region and another leads to vacancy flux divergence. If the grain size is of the order of the lead width, a single grain boundary can span the lead width and can be a location for void formation and an open lead failure. Grain size differences at particular lead locations also provide sites for void growth. Experience suggests that structurally homogeneous films are desirable with increasingly smaller geometry interconnections (2-6 lam). Furthermore, optimization of the grain size with respect to lead width needs to be considered. Gold film resistors 6.5 lam in width, 0.8 lam in thickness and 1125 ~tm in length were subjected to high current stress in 150 ~'C air ambience. MTF data as a function of current density j are presented in Fig. 6. We note that the M T F is longer for evaporated Au films with larger grain size than for sputtered films with a small grain size. In the same figure the M T F data for AI conductors are presented for comparison. In certain applications where high current density requirements exist, Au film interconnections are preferred.
lOO( 50(
=. loc
\
5o
O
I
1.5
2!0
Z.15
3.1
315
4.10
5
CURRENT DENSITY (106 A/cm21
Fig. 6. The M T F vs. current density for Au and AI film resistors: curve 1, evaporated Au films ( M o - A u ) ; curve 2, annealed sputtered Au films (Ti : W - A u ) ; curve 3, unannealed sputtered Au films (Ti : W - A u ) ; curve 4, large grain AI films with protective coating (r.f. silane SiO2, silane SiO2).
4.
TWO-LEVEL INTERCONNECTIONS
Improvements in the design and fabrication of complex MSI and LSI circuits require the use of multilevel (at least two) interconnections to achieve higher
79
METALLIZATION IN MICROELECTRONICS
T !
|lldl
I,q
V
~|
.--__..q
L
Fig. 7. The impact of two-levelinterconnections on a 256-bit TTL RAM.
packing density and speeds and a reduced bar size. The impact of two-level interconnections on the design and performance of an MSI circuit is shown in Fig. 7. Some metal-insulator combinations employed to achieve multilevel interconnections are: (a) AI/SiO2/AI 3"23-2L34, (b) AI/AI2Oa/A1 35-37, (c) M o Au-Mo/SiOz/Mo-Au and (d) T i W - A u - T i W / S i O 2 / T i W - A u 13. Aluminum and gold films provide the desired low resistive interconnections, and SiO2 o r A l x O 3 provide the necessary insulation between layers. The primary components of a two-level interconnection system are (a) crossovers (a second-level lead crossing the first-level lead separated by an insulator (SiO2) layer) and (b) vias (locations'for level-to-level contact through a hole in the insulator). The topography of the oxide layer covering first-level leads (e.g. reentrant folds developed over vertical edges of first-level leads) has been a major factor affecting the integrity of crossovers because of poor metal coverage on these oxide steps. The anodic two-level A1/AI2OCAI system, which produces an almost flat topography for the second-level metal, was introduced to solve the crossover problem. In the fabrication of etched two-level interconnections, the desirability of sloped first-level leads to generate smooth oxide contours for second-level metal coverage has been well recognized. Hillock formation on the first-level leads has also been a major concern in fabrication of interlevel short free crossovers. Poor photoresist coverage over hillocks can permit insulator removal near the hillocks
80
P. B. GHATE, J. C. BLAIR, C. R. FULLER
during via etching, providing a shorting path between levels at crossovers. Hillock formation results from mass migration due to compressive stresses acting on the film when it is heated for photoresist operation, contact sintcring, insulator deposition etc. Hillock density can be minimized by use of large grain films. The addition of impurities such as Cu to A1 suppresses hillock growth and increases electromigration resistance 21. Copper-doped AI films can be deposited by several techniques : flash evaporation, dual electron guns or filaments, magnetron sputtering etc. We have found that copper concentration control is readily maintained by depositing from an r.f. induction-heated source. A1 + C u films with 1-2 at. o~ of Cu at 3 3.5 la~ cm resistivity are readily obtained. The thickness of first-level metal leads is dictated by the current density and the metal coverage requirements on oxide steps at contact windows. An AI film 1-1.2 ~tm thick is used for first-level leads. Insulator films considerably thicker than the first-level leads have been suggested to ensure insulator integrity between levels. Thicker insulator films pose internal stress-cracking problems. This problem can be eliminated by the use of thinner A1 + Cu film conductors without loss of reliability. Sloped first-level leads, realized by optimizing photoresist and etching operations, provide the desired insulator profiles for second-level coverage on steps. Several dielectrics such as sputtered quartz, chemically vapor-deposited silicon dioxide, anodic oxide, silicon nitride, polyimide and a combination of sputtered and chemically vapor-deposited oxides have been explored for multilevel insulators. Dielectric selection for multilevels is governed by several factors such as pinhole density, coverage at metal edges, internal stresses, via etching, reliability etc. For most applications chemically vapor-deposited SiO 2 provides satisfactory insulation for multilevel interconnections. The etching of vias in insulators is a critical step. Proper process controls must be established to achieve a reproducible process. An AI A1 interface resistance of the order of 10-v ~ cm 2 is observed in clean vias. Incomplete removal of oxide in vias produces very high interface resistance (about 10 -2 ~ cm2), resulting in nonfunctional integrated circuits. Sputter etching of vias prior to second-level metal deposition appears to be one of the solutions that overcome the high resistance via problem. Continuity of the second-level leads is no longer a problem with smooth oxide contours over the edges of sloped first-level leads. Test structures 23 consisting of long via chains and a number of crossovers (serpentine metal patterns crossing over each other) are used to optimize two-level interconnection processes and to determine interconnection yields. The results of such experiments are useful in developing the circuit design layout rules. In Fig. 8, scanning electron micrographs of vias and crossovers for an A I + C u / S i O z / A I system are presented. A metallization process scheme useful for LSI can be as follows : PtSi/Ti : W-Al + Cu/SiO2/Al where PtSi forms the ohmic and Schottky contacts, T i : W acts as a barrier layer, A1 + Cu acts as a first-level conductor, SiO z serves the purpose of an interlevel insulator and AI acts as a second-level conductor. Such a metallization process has been applied in the fabrication of two-level interconnections on LSI circuits.
Fig. 8. Two-level interconnections on an IC: (A) circuit; (B) crossover; (C) via; (D) via cross section.
O~
z a
©
Q -4
O r~ r" rrl
7~
Z
-]
U"
-] >
82
P. B. G H A T E , J. ( ' . B L A I R , ( ' . R. F U L L E R
5,
BONDING
AND ASSEMBLY
Major advances are being witnessed in the chip bonding technology. Thc bonding of gold wires to A1 pads one step at a time is being replaced by automated wire bonding. The reliability of gold ball bonds attached to AI pads has been problematical because of Au-AI intcrmetallic formation 38. Beam lead processing eliminates this problem by attaching gold beams to gold pads on 1Cs. Competitive cost pressures have led to the development of "'gang bonding" 3 9 . 4 0 . Here gold or copper bumps are formed on a passivated slice at the bond pad locations. A barrier metal such as Ti, Pt, Cr, Cr + Ag etc. is deposited on the A1 pads of conventionally metallized ICs and gold or Cu bumps (10 25 lam in height) are formed. Chips on these slices are separated and carried on an adhesive tape together with a tape of tin-plated copper leads for fluxless contact soldering by.a gang lead bonder in a single step. The gang bonding process promises high yield and high throughput. The reliability of lead attachment to bumps will depend strongly on the effectiveness of the barrier layer between the gold bumps and the aluminum pads. The adhesion of these bumps to chips will be one of the parameters that will determine the MTF oflCs. Metallization processes for interconnections need to be compatible with advanced bonding techniques. 6.
FUTURE
TRENDS IN METALLIZATION
The increasing demand for high performance (speed) and high density (large number of components, e.g. diodes, transistors, resistors and capacitors) LSI circuits is being met by new device dcvelopment, circuit designs and by continuous shrinkage of geometrical dimensions. Metal interconnections for some LSI circuits
0.6 0.4 fOPTICAL
-- 3OO
IMAGING
2OO
0.
150
loo ~
0.
6O ~ N E_BEAM.r. / / " " X-RAYS
3O
z ~ 1 ~
z0.0,
4K
MEMORY
20 15
0. 01 '
'
'
' I~70.
'
'
'
'
1475'
i
i
]~BO
i
i
i
YEAR
F i g . 9. The trend in bar size and minimum geometry for complex 1Cs.
I
METALLIZATION IN MICROELECTRONICS
83
occupy a significant (almost 50 ~ ) portion of the bar area. Longer interconnection paths contribute to signal propagation delays, lowering the circuit speed. Multilevel interconnections aid in the reduction of bar size and in improving the circuit performance. Figure 9 shows the trend in the reduction of linewidths and spacings over the past 10 years. Optical patterning techniques are reaching their physical limits as linewidths and spacings are approaching the wavelength of light that is used for photoresist exposure. Practical limits in today's IC manufacturing environment appear to be 0.1 mil (2.5 lam) lines and spaces. The trend in increasing the device packing density by reduction of linewidths and spacings will continue through developments in electron beam technology and X-ray lithography for patterning submicron geometries 26-29. Use of electron beam (or X-ray) patterning for LSI circuit fabrication will require re-evaluation of present metallization practices. The formation of thousands of small metal-silicon contacts will be a challenging problem. The specific contact resistance for typical base surface concentrations is of the order of 10-5 f~ cm 2. The contact resistance for a 1 lam 2 contact may be as high as 1 k~. This interface resistance will depend on the silicon surface preparation. The metal-silicon reaction at the interface will be highly sensitive to the impurities and the oxide layers formed in the contacts prior to metal deposition. Characterization techniques capable of characterizing the surfaces in these small contact areas must provide the understanding necessary to optimize the processes. It appears that the current densities in these submicron wide IC interconnections will be of the order of 1 x 10 6 A cm -z (the conventional LSI circuit current density is 2 x 105 A c m - z maximum). Small grain size films desirable for submicron lead definition offer a large number of grain boundary diffusion paths for electromigration. Reliability studies on small grain metal film interconnections will be needed to set current density design limits. Microstructure control of metal films by deposition process optimization will be a key factor in fabricating reliable interconnections. Other parameters that need to be controlled are metal coverage on oxide steps, film thickness uniformity and surface roughness (hillock formation). Stringent process controls will be needed in metal removal steps. Dry processing such as sputter etching, ion milling and plasma processing may provide a better control in metal removal than the conventiorial wet etching process' does. Finally, it must be noted that metallization is only a part of the IC fabrication process, and it has to be compatible with the rest of the IC processing. Furthermore, metallization is one of the last critical steps to be performed in LSI circuit fabrication, and considerable cost has already been incurred in slice processing prior to this step. It is highly desirable to establish well-characterized metallization processes. ACKNOWLEDGMENTS
It is a pleasure to acknowledge the technical support by Willie McCandless, Howard Schindler, Robbie Skinner and Naomi White. We wish to thank Art Wilson for helpful discussions on patterning and Gary McGuire for the Auger analysis.
84
P. B. GHATE, J. ('. BI,AIR, ('. R. FULLER
REFERENCES
1 J.A. Cunningham, Solid-State Electron., 8 (1965) 735. 2 M.P. Lepselter, Bell Syst. Tech. J., 45 (1966) 233. 3 H. Sello, in B. Schwartz (ed.), Ohmic Contacts to Semieomh~ctors, The Electrochemical Society Softbound Symposium Scries, New York, 1969, p. 277. 4 J.C. Blair and P. B. Ghate, Weseon Teeh. Papers, 5, Wcscon, Los Angeles, Calif., 1971, Session 2, paper 1. 5 R . W . Wilson and L. E. Terry, Weseon Teeh. Papers, 5, Wescon, Los Angeles. Calif., 197 I, Session 2. paper 2. 6 G.L. Schnable and R. S. Keen, Proc. IEEE, 56 (1969) 1570 : IEEE Trans. Electron Devices, 16 (1969) 322. 7 A.J. Learn, J. Eleetroehem. Sot., 123 (1976) 894. 8 J.C. Blair and P. B. Ghatc, J. Vae. Sei. Technol., 14 (1977) 79. 9 P . A . T o t t a a n d R . P. Sopher, I B M J . Res. Dev, 13(1969) 226. 10 G.J. V a n G u r p , Appl. Phys. Lett.,19(1971)476:J. Appl. Phys.,44(1973) 2040. t 1 M . P . Lepselter and J. M. Andrews. in B. Schwartz (ed.), Ohmic Contacts to Semieonductor,~, The Electrochemical Society Softbound Symposium Series, New York, 1969, p. 159. 12 U.S. Patent No. 3,833,842 (March 9, 1976), to J. A. C u n n i n g h a m and C. R. Fuller. 13 J. A. Cunningham, W. R. Gardner and S. J. Wood, in B. Schwartz (ed.), Ohmic Contacts to Semiconductors, The Electrochemical Society Softbound Symposium Series, New York, 1969, p. 299. 14 J . M . Morabito and M. J. Rand, Thin Solid Films, 22 (1974) 293. 15 S. D a n y l u k a n d G . E. McGuire, J. Appl. Phys.,45(1974) 5141. 16 T.J. Kingzett and C. A. Ladas. J. Eleetroehem. Soe., 122 (1975) t 729. 17 R.J. Blattner, C. A. Evans, Jr., S. S. Lau, J. W. Mayer and B. M. Ullrich, J. Electrochem. Sot., 122 (1975) 1732. 18 J . R . Black, IEEE Trans. Electron Devices, 16 (1969) 338. 19 J.A. Blech and E. S. Meieran, Proe. 8th Annu. S)'mp. on Reliability Physics, IEEE, New York, 1970, p. 243. 20 J.C. Blair, P.B. G h a t e a n d C . T. Haywood. Appl. Phys. Lett.,17(1970)281. 21 F . M . D'Heurle and R. Rosenberg, Ph3w. Thin Films, 7 (1973)257 310. 22 L. Braun, Microeleetron. Reliab., 13 (1974) 215 228. 23 P.B. Ghate, Failure mechanism studies in multilevel metallization systems, Rome Air Development Center, Air Foree Systems Command, Gr!ffiss Air Force. New York, Final Teeh. Rep. R A D C TR-71186, September 1971 24 C.J. Santaro and D. L. Tolliver. Proe. IEEE, 59 ( 1971 ) 1403. 25 J.L. Vossen, G. L. Schanble and W. Kern, J. Vac. Sci. Teehnol., 11 (1974) 60. 26 G.L. Varnell, D. F. Spicer, A. C. Roger and R~ D. Holland, Extemled Abstr. Electroehem. Sot., 74 1 (218) (1974) 510. 27 E.I. Gordon and D. R. Herriott, IEEE Trans. Electron Deviees, 22 (1975) 371. 28 F . F . Fang, M. Hatzakis and C. H. Ting, J. Vac. Sei. Technol., 10 (1973) 1082. 29 S.E. Bernacki and H. 1. Smith. 1EEE Trans. Electron Devices, 22 (1975) 421. 30 1. A. Blech, Thin Solid Films, 6 (1970) 113. 31 T. Yanagawa and I. Takekoshi, IEEE Trans. Electron Devices, 11 (1970) 964. 32 J.C. Blair, C. R. Fuller, P. B. Ghate and C. T. Haywood, J. Appl. Phys., 43 (1972) 307. 33 H.B. Huntington and A. R. Grone, J. Phys. Chem. Solids, 20 (1961) 76, 34 P.B. Ghate, W. R. Gardner and D. L. Crosthwait, 1EEE Trans. Reliab., 22 (1973) 186. 35 M. Tsunemitsu and M. Shiba. IEEE Int. Electron Device Meeting, October 1969, IEEE, New York, 1969, Abstract 18.4. 36 W. R. McMahon, 1EEE Int. Electron Device Meeting, October 1970, IEEE, New York, 1970, Abstract 7.1. 37 G . C . Schwartz and V. Platter. J. Eleetroehem. Sot., 122 (1975) 1508. 38 E. Philofsky, Solid-State Electron., 13 (1970) t 39 I. 39 J. Lymann, Electronics, 48 (26) (1975) 61. 40 T. Angelucci, Sr., Solid State Technol., 19 (7) (1976) 2 I.