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Microprocessor based harmonic restraint differential protection scheme for a transformer
Journal of Microcomputer Applications (1992) 15, 169-l 76 COMMUNICATION
Microprocessor based harmonic restraint differential protection scheme for a transformer R. K. Bansal, B. K. Joshi, S. P. Singh and R. N. Bandopadhaya Department of Electrical Engineering Institute of Technology, Banaras Hindu University, Varanasi - 221 005 India
This paper presents a microprocessor based differential protection scheme for a single phase transformer with harmonic restraint feature to avoid mal-operation during inrush current conditions. The protection scheme is implemented by means of a single microprocessor of intel’s 8088 type. The relay has been tested satisfactorily by an arranged circuit for differential protection of a test transformer in the laboratory for the above condition. The test results indicate that the relay detects the inrush or other abnormal conditions satisfactorily within an overall time of about 26 ps.
1.
Introduction
In recent years there has been a growing need of very reliable and fast protection schemes for power system network, which can provide discrimination between transient and fault conditions. A modern digital computer can fulfill these requirements with sufficient accuracy. It has been identified that different protection systems are likely to be parts of a hierarchical computer system within the sub-station [1,2]. The most common technique for preventing false tripping during energization of a power transformer is the use of a ‘harmonic restraint’ relay [3,4]. A key to the design of a harmonic restraint function is the richness of second harmonics in the inrush current. However, the conventional harmonic restraint approach in differential protection is not fast or reliable [5,6]. Jamil-Asghan et al. [7] have proposed a solid state scheme to block the relay operation due to magnetizing inrush. Desai et al. [8,9] have proposed a novel technique for detecting the inrush based on current wave slopes. This scheme utilizes the fact that the current magnitude and the rate of change of current are low at the initial stage after zero crossing for the inrush condition. However, the principle of second harmonic detection is found to be sufficient and reliable for distinguishing the inrush from other abnormal conditions and is therefore explored in this work. It is known that the magnitude of second harmonic in the inrush current is greater than about 16% than that of first harmonic. The harmonic restraint function is so designed that the relay restraints during the magnetizing inrush, while during an internal fault the harmonics generated by CT saturation does not block the operation of the relay. Different algorithms are developed for digital filters for the harmonics. The algorithm based on the non-recursive filters [lo] has the advantage over the recursive filters [I l] that the fast tripping times are achieved for a number of faults that occur within the transformer. The former is therefore adopted.
169 0745-7138/92/020169+08 $03.00/O
0 1992 Academic Press Limited
170
2.
R. K. Bansal et al.
Development
of digital
filters
In digital filtering of the harmonic by a non-recursive filter, the desired harmonic is extracted from the samples of the differential signal by weighting the input samples over a certain time interval. For on-line filtering, one of the necessary requirements is of minimum calculation time which is chiefly governed by the number of multiplications. The number of multiplications needed depends on the sampling frequency (f,) and the order of harmonic (m) that is to be filtered. It is found that for filtering first and second harmonics the minimum number of multiplications are required for a sampling frequency of 600 Hz and therefore it is most suitable from this consideration. The filter structures are shown in Fig. 1, on the basis of which appropriate software has been developed to determine the contents of first and second harmonics in the differential signal.
3.
Algorithm
development
Figure 2 shows the flowchart of the differential protection scheme with its harmonic blocking mechanism. The input of the protection scheme consists of the differential signal and the logic signal used for sampling process in ‘sample and hold’. The logic signal that has been used for the sampling process is a continuous square wave with a frequency of 600 Hz, generated with the help of a square-wave generator. The program starts with a checking routine for the status (whether high or low) of the logic signal. As soon as the low status of the logic signal is detected, the microprocessor starts analogue to digital conversion of the sample of the differential signal held in the sample and hold.
cl
Delay of
I
sample
Figure 1.
Digital
filters for calculations
of 1st & 2nd harmonics
Microprocessor based harmonic restraint differential protection scheme
1
Set counter
KI =I2
171
I
1 Set AMP OF IDIFF = 0
I
i Set counter
K2 = 0
2
4
3
Test for the status (high or low) of the logic SIgnal
1
I Do A/D cowerslo”. shift down the level and store the sample
Make the sample positive if 11IS negative and update the omphtude
I
I
I
Filter 1st and 2nd harmonics magnitudes
and store their
I
G I+
output Inrush signal
Compare 1st and 2nd harmonics Is Inrush present?
Is internal fault? YES Increment
K2
NO
output trip sbgnal
3<
Figure 2.
Flow chart
of the protection
scheme
After conversion, it stores this data at some specified memory location. Continuing in this manner, 13 consecutive data-samples are obtained, following which the program moves on to the calculation of first and second harmonics. While storing the datasamples the amplitude of the differential signal is also stored. After calculation of first and second harmonics it compares their magnitudes. If the magnitude of the second harmonic is greater than 16% of the magnitude of the first harmonic, inrush is assumed. When inrush is detected, the microprocessor generates an analogue signal by means of digital to analogue conversion giving an indication signal to the inrush. The program then returns to the checking routine and takes the next sample.
172
R. K. Bnnsal et al.
This whole process is repeated and checking is made for inrush or internal fault by comparing the amplitude, in the latter case with a selected threshold value. If an internal fault is detected in two consecutive samples, a trip command is sent and the execution of the program is terminated. The total time of the decision taken by the relay including sampling time, A/D conversion time and calculation time is approximately 26 us, i.e. about one and a quarter of a cycle.
4.
Implementation
of differential
protection
Figure 3 shows the scheme of the microprocessor system that has been used for testing the implemented protection algorithm. A 5 KVA, 220 V/220 V single phase transformer is connected by means of current transformers, one on either side, to a low resistance of high current rating such that the difference of the primary and secondary currents flows through it. The value of the resistance is chosen from consideration of the maximum magnitude of the inrush current expected and CT ratio. Also, since the analogue signal should be unipolar (a constraint imposed by the A/D converter used) a level shifter is used to shift the differential voltage signal by 2 V. Thus, the shifted differential signal, which is unipolar, is now fed to the A/D converter. In the program, a provision is made to lower down the values of all the samples by 2 V so that the original waveform can be obtained before starting any further processing. The circuit of the level shifter used is shown in Fig. 4. The microprocessor system used has been built around an Intel 8088 microprocessor. The processor operates with a 10 MHz clock frequency. The multiplexer (MUX), A/D and D/A converters are controlled by software. The A/D converter used is a 1Zbit converter. The whole execution of the protection algorithm takes place in less than 1666 us. At the end of one execution cycle, the program jumps back to the checking routine.
5.
Observations
and test results
During the execution of the program, the following types of data are stored: (i) maximum magnitude of the signal in one cycle; (ii) magnitude of the first harmonic in Control
bus
t DIfferentlo slgnal
Level shifter
-
Sample and hold
V
Figure 3.
Block diagram
V
PP
M U
RAM ROM
-
ADC
of microprocessor
Inrush
system used
Microprocessor based harmonic restraint differential protection scheme
T
173
+Vcc(‘5“)
OUi 3.2
K
560
0
/
0
L 7
Figure 4.
L-l
Level shifter
one cycle; (iii) magnitude of the second harmonic in one cycle; (iv) fault counter for confirming the internal fault condition. Some of the waveforms taken from the CR0 are as shown in Fig. 5(a,b). The figure gives a clear picture of the sampled signal that is actually fed to the microprocessor unit. The periods of sampling and holding of the signal by S/H can be clearly seen. On the basis of observations obtained during the tests performed in the laboratory, some relevant results obtained are tabulated in Table 1. For a simulated condition corresponding to an internal fault, the fault counter value is 2 while under no fault and
A + f +
(31
0-I V div“ 5 mS dlv-’
(4)
A + f +
Figure Sa.
Oscillogram
of actual
signals fed to the microprocessor
20 mV dlv-’ 5 mS dw-’
1. 2. 3. 4. 5. 6. 7. 8.
S.N.
OOOA 0097 0062 oooc 0012 0084 0024 005F
HEX value
10 151 98 12 18 132 36 95
DEC value
Magnitude of 1st harmonic (I,)
0001 0001 0000 0000 004D 0063 0024 0039
HEX value
1 1 0 0 77 99 36 57
DEC value
0084 OOc5 OOAC 0017 OlB3 0131 0107 0159
____._ HEX value
Max. magnitude
132 197 172 23 435 305 263 345
DEC value
among
160 240 210 28 530 360 320 420
Equiv. voltage (mv) 0000 0002 0002 0000 0000 0000 0000 0000
Fault counter value W
conditions
13 samples
Test results obtained for d@erent simulated
Magnitude of 2nd harmonic (I,)
Table 1.
10 0.66 0 0 428 75 100 60
% of 2nd harmonic &/I,)%
No fault Fault Fault No fault Inrush Inrush Inrush Inrush
Result
Microprocessor based harmonic restraint differential protection scheme
A -0.1 f -5mS
(5) I-
V dw-’ div“
A f -+
( 6)
175
0-I V dlv-’ 5 mS div.’
f r
r
I-
II-
L
r
L ___ _- --
L L c
r
r r-
A -0-I f -
(7)
V dw-’ 2 mS div-’
(8)
7-
r/
A f c
L
f
L L
r
r
r -
L
-
50 mV dlv-’ 5 mS div-’
Figure 5b.
_---
-r
r
L
_-I_-
L L -*
Ie/-
Oscillogram of actual signals fed to the microprocessor
inrush current its value is zero. In case of inrush, the second harmonic content is greater than 16% of the first harmonic.
6.
Conclusion
A microprocessor based differential protection with inrush restraint has been designed, fabricated and tested. The system continuously monitors the signals and gives a trip signal as the fault occurs. However, under switching inrush current condition an indicating signal, rather than a tripping output is sent. The test results, as given in Table 1, indicate satisfactory performance when compared with similar work reported in the reference.
References 1. Computer Relaying. IEEE Tutorial Course, 79 EH0148-7-PWR. 2. A. G. Phadke. April 1980. Recent Development in Digital Computer Based Protection and Control in Electric Power Sub-station, presented at Conference on Power System Protection, The Institution of Engineers. Madras, India. 3. L. F. Kennedy & C. D. Hayward. 1948. Harmonic-Current-Restrained Relays for Differential Protection. AIEE Trans., Vol. 67, Part II, pp. 1005-1022. 4. C. A. Mathews. 1954. An Improved Transformer Differential Relay. AZEE Trans., Vol. 73, Part III, pp. 645-650.
176
R. K. Bansal et al.
5. K. L. Sharp & W. E. Glassburn. 1958. A Transformer Differential Relay with Second Harmonic Restraint. AZEE Trans., Vol. 77, Part III, pp. 913-998. 6. J. A. Sykes & I. F. Morrison. 1972. A Proposed Method of Harmonic Restrained Differential Protection of Transformers by Digital Computer. IEEE Trans., Vol. 91, pp. 12661273. 7. M. S. Jamil-Asghar, M. Mohibullah & M. Salman Beg. 1986. A Solid State Relay for Transformer Switching. International Journal Electronics, 61, 539-542. 8. B. T. Desai, H. 0. Gupta & M. K. Vasantha. 1989. New One Cycle Static Blocking Scheme for Inrush in Differential Relay. ZEE Proc., Vol. 136, Pt. C, No. 1, pp. 48-54. 9. B. T. Desai, H. 0. Gupta & M. K. Vasantha. 1988. New One Cycle, Microprocessor Based Differential Relay for Transformer Protection. Journal Microcomputer Applications, 11, 135-144. 10. A. J. Degens & J. J. M. Langedijk. 1985. Integral Approach to the Protection of Power Transformers by means of a Microprocessor. Electric Power and Energy Systems, 7, 3746. 11. J. S. Jhorp & A. G. Phadke. 1982. A Microprocessed Based Three-phase Transformer Differential Relay. ZEEE Trans., Vol. PAS-101, No. 2, pp. 426432. R. K. Bansal originates from Dehradun, India. He obtained the B.Tech. degree in Electrical Engineering from Banaras Hindu University, India in 1990. Presently he is working in Reliance Petrochemicals Ltd., &rat, India.
B. K. Josh originates from Dehradun, India. He obtained the B.Tech. degree in Electrical Engineering from Banaras Hindu University, India in 1990. He then worked in Reliance Industries Ltd., Raigad, India.
Dr. S. P. Singh was born in Varanasi, India, on September 5, 1957. He received the B.E.(Electrical) and M.E.(Electrical) degrees from Allahabad University, India, in 1978 and 1981 respectively and PhD from Banaras Hindu University, India in 1990. He joined the Department of Electrical Engineering, BHU in 1981 where he is presently working as Senior Lecturer. His main research interests are in Load flow, sparsity techniques, expert system and microcomputer applications to Power System problems. Dr. R. N. Bandopadhaya was born at Patna in India on November 18, 1940. He obtained his BSc (Engg) degree from Patna University (India) in 1964 in Electrical Engg. and M.Tech. degree from Indian Institute of Technology, Kharagpur (India) in 1967 with Power Systems Engg. specialization. After working as a Lecturer in Jalpaiguri, Govt. Engg. College, West Bengal (India) for some time, he joined the Institute of Technology, Banaras Hindu University, Varanasi (India) in 1976 as a Lecturer in Electrical Engg. He obtained his PhD degree from the same Institute in 1984 and is presently working as a Reader in the Electrical Engg. Dept. of the Institute. His research interests are in the areas of synchronous machine dynamics and transients and modern trends in power system protection.
Microprocessor based harmonic restraint differential protection scheme for a transformer R. K. Bansal, B. K. Joshi, S. P. Singh and R. N. Bandopadhaya Department of Electrical Engineering Institute of Technology, Banaras Hindu University, Varanasi - 221 005 India
This paper presents a microprocessor based differential protection scheme for a single phase transformer with harmonic restraint feature to avoid mal-operation during inrush current conditions. The protection scheme is implemented by means of a single microprocessor of intel’s 8088 type. The relay has been tested satisfactorily by an arranged circuit for differential protection of a test transformer in the laboratory for the above condition. The test results indicate that the relay detects the inrush or other abnormal conditions satisfactorily within an overall time of about 26 ps.
1.
Introduction
In recent years there has been a growing need of very reliable and fast protection schemes for power system network, which can provide discrimination between transient and fault conditions. A modern digital computer can fulfill these requirements with sufficient accuracy. It has been identified that different protection systems are likely to be parts of a hierarchical computer system within the sub-station [1,2]. The most common technique for preventing false tripping during energization of a power transformer is the use of a ‘harmonic restraint’ relay [3,4]. A key to the design of a harmonic restraint function is the richness of second harmonics in the inrush current. However, the conventional harmonic restraint approach in differential protection is not fast or reliable [5,6]. Jamil-Asghan et al. [7] have proposed a solid state scheme to block the relay operation due to magnetizing inrush. Desai et al. [8,9] have proposed a novel technique for detecting the inrush based on current wave slopes. This scheme utilizes the fact that the current magnitude and the rate of change of current are low at the initial stage after zero crossing for the inrush condition. However, the principle of second harmonic detection is found to be sufficient and reliable for distinguishing the inrush from other abnormal conditions and is therefore explored in this work. It is known that the magnitude of second harmonic in the inrush current is greater than about 16% than that of first harmonic. The harmonic restraint function is so designed that the relay restraints during the magnetizing inrush, while during an internal fault the harmonics generated by CT saturation does not block the operation of the relay. Different algorithms are developed for digital filters for the harmonics. The algorithm based on the non-recursive filters [lo] has the advantage over the recursive filters [I l] that the fast tripping times are achieved for a number of faults that occur within the transformer. The former is therefore adopted.
169 0745-7138/92/020169+08 $03.00/O
0 1992 Academic Press Limited
170
2.
R. K. Bansal et al.
Development
of digital
filters
In digital filtering of the harmonic by a non-recursive filter, the desired harmonic is extracted from the samples of the differential signal by weighting the input samples over a certain time interval. For on-line filtering, one of the necessary requirements is of minimum calculation time which is chiefly governed by the number of multiplications. The number of multiplications needed depends on the sampling frequency (f,) and the order of harmonic (m) that is to be filtered. It is found that for filtering first and second harmonics the minimum number of multiplications are required for a sampling frequency of 600 Hz and therefore it is most suitable from this consideration. The filter structures are shown in Fig. 1, on the basis of which appropriate software has been developed to determine the contents of first and second harmonics in the differential signal.
3.
Algorithm
development
Figure 2 shows the flowchart of the differential protection scheme with its harmonic blocking mechanism. The input of the protection scheme consists of the differential signal and the logic signal used for sampling process in ‘sample and hold’. The logic signal that has been used for the sampling process is a continuous square wave with a frequency of 600 Hz, generated with the help of a square-wave generator. The program starts with a checking routine for the status (whether high or low) of the logic signal. As soon as the low status of the logic signal is detected, the microprocessor starts analogue to digital conversion of the sample of the differential signal held in the sample and hold.
cl
Delay of
I
sample
Figure 1.
Digital
filters for calculations
of 1st & 2nd harmonics
Microprocessor based harmonic restraint differential protection scheme
1
Set counter
KI =I2
171
I
1 Set AMP OF IDIFF = 0
I
i Set counter
K2 = 0
2
4
3
Test for the status (high or low) of the logic SIgnal
1
I Do A/D cowerslo”. shift down the level and store the sample
Make the sample positive if 11IS negative and update the omphtude
I
I
I
Filter 1st and 2nd harmonics magnitudes
and store their
I
G I+
output Inrush signal
Compare 1st and 2nd harmonics Is Inrush present?
Is internal fault? YES Increment
K2
NO
output trip sbgnal
3<
Figure 2.
Flow chart
of the protection
scheme
After conversion, it stores this data at some specified memory location. Continuing in this manner, 13 consecutive data-samples are obtained, following which the program moves on to the calculation of first and second harmonics. While storing the datasamples the amplitude of the differential signal is also stored. After calculation of first and second harmonics it compares their magnitudes. If the magnitude of the second harmonic is greater than 16% of the magnitude of the first harmonic, inrush is assumed. When inrush is detected, the microprocessor generates an analogue signal by means of digital to analogue conversion giving an indication signal to the inrush. The program then returns to the checking routine and takes the next sample.
172
R. K. Bnnsal et al.
This whole process is repeated and checking is made for inrush or internal fault by comparing the amplitude, in the latter case with a selected threshold value. If an internal fault is detected in two consecutive samples, a trip command is sent and the execution of the program is terminated. The total time of the decision taken by the relay including sampling time, A/D conversion time and calculation time is approximately 26 us, i.e. about one and a quarter of a cycle.
4.
Implementation
of differential
protection
Figure 3 shows the scheme of the microprocessor system that has been used for testing the implemented protection algorithm. A 5 KVA, 220 V/220 V single phase transformer is connected by means of current transformers, one on either side, to a low resistance of high current rating such that the difference of the primary and secondary currents flows through it. The value of the resistance is chosen from consideration of the maximum magnitude of the inrush current expected and CT ratio. Also, since the analogue signal should be unipolar (a constraint imposed by the A/D converter used) a level shifter is used to shift the differential voltage signal by 2 V. Thus, the shifted differential signal, which is unipolar, is now fed to the A/D converter. In the program, a provision is made to lower down the values of all the samples by 2 V so that the original waveform can be obtained before starting any further processing. The circuit of the level shifter used is shown in Fig. 4. The microprocessor system used has been built around an Intel 8088 microprocessor. The processor operates with a 10 MHz clock frequency. The multiplexer (MUX), A/D and D/A converters are controlled by software. The A/D converter used is a 1Zbit converter. The whole execution of the protection algorithm takes place in less than 1666 us. At the end of one execution cycle, the program jumps back to the checking routine.
5.
Observations
and test results
During the execution of the program, the following types of data are stored: (i) maximum magnitude of the signal in one cycle; (ii) magnitude of the first harmonic in Control
bus
t DIfferentlo slgnal
Level shifter
-
Sample and hold
V
Figure 3.
Block diagram
V
PP
M U
RAM ROM
-
ADC
of microprocessor
Inrush
system used
Microprocessor based harmonic restraint differential protection scheme
T
173
+Vcc(‘5“)
OUi 3.2
K
560
0
/
0
L 7
Figure 4.
L-l
Level shifter
one cycle; (iii) magnitude of the second harmonic in one cycle; (iv) fault counter for confirming the internal fault condition. Some of the waveforms taken from the CR0 are as shown in Fig. 5(a,b). The figure gives a clear picture of the sampled signal that is actually fed to the microprocessor unit. The periods of sampling and holding of the signal by S/H can be clearly seen. On the basis of observations obtained during the tests performed in the laboratory, some relevant results obtained are tabulated in Table 1. For a simulated condition corresponding to an internal fault, the fault counter value is 2 while under no fault and
A + f +
(31
0-I V div“ 5 mS dlv-’
(4)
A + f +
Figure Sa.
Oscillogram
of actual
signals fed to the microprocessor
20 mV dlv-’ 5 mS dw-’
1. 2. 3. 4. 5. 6. 7. 8.
S.N.
OOOA 0097 0062 oooc 0012 0084 0024 005F
HEX value
10 151 98 12 18 132 36 95
DEC value
Magnitude of 1st harmonic (I,)
0001 0001 0000 0000 004D 0063 0024 0039
HEX value
1 1 0 0 77 99 36 57
DEC value
0084 OOc5 OOAC 0017 OlB3 0131 0107 0159
____._ HEX value
Max. magnitude
132 197 172 23 435 305 263 345
DEC value
among
160 240 210 28 530 360 320 420
Equiv. voltage (mv) 0000 0002 0002 0000 0000 0000 0000 0000
Fault counter value W
conditions
13 samples
Test results obtained for d@erent simulated
Magnitude of 2nd harmonic (I,)
Table 1.
10 0.66 0 0 428 75 100 60
% of 2nd harmonic &/I,)%
No fault Fault Fault No fault Inrush Inrush Inrush Inrush
Result
Microprocessor based harmonic restraint differential protection scheme
A -0.1 f -5mS
(5) I-
V dw-’ div“
A f -+
( 6)
175
0-I V dlv-’ 5 mS div.’
f r
r
I-
II-
L
r
L ___ _- --
L L c
r
r r-
A -0-I f -
(7)
V dw-’ 2 mS div-’
(8)
7-
r/
A f c
L
f
L L
r
r
r -
L
-
50 mV dlv-’ 5 mS div-’
Figure 5b.
_---
-r
r
L
_-I_-
L L -*
Ie/-
Oscillogram of actual signals fed to the microprocessor
inrush current its value is zero. In case of inrush, the second harmonic content is greater than 16% of the first harmonic.
6.
Conclusion
A microprocessor based differential protection with inrush restraint has been designed, fabricated and tested. The system continuously monitors the signals and gives a trip signal as the fault occurs. However, under switching inrush current condition an indicating signal, rather than a tripping output is sent. The test results, as given in Table 1, indicate satisfactory performance when compared with similar work reported in the reference.
References 1. Computer Relaying. IEEE Tutorial Course, 79 EH0148-7-PWR. 2. A. G. Phadke. April 1980. Recent Development in Digital Computer Based Protection and Control in Electric Power Sub-station, presented at Conference on Power System Protection, The Institution of Engineers. Madras, India. 3. L. F. Kennedy & C. D. Hayward. 1948. Harmonic-Current-Restrained Relays for Differential Protection. AIEE Trans., Vol. 67, Part II, pp. 1005-1022. 4. C. A. Mathews. 1954. An Improved Transformer Differential Relay. AZEE Trans., Vol. 73, Part III, pp. 645-650.
176
R. K. Bansal et al.
5. K. L. Sharp & W. E. Glassburn. 1958. A Transformer Differential Relay with Second Harmonic Restraint. AZEE Trans., Vol. 77, Part III, pp. 913-998. 6. J. A. Sykes & I. F. Morrison. 1972. A Proposed Method of Harmonic Restrained Differential Protection of Transformers by Digital Computer. IEEE Trans., Vol. 91, pp. 12661273. 7. M. S. Jamil-Asghar, M. Mohibullah & M. Salman Beg. 1986. A Solid State Relay for Transformer Switching. International Journal Electronics, 61, 539-542. 8. B. T. Desai, H. 0. Gupta & M. K. Vasantha. 1989. New One Cycle Static Blocking Scheme for Inrush in Differential Relay. ZEE Proc., Vol. 136, Pt. C, No. 1, pp. 48-54. 9. B. T. Desai, H. 0. Gupta & M. K. Vasantha. 1988. New One Cycle, Microprocessor Based Differential Relay for Transformer Protection. Journal Microcomputer Applications, 11, 135-144. 10. A. J. Degens & J. J. M. Langedijk. 1985. Integral Approach to the Protection of Power Transformers by means of a Microprocessor. Electric Power and Energy Systems, 7, 3746. 11. J. S. Jhorp & A. G. Phadke. 1982. A Microprocessed Based Three-phase Transformer Differential Relay. ZEEE Trans., Vol. PAS-101, No. 2, pp. 426432. R. K. Bansal originates from Dehradun, India. He obtained the B.Tech. degree in Electrical Engineering from Banaras Hindu University, India in 1990. Presently he is working in Reliance Petrochemicals Ltd., &rat, India.
B. K. Josh originates from Dehradun, India. He obtained the B.Tech. degree in Electrical Engineering from Banaras Hindu University, India in 1990. He then worked in Reliance Industries Ltd., Raigad, India.
Dr. S. P. Singh was born in Varanasi, India, on September 5, 1957. He received the B.E.(Electrical) and M.E.(Electrical) degrees from Allahabad University, India, in 1978 and 1981 respectively and PhD from Banaras Hindu University, India in 1990. He joined the Department of Electrical Engineering, BHU in 1981 where he is presently working as Senior Lecturer. His main research interests are in Load flow, sparsity techniques, expert system and microcomputer applications to Power System problems. Dr. R. N. Bandopadhaya was born at Patna in India on November 18, 1940. He obtained his BSc (Engg) degree from Patna University (India) in 1964 in Electrical Engg. and M.Tech. degree from Indian Institute of Technology, Kharagpur (India) in 1967 with Power Systems Engg. specialization. After working as a Lecturer in Jalpaiguri, Govt. Engg. College, West Bengal (India) for some time, he joined the Institute of Technology, Banaras Hindu University, Varanasi (India) in 1976 as a Lecturer in Electrical Engg. He obtained his PhD degree from the same Institute in 1984 and is presently working as a Reader in the Electrical Engg. Dept. of the Institute. His research interests are in the areas of synchronous machine dynamics and transients and modern trends in power system protection.