New one cycle, microprocessor based differential relay for transformer protection

Journal of Microcomputer COMMUNICATION:

Applications

APPLICATION

(1988) 11, 135-144 NOTE

New one cycle, microprocessor relay for transformer protection

based differential

B. T. Desai, H. 0. Gupta and M. K. Vasantha Electrical India

Engineering

Department,

Universit.v of Roorkee,

Roorkee

This paper presents a fully selective new one cycle microprocessor for transformer protection.

(U.P.) ( 247667.

based differential

relay

The relay was tested and was found to take care of maloperation due to inrush, current transformer (CT) saturation with internal fault, unsaturated CT with external fault, saturation of one CT with external (heavy through fault) or internal fault etc., without sacrificing the performance of the differential relay under genuine fault conditions. The relay behaviour has been extensively tested by arranged circuits for differential protection of transformers in the laboratory for all above conditions.

1.

Introduction

The advent of EHV and UHV transmission and the comparatively high working flux density of transformers, due to the introduction of grain oriented silicon-steel as core material, means that protective devices must be fast reacting. They must detect the magnitude of transient current, normal fault current and fault current with different situations in the system, and discriminate between transient over-current and fault current surely and quickly. in one or two cycles, to produce a blocking or tripping signal as required. The present day harmonic restraint approach in differential protection is not fast or reliable [2,3]. Statistical data show that in 30% of tested cases using this approach, relays operated incorrectly [ 11. The relay developed by the authors is based on a waveform approach. The developed relay eliminates undesired tripping and produces a blocking signal within one cycle as required. For relay blocking during switching and heavy through fault conditions, the presented relay uses the principle of simultaneous occurrence of the instantaneous current magnitude (i) low level (zero) and the rate of change of current (di/dt) magnitude low level (zero) (Figure 1), for initial value of time period of about 30” or 45” from zero crossing of positive rise of rectified difference current wave, compared to the fault current and load current wave-form [Figures l(a), (b) and 51. Hence the important features of the difference current waveform of inrush and heavy through fault are exploited to discriminate between them. The important features of the difference current waveform (a) on inrush, (b) heavy through fault and (c) saturation of one CT with external fault (i.e. low i and dijdt) conditions have been exploited to discriminate these conditions from (d) internal short 135 0745~7138/88/020135

+ 10 $03.00/O

@J 1988 Academic

Press Limited

136

Figure 1. CT primary waveform with normal

and secondary time constant.

waveforms, for inrush. (a) CT primary waveform. (c) CT secondary waveform with higher burden.

(b) CT secondary

circuits and (e) internal short circuits with CT saturation (i.e. high i and di/dt level for first 45” after zero crossing), thereby to provide adequate restraint or tripping accordingly.

Features reponse

2.

2.1

of difference

wave

forms and relay

Inrush

(a) Inrush current wave-shapes magnitude (di/dt) and current zero-crossing (Figure 1) which (b) There is also an opposite rate toward zero falls with the 2.2

current

applied to a relay have low rate of change of current (i) magnitude levels for about the first 40” to 45” after is not possible with a fault current [4]. polarity current due to the CT. Its magnitude and decay rise in CT time constant and vice versa (Figure 1) [4].

Heav_v through fault

The features of the differential current wave under heavy through fault conditions or CT saturation with heavy external fault is similar to the inrush wave form [5] [Figure 6(d)], where this relay is generating blocking, i.e. normal restraining. 2.3

Heavy internal

fault

Under a heavy internal fault the CTs get saturated, yet the wave form of the difference current has considerable values of i and di/dt for about 40” to 60” after zero crossing; hence the relay is not blocked [Figure 2(c)].

Differential relay for transformer protection 2.4

137

Normal internal fault condition

The difference current wave under an internal fault condition is sinusoidal in nature, with or without the maximum value of the decaying d.c. component condition. With the maximum possible decaying d.c. component fault current, the value of transient component at the end of first cycle is 0,882 I,,, (I,,,= peak of fault curent wave). The instantaneous current magnitude level and rate of change of current (di/dt) level for about 40” to 60” are sufficient to operate the relay for an internal fault condition, i.e. not to generate blocking in the relay [Figure 2(a)].

(b)

/

(d)

I-.-Figure 2. (a) Exponentially decreasing cosine curve for fault current. (b) Saturation current. (c) Rectified differential case of an external fault.

current

in the case of an internal

effect of CT on secondary fault. (d) Differential rectified current in the

138

B. T. Desai et al.

2.5

Over excitation

condition

The difference current under an over-excitation condition of the transformer contains only the fifth harmonic, as the third harmonic is precluded by the transformer or CT delta connection and hence a typical two peaks in every half cycle wave. Here the relay is not blocked for over voltage, i.e. the over excitation condition.

3.

Setting

for blocking

scheme

The analysis of CT performance for magnetizing inrush and fault current [4] and its verification with the help of laboratory models [4] and photographs [Figure l(a)-(c)]. shows the influence of CT on inrush. The value of the transient component at the end of first cycle in the worst condition is 0.882 1, [4]. Hence the available minimum peak will be 0.118 Z, (Appendix 1). From the above analysis it is clear that (a) The suggested instantaneous current amplitude level for inrush is lower than (0.118 I,) (CT ratio), and (b) The suggested rate of change of current level setting for inrush is lower than 0.1181 & 29 Note that both the above conditions

A/degree.

should

be satisfied

for inrush.

Figure 3. Oscillographic record of relay scheme. (a) Top: CT secondary waveform of inrush. rectified inrush waveform applied to channels 1. 3 and 5. (b) Top: CT secondary waveform of inrush. one-cycle blocking signal produced by PB7

Bottom: Bottom:

Differential relay for transformer protection

4.

Block schematic

and realization

139

of relay

A biased differential relay function involving comparison of the difference current magnitude with set magnitude for through bias restrain, CT mismatch and excitation current, has been implemented using a level detector and an 8085A processor, along with discrimination for external fault, inrush, internal fault and heavy external fault using software. The operation time for the relay is one cycle (Figure 3(a) and (b)].

5.

Relay hardware

The block schematic of the relay is shown in Figure 4. The required signals for biased differential relaying are derived from the CTs, and given to the differential circuits to obtain voltages proportional to the differential current. The rectified differential current signal of phases R, Y and B are then applied to channels 1, 3 and 5 respectively. The rectified differential current signals are also filtered through a filter circuit to get the equivalent dc. voltage. The signals are compared by level detectors. The reference level (B) applied to the level detectors takes care of the difference of current level obtained by CTs mismatching, normal no load current and through current biasing. The outputs of these level detectors are fed to channels 0, 2 and 4 in sequence. The output of differential current circuit of phase R is fed to zero-crossing detector. The square-wave output of the zero-crossing detector is fed to a rising edge triggered monostable to get an interrupt pulse, utilized to initialize the 8085A. Whenever there is a fault/inrush the signal at one (or more) of the channels 0,2 and 4 becomes high. This is indicated by the zero (LSB) bit-line of port B (PBO) initialized as an output port. The rectified outputs (unfiltered) of the corresponding channels (1, 3. 5) are sampled with proper delay and stored [in M(HL)]. After processing the samples, if necessary a blocking signal would have generated by PB7 as an active high, which actuates the slave relay of breaker trip circuit and the alarm circuit. PBO is used as an interlock for PB7 to achieve reliability and to avoid maloperation (Figure 4). The practical approach to setting the required level of Kl (i) and K2 di/dt) is clearly understandable from Figure 5. The values of Kl and K2 depend on the selected time interval between zero crossing to sample one (SMPl) and the time interval between sample one (SMPl) and sample two (SMP2). The praposnate value of Ai magnitude for an inrush wave with time interval of 1 ms is 07 H. Hence di/dt for inrush is 07 H/ms. Similarly for fault current it is 19 H. Hence the dijdt for fault current is 19 H/ms. Therefore the suggested value of K2 is slightly higher than 07 H/ms and lower than 19 H/ms, but it should not be lower than the di/dt value of a normal transformer load current. The praposnate current i magnitude level is decided by the SMPl value of inrush and fault current. The SMPl value for a fault is 4B H. Hence the Kl value is higher than 13 H and lower than 4B H but the K 1 value should not be lower than the SMPl value for a normal transformer load current. Similarly for a 2 ms interval, the computed values for K I and K2 (see Figure 5) are 13 H
140

B. T. Desai

et al.

Differential relay for transformer protection

141

I Time kns)

I msdelay-

\

Fault i,=k5V, 12=2V, A;/df=lSH, /=4ElH Inrush il=0.25V, /;=0.38V, A;/d1=07H/ms, i=l3H 2 ms delayFault i,=,2.3V, &3,5V, Ai/dl=07H/ms, i=73H Inrush /,=0.38V, iz=0.75V, Ai/df=9H, i=l3H

Figure 5.

6.

‘,

Waveform

at channels

\

/ \,

/

//

,I’ \ ___’ ’

I, 3 and 5.

Relay software

The relay software monitors the output of the level detector from 0, 2 or 4 channels continuously in sequence. If any of these outputs is high, PBO is immediately made active high, and two samples at 2 ms (or 1 ms) intervals are taken immediately, providing the proper delay, after zero crossing of unfiltered output of that particular phase and are stored in M(HL) (i.e. channels 1, 3 or 5). The current level and rate of change of current, after zero crossing, as shown in Figure 4, of respective phase is computed from samples. The computed i level and di/dt levels are then compared with the set levels, Kl and K2. If the i and di/dt levels are lower than the set levels, blocking is provided by PB7 as an active high and will be latched for the required duration using a delay (Figure 6). If any one of, or both the i and di/dt levels are high, an interrupt is enabled and the processor goes into a HALT state, waiting for the interrupt. The CPU engagement for the above operation is about 3 to 5 ms. A reduction in time up to 1 ms can be achieved by using a hardware delay.

7.

Conclusion

A low cost, fast and simple structure relay based on a single chip microprocessor has been developed. This relay is attractive for large and medium size power transformers for fast and reliable protection.

Enable

Initlollze

6.

(6 5)

program-

Figure

interrupt

ports,

Program

tlow chart for the relay, (a) Main program

(b) Main differential

in A

relay program.

Cc)

give

(c) Inrush

1 Inrush,

subroutine

blocking

& Find rate of change of current kWAt)a/ms

(AI)

variation

current

Find

Y

Toke two samples at the ntervol of 2 ms afterzero crossing of the rectified (Y phase) difference current and swe

Take two samples at the nterval of 2 rns after zerc crossing of the rectlfled CR phase) difference current and save

L

Y

R

program

Return

Fault, give trip signal 4,

Take two samples at the Interval of 2 ms after zero crossing of the rectified (6 phase) dtfference current and save

6

a 5

4

rl

F

Differential

relay for transformer protection

143

References 1. A. M. Fedoseev 1961. Osnwy Velgoni Zushchity. Gosenergaizdat. differential relay with second-harmonic 2. K. L. Sharp & W. E. Glassburn 1958. A transformer restraint. Transactions of the AIEE, 77 (Pt III). 913-998. 1972. A proposed method of harmonic restrained differential 3. J. A. Sykes & I. F. Morrison protection of transformers by digital computer. Transactions qf the IEEE, 91, 1266-1273. 4. B. T. Desai & H. 0. Gupta 1987. A simple laboratory method to study the magnetising inrush current patterns for power transformers, Proceedings ITMA International Conference on Transformers 13-14 February, New Delhi. 5. L. F. Kennedy & C. D. Hayward 1937. Harmonic current restrained relays for differential protection. Transactions qf the AIEE, 262-270.

B. T. Desai obtained a BE in electrical engineering from SV Regional Engineering College, Surat and an ME in power systems from Birla Engineering College, Vallabh Vidya Nagar (Gujarat) in 1980. He is working as Assistant Professor in Electrical Engineering at the Birla Engineering College. Has published several research papers. Currently he is working towards the PhD degree at University of Roorkee under the QIP Scheme. His research interests are in the area of on-line application of microprocessors and computers to power systems protection and control.

Dr H. 0. Gupta obtained a BE in electrical engineering from Government Engineering College, Jabalpur, an ME in systems engineering and operation research and a PhD from University of Roorkee, Roorkee, in 1975 and 1980 respectively. Following graduation he worked as a lecturer in the Electrical Engineering Department of MACT Bhopal. Presently he is working as a reader in electrical Engineering Department of University of Roorkee, Roorkee. He visited McMaster University, Hamilton, Canada from 1981 to 1983 as a post doctorate fellow. He has published a number of research papers, technical reports and development technical software for mainframe and microcomputers. His research interests are in the area of computer aided design, reliability engineering, power network optimization and power transformers.

M. K. Vasantha obtained a BE in electrical engineering from IISc. Bangalore and an MTech in control and drives from IIT, Bombay. He is presently working as a reader in the Electrical Engineering Department, University of Roorkee. Roorkee. His research interests are in the area of microprocessor and computer application to control systems. He has published a number of research papers, technical reports and developed technical software for mainframes and microcomputers.

144

B. T. Desai et al.

In fault, the primary i, = I,[sin(wt

current

of the CT is given by

- a) - sina e _I’]

where T= Primary circuit time constant (L/R) a = Angle at which fault occurs. The magnetizing current for the above primary

current

is expressed

as

LR2 --[sin(wt + x - A) - sin(a - A)e-’ ‘1 lm=;Rf+

L2w'

- I,[T/( T- T,)]sina(e- ’ ’ ~ e “‘I)

and iI = I m(cos co-

e--l”).

But the secondary

current

i2= i, - i, and z, = ~LW T,=(L,+LJIR> A=tan-,w(L,+ T= L/R i2= I,,,[cos Simplifying

L,) 4

wt-

(Rz/Z,)cos(wt - A) + ( Rz/Zz)cosA - e-‘:Q] + f,,,[T/( T- T,)](em”’ -e ml‘1)- I,e

the equation,

expanding

i,=I,[Lw/Z,sin(wt-A)+(Rz/Zz)Le~l’?l+

the exponential

and neglecting

higher order terms,

t/T,-e-“‘1.

(2)

for I= 2@j,

i, zz - I,e-““‘“‘!r;

for T,=O.l.

6=90”,

w=314.

i,=1,,,(0.2301 -em2”!“‘);

for T,= 0.4, iz = 1JO.058575 - eL”‘“‘); for t=2n/w+t, T= 0.1 s or 0.4 s At = 0.001 s and assuming

X/R = 50. The value of i, from equation

(1) is

iz z 0.882 I,,,. Therefore

at the end of the first cycle the transient

‘,I. (I)

component

has the value O-882 I,,,