Modelling co-operative knowledge systems in design

EngngApplic. Artif. Intell.Vol.4, No. 2, pp. 109-119, 1991 Printedin GreatBritain

0952-1976/91 $3.00+0.00 PergamonPresspie

Contributed Paper

Modelling Co-operative Knowledge Systems in Design R. S A D A N A N D A Asian Institute of Technology, Bangkok N. M A N I Asian Institute of Technology, Bangkok

Understanding co-operative knowledge systems is becoming a central issue in A I research. The questions centre around the complexity of managing separate knowledge sources in terms of heterarchical and hierarchical organisation structures, and convergence of the planning and design cycles. Engineering design is characterised by no predetermined solution path and by the integration of multiple domains of knowledge at various levels of abstraction. A conceptual blackboard architecture is introduced to model co-operation among disparate knowledge sources associated with engineering design on a software framework. A trade-off approach brings in co-operation among the disparate knowledge sources. For pedagogical purposes, the floorplanning of VLSI circuit design is simulated using the framework. Keywords: Artificial Intelligence, blackboard, CAD, co-operative knowledge systems, engineering design, floor planning, message passing, multi-blackboard, VLSI.

INTRODUCTION

knowledge, being exchanged at greater speeds between the subsystems of the manufacturing process. A number of technical reasons, including the advances One area that deals with a large amount of domainin processors and communication systems, are directing specific knowledge and a considerable amount of research efforts towards the development of techniques problem-solving skill is the area of engineering design. for co-operative problem solvers. Additionally, the The engineering design problem falls under the class of need for co-operation is inherent in many of the probsynthesis problems. It is characterised by a large solulems that Artificial Intelligence researchers are tion space and a sequence of decision-making steps at attempting to solve. AI problems are often spatially each state in the solution space. The design problem and conceptually distributed: spatially distributed as in takes as input the specification of the desired functions the case of multiple machines working in a factory and the constraints on the artefact, and produces as environment or multiple computers in a network output the specification of the structure of the artefact attempting to solve a problem, and conceptually (or that realizes the desired functions and satisfies the functionally) distributed as in the case of a group of constraints. Thus, engineeering design can be characexperts sitting together in a committee to settle a terised as a constrained function-to-structure mapping, problem. The development of expert systems with high and can be viewed as a process of configuring a system performance ratings necessarily brings in the question which will satisfy a number of requirements arising of integrating them to achieve a set of global goals. It from many different sources. Most engineering design has been suggested that the future of expert systems involves a large number of design components with development would be severely restrained by conflicts multiple technologies. For example, in the aircraft in plans, strategies and methods as well as by inconsisindustry, designing an aircraft involves the integration tencies in multiple sources of knowledge. Further, one of technologies from metallurgy, aerodynamics, elecof the effects of increased automation in the manufactronics and communication. Thus, a complex engineerturing process is the increased integration of individual ing design involves design teams, each specializing in a machines within the manufacturing system, resulting in specific field. A computer-aided design approach is a need to handle greater volumes of information and being extensively adopted for complex engineering design problems. At the macroscopic level, the comCorrespondence shouldbe sent to: R. Sadananda,ComputerScience plexity of design tasks requires wider pooling of funds, Division, Asian Institute of Technology, GPO Box 2754, Bangkok-10501, Thailand. talents and other kinds of resources. The participation 109 EAAI

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of large design teams brings the need to communicate design decisions in an interactive manner. At an international level, for example, the formation of the Semiconductor Research Corporation (SRC) is an effort to bring in co-operation between organizations. It should be noted that an era of collaboration among competitors has arrived, where almost every vendor of semiconductor products is now engaged in at least one multi-company collaboration to develop new processes, tools and technologies. The increasing number of knowledge sources contributing to design decisions makes it necessary to represent design objects in multiple-re'presentation paradigms. The problems of co-operation between various knowledge sources, and the issues involved in processes with different local goals working together, have significance at both the microscopic and the macroscopic levels, beyond the technical domains. Thus, we move to other reasons for modelling such systems, viz. social and philosophical ones. To model concepts such as cooperation, conflict, negotiation, trade-offs and bargaining would have a bearing in social science, philosophy and other disciplines. A detailed discussion and a comprehensive review of various approaches to achieve co-operative problem solving have been presented in Durfee et al.'- During the last few years, blackboard-based systems have become popular. Blackboard systems have been built to solve many real-world problems. 3 Reviews of various blackboard implemenations are available in Refs 4 and 5. A blackboard model for maintenance management of shopfloor machinery is presented in Refs 6 and 7, and its application for distributed problem solving is discussed in Ref. 8. A contract-net framework for cooperative modelling, discussed in Ref. 9, adopts the Manager-Contractor formalism to divide a complex task into subtasks, and maintain coordination among the subtasks. Negotiation as a co-operation strategy in resolving conflicts in the air-traffic control domain is reported in Ref. 10, and in the cognitive modelling domain in Ref. 11. A functionally-accurate, cooperative (FA/C) approach for co-operation between distributed network nodes and its implementation on a Distributed Vehicle Monitoring Testbed (DVMT) is reported in Ref. 12, while a co-operative approach for office automation is given in Ref. 13. A critical discussion of various kinds of schemes of co-operative knowledge management in addition to the blackboard scheme has been brought out in Ref. 2. From these examples, it is clear that only a fraction of the effort in this area has gone into engineering design. The field of VLSI circuit design is a resource;ntensive engineering discipline.t4 About two thousand years after the Iron Age, the Silicon Age has arrived. Silicon-based tools are now being sought to replace intellectual power in a manner similar to stone and iron tools replacing muscle power. The electronic devices are becoming increasingly powerful as they are becom-

ing smaller. The market potential for innovative design is very large and the world-wide competition is intense. Even small errors in manufacture can lead to disastrous consequences, and the potential for large gains is associated with high risks. On account of the fast-changing world scenario, market windows are short. That explains the world-wide interest in VLSI design activity and attempts at co-operation between groups which usually compete in business, as has been pointed out earlier. CO-OPERATION BETWEEN K N O W L E D G E SOURCES IN VLSI DESIGN

On the technical side, there is a high demand to increase the designer's efficiency. This can be achieved only if there are efficient means to handle the vast amounts of knowledge associated with all aspects of technology. In general, the conventional design of an integrated circuit consists of three major design phases,t~. 1~viz. the specification phase, leading in turn to the synthesis phase, and the physical design phase. Each of the design phases comprises many subtasks. However, several rounds of iteration are required before a design is acceptable. Further, the "chip development" cycle includes the manufacture. As the complexity of the chip increases, the redesign problem, which often arises at the time of manufacture (and often even after that), becomes severe. As in any other domain, two approaches to design are philosophically identifiable. In the bottom-up approach, the designer starts at the transistor or gate level and designs subcircuits of increasing complexity, which are then interconnected to realize the required functionality. In the top-down approach, the designer repeatedly decomposes the system-level specifications into groups and subgroups of simpler tasks. The lowestlevel tasks are ultimately implemented in silicon, either with standard circuits that have been previously designed and tested, or with low-level circuits designed to meet the required specifications. During the design process, three different representations, namely behavioural, structural and physical, are commonly used to show different aspects of the system under design. ~7 Behavioural representations describe the circuit functions in terms of Boolean and algorithmic expressions. Structural representations describe the composition of the circuit in terms of cells, components, and interconnections among the components. Physical representations are characterized by information used in the manufacture or fabrication of physical systems. The VLSI design involves mapping the behavioural representation into the physical representation. These representations divide the entire VLS1 design space into three axes of a tripartite model (Y Chart), which meet at a common vertex as shown in Fig. 1. The three axes are divided into hierarchical levels of abstraction, with the highest level at the outermost concentric circle and

R. SADANANDA and N. MANI: CO-OPERATIVE KNOWLEDGE SYSTEMS

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T O P O L O G I Z E W 9 for CMOS leaf cell layout generation and F L U T E 2° for custom integrated circuit floorplanning are examples of the many attempts at developing knowledge-based C A D tools. Each is aimed at a specific subtask in the design space. Ulysses 21 and Cadre 22 are systems developed for custom-integrated circuit-layout management. These systems manage different CAD tools in a co-operative design environment, but lack sophisticated hierarchical control.

~ \~ ~~at~e/\ "(-P)/c allestimTs,details// FLOORPLANNING IN VLSI CIRCUIT DESIGN

J physicalpartitions Physical Fig. 1. The VLSI circuit design representation model. the lowest level near the common vertex. CAD tools are used to transform the design subtasks from one axis to another, or from one level to the next lower level on the same axis. The decisions taken at any design stage will have an impact at the subsequent stages. During the initial synthesis stage, for example, the decisions taken at the functional circuit modules concerning the aspect ratios and I/O pin positions would affect the final chip in terms of overall area, interconnection density and electrical characteristics. Therefore, it is worthwhile to look at VLSI design as an activity involving decisions at various levels in a three-axis space, with these decisions mutally interacting. Automation of the complex design flow calls for a new model that reflects the interactions amongst the several stages in the design. The model should be such that it captures the expert designer's thought process while scheduling the design. Having just a set of C A D tools to solve the design steps may not be the best approach for arriving at a model because most of the tools could be efficient in their specific domains, but rarely solve the problem in a way that human experts do. Also, the lack of a capability to model the interaction amongst the subtasks of the design, results in a design that is much less efficient compared to one compiled by an expert human designer. A direct consequence of this is a need to backtrack and iterate the design flow. This naturally increases the design turnaround time. A mechanism is also needed to coordinate the action taken by many experts, and to take care of any conflicts that may arise in scheduling tasks. Efforts have been taken to develop knowledge-based C A D tools for the synthesis, analysis and physical design phases of the VLSI design. The design automation assistant D A A TM for synthesising computer architectures from algorithmic descriptions,

As seen in Fig. 1 and the discussions above, there is a need to develop a n architecture for the overall design of VLSI in terms of a large system of cooperating knowledge sources. Given the complexity of such a project, with the present state of our understanding of co-operative distributed knowledge sources and their interactive behaviour, such an idea is conceptually and computationally prohibitive. For the purposes of this paper, we discuss the design of a floorplan which has received considerable attention. There are a number of advantages in attempting to model the floorplan in terms of co-operating knowledge sources and the interactions between them. With the rapid development of semiconductor technology, the critical bottleneck in the design appears at the physical design stages. This partly explains why there is a great interest in the area among the VLSI community. Further, the floorplan design calls for know-how at various levels in the Y-chart representation model and all the dimensions in the same level. Therefore, this is a reasonably rich area in which to try modelling cooperative knowledge sources. We consider floorplanning as the process of intelligently assigning dimensions to the functional modules, and placing the components on a silicon base that will satisfy most of the design constraints and provide acceptable chip boundaries and good estimations of wirelength. A reduction in chip area will have positive effects on the yield of the chip, but can produce negative effects on the power dissipation. ~6 Similarly, reductions in wirelength will have positive effects on the signal propagation delay, but can produce negative effects on the chip area. A trade-off in arriving at a design solution becomes necessary. The human designer, in general, performs the floorplan task easily as a result of possessing and manipulating a huge amount of knowledge, gained by experience, which cannot be coded on algorithms. The quality of this knowledge differentiates between novice and experienced designers. A number of floorplan methods have been reported in the literature, including the force-directed approach 23 the min-cut/slicing approach, 24,25 rectangular dualization 26 and simulated annealing approach. 2v The force-directed approach models an attractive force F between two modules connected by nets as the

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n u m b e r of c o m m o n connections times the distance between the two modules. This approach assumes modules as point objects, and hence a scheme must be devised to prevent overlap in modules with irregular dimensions. In the rectangular dualization approach, a layout structure graph is first transformed into a planar graph and an optimal rectangular dual is sought for the planar graph. This approach may not be readily modified to take into account various constraints. A divideand-conquer scheme is used in the min-cut/slicing approach. The slicing structure is resistive in area utilization, but the slice-line forms a cyclic-constrainfree routing channel and provides easy routability of the nets. The simulated annealing approach is computation-intensive and may not be readily adapted to deal with various constraints. The automation of the floorplanning process has been the subject of research, and many algorithms have been proposed. ~'~'2'~ In this paper, we describe the authors' efforts in modelling co-operation among the disparate knowledge sources involved in the VLSI design situation, particular to floorplanning. It is necessary to recognise that physical design involves several subtasks which when described in abstract terms would prove to be NP hard. It is therefore instructive to attempt a model for a co-operative knowledge-based approach to some of these subtasks.

circuits. The net representation also includes multiterminal nets. The resulting floorplan has rectangular dimensions. Partitioning a set of functional modules in a circuit implies dividing the modules into two subsets of modules. Let the set Z of modules in the circuit be partitioned into two subsets of modules A and B. Then we have A c Z ; B = Z ; A N B = ~ ; A U B = Z . The cutset is the set of nets that contains modules in both A and B of the partition. Slicing is the process of cutting a rectangular region into two smaller rectangular regions by either a horizontal or a vertical line segment. The line segment is called a slice-line or cut-line. The slicing operations are repeated for each newly formed rectangle, with the slice-line direction chosen to be perpendicular to the previous slice-line. A channel graph, G = (V, E), is an undirected graph where each edge, e • E, corresponds to a cut-line, and each vertex ~ • V, corresponds to either the intersection point of a horizontal and a vertical cut-line, or one of the four corners of the slicing structure. A slicing structure is the assignment of modules which satisfies the slicing criteria. A slicing tree is an ordered tree for describing a slicing structure. Each parent node of the tree has an associated slice-line direction (horizontal or vertical) and represents a bounded chip region.

Terms and notations

We explain the terms used in our discussion in this section. A cell is a primitive element that will perform certain basic logic functions like A N D , O R , N O T , N A N D and N O R operations. A functional module consists of one or more types of cells interconnected to perform the required function. Each module has signal points for interconnections between modules. The aspect ratio of a functional module is the ratio of width to length. A net represents a set of electrically equivalent signal points that need to be interconnected in the circuit. A net consists of at least two electrically equivalent signal points in the circuit and each signal point in the circuit is in only one net, that is, nets are disjoint. A net is called a multi-terminal net if it consists of three or more signal points. A V L S I circuit is a network consisting of a set of functional modules interconnected by a set of nets through the signal points. The floorplan model consists of a VLS1 circuit with a set M of functional modules and a set N of nets. All the functional modules are assumed to be rectangular, with known and unknown dimensions. The knowndimension modules have either a single aspect ratio (fixed modules) or multiple aspect ratios (flexible modules). For the unknown modules, the dimensions have to be estimated from their low-level functional

A CO-OPERATIVE MODEL FOR FLOORPLAN DESIGN IN VLSI C I R C U I T S

The model has been conceived with the view that VLSI design in general, and floorplan design in particular, can best be handled through an effective and efficient co-operation of multiple knowledge sources. Therefore, an important issue was the design of a model that would facilitate the interaction between the different knowledge sources. Various paradigms have been proposed to deal with co-operation between multiple knowledge sources as blackboard model, ~ contract-net model, ~ and scientific community model, to name a few. z It was decided here to use the blackboard model, which suits the complexity of VLSI design better than the other paradigms. Further, such a model allows the addition and substitution of knowledge sources and the exploration of different control and communication strategies. The VLSI design task has been decomposed into subtasks, and Knowledge Sources (KSs) are modeled to solve each sub-task. A KS is viewed as an agent that contains knowledge of a particular aspect of the domain problem, and is useful in solving that problem by taking action based on its knowledge, so as to make a contribution to the overall solution. The KSs are hierarchically organized, and a multiple-blackboard architecture has been proposed to provide communication channels among the KSs, as shown in Fig. 2. This hierarchical

R. S A D A N A N D A and N. MANI: C O - O P E R A T I V E K N O W L E D G E SYSTEMS

structure provides a convenient way to decompose design tasks into sub-tasks and sub-sub-tasks till a manageable size is obtained. The knowledge source representation We represent a KS as consiting of two kinds of knowledge: metaknowledge (i.e. knowledge about knowledge) and domain knowledge. The metaknowledge consists of knowledge about information exchange and knowledge about data transformation. During execution, a KS always needs to exchange information with other KSs in order to co-operate. When and how to do this are entirely determined by using the information exchange knowledge. The data transformation knowledge is used to interpret information sent by other KSs, because different KSs use different representation schemes. The domain knowledge is the main body of the knowledge that a KS possesses. It represents the domain knowledge necessary to accomplish the tasks from the domain. A multi-blackboard architecture We propose a multi-blackboard architecture to provide communication channels among KSs at different levels. The reasons for this architecture are the following: 1. The multi-blackboard architecture is the most suitable for the hierarchical organization of the KSs that has been proposed. 2. A single blackboard will become a bottleneck when the number of KSs increases. 3. Since each blackboard contains a relatively small amount of information about a complex task, the architecture will be able to reduce information complexity. 4. Managing the multi-blackboard architecture is easier than managing a single, large blackboard because the management can be spread over several KSs. As can be seen from Fig. 2, each blackboard is shared among KSs at any level, such as BB~), BB,, BB~. The blackboards provide communication channels among KSs at the same level, and they are also bridges between different stages of analysis. For example, KSH, KS~2. . . . KS~u exchange information through BB~, so that they can co-ordinate with each other. After they obtain some result, KS. will collect them from BB~. If these results are useful for other high-level KSs such as KS2, KS3 . . . . KSA, they will be transferred to BB() for exchange at higher levels. Finally, CS~ summarises the results on BB0 and will give the final results. From this paradigm, it can be seen that the intermediate results from KS at a certain layer are stored on the blackboard at the level. Only those intermediate results which may be useful for higherlevel analysis are transferred by a higher-level KS to the blackboard at the higher level. Irrelevant information will never appear in the higher-level blackboard.

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This approach is similar to data hiding in software engineering. In order to provide effective inter-KS communication, each blackboard is considered to have one public area and several private areas. The number of private areas depends on the number of KSs attached to that level. Each private area corresponds to a KS, as depicted in Fig. 3(a). A private area may be further subdivided into two sections: a local section and a global section, as shown in Fig. 3(b). Inter-KS communication and control strategies Each KS uses its own private area as its working memory. All intermediate results it obtains are put in the area, in either the local section or the global section. The information in the global section may be read by other KSs, but not that in the local section. If a Ks "thinks", by using its information exchange knowledge, that the intermediate result will be useful to other KSs, then it will put the result in the global section. Otherwise, the result will be put in the local section, and can be used only by that KS. This hides irrelevant information from other KSs. This method is similar to the concept of data hiding in software engineering. All writing operations of the KSs are limited to their private areas. The public area is a special area on the blackboard. Any KS can read information from or write data to the public area, which acts as message board. When a KS finds an intermediate result which is useful to some other KSs, it will put a message announcement in the public area. The contents of the announcement include an abstract of the result, name of the announcer, and names of the possible receivers (those KSs that may find the information helpful) given as: message (sender, information-abstract, list of possible receivers). During execution, a KS checks the message board when it needs help from other KSs. First, it has to find a Top-level control source

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(a)

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Now, based on abstracts], KSL, may not need the information. So KSt2 will not read abstrach~, but will delete its name and then the announcement itself as there are no more beneficiaries. From the above, we have seen that inference among KSs occurs only in the public area. However, there is no possibility of more than one KSs simultaneously operating on the same data. This multi-blackboard approach provides a tradeoff between the efficiency of the blackboard and the amount of data that must be shared.

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message in which it is one of the potential receivers. Then it should check the abstract of information to see whether it is really useful. Finally, if useful, the information is obtained by using the announcer and the abstract as the index. When the receiver and the sender are not at the same level, the information may be put in the receiver's global section or local section, depending on whether or not the information is useful to other high-level KSs. If two KSs are at the same level, the receiver must put the information in the local section of the private area. After a KS reads a message, it deletes its name from the name list of the beneficiaries. The last KS to read, will delete the message after it finishes reading. A simple example is given to show how these strategies work. Suppose at a certain time of execution, KS~ obtains results which it thinks are useful to KS] and KS~2. Also, KS~2 obtains a result that is useful to KS~L, and KSm. Then KS~ and KS]2 will put their announcements in the public area as message(KS,i, abstract,~, (KS], KS~2)), message(KSi2, abstract12, (KS]t, KSm)). Assume that KS~, KSI2, KSm need help from other KSs. Then they may read these two announcements to examine the abstracts. If, after examining the abstracts, KS~ and KSm find that the information is helpful, then they will get access to the private areas of KS~ and KSI2 and read the information from the global sections of KS~] and KSl2. After reading, KS~ and KSm delete their names from the announcements. At this stage, the information in the public area is:

The input description to the system specifies the circuit being floor-planned. It consists of a list of modules, a list of nets interconnecting them and a list of boundary constraints. The net list supports multiterminal nets. To provide flexibility, each module is allowed to have a number of alternative rectilinear dimensions and orientations. The net list contains the connectivity information of all the nets in the circuit. The boundary constraints include the aspect ratios of the modules and preferred module locations. The output gives the position of the modules represented by the (x, y) co-ordinates of the centres and their length, width attribute values. The outer boundary of the floorplan is represented by its length and width. The floor-plan system consists of eleven KSs organised in three layers. There are four blackboards BB,, BB], BB~ and BB3, used as communication channels among the KSs. The basic organization of the system is shown in Fig. 4. The floor-plan sub-tasks were modelled as the following KSs: 1. Hypothesis generator ( H G ) 2. Network partition (NP) 3. Hierarchy tree generator ( H T G ) 4. Topology generator (TG) 5. Boundary shape function (BSF) 6. Module geometry generator ( M G G ) 7. Wire length estimator (WLE) 8. Area utilization estimator ( A U E )

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R. SADANANDA and N. MANh CO-OPERATIVE KNOWLEDGE SYSTEMS

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9. Relative floorplan generator (RFG). 10. Geometry layout realisation (GR) 11. Floorplan evaluation (FE).

Relative floorplan (topology generation) task (RFG) During the relative floorplan design phase, the knowledge sources generate a relative placement of the functional modules by interacting through the blackboard. The human floorplan designer's experience and the knowledge about similar design problems are captured and represented in the hypothesis generator (HG) in the form of facts and rules. From the input description, HG generates the possible topological plan hypotheses that are represented in the form of topological relation constraints. e.g.

groups these functional modules into two groups A and B such that the following conditions are satisfied: 1. The number of nets crossing the cut-line, C(A, B), is as small as possible. 2. The area of the modules in each group is nearly equal. This is equivalent to keeping the difference in module area of the two groups, D(A, B), as small as possible. While partitioning the modules, NP needs to satisfy the above two goals. Since the two conditions are contradictory in nature, we use a trade-off function F(A, B) for the partition A and B. This is given by the weighted sum of the above attributes as

F(A, B)= Wd* D(A, B)+ Wc*C(A, B),

A B O V E ( A L U , MEMORY). LEFT(MEMORY, REGISTERFILE). N O R T H ( R E G I S T E R F I L E , BUFFER).

The above hypothesis gives the guidelines that the A L U module is to be placed above the M E M O R Y module; the M E M O R Y module is to be placed to the left of the R E G I S T E R F I L E module; and the R E G I S T E R F I L E and B U F F E R modules are preferred to be placed in the northen part of the chip. Such design hypotheses are used during the topology assignment to modules. The network partition knowledge source (NP) incorporates a heuristic to partition the functional modules into two groups, such that the total area of the functional modules in each group is nearly equal and the number of nets common to the two groups is at a minimum. The module-partitioning process is considered as equivalent to dividing a rectangular region which is large enough to contain all the modules without overlapping into two sub-regions by horizontal or vertical line segments. The NP repeats the partition process until the partition leads to a single module. At this stage the starting rectangle will have been cut into a set of regions, each of which uniquely corresponds to a single module. The partition knowledge source, NP,

where D(A, B) is the difference in area of the two partitions, C(A, B) is the number of nets crossing the cut-line, and Wd and Wc are the importance attached to the area difference and nets crossing the partitions respectively, and take values in the range [1 to 100]. During partitioning of the circuit modules, HTG generates a hierarchical tree structure to represent the sequence of partition. A node in the hierarchical tree represents the topology frame representation in the intermediate result panel of the blackboard. Each nonleaf node of the tree represents the bounded region which completely encloses all modules in the node's subtrees and the direction of its corresponding cut-line (namely + for horizontal, * for vertical). Each leaf node corresponds to a single module. Figure 5 shows the binary slicing tree and the corresponding slicing floorplan. A slicing tree can be viewed as either a topdown or a bottom-up description of a slicing floorplan. From the top-down point of view, a slicing tree specifies how a given rectangle is cut into smaller rectangles by horizontal and vertical cuts. From the bottom-up point of view, the slicing tree specifies how smaller slicing floorplans are combined recursively to yield larger slicing floorplans. We can interpret the symbols + and * as two binary operators between slicing floorplans. IfA and B are two slicing floorplans, then we can

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interpret A + B = resulting floorplan obtained by placing B on top of A, A * B = resulting floorplan obtained by placing B to the right of A, shown in Fig. 6. This slice tree provides a good representation of the relative floorplan design. The topology of the slice tree depends on 1. Assigning a slice line direction to each non-leaf node in the tree, 2. Assigning the orientation of a child node with respect to the parent node, viz. left, right of the vertical slice line or top, bottom of the horizontal slice line. A number of slicing tree topologies can be generated, corresponding to different sequences of horizontal and vertical slice lines. Since a slice line can be either horizontal or vertical in direction, for a floorplan containing n functional modules, 2 ~'- ~ possible tree topologies can be generated. The hypothesis generator H G guides the assignment of a direction to a slice line from the hypothesis generated from the input description. For example, the hypothesis A B O V E ( A L U , M E M O R Y ) suggest that the slice line direction between these two modules is horizontal, while L E F T ( M E M O R Y , R E G I S T E R F I L E ) suggests that the slice line direction between these two modules is vertical. The KS H T G communicates with H G through the blackboard BB~ for assigning the slice line direction. The tree thus generated corresponds to the floorplan that satisfies the maximum number of given constraints. In the absence of any related hypothesis, H T G will assign vertical and horizontal directions alternately at each partition stage. This enables fairly uniform distribution of the modules. While assigning orientation of the child nodes to its parent node, the T G suggests the possible orientation by placing the modules in a particular order. For example, the hypothesis A B O V E ( A L U , M E M O R Y ) suggests the A L U module above the M E M O R Y module, and hence the M E M O R Y module to the left child and the A L U module to the right child of a tree

B

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Fig. 6. Binary operators for slicing floorplans.

node. Changing the order of the modules in the hypothesis to A B O V E ( M E M O R Y , ALU) would suggest that the M E M O R Y module is above the ALU module, and hence allocates the ALU module to the left and the M E M O R Y module to the right child of the tree node. In the absence of any related hypothesis, the left child of the parent node is assigned to the bottom or left module of a vertical slice line, and the right child of the parent node is assigned to the top or right of a horizontal slice-line.

Geometry realisation task (GR)

Boundary geometry generation During the geometrical realization task phase, the length and width of the floorplan outer boundary and that of individual modules and their position (x, y) coordinates are determined by the boundary knowledge source BSF. Since the input description consists of functional modules with single and multiple dimensions, each module is represented by a set of ordered pairs of real positive numbers (x, y), known as a shape function, where x is the width and y is the length. This shape function is a piece-wise linear function y = f ( x ) as suggested in Reference 20. Figure 7 shows the shape function for a module H that has three possible dimensions (1,4), (2, 2), (4, 1). The shape function describes all possible shapes and orientations that the module can hold. When the order of the (x, y) values is changed, we get an inverse shape-function which is represented by x=g(y). These shape functions are used to efficiently allocate a rectangular region for each module within the slicing structure. The knowledge source BSF traverses the tree in a bottom-up manner (post order) and generates the shape function of each node in the tree. The knowledge source BSF calculates the shape function at a parent node by adding the two shape functions at the children nodes. The composite shape function at the root node will define the set of possible floorplan outer dimensions. The BSF chooses a single (x, y) pair as the boundary dimension that satisfies the aspect ratio constraint.

Module geometry and position generation After selecting a single (x,y) pair of the floorplan and knowing the slice-line direction at the root node, M G G solves the shape-function to find the location of the slice-line at the root. It is important to note that the x-location of a horizontal slice-line is constrained by the bounded region associated with its parent and the ylocation is the only unknown. Similarly, for a vertical slice-line, its y-location is constrained by its parent region and the x-location is the only unknown. The MGG continues the process of solving the shape function for all the non-leaf nodes in the slicing tree and the position of the slice line is determined. As the leaf nodes are reached, its module dimensions, orientation and position are known.

R. S A D A N A N D A and N. MANI: C O - O P E R A T I V E K N O W L E D G E SYSTEMS

117

H = (1,4), (2,2), (4,1).

4

I

I

I

I

I

1

2

3

4

5

,-x 1

2

Fig. 7. Module shape function for three aspect ratios.

Floorplan

evaluation

task (FE)

The evaluation of the floorplan is based on the chip area and wirelength goal attributes. The wire length estimator (WLE) performs a greedy global routing in order to estimate the overall wire length for the nets. Since the slicing structure is employed, each cut-line corresponds to a routing channel. The W L E finds the path length for each net through these routing channels. For a given slicing structure, the W L E generates a channel graph and a wire length matrix WL[i, ]] whose entries specify the cut-line length between vertices i and j in the channel graph. From the wirelength matrix WL, the W L E estimates the path of each net by traversing the edge of the graph using Dijkstra's algorithm as given in Ref. 30. The A U E calculates the boundary rectangle area from the shape function of the root node in the tree to estimate the chip area utilization. The shape function of the root node gives the boundary width and length. Area = boundary width * boundary length The A U E communicates with the W L E through the blackboard to estimate the overall wire length. The wirelength and the chip area reflect the trade-off weights Wd and Wc chosen during the partitioning process. The quality of the floorplan can be studied by assigning different weights to Wc and Wd.

neighbours in A and to modules in B. If a~ is moved from A to B, this will change D(A, B) and C(A, B) and thus affect the trade-off, T(A, B). We should identify the sequence of module movements which would produce overall improvements in T(A, B). A simple heuristic proposes that giving more weight to C(A, B) would lead to a smaller number of wires crossing the cut-line. This would indirectly reduce the overall wirelength. We have adopted the heuristic network partition approach with multi-terminal nets as in Ref. 31. To update the trade-off, we identify a net, called a fundamental net. A net is fundamental, if there exists a single module, on it, which when moved will affect C(A, B). This will occur if and only if either A or B contains exactly one or zero of its modules. There are four cases, as shown in Fig. 8. 1. If a net contains one or more modules in A and zero modules in B, then moving a single one of its modules, a ~ A , will add the net to

C(A, B). 2. If a net contains one or more modules in B and zero modules in A, then moving a single one of its modules, b~eB, will add the net to

C(A, B). 3. If a net contains single module a~ c A and one or more modules in B, then moving a~ will delete the net from C(A, B). 4. If a net contains single module b~ c B and one A

IMPLEMENTATION The co-operative nature of the knowledge sources is well modelled in the relative floorplan task process with the trade-off function. We adopted only two goals, reductions in chip area and in the total estimated wirelength. The heuristic approach begins by randomly partitioning the set of modules Z into two groups A and B and iteratively improving its trade-off T(A, B) by performing a sequence of module movements. At each iteration, two subsets A(s) c A and B(s) c B are identified to be swapped with each other in an effort to produce an improved partition. Consider the case where a single module a~ c A has connections both to its

B

AIB I

I

(1) A

'

(2)

B

(3)

A

(4)

Fig. 8. A fundamental net and its partition.

B

118

R. S A D A N A N D A and N. MANI: C O - O P E R A I ' I V E K N O W L E D ( I E SYSTEMS

t~/

_F?ag]iob~e

I

I

I

I

I

1

2

3

4

5

[ = (2,3),

(3,2)

3I_

.×

2

2

3

Fig. 9. Module shape function with two aspect ratios.

~r,-'//f.

Feasible region

I

I

I

I

t -,.-x

1

2

3

4

5

J = (2,5), (3,4), (4,3).

2

3

4

Fig. 10. Summation of the shape functions.

or more modules in A, then moving bt will delete the net from C(A, B). If a net is not a fundamental one it will not affect C(A, B) by a movement of one of its modules. Thus at each iteration of the heuristic we determine those nets which are fundamental, and update the tradeoff. This greatly improves the partition procedure. The shape function at a node in the tree structure is obtained by summing the shape functions of its left and right child nodes. Figure 9 shows the shape function for the module 1= (2, 3), (3, 2). Figure 10 shows the summation of the module shape function of Figs 9 and 7. The summation occurs for x ~>2, because both functions are defined within this region. In a point-by-point manner, at each x > 2, the corresponding y dimension is summed, producing a composite shape function J = (2, 5), (3, 4), (4, 3). However, we have to take into account the slice line direction while adding the shape function. The shape functions of nodes with a horizontal slice line have to be inverted before adding. The summation process is continued until the root node of the slicing tree is reached. At each summation step, the resulting function is saved in the slicing tree at its corresponding node. Thus, each non-leaf node of the tree will have an associated shape function. The complete chip boundary is computed by post-order traversal of the slicing tree. After choosing the boundary

shape, the shape function at each node of the tree is recursively solved to find individual module locations, and their lengths and widths. CONCLUSIONS The design approach described here involves the use of a blackboard architecture to bring about cooperation among several knowledge sources. The design is evaluated, based on the measure of overall wirelength, and chip area. The floorplan design activity brings in knowledge at various levels of detail and complexity. By adopting a hierarchical multiblackboard architecture, and by providing independent knowledge sources and effecting their interaction, we have attempted to meet these objectives. The developed frame is simulated with two real-world IC floorplan data sets on a SUN 3/60 workstation. In the first case, with 14 modules, 100 pins and 50 nets, the effective chip-area utilization was 78.62%. For the second case, with 22 modules, 180 pins and 78 nets, the effective chip-area utilization was 80.87%. Incorporating more knowledge modules into the floorplan system, and extending the framework to cell placement and routing aspects of VLSI design, are under experimentation. The issues of knowledge acquisition, representation,

R. SADANANDA and N. MANI: CO-OPERATIVE KNOWLEDGE SYSTEMS

and interaction leading to the construction of artefacts brings together a variety of disciplines. These may be o l d , as i n p h i l o s o p h y ; e s t a b l i s h e d , as in m a t h e m a t i c s ; o r e m e r g i n g , a s i n a r t i f i c i a l i n t e l l i g e n c e . T h e V L S I a r e a , in v i e w o f its c o m p l e x i t y , o f f e r s e p i s t e m o l o g i c a l c h a l l e n g e s a n d at t h e s a m e t i m e u n p r e c e d e n t e d c o m m e r c i a l opportunities. Therefore, the long-term objective of this research to model co-operation among the knowledge sources to develop an integrated model for VLSI d e s i g n is w o r t h w h i l e , a l t h o u g h it is a h a r d t a s k .

Acknowledgements--The authors wish to thank Dr Kanchit Malaivongs, Professor H. N. Phien and Professor D. L. van Oudheusden for their helpful suggestions to a piece of research which gave rise to this paper. Particular gratitude is due to Professor M. G. Rodd who encouraged us to develop this paper. The painstaking efforts put in by the unnamed referees are gratefully acknowledged.

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