Modelling of the surface potential evolution for a stressed submicronic MOSFET

MEJ 664

Microelectronics Journal Microelectronics Journal 31 (2000) 91–94 www.elsevier.com/locate/mejo

Modelling of the surface potential evolution for a stressed submicronic MOSFET R. Marrakh, A. Bouhdada* Laboratoire de Physique des Mate´riaux et de Microe´lectronique, Universite´ Hassan II, Faculte´ des Sciences Aı¨n Chok, Km8, Route d’El Jadida, BP 5366 Maaˆrif, Casablanca, Morocco Accepted 12 April 1999

Abstract We propose a model to determine the surface potential evolution for a stressed submicronic MOSFET. Stress conditions are chosen in a manner so that the interface states generated by the hot electron injection at the Si–SiO2 interface are dominant. The stress generated defects vary in time and are simulated by a spatial and temporal Gaussian distribution centred close to the extremity of the channel near the drain. The gaussian parameters (standard deviation and maximum) vary according to the stress time. The surface potential model is derived by solving the two-dimensional Poisson’s equation according to the spatial and temporal charge variation in the channel and electric field during stress time. q 1999 Elsevier Science Ltd. All rights reserved. Keywords: MOSFET; Surface potential evolution; Poisson’s equation

1. Introduction

2. Defect modelling

The degradation of the NMOS transistors caused by hot carrier injection in the oxide and at the Si–SiO2 interface constitutes a potential limit to device scaling. Indeed, the transistor miniaturisation entails the presence of higher electric fields. These high electric fields increase the injection of the hot carriers in the oxide and at the interface. Therefore, localised defects near the drain are created [1–3]. These defects generate a parasitic currents [4–8] and contribute to the device ageing and degradation. An understanding of the physical phenomenon of the degradation process is required in order to find technological solutions to minimise the ageing effect and device performances degradation. The analysis of the surface potential evolution offers some interesting information on performance degradation and device reliability [9]. An analytic surface potential model which takes into account the evolution of the interface charges injected at the Si–SiO2 interface during stress is elaborated. This model is obtained by resolving the twodimensional Poisson’s equation according to the spatial and temporal charge evolution in the channel and electric field during stress time.

The stress induces by the hot carrier injection in the oxide and at the Si–SiO2 interface. In general the large electric field is strongly localised near the drain, therefore, defects are similarly concentrated. These defects can also be non-uniformly distributed along the channel. Indeed, the region in which the impact ionisation takes place becomes equal to the channel length [10]. In contrast, for VG ˆ VD/2 (maximum substrate current) the interface defects density is greater than the oxide one [11,12]. Consequently, we are only interested in the interface defects induced during stress. These defects are simulated by a spatial and temporal Gaussian distribution centered near the drain (Fig. 1), with parameters depending (standard deviation and maximum) on time and stress conditions. The defect density is modeled by: ! 2…x 2 xc †2 ; …1† Nit …x; t† ˆ Nitmax …t† exp 2s…t†2

* Corresponding author. E-mail address: [email protected] (A. Bouhdada)

where t is the stress time and xc the Gaussian centre. The maximum defect density Nitmax …t† and the standard deviation s (t) depend on transistor technology and stress conditions (length, temperature, polarisation, etc.). Nitmax …t† is given by   a n ID n t ; …2† Nitmax …t† ˆ W Se Vth where Se ˆ 10 215 cm 2 is the average capture cross section, Vth ˆ 107 cm/s is the thermal velocity, the exponent n is

0026-2692/00/$ - see front matter q 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-269 2(99)00092-0

92

R. Marrakh, A. Bouhdada / Microelectronics Journal 31 (2000) 91–94

equation [9]: 22 cs …x; t† 2 k2 cs …x; t† 2x2   Qdep q 2 2 N …x; t† ; ˆ 2k VGS 2 VFB 2 Cox Cox it

…4†

where 12Cox ; 61s Wd 1 Cox Wd2

k2 ˆ

VGS, VFB, Cox, 1 s, Wd and Qdep are the gate bias, the flat-band voltage, the oxide capacitance per unit area, the dielectric permittivity, the depletion depth and the depletion charge, respectively. The resolution of Eq. (4) gives the surface potential profile:

cs …x; t† ˆ VGS 2 VFB 2

Fig. 1. Illustration of the Gaussian spatial distribution of defects localised at the interface.

equal to 0.5, a, a technological factor, W, the channel width and ID, the drain current. s (t) is given by:

s…t† ˆ s0 1 b log…t†;

…3†

b is a factor which depends on stress conditions. 1=3 1=2 s0 ˆ 0:22tox Xj

for L $ 0:5 mm;

1=8 1=3 1=5 s0 ˆ 1:7 × 1022 tox Xj L

for L # 0:5 mm;

L is the channel length, tox, the oxide thickness and Xj, the depth junction. Fig. 2(a) shows the simulation results of the spatial and temporal defect density evolution at the Si–SiO2 interface. The transistor parameters are: L ˆ 0.35 mm, tox ˆ 10 nm, Xj ˆ 0.2 mm, W ˆ 50 mm, the channel doping is Nb ˆ 10 17 cm 23, the source/drain doping is NS,D ˆ 10 20 cm 23, the temperature is T ˆ 300 K and the electrical conditions are VGS ˆ 2.5 V and VDS ˆ 5 V. These curves show the evolution of the interface defect distribution during stress. The variation of the maximum defects density during stress time is shown in Fig. 2(b).

! p qs…t†kNitmax …t† k2 s…t†2 1 2p exp 4Cox 2 ! ( 1 2 …x 2 x0 1 ks…t† † × exp…k…x 2 x0 †† erf p 2s…t† !) 1 2 …x 2 x0 2 ks…t† † 2exp…2k…x 2 x0 †† erf p 2s…t† 1 C1 exp…kx† 1 C2 exp…2kx†;

The spatial and temporal space charge variation must be taken into account in the surface potential model. The injected charges at the Si–SiO2 interface during stress are simulated by the Gaussian distribution (1). The surface potential variation along the channel is described by the following differential

…5†

where erf is the error function. The boundary conditions at the source and drain edges are:

cs …x ˆ 0† ˆ Vbi ;

…6†

cs …x ˆ L† ˆ VDS 1 Vbi ;

…7†

where Vbi is the built-in potential of the source/drain junction and VDS, the drain bias. Using relations (6) and (7) we obtain the following expressions of the constants C1 and C2: C1 ˆ

Vbi …1 2 exp…kx†† 1 …Td 2 VDS † exp…kx† 2 Ts ; 1 2 exp…2kx†

C2 ˆ

Vbi …1 2 exp…2kx†† 1 …Td 2 VDS † exp…2kx† 2 Ts ; …9† 1 2 exp…22kx†

where 3. Modelling of the surface potential c s(x, t)

Qdep Cox

…8†

! p qs…t†kNitmax …t† Qdep k2 s…t†2 Ts ˆ VGS 2 VFB 2 1 2p exp Cox 2 4Cox ( ! 1 …2x0 1 ks…t†2 † × exp…2kx0 † erf p 2s…t† !) 1 2 2exp…kx0 † erf p …10† …2x0 2 ks…t† † ; 2s…t†

R. Marrakh, A. Bouhdada / Microelectronics Journal 31 (2000) 91–94

93

Fig. 2. (a) Time evolution of the defect density along the channel. (b) Evolution of the maximum defect density versus stress time.

p qs…t†kNitmax …t† Qdep k2 s…t†2 Td ˆ VGS 2 VFB 2 1 2p exp 4Cox Cox 2

! 1 2 p  × exp…k…L 2 x0 †† erf …L 2 x0 1 ks…t† † 2s…t† !) 1 2 : 2exp…2k…L 2 x0 †† erf p …L 2 x0 2 ks…t† 2s…t†

!

(

…11†

Fig. 3 shows the evolution of the surface potential under the maximum substrate current condition (VGS ˆ VDS/2). The minimum surface potential decreases and moves towards the drain when stress time increases. This decrease becomes more pronounced at the damaged zone. The surface potential variation can reach 1 V after 15 h of stress, whereas in the case of the virgin transistor the surface potential remains practically constant along the channel and its variation is about 0.35 V.

94

R. Marrakh, A. Bouhdada / Microelectronics Journal 31 (2000) 91–94

Fig. 3. Evolution of the surface potential distribution during stress time.

4. Conclusion The simulation of the surface potential variation during stress allows us to validate some assumptions concerning the interface states generation by the hot electrons injected at Si–SiO2 interface. This method permits to establish the space charge r (x, t) and the electric field E(x, t) according to stress time. The surface potential model can be exploited to determine the threshold-voltage shift to characterize the device ageing effects.

[5]

[6]

[7]

[8]

References [9] [1] H.-H. Li, Y.-L. Chu, C.-Y. Wu, A novel charge-pumping method for extracting the lateral distributions of interface-trap and effective oxide-trapped charge densities in MOSFET devices, IEEE Trans. Electron. Dev. 44 (1997) 782–791. [2] C. Chen, T.-P. Ma, Direct lateral profiling of hot-carrier-induced oxide charge and interface traps in thin gate MOSFET’s, IEEE Trans. Electron. Dev. 45 (1998) 512–520. [3] D.S. Ang, C.H. Ling, unified model for the self-limiting hot-carrier degradation in LDD n-MOSFET’s, IEEE Trans. Electron. Dev. 45 (1) (1998) 149–159. [4] J.-Y. Yang, S.S.-S. Chung, P.-C. Chou, C.-H. Chen, M.-S. Lin, A new approach to modeling the substrate current of pre-stressed and post-

[10]

[11]

[12]

stressed MOSFET’s, IEEE Trans. Electron. Dev. 42 (6) (1995) 1113– 1119. Y.-B. Park, D.K. Schroder, Degradation of thing tunnel gate oxide under constant Fowler–Nordheim current stress for a Flash EPROM, IEEE Trans. Electron. Dev. 45 (1998) 1361–1368. A. Bouhdada, S. Bakkali, A. Touhami, Modelling of gate induced drain leakage GIDL in relation with technological parameters and temperature, Microelectron. Reliability J. 37 (4) (1997) 649–652. A. Bouhdada, S. Bakkali, A. NouaC ¸ ry, A. Touhami, Relation between the leakage currents and the defects created in oxide and interface in short channel NMOS transistor, Microelectron. J. 28 (1) (1997) 85– 91. A. Bouhdada, A. NouaC ¸ ry, S. Bakkali, A. Touhami, R. Marrakh, Effect of defects localised in the oxide of submicrometer NMOS transistor on substrate and drain currents, Microelectron. J. 30 (1999) 19–22. Y.-S. Jean, C.-Y. Wu, The threshold-voltage model of MOSFET devices with localized interface charge, IEEE Trans. Electron. Dev. 44 (1997) 441–446. S. Saha, C.S. Yeh, B. Gadepally, Impact ionisation rate of electrons for accurate simulation of substrate current in submicron devices, Sol. State Electron. 36 (10) (1993) 1429–1432. M. Song, K.P. MacWilliams, J.C.S. Woo, Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K, IEEE Trans. Electron. Dev. 44 (2) (1997) 268–275. S.-M. Cheng, C.-M. Yih, J.-C. Yeh, S.-N. Kuo, S.S. Chung, A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET’s under various bias stress conditions, IEEE Trans. Electron. Dev. 44 (11) (1997) 1908–1913.