Surface potential equation for bulk MOSFET

Solid-State Electronics 53 (2009) 11–13

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Surface potential equation for bulk MOSFET G. Gildenblat a,*, Z. Zhu a, C.C. McAndrew b a b

Ira A. Fulton School of Engineering, Electrical Engineering, Arizona State University, Tempe, AZ 85281, USA Freescale Semiconductor Inc., Tempe, AZ 85284, USA

a r t i c l e

i n f o

Article history: Received 28 May 2008 Received in revised form 12 September 2008 Accepted 19 September 2008 Available online 11 November 2008

a b s t r a c t The physical background of the commonly used approximate MOSFET surface potential equation is explained by comparison with the exact result. A new well-conditioned surface potential equation over the extended temperature range essential for cryogenic CMOS applications is obtained by explicitly accounting for incomplete impurity ionization simultaneously with the imref splitting present in MOS transistors. Ó 2008 Elsevier Ltd. All rights reserved.

The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Surface potential Compact model MOSFET

Surface potential-based compact models of MOS transistors, including the new international industry standard [1], are based on the surface potential equation (SPE) in the form published in [2] which represents a correction to the original SPE of Pao and Sah [3]. The latter becomes unphysical in a narrow region near the flat-band voltage. The physics behind this correction was explained in [4]. While the form of SPE introduced in [2,4] is universally accepted, its origin has been questioned and a different derivation has been suggested [5]. The purpose of this note is to clarify the physical origin of the SPE in [2,4], and to develop an SPE for the extended temperature range 10–400 K. This not only clarifies the SPE formulation but also enables compact modeling of MOS transistors in the presence of substrate impurity freeze-out. The SPEs in both [2,3] can be written in the form1

is the absolute dielectric constant of Si, pb is the bulk concentration of holes and u ¼ ws =/t where ws denotes the surface potential. The difference between SPEs in [2] and [3] comes from using different expressions for H(u). In [3], assuming that the vertical dependence of the minority carrier imref (electrons in the n-channel MOSFET considered here) can be neglected, it was found that HðuÞ ¼ HPS ðuÞ where

ðV gb  V fb  ws Þ2 ¼ c2 /t HðuÞ;

where Fp0 and Fn0 are the imrefs of the holes and electrons at the surface (Si/SiO2 interface). This equation is problematic for low u (near flat-band) where it predicts negative values of H, i.e., negative values of E2s as described in [2,4]. For this reason in [2] the expression for H(u) was modified as follows: HðuÞ ¼ H0 ðuÞ where

ð1Þ

where

HðuÞ ¼

es E2s 2q/t pb

ð2Þ

represents the normalized square of the surface electric field Es. Here Vfb is the flat-band voltage, /t ¼ kB T=q is the ‘‘thermal potential,” q denotes the absolute value of the electron’s charge, es * Corresponding author. E-mail address: [email protected] (G. Gildenblat). 1 This equation is often referred to as the ‘‘voltage equation.” 0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2008.09.007

HPS ðuÞ ¼ eu þ u  1 þ

  nb u k0 eu   1 ; k0 pb

ð3Þ

nb is the bulk concentration of electrons, and k0 is expressed in terms of the surface value of the imref splitting:

k0 ¼ exp

  F p0  F n0 ; q/t

H0 ðuÞ ¼ eu þ u  1 þ

ð4Þ

nb k0 ðeu  u  1Þ: pb

ð5Þ

This expression was not arrived at ‘‘empirically” (as suggested in [5]), since no experimental data were involved in the analysis in [2]. Instead, in [2] the authors were looking for an expression of the form

12

G. Gildenblat et al. / Solid-State Electronics 53 (2009) 11–13

HðuÞ ¼ eu þ u  1 þ

nb k1 ðeu  k2 u  1Þ pb

ð6Þ

with constant k1 and k2 such that H(u) is positive definite [i.e., H(u) > 0 for u–0 and H(0) = 0] and reverts to HPS when the latter equation is valid (i.e., in strong inversion). Expansion of the exponential terms immediately yields k1 = k0 and k2 = 1 and (5) follows as first given in [2]. This procedure does not constitute a derivation of (5), which requires evaluation of the integral

E2s ¼ 

2/t

es

Z

u

qðwÞdw;

ð7Þ

0

where the charge density is

qðwÞ ¼ q½pb ðew  1Þ þ nb ð1  kew Þ;

ð8Þ

w ¼ w=/t is the normalized electrostatic potential (w = u at the surface) and

k ¼ exp

  Fp  Fn kB T

ð9Þ

is expressed in terms of the electron (Fn) and hole (Fp) imrefs. While in n-channel MOSFETs Fp is approximately fixed, the minority carrier imref Fn is position dependent, including in the vertical (i.e., normal to the Si surface) direction, hence so is k. This makes it impossible to obtain an ‘‘exact” closed-form expression for Es or H(u) from (7), which means that (5) is simply a well-conditioned approximation of the exact result. This observation makes it difficult to agree with the analysis in [5] which is presented as a derivation of (5). The authors start with their Eq. (6), assume that the electron imref is position independent, obtain a modified expression for the charge density (the unlabeled equation on p. 1322 of [5]) and evaluate the integral in (7) to arrive at (5). But their Eq. (6) for the doping density ND, which predicts N D / k (in our notations), indicates that ND is a function not only of position but also of the MOSFET terminal voltages. Similarly, the modified equation for the charge density contradicts the standard result of semiconductor physics given by (8) above. The problem, of course, is that the authors neglect the position dependence of the minority carrier imref, which as has been already shown in [4] is what makes it necessary to use (5) instead of (3). Returning to the origin of (5) we note that the analysis in [2] suffers from the disadvantage of starting with (3). This may create an impression that, Fn or k must be assumed to be position independent to arrive at (5). But this impression is incorrect. To clarify the issue we present a different justification of (5) as an approximation to (7). Combine (2), (7) and (8) to obtain

HðuÞ ¼ eu þ u  1 þ

nb pb

Z

u

kðew  1Þdw þ

0

Z

u

 ðk  1Þdw :

ð10Þ

0

w

Since the function e  1 does not change sign on the interval (0,u) one can use the first mean value theorem of integral calculus to write

Z

u

kðew  1Þdw ¼ kðnÞ

0

Z

u

ðew  1Þdw

ð11Þ

0

with n 2 ð0; uÞ so that

HðuÞ ¼ eu þ u  1 þ

nb ½kðnÞðeu  u  1Þ þ ðkav  1Þu; pb

ð12Þ

where

kav ¼

1 u

Z 0

u

k dw:

ð13Þ

This result is exact but not directly applicable since kðnÞ and kav are neither known nor constant. However, one can see immediately that (5) is not an exact representation of (7) or, equivalently, (12) and hence cannot be derived from physics based boundary conditions without additional approximations. For the purpose of compact modeling, however, the difficulty is not severe. Indeed, the term in square brackets in (12) corresponds to the contribution of the minority carriers and is numerically significant only when the exponential term eu is dominant. In this region (as shown in [4]) k  k0 within the surface region where the current flows, so approximating kðnÞ ¼ k0 is reasonable. This yields (5) after neglecting the term ðnb =pb Þðkav  1Þu, which is always small for realistic values of u, nb and pb. This establishes (5) as the one of many possible approximations to the exact result. Another approximation that is based on (5) and is also positive definite is given in [1] and has some additional advantages for the construction of compact models. The work in [1–5] assumes complete ionization of the impurities (acceptors for the uncompensated n-channel MOSFET considered here). For the extended temperature range it is necessary to take into account impurity freeze-out [6–8]. Indeed, while impurity freeze-out is negligible in the space-charge region of a MOSFET [9,10], it is essential near the flat-band region and significantly affects the device characteristics [11,12]. Development of the SPE for the extended temperature range further clarifies the technique used in [2,4] and is of interest for MOSFET compact modeling for low-temperature applications (e.g., in radio astronomy, space missions and related activities). The SPE in the presence of impurity freeze-out has been used in [6–8] for MOS capacitors and in [9] for MOS transistors described using the extended temperature range Pao–Sah model. The SPE of [11] is a straightforward extension of that in [3] and is given by (1) with HðuÞ ¼ H1 ðuÞ where

H1 ðuÞ ¼ expðuÞ  1 þ

nb Na ko ½expðuÞ  1 þ pb pb

 ln f1 þ k½expðuÞ  1g;

ð14Þ

where Na denotes the acceptor concentration and k is the degree of ionization in the bulk:

k ¼ ðN a Þb =Na ;

ð15Þ

ðN a Þb

where is the bulk concentration of the ionized acceptors. The variable ‘‘a” used in [11] is related to k by kða þ 1Þ ¼ 1. For the purpose of the present study it is convenient to set

Na ¼

ðNa Þb pb  nb ¼ ; k k

ð16Þ

whence (14) becomes

nb H1 ðuÞ ¼ expðuÞ  1 þ ko ½expðuÞ  1 pb   1 nb þ 1 ln f1 þ k½expðuÞ  1g: k pb

ð17Þ

It is worthwhile to consider two special cases of (17). In a MOS capacitor Fpo = Fno, ko = 1 and from (3), (17) one recovers the results given in [6–8] (except that in [7,8] surface degeneracy, which is neglected in (14), is accounted for). For MOS transistors operating near room temperature the ionization of acceptor impurities is complete, k  1, and (17) reverts to (3). In general, just as (3), (17) is derived assuming fixed electron imref and suffers from the same problem: unphysical behavior in a narrow region near u = 0. Specifically, from (17),

H1 ðuÞ ¼

nb ðko  1Þu þ Oðu2 Þ; pb

u ! 0:

ð18Þ

13

G. Gildenblat et al. / Solid-State Electronics 53 (2009) 11–13

Thus (cf. Fig. 1) it is possible that H1 ðuÞ < 0 for sufficiently low u which contradicts (1). We are once again faced with the need to condition (17) so that HðuÞ P 0 for all u. To search for a better conditioned H over the extended temperature range, we separate the contributions of the majority (H1h) and minority (H1e) carriers to H1

1.2

H1 ¼ H1h þ H1e ;

0.6

H1h ¼ eu  1 þ gðuÞ;   nb gðuÞ H1e ¼ ko eu  1  ko pb

ð20Þ ð21Þ

and

1 ln ½1 þ kðeu  1Þ: k

ð22Þ

Since the problem with either (17) or its special case (3) is an incorrect description of the minority carrier contribution H1e associated with the assumption of a position independent electron imref, only H1e needs to be modified. Indeed, H1h(u) P 0 for all u. Following the procedure adopted above for the transition from (3) to (5) we search for constant k3 such that

nb ko ½eu  1  k3  gðuÞ P 0 pb

ð23Þ

for all u. This yields k3 = 1 and by changing H1e into H2e we obtain well-conditioned expression

H2 ðuÞ ¼ H1h ðuÞ þ H2e ðuÞ

ð24Þ

or

H2 ðuÞ ¼ eu  1 þ gðuÞ þ

nb ko ½eu  1  gðuÞ: pb

ð25Þ

The commonly used expression (5) now appears as a special case of (25) corresponding to k ¼ 1 and gðuÞ ¼ u (complete impurity ionization). Just as at room temperature the transition from H1 ðuÞ to H2 ðuÞ is significant only for exceedingly small u (cf. Fig. 1) and does not affect MOSFET electrical characteristics (cf. Fig. 2). The SPE given by (1) with HðuÞ ¼ H2 ðuÞ is capable of reproducing the details of low-temperature device characteristics including the well-known behavior near the flat-band voltage observed in MOS capacitors operating in the freeze-out region (cf. Fig. 2). This

eq. (17) eq. (25)

40

H

30

20

10

15

0.4 0.2

ox

0

eq. (3) eq. (5) eq. (17) eq. (25)

−0.2

gðuÞ ¼

H2e ¼

gg

where

0.8

C /C

ð19Þ

1

10

0

−10 −5

−4

−3

−2

−1

0

ψs, nV

1

2

3

4

Fig. 1. Comparison of expression (17) and (25) for Fno  Fpo = 0.6 eV, T = 230 K and Na = 1017 cm3.

−0.4 −0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Vgb−Vfb, V Fig. 2. Capacitance–voltage characteristics of MOS device computed using (17) and (25) for Vbs = 0.5 V, Vds = 0 V, T = 30 K, Na = 1017 cm3 and tox = 2 nm.

behavior is caused by the rapid change in the number of the ionized impurities when the hole imref passes through the energy level of acceptors [6–8]. The results are not affected by changing H1(u) into H2(u) except that occasional simulator crashes associated with negative H1(u) are now eliminated using the better conditioned H2(u). As shown in Fig. 2 this experimentally observed behavior [7,8] cannot be modeled with HPS(u) or H0(u). In conclusion, we have demonstrated that the need for the approximation of the exact SPE comes from the well-known position dependence of the minority carrier imref, and that the commonly used SPE of ref [2] cannot be derived by ignoring this dependence. Generalization of this approximation valid over an extended temperature range is given by (25). We also note that the problem with the SPE in [3] that is the subject of analysis in [2,4,5] is relatively minor and that [3], which is the first surface potential-based MOSFET model, remains the foundation of this approach to compact modeling. References [1] Gildenblat G, Li X, Wu W, Wang H, Jha A, Langevelde RV, et al. PSP: an advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans Electron Dev 2006;53(9):1979–93. [2] McAndrew CC, Victory J. Accuracy of approximations in MOSFET charge models. IEEE Trans Electron Dev 2002;49(1):72–81. [3] Pao HC, Sah CT. Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid State Electron 1966;9:927–37. [4] Wu W, Chen T-L, Gildenblat G, McAndrew CC. Physics-based mathematical conditioning of the MOSFET surface potential equation. IEEE Trans Electron Dev 2004;51(7):1196–9. [5] Shangguan W, Saeys M, Zhou X. Surface-potential solutions to the Pao–Sah voltage equation. Solid State Electron 2006;50(7–8):1320–9. [6] Sah CT. Theory of the metal oxide semiconductor capcitor, Solid-State Electronic Laboratory Tech Rep No. 1, December 14, 1964. [7] Brown DM, Gray PV. Si-SiO2 fast interface state measurements. J Electrochem Soc 1968;115:760–6. [8] Gray PV, Brown DM. Freeze-out characteristics of the MOS varactor. Appl Phys Lett 1968;13(8):247–8. [9] Gaensslen FH, Jaeger RC. Temperature dependent threshold behavior of depletion mode MOSFETs. Solid State Electron 1979;22(4):423–30. [10] Gildenblat G, Colonna-Romano L, Lau D, Nelson DE. Investigation of cryogenic CMOS performance. IEDM 1985;31:268–71. [11] Huang C-L, Gildenblat G. Measurements and modeling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60–300 K. IEEE Trans Electron Dev 1990;37(5):1289–300; Huang C-L, Gildenblat G. Correction to Measurements and modeling of the nchannel MOSFET inversion layer mobility and device characteristics in the temperature range 60–300 K. IEEE Trans Electron Dev 1991;38(3):680. [12] Gildenblat G, Foty D. Low temperature models of metal oxide semiconductor field-effect transistors. Int J High Speed Electron Syst 1995;6(2):317–73.