Monolithic 10-bit d-a converter avoids postprocess trimming

World Abstracts These abstracts are the last by Charles E. Jowett who sadly died in November 1985. 1. Integrated Circuit Technology Integrated circuit design verification tools. L. SZANTO Microelectron. Reliab. 24, 259 (1984) Integrated circuit design results in two main data files: data defining a set of masks (D I) which are the final goal of the design and data defining the schematic drawing (D2), which is a convenient form of the circuit function description. In an overview fashion a design verification system is treated in the first part of this paper. It consists of design rule checking and circuit reconstruction from D1, data file D2 translation to schematic diagram description, logic simulation of the two extracted diagrams, and mutual comparison of their technology. In the second part of this paper the following items are discussed in more detail: graphic description language - an extension of CIF for schematic drawing definition, the KOS subsystem for schematic diagram extraction from D2, and the mixed level diagram logic simulator LOMACH-MIXED. Fault-tolerant design techniques for semiconductor memory applications. F.J. AICItELMANN, Jr. IBMJ. Res. Develop. 28 (2), 177 (March 1984) Advances in semiconductor memory technology towards higher-density and higher-performance memory chips have created new reliability challenges for the memory system designer. An example would be the multiple-bit-per-chip organization with the chip outputs used in the same word. This design structure would be prone to uncorrectable errors with convetionally implemented single-error-correcting doubt-error-detecting codes. With these newer chips, memory system designers will have to give special attention not only to the type of failures but to ways of minimizing the system impact of reliability defects. In this paper, a number of design approaches are presented for minimizing the effects of chip failures through the use of organizational techniques and through enhacements to conventional error checking and correction facilities. The fault-tolerant design techniques described are compatible with most existing memory designs. An evaluative comparison of these techniques is included, and their application and utility discussed. Design of a 3-micron CMOS cell library. C.P. LINCOLN Electl. Commun. 58, 384 (1984) A new CMOS standard cell library has been designed for producing .more complex and higher speed semi-custom VLSI circuits using the emerging 3/~m technologies. The library has been designed to be compatible with p- and nwell CMOS processes, one and two-layer metallization, and suitable single- or double-sided cell autolayout software.

Reliability problems with VLSI. FAUSTO FANTINI Microelectron. Reliab. 24,275 (1984) The exraordinary development of the integrated fcircuits has gone hand in hand with an increase in reliability; however the speed of evolution itself brings about great reliability risks, due to strong competition in the market, and the reduction in the dimensions of the devices causes an increase in the electric fields and current densities. The failure mechanisms that are expected to be most dangerous are thin oxide breakdown, hot electron effects, metal-semiconductor interactions, eleetromigration and soft errors induced by energetic particles. Failure analysis of complex devices requires advanced and costly techniques at the limits of the capabilities of analytical instrumentation.

Monolithic 10-bit d-a converter avoids postprocess trim. ming. PETER H. SAUL Electronics 144 (14 June 1984) Innovative circuit design, in conjunction with digital processing, offers a high-speed digital-to-analog converter that settles in 12 ns.

MOS technology for VLSI. G. DECLERCK, K. DE MEYER and L DUPAS Aficroelectron. Reliab. 24,205 (1984) The scaling laws for MOS tranistors are reviewed and the optimum performance predicted for both n-channel and p-channel devices are discussed. The physical and technological limitations for MOS VLSI are then described and some important technological challenges such as the implementation of new isolation techniques are pointed out. The mobility degradation effect due to velocity saturation is explained and illustrated bY experimental data. The various limitations to the maximum operating voltage of scaled devices are discussed. Finally, some considerations about speed and power consumption of sealed technologies are made.

Designers ~eigh options for 256-K dynamic-RAM processes.

PETER LINDER, R O G E R NORWOOD and }IGAI HUNG HONG Electroniocs 104 (12 July 1984) Hidden-refresh models make dynamic RAMs look stat i c , while alternate addressing modes vary width of single parts.

MICROELECTRONICS JOURNAL Vo116 No 6 9 1985 Benn Electronics Publications Ltd0 Luton 52