- Email: [email protected]
Monolithic integration of InP-based transistors on Si substrates using MBE
ARTICLE IN PRESS Journal of Crystal Growth 311 (2009) 1979–1983
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Monolithic integration of InP-based transistors on Si substrates using MBE W.K. Liu a,, D. Lubyshev a, J.M. Fastenau a, Y. Wu a, M.T. Bulsara b, E.A. Fitzgerald b, M. Urteaga c, W. Ha c, J. Bergman c, B. Brar c, W.E. Hoke d, J.R. LaRoche d, K.J. Herrick d, T.E. Kazior d, D. Clark e, D. Smith e, R.F. Thompson e, C. Drazek f, N. Daval f a
IQE, Inc., Bethlehem, PA 18015, USA Massachusetts Institute of Technology, Cambridge, MA, USA c Teledyne Scientific Company, Thousand Oaks, CA, USA d Raytheon RF Components, Andover, MA, USA e Raytheon Systems Ltd., Glenrothes, Fife, Scotland, UK f SOITEC, Parc Technologique des Fontaines, Bernin, Crolles Cedex, France b
a r t i c l e in fo
abstract
Available online 1 November 2008
We report on a direct epitaxial growth approach for the heterogeneous integration of high-speed III–V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBT) structures were successfully grown on Si-on-lattice-engineered- substrate (SOLES) and Ge-on-insulatoron-Si (GeOI/Si) substrates using molecular beam epitaxy. Structurally, the epiwafers exhibit sharp interfaces and a threading dislocation density of 3.5 107 cm 2 as measured by plan-view transmission electron microscopy. HBT devices fabricated on GeOI/Si substrates have current gain of 55–60 at a base sheet resistance of 650–700 O/sq, and ft and fmax of around 220 GHz. HBT structures with DC and RF performance similar to those grown on lattice-matched InP were also achieved on patterned SOLES substrates with growth windows as small as 15 15 mm2. These results demonstrate a promising path of heterogeneous integration and selective placement of III–V devices at arbitrary locations on Si CMOS wafers. & 2008 Elsevier B.V. All rights reserved.
PACS: 81.05.Ea 81.05.Cy 85.30.Pq 84.40.Lj 68.55.Ac Keywords: A3. Molecular beam epitaxy A3. III–V on Si integration B1. GeOI/Si B1. SOLES B1. Si B1. InP B3. InP-HBT
1. Introduction Heterogeneous integration of high-speed III–V devices with Si CMOS circuitry has attracted significant interest for its potential in next generation monolithic hybrid integrated circuits (ICs) for analog and digital applications. A successful integration scheme will provide circuit designers with the ultimate technological flexibility of ‘‘best junction for the function’’ without compromising the yield and scalability of CMOS or the speed and breakdown of the III–V devices. Various approaches have been proposed to achieve this hybrid combination, from pick-and-place die transfer to full wafer bonding to direct growth of III–V devices on Si, but all lack aspects of the full benefits of III–V/Si integration. The approach we adopted is the direct molecular beam epitaxial (MBE) growth of III–V materials on Si utilizing composite Si-based substrates such as Ge-on-insulator-on-Si (GeOI/Si) and Si-on-lattice-engineered-
Corresponding author.
E-mail address: [email protected] (W.K. Liu). 0022-0248/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2008.10.061
substrate (SOLES). We have previously reported on the proof-ofconcept growths of InP-based transistors on un-patterned GeOI/Si substrates using composite InAlAs/GaAs metamorphic buffer (M-buffer) layers and compared their performance with baseline structures grown on InP, GaAs and Ge substrates [1–3]. In this work, we will focus on the MBE growth of InP-based heterojunction bipolar transistors (HBTs) on patterned GeOI/Si and SOLES substrates. There are several unique challenges in the epitaxy process that are critical to achieve high-quality InP-based device structures on patterned GeOI/Si and SOLES substrates. These include patterning, surface preparation, and growth methods that support the nucleation of low defect density, anti-phase domain (APD) free GaAs on the Ge surface of the GeOI/Si and SOLES substrates; prevention of Ge out-diffusion; growth of low defect density, device-quality InP-based structures on GaAs surface using a suitable M-buffer; and epitaxial growth inside the Ge windows. While GaAs and Ge are closely lattice-matched (Da/a0.07%), epitaxial growth of GaAs on Ge is prone to APD formation because of its polar-on-non-polar nature. APDs can be suppressed in MBE growth by using off-cut substrates, by optimizing the initial
ARTICLE IN PRESS 1980
W.K. Liu et al. / Journal of Crystal Growth 311 (2009) 1979–1983
nucleation condition, and by using thermal annealing techniques [4]. A variety of M-buffers have been used to facilitate the growth of InP-based devices on GaAs substrates [5–7]. The basic requirement of an M-buffer is to accommodate the lattice mismatch between GaAs and the InP-based alloys of the device structure and to absorb this strain while minimizing the nucleation of dislocations. The resulting surface should also have low roughness and minimal warp for device reliability and processing requirements. Graded InAlAs-based M-buffers have been used for production of InP-based metamorphic high-electron mobility transistors (M-HEMT) on GaAs substrates with proven reliability and device yield [8]. Figures-of-merit achieved include rms surface roughness in the 20–30 A˚ range for a 5 5 mm2 scan and channel charge mobility product almost identical to HEMTs grown on InP substrates. Similar characteristics have also been reported for M-HEMTs grown on un-patterned Ge and GeOI/Si substrates [1]. Less work has been done on metamorphic HBT (M-HBT) structures mainly because minority-carrier devices are in general more sensitive to dislocation density. Using a graded InAlAs M-buffer, we have achieved 80–90% of the large-area device figure-of-merit (DC current gain/base sheet resistance) on bare, un-patterned GaAs, Ge and GeOI/Si substrates with comparable breakdown voltage relative to control structures on InP substrates. Typically, the dislocation density for both M-HEMT and M-HBT structures is estimated to be in the 106–107 cm 2 range [1–3]. Due to the high sticking coefficients of group-III atoms, selective growth of InGaAs-based materials on masked area is difficult to achieve by MBE. The growth proceeds across the entire wafer, resulting in a polycrystalline growth on the mask material that requires a patterned dry etch process for its removal. The epitaxial challenge is to find the optimal growth condition for high filling factor within the windows opened through the mask, while maintaining good quality GaAs on Ge nucleation and InP device growth on the Ge surface inside these windows. Epitaxial growth on the limited area within the Ge windows could reduce the likelihood of misfit dislocations in the active layers by limiting misfit dislocation length and by reducing dislocation interaction and multiplication [9]. Potentially, small-area growth within the windows may also enhance dislocation filtering within the M-buffer and hence help reduce the threading dislocation density [9]. Our goal is to achieve a filling factor in the Ge windows that will allow placement of the active device junctions to within 5 mm from the edge of the window opening for intimate heterogeneous integration. In this work, InP-based HBT structures on GeOI/Si and SOLES wafers were used to demonstrate the potential of fabricating multi-level ICs with III–V circuitry integrated with Si CMOS logic. Surface morphology, structural properties, and interfacial quality of the epilayers grown on bare GeOI/Si were confirmed, followed by characterization of epilayers grown on patterned GeOI/Si and SOLES substrates. DC and RF characteristics of large- and smallarea HBTs fabricated on both bare and patterned GeOI/Si and SOLES substrates were then evaluated and Gummel plots, common-emitter IV characteristics, as well as ft/fmax data were extracted.
2. Experimental details HBT growths were performed on 100 mm diameter GeOI/Si and SOLES substrates provided by SOITEC using Smart-CutTM technology [10,11]. Essential features of these substrates include compatibility with Si CMOS fabrication processes, easy electrical isolation, and a lattice constant (Ge) suitable for growth and integration of III–V devices. The III–V on SOLES integration
BPSG
BPSG III-V Devices
Si SiO2
Si SiO2
Ge(100) 6°off SiO2 Si (100) Handle Wafer
Fig. 1. Schematic showing the placement of III–V epilayers in the growth window of a SOLES substrate.
scheme discussed in this work is illustrated in Fig. 1. The SOLES substrate contains a sandwiched Ge layer that is used as a template for III–V growth. From the top down, the SOLES wafer comprises of a Si layer, SiO2, Ge, SiO2, and a Si substrate. The topmost silicon layer is used for SOI CMOS fabrication to realize an integrated CMOS/HBT process. The crystal orientation of the thin embedded Ge layer was 61 off (0 0 1) toward /111S, which promotes III–V epilayer growth with minimal APD formation [12,13]. A boron–phosphorous–silicated-glass (BPSG) layer is initially deposited on the SOLES substrates to protect the Si CMOS layer. Growth windows with a wide variety of sizes are patterned by etching through the BPSG, the topmost Si layer, and the first buried oxide layer with a combination wet/dry etch process that exposes the buried Ge. Etching and cleaning processes have been optimized to control the sidewall profile and minimize the damage to the Ge layer to ensure high quality III–V growth. In order to monitor growth by RHEED and to use optical pyrometry for temperature control, a large 25 25 mm2 window was patterned in the center of test wafers. All III–V epitaxial growths for this work were performed on a multi-wafer Oxford Instruments V-100 MBE system equipped with group V As- and P-valved crackers and with conventional effusion cells for the group-III materials. Si was used for n-type doping, and p-type doping was achieved using a CBr4 gas source. Prior to MBE growth, the substrates were subjected to a UV ozone cleaning and the native oxide on the Ge surface was removed by thermal desorption at a temperature 500 1C. A single-stage growth process at 600 1C was used for the initial nucleation of GaAs on Ge and subsequent GaAs buffer has previously been shown to be effective in limiting APDs, minimizing Ge outdiffusion, and providing a low dislocation density on un-patterned GeOI/Si [1,2]. Following the growth of 0.6 mm of GaAs, a 1.1 mm InAlAs-based linearly-graded M-buffer layer with an inverse step was grown to transition to the lattice constant of InP. Details of the growth of the graded InAlAs M-buffer can be found elsewhere [5]. The HBT structure used in this work is a standard double heterojunction design with InP collector and emitter, and with a 400 A˚ thick InGaAs base C-doped at 4 1019 cm 3. An InGaAs setback layer and chirped super-lattice grade were used to remove the conduction band discontinuity at the base-collector interface [14]. Various characterization methods were used to analyze the quality of the epitaxial material. Surface morphology was evaluated via Nomarski contrast optical microscopy, atomic force microscopy (AFM), and scanning electron microscopy (SEM). The structural properties were assessed by high-resolution X-ray diffraction (XRD) and cross-sectional transmission electron microscopy (TEM). Small-area devices were fabricated using a standard non-selfaligned triple-mesa HBT process. After contact formation and
ARTICLE IN PRESS W.K. Liu et al. / Journal of Crystal Growth 311 (2009) 1979–1983
semiconductor mesa etching, the devices were passivated and the surface was planarized with a spin-on-dielectric (BCB). Contact vias were etched in the BCB and first level interconnects were deposited to complete fabrication. DC and RF measurements were performed to extract typical parameters.
1981
Misfit Dislocations
5.7 μm
3. Results To evaluate the effectiveness of our GaAs nucleation process and M-buffer design, TEM was used to evaluate the structural quality of InP-HBT epi grown on GeOI/Si substrate. Examination of the GaAs/Ge interface reveals only limited APB formation, and in the regions where APBs did form, they quickly annihilated within the first 100 A˚ of the film growth. As shown in the cross-sectional TEM micrograph in Fig. 2, the main dislocation network is localized within the graded InAlAs M-buffer layer where the lattice parameter transitioned from that of GaAs to InP. The InPHBT layers above the M-buffer have well-defined interfaces. The threading dislocation density measured by plan-view TEM was found to be around (3.570.6) 107 cm 2 (Fig. 3). While the device characteristics of these wafers seem to be reasonable, more growth optimization work is currently underway to drive down the dislocation density and to understand its effect on long-term device reliability. In order to obtain device material quality on patterned substrates, MBE growth conditions must satisfy several additional requirements beyond that of standard growth on un-patterned substrates. While smooth epi inside the windows is a prerequisite, polycrystalline growth is expected on the BPSG-masked area. Problems can arise in future processing of the wafers if this polycrystalline material is too rough. Ga droplet formation on exposed Si along the sidewall of the windows can also promote polycrystalline, wire-like growth that can protrude into the window openings, thus shrinking the area for high quality III–V
Fig. 3. Plan-view TEM evaluation of residual dislocation density at the top of an InP-HBT structure on un-patterned GeOI/Si substrate. Images from two representative regions are shown.
20.0
10.0
25 µm 0
Poly crystal on BPSG
Single crystal inside growth window
10.0
0 20.0µm
Polycrystalline material removed Single crystal inside growth window < 2µm
Fig. 4. Surface morphology of InP-HBT structures grown on patterned SOLES substrates: (a) Nomarski, (b) AFM with rms roughness of 13 A˚ (same area as (a)), and SEM images (c) before removal of the polycrystalline material and (d) after removal of the polycrystalline material (close-up of one of the growth windows).
InGaAs Base InP Collector InP Subcollector
14 Threads
11 Threads
InP-HBT
InAlAs Buffer
GaAs Ge SiO2 Si 500 nm Fig. 2. Cross-sectional TEM image of an InP-HBT structure grown on an unpatterned GeOI/Si substrate.
growth. To minimize the roughness of the polycrystalline material and nucleation along the window sidewalls, growth conditions previously optimized for un-patterned growth had to be modified for patterned substrates. Instead of using a 600 1C single-stage growth, the GaAs buffer layer was grown at reduced temperature to minimize Ga surface migration during epi growth and inhibit droplet formation and wire nucleation. Growth conditions for the initial GaAs nucleation on Ge, graded M-InAlAs M-buffer, and InP-HBT structure remained the same for both patterned and un-patterned substrates. The surface morphology of an InP-HBT structure grown on a patterned SOLES substrate is depicted in Fig. 4. The Nomarski (Fig. 4a) and AFM (Fig. 4b) images inside the windows exhibit cross-hatch patterns characteristic of high-quality metamorphic growth with low rms roughness of 13 A˚ for a 20 20 mm2 AFM scan. Similar roughness levels were observed for HBTs grown on patterned GeOI/Si substrates. SEM images taken before and after removing the polycrystalline material from HBTs on patterned SOLES reveal a gap of only 2 mm between the sidewall of the window and the smooth epi region inside. Well-defined window edges, flat, smooth epi with high filling factor inside the growth windows, as well as low roughness polycrystalline material on the
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InP-HBT layers on top can be clearly seen in the HRXRD spectra shown in Fig. 5. The FWHM for the GaAs and HBT layers are close to the values measured on bare substrates, indicating that structural quality of material grown on patterned substrates is close to material previously grown on bare substrates. It is widely understood that minority-carrier devices such as HBTs are more sensitive to dislocations and defects near the heterojunctions, with typical degradation observed in the current gain (b) and in the base-collector breakdown voltage [5]. Large-area device DC parameters of InP-HBT structures grown on un-patterned Ge and GeOI/Si substrates have been shown to compare favorably with baseline structures grown on InP and GaAs substrates with minimal degradation in b and breakdown voltage [2]. InP-HBT structures on un-patterned GeOI/Si substrates were then fabricated into small-area devices with emitter area 0.5 5.0 mm2. Gummel plot and RF data shown in Fig. 6 reveal DC current gain of over 40 and ft, fmax of 220 GHz. To evaluate the InP-HBT structures grown on patterned SOLES substrate, small-area devices were fabricated within various sizes of growth windows. An SEM image of an array of InP-HBT devices fabricated on patterned SOLES substrates prior to final device passivation is shown in Fig. 7a. The distance between the active junction area and the window edge is o5 mm, which is important for heterogeneous interconnect requirements between the III–V devices and the CMOS circuit. Good DC and RF device characteristics were measured for devices in windows as small as 15 15 mm2. Devices with emitter area of 1 3 mm2 exhibit b of 40 and a common-emitter breakdown voltage BVCEO=6 V at a current density of 10 mA/mm2. An ft of 190 GHz was extrapolated
masked area demonstrated here are encouraging features for III–V device cluster fabrication on CMOS wafers. The structural quality of the epi material was then evaluated. The XRD spectra of InP-HBT structures grown on patterned GeOI/Si and patterned SOLES substrates were qualitatively the same as those obtained from growth on un-patterned GaAs substrates. Well-defined peaks from the GaAs buffer layer on Ge, the linearly-graded InAlAs M-buffer with an inverse step, and the
1E+05 on GaAs (reference) on patterned SOLES
GaAs substrate
Intensity (cps)
1E+04 M-HBT
1E+03 Ge+GaAs
1E+02 1E+01 1E+00 31.0
Linearly-graded InAlAs M-buffer
31.5
32.0 32.5 ω-2θ (degree)
33.0
33.5
Fig. 5. High-resolution XRD (0 0 4) spectra of InP-HBT epi inside the growth window of a patterned SOLES substrates. Reference spectrum from the same structure grown on GaAs substrate is also shown.
40
10
-4
10
-6
10
-8
AE = 0.5x5 µm = 40
2
|H21| (red), U (blue) (dB)
Base, Collector Current (A)
10-2 Ic
Ib
10-10 10-12
0
0.2 0.4 0.6 0.8 Base-Emitter Voltage (V)
1
AE = 0.5x5 µm2 IC = 7.8 mA
35 30
VCE = 1.5V
25 20 15 10 5 0 109
ft = 224 GHz fmax = 219 GHz
1010 1011 Frequency (GHz)
1012
Fig. 6. (a) Gummel plot and (b) unilateral power gain and short circuit current gain versus frequency plot for small-area (0.5 5 mm2) HBT devices fabricated on unpatterned GeOI/Si substrates.
Fig. 7. (a) SEM image of an array of InP-HBT devices fabricated on a patterned SOLES substrate prior to final device passivation and (b) close-up of a single InP-HBT device.
ARTICLE IN PRESS W.K. Liu et al. / Journal of Crystal Growth 311 (2009) 1979–1983
from the RF plots, consistent with previous results demonstrated on GeOI/Si substrates and comparable to what one would expect from a lattice-matched InP-HBT with the same device dimensions [15]. The extraction of fmax was hampered by the deviation from the 20 dB/decade roll-off characteristic of the unilateral power gain versus frequency curve, probably caused by the underlying conductive Si substrate used in this work [15]. Improvements in RF performance can be expected with further lateral scaling of the transistors and the use of a more resistive transferred Ge layer and Si handle substrate.
4. Summary The MBE growth of InP-based HBT structures on GeOI/Si and patterned SOLES substrates has been successfully demonstrated, with high-quality epilayers obtained on the latter with a minimum window size of 15 15 mm2. Smooth surfaces with an AFM rms roughness of 13 A˚ with minimal exclusion area at the window edges make the proposed MBE growth sequence on patterned SOLES substrates suitable for monolithic III–V device integration into Si CMOS circuitry. Large-area device characteristics for InP-HBTs on GeOI/Si substrates were comparable to reference structures grown on InP and Ge substrates. Small-area HBTs on GeOI/Si substrates show excellent DC current gain (b 440) and RF figures-of-merit (peak ft/fmax220 GHz). For a first time, InP-based HBTs grown on patterned SOLES substrates were demonstrated and characterized. Small-area HBT devices, with 1 3 mm2 emitter area, fabricated on patterned SOLES substrates with windows as small as 15 15 mm2, demonstrate b of 40, BVCEO=6 V at current density of 10 mA/mm2, and with extrapolated ft of 190 GHz. This work demonstrates the viability of this approach in the development of monolithic integration of III–V devices with CMOS technology.
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Acknowledgements The authors thankfully acknowledge DARPA COSMOS Program (N00014-07-C-0629, Program Manager: Dr. Mark Rosker, COTR: Dr. Harry Dietrich). MIT acknowledges research funding support from the Army Research Office (ARO). References [1] D. Lubyshev, J.M. Fastenau, W.K. Liu, Y. Wu, M.T. Bulsara, E.A. Fitzgerald, W.E. Hoke, J. Vac. Sci. Technol. B 26 (2008) 1115. [2] D. Lubyshev, J.M. Fastenau, Y. Wu, W.K. Liu, M. Urteaga, W. Ha, J. Bergman, B. Brar, M.T. Bulsara, E.A. Fitzgerald, W.E. Hoke, J.R. LaRoche, K.J. Herrick, T.E. Kazior, 20th InP and Related Materials Conference, Versailles, France, 25–29, 2008 (MoB2.3). [3] K.J. Herrick, M. Urteaga, A.W.K. Liu, D.I. Loubychev, J.M. Fastenau, E. Fitzgerald, M. Bulsara, B. Brar, W. Ha, J. Bergman, T. Kazior, N. Daval, 2008 MRS Spring Meeting, San Francisco, CA, Mar 24–28, 2008 (C2.1). [4] R.M. Sieg, S.A. Ringel, S.M. Ting, E.A. Fitzgerald, R.N. Sacks, J. Electron. Mater. 27 (1998) 900. [5] D.I. Lubyshev, J.M. Fastenau, X.-M. Fang, Y. Wu, C. Doss, A. Snyder, W.K. Liu, M.S.M. Lamb, S. Bals, C. Song, J. Vac. Sci. Technol. B 22 (2004) 1565. [6] R.E. Leoni III, W.E. Hoke, C.S. Whelan, P.F. Marsh, P.C. Balas II, J.G. Hunt, K.C. Hwang, S.M. Lardizabal, C. Laighton, S.J. Lichwala, Y. Zhang, T.E. Kazior, Digest of Papers, 2002 International Conference on Compound Semiconductor Manufacturing Technology, (ISBN 1-893580-03-2, GaAs MANTECH, St. Louis, 2002), p. 272. [7] Y.M. Kim, M.J.W. Rodwell, A.C. Gossard, J. Electron. Mater. 31 (2001) 196. [8] P.C. Balas II, C.S. Whelan, M. Benedek, W. Stiebler, J. Kim, L.M. Aucoin, Technical Digest 2002 Compound Semiconductor Manufacturing Expo, IOP, Bristol, UK, 2002, p. 4. [9] E.A. Fitzgerald, J. Vac. Sci. Technol. B 7 (1989) 782. [10] C. Maleville, C. Mazure´, Solid State Electron. 48 (2004) 1055. [11] Smart-CutTM is a registered trademark of Soitec. [12] R.M. Sieg, S.A. Ringel, S.M. Ting, E.A. Fitzgerald, R.N. Sacks, J. Electron. Mater. 27 (1998) 900. [13] S.M. Ting, E.A. Fitzgerald, J. Appl. Phys. 87 (2000) 2618. [14] M. Dahlstro¨m, X.-M. Fang, D. Lubyshev, M. Urteaga, S. Krishnan, N. Parthasarathy, Y.M. Kim, Y. Wu, J.M. Fastenau, W.K. Liu, M.J.W. Rodwell, IEEE Electron Device Lett. 24 (2003) 433. [15] W. Ha, M. Urteaga, J. Bergman, B. Brar, W.K. Liu, D. Lubyshev, J.M. Fastenau, Y. Wu, M.T. Bulsara, E.A. Fitzgerald, W.E. Hoke, J.R. LaRoche, K.J. Herrick, T.E. Kazior, D. Clark, D. Smith, R.F. Thompson, C. Drazek, N. Daval, 66th Device Research Conference, Santa Barbara, CA, Jun 23–25, 2008 (IV.B-9).
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Monolithic integration of InP-based transistors on Si substrates using MBE W.K. Liu a,, D. Lubyshev a, J.M. Fastenau a, Y. Wu a, M.T. Bulsara b, E.A. Fitzgerald b, M. Urteaga c, W. Ha c, J. Bergman c, B. Brar c, W.E. Hoke d, J.R. LaRoche d, K.J. Herrick d, T.E. Kazior d, D. Clark e, D. Smith e, R.F. Thompson e, C. Drazek f, N. Daval f a
IQE, Inc., Bethlehem, PA 18015, USA Massachusetts Institute of Technology, Cambridge, MA, USA c Teledyne Scientific Company, Thousand Oaks, CA, USA d Raytheon RF Components, Andover, MA, USA e Raytheon Systems Ltd., Glenrothes, Fife, Scotland, UK f SOITEC, Parc Technologique des Fontaines, Bernin, Crolles Cedex, France b
a r t i c l e in fo
abstract
Available online 1 November 2008
We report on a direct epitaxial growth approach for the heterogeneous integration of high-speed III–V devices with Si CMOS logic on a common Si substrate. InP-based heterojunction bipolar transistor (HBT) structures were successfully grown on Si-on-lattice-engineered- substrate (SOLES) and Ge-on-insulatoron-Si (GeOI/Si) substrates using molecular beam epitaxy. Structurally, the epiwafers exhibit sharp interfaces and a threading dislocation density of 3.5 107 cm 2 as measured by plan-view transmission electron microscopy. HBT devices fabricated on GeOI/Si substrates have current gain of 55–60 at a base sheet resistance of 650–700 O/sq, and ft and fmax of around 220 GHz. HBT structures with DC and RF performance similar to those grown on lattice-matched InP were also achieved on patterned SOLES substrates with growth windows as small as 15 15 mm2. These results demonstrate a promising path of heterogeneous integration and selective placement of III–V devices at arbitrary locations on Si CMOS wafers. & 2008 Elsevier B.V. All rights reserved.
PACS: 81.05.Ea 81.05.Cy 85.30.Pq 84.40.Lj 68.55.Ac Keywords: A3. Molecular beam epitaxy A3. III–V on Si integration B1. GeOI/Si B1. SOLES B1. Si B1. InP B3. InP-HBT
1. Introduction Heterogeneous integration of high-speed III–V devices with Si CMOS circuitry has attracted significant interest for its potential in next generation monolithic hybrid integrated circuits (ICs) for analog and digital applications. A successful integration scheme will provide circuit designers with the ultimate technological flexibility of ‘‘best junction for the function’’ without compromising the yield and scalability of CMOS or the speed and breakdown of the III–V devices. Various approaches have been proposed to achieve this hybrid combination, from pick-and-place die transfer to full wafer bonding to direct growth of III–V devices on Si, but all lack aspects of the full benefits of III–V/Si integration. The approach we adopted is the direct molecular beam epitaxial (MBE) growth of III–V materials on Si utilizing composite Si-based substrates such as Ge-on-insulator-on-Si (GeOI/Si) and Si-on-lattice-engineered-
Corresponding author.
E-mail address: [email protected] (W.K. Liu). 0022-0248/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2008.10.061
substrate (SOLES). We have previously reported on the proof-ofconcept growths of InP-based transistors on un-patterned GeOI/Si substrates using composite InAlAs/GaAs metamorphic buffer (M-buffer) layers and compared their performance with baseline structures grown on InP, GaAs and Ge substrates [1–3]. In this work, we will focus on the MBE growth of InP-based heterojunction bipolar transistors (HBTs) on patterned GeOI/Si and SOLES substrates. There are several unique challenges in the epitaxy process that are critical to achieve high-quality InP-based device structures on patterned GeOI/Si and SOLES substrates. These include patterning, surface preparation, and growth methods that support the nucleation of low defect density, anti-phase domain (APD) free GaAs on the Ge surface of the GeOI/Si and SOLES substrates; prevention of Ge out-diffusion; growth of low defect density, device-quality InP-based structures on GaAs surface using a suitable M-buffer; and epitaxial growth inside the Ge windows. While GaAs and Ge are closely lattice-matched (Da/a0.07%), epitaxial growth of GaAs on Ge is prone to APD formation because of its polar-on-non-polar nature. APDs can be suppressed in MBE growth by using off-cut substrates, by optimizing the initial
ARTICLE IN PRESS 1980
W.K. Liu et al. / Journal of Crystal Growth 311 (2009) 1979–1983
nucleation condition, and by using thermal annealing techniques [4]. A variety of M-buffers have been used to facilitate the growth of InP-based devices on GaAs substrates [5–7]. The basic requirement of an M-buffer is to accommodate the lattice mismatch between GaAs and the InP-based alloys of the device structure and to absorb this strain while minimizing the nucleation of dislocations. The resulting surface should also have low roughness and minimal warp for device reliability and processing requirements. Graded InAlAs-based M-buffers have been used for production of InP-based metamorphic high-electron mobility transistors (M-HEMT) on GaAs substrates with proven reliability and device yield [8]. Figures-of-merit achieved include rms surface roughness in the 20–30 A˚ range for a 5 5 mm2 scan and channel charge mobility product almost identical to HEMTs grown on InP substrates. Similar characteristics have also been reported for M-HEMTs grown on un-patterned Ge and GeOI/Si substrates [1]. Less work has been done on metamorphic HBT (M-HBT) structures mainly because minority-carrier devices are in general more sensitive to dislocation density. Using a graded InAlAs M-buffer, we have achieved 80–90% of the large-area device figure-of-merit (DC current gain/base sheet resistance) on bare, un-patterned GaAs, Ge and GeOI/Si substrates with comparable breakdown voltage relative to control structures on InP substrates. Typically, the dislocation density for both M-HEMT and M-HBT structures is estimated to be in the 106–107 cm 2 range [1–3]. Due to the high sticking coefficients of group-III atoms, selective growth of InGaAs-based materials on masked area is difficult to achieve by MBE. The growth proceeds across the entire wafer, resulting in a polycrystalline growth on the mask material that requires a patterned dry etch process for its removal. The epitaxial challenge is to find the optimal growth condition for high filling factor within the windows opened through the mask, while maintaining good quality GaAs on Ge nucleation and InP device growth on the Ge surface inside these windows. Epitaxial growth on the limited area within the Ge windows could reduce the likelihood of misfit dislocations in the active layers by limiting misfit dislocation length and by reducing dislocation interaction and multiplication [9]. Potentially, small-area growth within the windows may also enhance dislocation filtering within the M-buffer and hence help reduce the threading dislocation density [9]. Our goal is to achieve a filling factor in the Ge windows that will allow placement of the active device junctions to within 5 mm from the edge of the window opening for intimate heterogeneous integration. In this work, InP-based HBT structures on GeOI/Si and SOLES wafers were used to demonstrate the potential of fabricating multi-level ICs with III–V circuitry integrated with Si CMOS logic. Surface morphology, structural properties, and interfacial quality of the epilayers grown on bare GeOI/Si were confirmed, followed by characterization of epilayers grown on patterned GeOI/Si and SOLES substrates. DC and RF characteristics of large- and smallarea HBTs fabricated on both bare and patterned GeOI/Si and SOLES substrates were then evaluated and Gummel plots, common-emitter IV characteristics, as well as ft/fmax data were extracted.
2. Experimental details HBT growths were performed on 100 mm diameter GeOI/Si and SOLES substrates provided by SOITEC using Smart-CutTM technology [10,11]. Essential features of these substrates include compatibility with Si CMOS fabrication processes, easy electrical isolation, and a lattice constant (Ge) suitable for growth and integration of III–V devices. The III–V on SOLES integration
BPSG
BPSG III-V Devices
Si SiO2
Si SiO2
Ge(100) 6°off SiO2 Si (100) Handle Wafer
Fig. 1. Schematic showing the placement of III–V epilayers in the growth window of a SOLES substrate.
scheme discussed in this work is illustrated in Fig. 1. The SOLES substrate contains a sandwiched Ge layer that is used as a template for III–V growth. From the top down, the SOLES wafer comprises of a Si layer, SiO2, Ge, SiO2, and a Si substrate. The topmost silicon layer is used for SOI CMOS fabrication to realize an integrated CMOS/HBT process. The crystal orientation of the thin embedded Ge layer was 61 off (0 0 1) toward /111S, which promotes III–V epilayer growth with minimal APD formation [12,13]. A boron–phosphorous–silicated-glass (BPSG) layer is initially deposited on the SOLES substrates to protect the Si CMOS layer. Growth windows with a wide variety of sizes are patterned by etching through the BPSG, the topmost Si layer, and the first buried oxide layer with a combination wet/dry etch process that exposes the buried Ge. Etching and cleaning processes have been optimized to control the sidewall profile and minimize the damage to the Ge layer to ensure high quality III–V growth. In order to monitor growth by RHEED and to use optical pyrometry for temperature control, a large 25 25 mm2 window was patterned in the center of test wafers. All III–V epitaxial growths for this work were performed on a multi-wafer Oxford Instruments V-100 MBE system equipped with group V As- and P-valved crackers and with conventional effusion cells for the group-III materials. Si was used for n-type doping, and p-type doping was achieved using a CBr4 gas source. Prior to MBE growth, the substrates were subjected to a UV ozone cleaning and the native oxide on the Ge surface was removed by thermal desorption at a temperature 500 1C. A single-stage growth process at 600 1C was used for the initial nucleation of GaAs on Ge and subsequent GaAs buffer has previously been shown to be effective in limiting APDs, minimizing Ge outdiffusion, and providing a low dislocation density on un-patterned GeOI/Si [1,2]. Following the growth of 0.6 mm of GaAs, a 1.1 mm InAlAs-based linearly-graded M-buffer layer with an inverse step was grown to transition to the lattice constant of InP. Details of the growth of the graded InAlAs M-buffer can be found elsewhere [5]. The HBT structure used in this work is a standard double heterojunction design with InP collector and emitter, and with a 400 A˚ thick InGaAs base C-doped at 4 1019 cm 3. An InGaAs setback layer and chirped super-lattice grade were used to remove the conduction band discontinuity at the base-collector interface [14]. Various characterization methods were used to analyze the quality of the epitaxial material. Surface morphology was evaluated via Nomarski contrast optical microscopy, atomic force microscopy (AFM), and scanning electron microscopy (SEM). The structural properties were assessed by high-resolution X-ray diffraction (XRD) and cross-sectional transmission electron microscopy (TEM). Small-area devices were fabricated using a standard non-selfaligned triple-mesa HBT process. After contact formation and
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semiconductor mesa etching, the devices were passivated and the surface was planarized with a spin-on-dielectric (BCB). Contact vias were etched in the BCB and first level interconnects were deposited to complete fabrication. DC and RF measurements were performed to extract typical parameters.
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Misfit Dislocations
5.7 μm
3. Results To evaluate the effectiveness of our GaAs nucleation process and M-buffer design, TEM was used to evaluate the structural quality of InP-HBT epi grown on GeOI/Si substrate. Examination of the GaAs/Ge interface reveals only limited APB formation, and in the regions where APBs did form, they quickly annihilated within the first 100 A˚ of the film growth. As shown in the cross-sectional TEM micrograph in Fig. 2, the main dislocation network is localized within the graded InAlAs M-buffer layer where the lattice parameter transitioned from that of GaAs to InP. The InPHBT layers above the M-buffer have well-defined interfaces. The threading dislocation density measured by plan-view TEM was found to be around (3.570.6) 107 cm 2 (Fig. 3). While the device characteristics of these wafers seem to be reasonable, more growth optimization work is currently underway to drive down the dislocation density and to understand its effect on long-term device reliability. In order to obtain device material quality on patterned substrates, MBE growth conditions must satisfy several additional requirements beyond that of standard growth on un-patterned substrates. While smooth epi inside the windows is a prerequisite, polycrystalline growth is expected on the BPSG-masked area. Problems can arise in future processing of the wafers if this polycrystalline material is too rough. Ga droplet formation on exposed Si along the sidewall of the windows can also promote polycrystalline, wire-like growth that can protrude into the window openings, thus shrinking the area for high quality III–V
Fig. 3. Plan-view TEM evaluation of residual dislocation density at the top of an InP-HBT structure on un-patterned GeOI/Si substrate. Images from two representative regions are shown.
20.0
10.0
25 µm 0
Poly crystal on BPSG
Single crystal inside growth window
10.0
0 20.0µm
Polycrystalline material removed Single crystal inside growth window < 2µm
Fig. 4. Surface morphology of InP-HBT structures grown on patterned SOLES substrates: (a) Nomarski, (b) AFM with rms roughness of 13 A˚ (same area as (a)), and SEM images (c) before removal of the polycrystalline material and (d) after removal of the polycrystalline material (close-up of one of the growth windows).
InGaAs Base InP Collector InP Subcollector
14 Threads
11 Threads
InP-HBT
InAlAs Buffer
GaAs Ge SiO2 Si 500 nm Fig. 2. Cross-sectional TEM image of an InP-HBT structure grown on an unpatterned GeOI/Si substrate.
growth. To minimize the roughness of the polycrystalline material and nucleation along the window sidewalls, growth conditions previously optimized for un-patterned growth had to be modified for patterned substrates. Instead of using a 600 1C single-stage growth, the GaAs buffer layer was grown at reduced temperature to minimize Ga surface migration during epi growth and inhibit droplet formation and wire nucleation. Growth conditions for the initial GaAs nucleation on Ge, graded M-InAlAs M-buffer, and InP-HBT structure remained the same for both patterned and un-patterned substrates. The surface morphology of an InP-HBT structure grown on a patterned SOLES substrate is depicted in Fig. 4. The Nomarski (Fig. 4a) and AFM (Fig. 4b) images inside the windows exhibit cross-hatch patterns characteristic of high-quality metamorphic growth with low rms roughness of 13 A˚ for a 20 20 mm2 AFM scan. Similar roughness levels were observed for HBTs grown on patterned GeOI/Si substrates. SEM images taken before and after removing the polycrystalline material from HBTs on patterned SOLES reveal a gap of only 2 mm between the sidewall of the window and the smooth epi region inside. Well-defined window edges, flat, smooth epi with high filling factor inside the growth windows, as well as low roughness polycrystalline material on the
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InP-HBT layers on top can be clearly seen in the HRXRD spectra shown in Fig. 5. The FWHM for the GaAs and HBT layers are close to the values measured on bare substrates, indicating that structural quality of material grown on patterned substrates is close to material previously grown on bare substrates. It is widely understood that minority-carrier devices such as HBTs are more sensitive to dislocations and defects near the heterojunctions, with typical degradation observed in the current gain (b) and in the base-collector breakdown voltage [5]. Large-area device DC parameters of InP-HBT structures grown on un-patterned Ge and GeOI/Si substrates have been shown to compare favorably with baseline structures grown on InP and GaAs substrates with minimal degradation in b and breakdown voltage [2]. InP-HBT structures on un-patterned GeOI/Si substrates were then fabricated into small-area devices with emitter area 0.5 5.0 mm2. Gummel plot and RF data shown in Fig. 6 reveal DC current gain of over 40 and ft, fmax of 220 GHz. To evaluate the InP-HBT structures grown on patterned SOLES substrate, small-area devices were fabricated within various sizes of growth windows. An SEM image of an array of InP-HBT devices fabricated on patterned SOLES substrates prior to final device passivation is shown in Fig. 7a. The distance between the active junction area and the window edge is o5 mm, which is important for heterogeneous interconnect requirements between the III–V devices and the CMOS circuit. Good DC and RF device characteristics were measured for devices in windows as small as 15 15 mm2. Devices with emitter area of 1 3 mm2 exhibit b of 40 and a common-emitter breakdown voltage BVCEO=6 V at a current density of 10 mA/mm2. An ft of 190 GHz was extrapolated
masked area demonstrated here are encouraging features for III–V device cluster fabrication on CMOS wafers. The structural quality of the epi material was then evaluated. The XRD spectra of InP-HBT structures grown on patterned GeOI/Si and patterned SOLES substrates were qualitatively the same as those obtained from growth on un-patterned GaAs substrates. Well-defined peaks from the GaAs buffer layer on Ge, the linearly-graded InAlAs M-buffer with an inverse step, and the
1E+05 on GaAs (reference) on patterned SOLES
GaAs substrate
Intensity (cps)
1E+04 M-HBT
1E+03 Ge+GaAs
1E+02 1E+01 1E+00 31.0
Linearly-graded InAlAs M-buffer
31.5
32.0 32.5 ω-2θ (degree)
33.0
33.5
Fig. 5. High-resolution XRD (0 0 4) spectra of InP-HBT epi inside the growth window of a patterned SOLES substrates. Reference spectrum from the same structure grown on GaAs substrate is also shown.
40
10
-4
10
-6
10
-8
AE = 0.5x5 µm = 40
2
|H21| (red), U (blue) (dB)
Base, Collector Current (A)
10-2 Ic
Ib
10-10 10-12
0
0.2 0.4 0.6 0.8 Base-Emitter Voltage (V)
1
AE = 0.5x5 µm2 IC = 7.8 mA
35 30
VCE = 1.5V
25 20 15 10 5 0 109
ft = 224 GHz fmax = 219 GHz
1010 1011 Frequency (GHz)
1012
Fig. 6. (a) Gummel plot and (b) unilateral power gain and short circuit current gain versus frequency plot for small-area (0.5 5 mm2) HBT devices fabricated on unpatterned GeOI/Si substrates.
Fig. 7. (a) SEM image of an array of InP-HBT devices fabricated on a patterned SOLES substrate prior to final device passivation and (b) close-up of a single InP-HBT device.
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from the RF plots, consistent with previous results demonstrated on GeOI/Si substrates and comparable to what one would expect from a lattice-matched InP-HBT with the same device dimensions [15]. The extraction of fmax was hampered by the deviation from the 20 dB/decade roll-off characteristic of the unilateral power gain versus frequency curve, probably caused by the underlying conductive Si substrate used in this work [15]. Improvements in RF performance can be expected with further lateral scaling of the transistors and the use of a more resistive transferred Ge layer and Si handle substrate.
4. Summary The MBE growth of InP-based HBT structures on GeOI/Si and patterned SOLES substrates has been successfully demonstrated, with high-quality epilayers obtained on the latter with a minimum window size of 15 15 mm2. Smooth surfaces with an AFM rms roughness of 13 A˚ with minimal exclusion area at the window edges make the proposed MBE growth sequence on patterned SOLES substrates suitable for monolithic III–V device integration into Si CMOS circuitry. Large-area device characteristics for InP-HBTs on GeOI/Si substrates were comparable to reference structures grown on InP and Ge substrates. Small-area HBTs on GeOI/Si substrates show excellent DC current gain (b 440) and RF figures-of-merit (peak ft/fmax220 GHz). For a first time, InP-based HBTs grown on patterned SOLES substrates were demonstrated and characterized. Small-area HBT devices, with 1 3 mm2 emitter area, fabricated on patterned SOLES substrates with windows as small as 15 15 mm2, demonstrate b of 40, BVCEO=6 V at current density of 10 mA/mm2, and with extrapolated ft of 190 GHz. This work demonstrates the viability of this approach in the development of monolithic integration of III–V devices with CMOS technology.
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Acknowledgements The authors thankfully acknowledge DARPA COSMOS Program (N00014-07-C-0629, Program Manager: Dr. Mark Rosker, COTR: Dr. Harry Dietrich). MIT acknowledges research funding support from the Army Research Office (ARO). References [1] D. Lubyshev, J.M. Fastenau, W.K. Liu, Y. Wu, M.T. Bulsara, E.A. Fitzgerald, W.E. Hoke, J. Vac. Sci. Technol. B 26 (2008) 1115. [2] D. Lubyshev, J.M. Fastenau, Y. Wu, W.K. Liu, M. Urteaga, W. Ha, J. Bergman, B. Brar, M.T. Bulsara, E.A. Fitzgerald, W.E. Hoke, J.R. LaRoche, K.J. Herrick, T.E. Kazior, 20th InP and Related Materials Conference, Versailles, France, 25–29, 2008 (MoB2.3). [3] K.J. Herrick, M. Urteaga, A.W.K. Liu, D.I. Loubychev, J.M. Fastenau, E. Fitzgerald, M. Bulsara, B. Brar, W. Ha, J. Bergman, T. Kazior, N. Daval, 2008 MRS Spring Meeting, San Francisco, CA, Mar 24–28, 2008 (C2.1). [4] R.M. Sieg, S.A. Ringel, S.M. Ting, E.A. Fitzgerald, R.N. Sacks, J. Electron. Mater. 27 (1998) 900. [5] D.I. Lubyshev, J.M. Fastenau, X.-M. Fang, Y. Wu, C. Doss, A. Snyder, W.K. Liu, M.S.M. Lamb, S. Bals, C. Song, J. Vac. Sci. Technol. B 22 (2004) 1565. [6] R.E. Leoni III, W.E. Hoke, C.S. Whelan, P.F. Marsh, P.C. Balas II, J.G. Hunt, K.C. Hwang, S.M. Lardizabal, C. Laighton, S.J. Lichwala, Y. Zhang, T.E. Kazior, Digest of Papers, 2002 International Conference on Compound Semiconductor Manufacturing Technology, (ISBN 1-893580-03-2, GaAs MANTECH, St. Louis, 2002), p. 272. [7] Y.M. Kim, M.J.W. Rodwell, A.C. Gossard, J. Electron. Mater. 31 (2001) 196. [8] P.C. Balas II, C.S. Whelan, M. Benedek, W. Stiebler, J. Kim, L.M. Aucoin, Technical Digest 2002 Compound Semiconductor Manufacturing Expo, IOP, Bristol, UK, 2002, p. 4. [9] E.A. Fitzgerald, J. Vac. Sci. Technol. B 7 (1989) 782. [10] C. Maleville, C. Mazure´, Solid State Electron. 48 (2004) 1055. [11] Smart-CutTM is a registered trademark of Soitec. [12] R.M. Sieg, S.A. Ringel, S.M. Ting, E.A. Fitzgerald, R.N. Sacks, J. Electron. Mater. 27 (1998) 900. [13] S.M. Ting, E.A. Fitzgerald, J. Appl. Phys. 87 (2000) 2618. [14] M. Dahlstro¨m, X.-M. Fang, D. Lubyshev, M. Urteaga, S. Krishnan, N. Parthasarathy, Y.M. Kim, Y. Wu, J.M. Fastenau, W.K. Liu, M.J.W. Rodwell, IEEE Electron Device Lett. 24 (2003) 433. [15] W. Ha, M. Urteaga, J. Bergman, B. Brar, W.K. Liu, D. Lubyshev, J.M. Fastenau, Y. Wu, M.T. Bulsara, E.A. Fitzgerald, W.E. Hoke, J.R. LaRoche, K.J. Herrick, T.E. Kazior, D. Clark, D. Smith, R.F. Thompson, C. Drazek, N. Daval, 66th Device Research Conference, Santa Barbara, CA, Jun 23–25, 2008 (IV.B-9).