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MOSFET performance enhancement by improved SOS material processes
MOSFET performance enhancement by improved SOS material processes by R. L. M a d d o x , A. L. Lin, I. Golecki* and H. L. Glass** Rockwell International Corporation, Microelectronics Research and Development Center, Anaheim, CA 92803 USA *Also Visiting Associate, California Institute of Technology, Mail Code 116-81, Pasadena, CA 91125 *~ Rockwell International Science Center, Anaheim, CA 92803
The performance of NMOS/SOS devices designed for near micron geometries is shown to be enhanced markedly by pre-process SOS material improvements. A description of the double solid phase epitaxial regrowth technique, DSPE, is presented including the results of several materials evaluation, techniques: Rutherford backscattering and channeling spectrometry, X-ray twin content, sheet resistance, spreading resistance, ultraviolet reflectivity, and Hall data vs. temperature. Post-MOS process evaluation data of materials and device properties is also presented, which includes: gated Hall data, SIMS, sheet resistance, majority and minority carrier mobility, threshold voltage, subthreshold current slope, back channel leakage current, and electrical carrier density profiles. Significantly enhanced device performance is reported, such as --- 20% improvement in all mobilities, factor of 100 reduction in twin content, factor of 5 to 10 reduction in backchannel leakage, and 15 to 25% improvement in subthreshold current slope. 1.
Introduction
The performance of any solid state microelectronic device is closely related to the crystalline quality of the material used. This is particularly true of CMOS on sapphire structures. Silicon on sapphire technology (SOS) utilizes an insulating substrate of sapphire to provide "ideal" isolation between devices made from a thin film of silicon deposited heteroepitaxially on the sapphire t. These devices are isolated electrically by sapphire in the vertical direction and laterally by silicon dioxide. The thickness of the silicon film is in the range 0.2 < t > 1.0/xm. The quality of the film improves substantially with film thickness. For example, 0.5 p.m film has very good crystalline quality at the top surface of the etailayer and substantially poorer quality at the silicon-sapphire interface. The distribution of defects is exponential, with the peak at the silicon-sapphire interface on the order of 4 x 10I - 106 planar faults/cm2~and -- 109 line defects/cm~-, as discussed in ref. 2. There are several means of improving the crystalline quality throughout the SOS film3. Most of these are based on one form or the other of solid phase epitaxial regrowth of the Si epilayer4 - a. The subject matter of this work describes the device and material improvement aspects of NMOS/SOS devices whose performance was enhanced by the double solid phase epitaxial regrowth technique, DSPE. NMOS devices were chosen because of their sensitivity to material properties, e.g., mobility and leakage, and due to the fact that the PMOS devices were of the buried channel type and not as straightforward to interpret. The process used to fabricate devices on the improved SOS miaterial is identical to that published and characterized earlier l~ except that the gate oxide was increased from 160/~ (for a 1 pm technology) to 300/~, to facilitate pulsed C-V measurements, 48
MICROELECTRONICS JOURNAL Vo115 No 5 9 1984 Benn Electronics Publications Ltd, Luton
1.5 MeV 4He + ANALYSIS ,x 12"
~m)
Si DEPTH SCALE
0.4
~" z:::) 0
1
0.2
1
0
I
0
I
I
I
.~.~.~.~^ ,,~ '
t. A
13d >-
t.
:~:'L':- a: 9 o J
:.
q'o~z %-
'~ ~.
.;'..~. ~..
|
,u)~ v
o
":~.::.,"?:" G ':'~ ....
/
m
"H'" " "';""":'::"...-.,~: "o','-~"
0
T '~ '?'-",
]
0.6
0.8
EACKSCATTERED ENERGY (MeV)
Fig. 1 Rutherford backscattering and axial channeling spectra of 0.48p.m thick, (100) SOS films. G (aligned): 400 keV, 2x10 '5 Si/cm~ + 2.5h, 560"C N,, + (80 keV, 2x10 ts Si/cm~ + 200 keV, 2.5 • I0 t5 Si/cm2) + 2h, 560"C, N2; H (aligned): same as G + 3h, 925~ N2; J (aligned): as-deposited (unimplanted) + 4.5h, 560"C; R (rotating random). See Table I for the values of the channeling yields and dechanneling rates.
TABLE I Channeling yields and average dechanneling rates for doubly recrystallized (G,H) and unimplanted control (J) SOS films. The corresponding spectra and detailed description of the samples are given in Fig. 1. Sample
Si Thickness, t (~m)
X
X
o
i
dx dz
Xt-Xo -
(#mx')
t
J
0.48
0.I0
0.58
1.0
G
0.48
0.060
0.20
0.29 (0.21)"
H
0.48
0.051
0.18
0.28
"Measured above and below buried, defective transition region.
2.
Experimental
2.1 DSPE Process Threeinch diameter SOS wafers with 0.5 ~m -+10% nominal silicon film thickness supplied by Union Carbide were used as the starting material. The films were deposited undoped at 910~ at a deposition rate of 1.1/zm/min. Initially the films were n type with a sheet resistance of -- 2 • 10a 1"//O. Half of each wafer was masked with 1.0/zm of densified silox such that, with the wafer flat at the bottom, the left side (pos.2) was the control sample and the right side (pos.4) was the DSPE sample. This system of control sampling was necessary due to the lack 40
MOSFET performance enhancement by improv~l SOS material proce==escontinued from page 49
of adequate wafer-to-wafer uniformity with respect to device performance experienced with SOS, as compared to bulk silicon. The DSPE process followed the following steps: a) The silicon film was amor~hized by a low current, high dose silicon implant with the 9 exception of the top 700 A of the film. The implant conditions were 400 keV, 2x 10 ~5 28Si/cm2, current density < 0.5 I.tA/cm 2, and 7~ angle of incidence from the wafer's surface. b) The top 700/~ of the silicon film, being of the best crystalline quality, was used as a seed to recrystallize the remainder of the film at 560~ in nitrogen. The recrystallized defect profile was verified by RBS measurements. c) The top of the silicon film was then similarly amorphized by a silicon implant; 80 keV, 2x 10~ 28Si/cm2 plus 200 keV, 2.5 x 10~ 2sSi/cm2 under the same current and angle conditions. d) Finally, the top portion of the silicon film was recrystallized using the previously recrystallized bottom portion of the film as a seed, at 560~ in nitrogen and a sample was checked by RBS. Typical RBS data is presented in Table I and Fig. 1. The material was characterized at each major step of the DSPE and MOS process by use of a blank drop-in chip at positions 2 and 4 described earlier. The difference, AR, between the ultraviolet reflectivity (UVR) at wave lengths of 280nm and 400rim has been suggested as an incoming SOS wafer acceptance criterion I~. In practice, a value of AR < 15 has been observed to provide adequate device results. The UVR data was taken at each of the four steps of the DSPE process as well as at the initial conditions. This is shown in the Appendix, Table A. The data presented this table is not straightforward to interpret except for the fact that values of AR->300 indicate amorphous surfaces as expected for the second Si implant. The volume fraction of twins was determined from measurements of the diffracted X-ray intensity of twin relections relative to parent reflections. The twin content, shown in Table II, documented the earliest observable results of the material improvements generated by the DSPE process. The data for the control (non-recrystaIlized) side of the wafers in Table II are a result of only the 560~ furnace operation. Note that a twin density of 0.03% is equal to the signal background level of the apparatus. By the end of MOS processing a reduction of 9 greater than a factor of 100 was observed. TABLE II X-ray twin content Step InitialCond. Ist Rextal 2nd Rextal End MOS Process
% Control (POS. 2) DSPE (POS. 4) 2.9
3.6
1.3
1.2
2.1 0.8
0.03 <0.03
The sheet resistance of the DSPE material will necessarily be smaller than that of the control sample due to the diffusion of aluminum that was released by the amorphization process from the sapphire substrate. This data is shown in Table III. This difference in sheet resistance was observable throughout the MOS process which includes the p type channel doping, -- 10~rcm-3. The reduction in sheet resistance of the DSPEmaterial, following the 925~ annealing, is related to the 'dissolution' of the band of extended line defects, (probably dislocation loops) present after 560~ recrystallization at a depth of ---0.3/.tm, at the original 50
TABLE III DSPE material sheet resistance (I//[]) WFR No
Initial Condition
Ist
925~ +
Rextal
2nd Rextal (All p type)
(n Type)
Test
Isol.* Oxidation
End of** MOS Process
I
i .9E8
2.7E4
3.5E7
5.1E4
5.0E3
4.7E3
2
1.6E8
3.0E4
3.7E7
8.9E4
6.5E3
5.5E3
3
2.5E8
2.8E4
1.7E8
7.3E4
6.7E3
6.1E3
4
1.6E8
2.5E4
1.2E8
I.IE5
6.5E3
5.7E3
5
2.0E8
2.6E4
3.6E7
6.0E4
5.9E3
5.0E3
11
4.1E8
2.2E4
3.6E7
9.8E4
7.1E3
6.1E3
+ 925"C, 60 min. in N2 * I l a d ~ 10trcm -s Boron doping, 250 keV, 5 x 10ncm -2 + 170 keV, 6 x 1011cm-~ + 1000~ 150 rain. N2 * * Had Boron V-m implant, 26 keV, 2 x 101Zcm-2 through 425~ sacrificial oxide.
amorphous/crystalline boundary (see RBS spectrum G in Fig. 1). Spreading resistance profiles of the net dopant concentration for the DSPE process are given in Fig. 2. The difference in dopant concentration due to diffusion of alluminum from the sapphire substrate can be demonstrated by an Arrhenius plot of the p type dopant concentration (after the first silicon implant and anneal) taken from Hall bar data as shown in Fig. 3. The Hall factor is assumed to be unity. The mobility and resistivity data versus temperature taken from the Hall bar data are also shown in this figure for DSE material. The slope of log N^ versus 1/T gives the accepted aluminum energy level in silicon, n SIMS data of the aluminum concentrationdepth profile in DSPE and control material at the end of MOS processing shown in Fig. 4. Although the particular control film shown in Fig. 4 had a mass 27 signal level of -~3 x 1015/cm3, other control samples yielded levels of (1-3) x 1016/cma. We believe these correspond to the instrumental background level, and not to real aluminum in the films. The origin of the increase in A1 signal in the near-interface region, as well as other instrumental aspects have been discussed in ref. 7. Note that the increase in A1 concentration after many high temperature steps corresponds to the 925~ data in Table III. The leveling off of the free carder concentration shown in Fig. 3a at temperatures below about 50~ indicates that impurity band conduction is dominant near the Si-Sapphire interface for dopant concentrations greater than 10~Scm-a approximately, zz Other studies describing results obtained by the DSPE process are given in references 13 through 16. A gated Hall bar structure ~7was used to measure the majority carder mobility by analysis of I-V characteristics (average drift mobility) and by Hsu's technique ta (drift mobility profile), in addidion to the Hall mobility on finished devices. These results will be dompared in the discussion. 2.2 MOS Process The NMOS/SOS process Used in this work I~was optimized for near-micron channel lengths. Basically, it has a grown oxide isolation structure (LOCOS), with polycide gates and N^ 2• 1017cm-z, as shown in the SIMS data of Fig. 5 for the DSPE material. The final sheet resistances of control and DSPE sampling are given in Table III. The gate oxide thickness was verified to be 300-+ 15.~, over the entire wafer. The shapes of the test device CoV curves showed no significant differences in fiat band voltage or surface state density. The drainsource breakdown voltage was 11.4 • 0.2 volts for all devices with L >- 2ptm. The molybdenum polycide gate sheet resistance was 11.5 • 0.7 f l / [ ] and the n § and p+ sheet resistances were 51
MOSFET performanceenhancementby improvedSOS material processes continued from page 51
105
I
n
1o4
lo3
Z
r (3 Z
t0
P 1.o
0.1 0
I
I
1
I
0.1
0.2
0.3
0.4
0.5
Si EPI THICKNESS (pm)
Fig. 2 Spreading resistance profiles on SOS test wafer a) as-deposited, b) after first Si implant and anneal, c) at conclusion of DSPE process. The spreading resistance data Was taken by Solecon, Inc., Costa Mesa, Ca.
120 and 165 f l / [ ] for phosphorus and boron doping respectively. The n § diffusio~ extended through the entire film thickness away from the gates with approximately 0.25/.tm junction depth adjacent to the gates. This structure retained the short channel otpimised structure while still reducing the junction capacitance to the minimum value possible. Source follower conductance measurements were used to determine the (extrapolated) threshold voltages and effective channel mobilities of the MOSFETs. Measurements of the logarithm of the source-drain current versus gate voltage were used to determine the leakage and the subthreshold current slope. The gate oxide thickness was obtained from 60 x 60/zm FET capacitance and SEM measurements. A curve tracer was used for initial device screening as well as breakdown voltage, some threshold voltage, and sheet resistance measurements. A test device yield exceeding 75% was obtained on all wafers processed. All device length and width measurements were obtained from SEM. 52
103/'1 ` ( ~ I0 IB
FOR PH 40 I
i
t~0
1017
~
1016
z~IO 15
'L
102 --
1014
10
101
I
10
20
30
lo3/r i% -I) FOa N8
[a]
I
~1o2
10
I 10
t
I
1
I Illl
IO2
t
I
t
t
t
ttw
IO*
103/T, I~
[b] Fig. 3 a) Hall bar resistivity and carrier concentration versus reciprocal temperature for SOS wafers that received only the 400 keV Si implant and first rect3'stallization anneal. The presence of aluminum diffused from the sapphire is indicated by the energy level obtained from the slope of the linear portion of the curve, b) Hall mobility versus reciprocal temperature for the devices in part a). 53
MOSFET performance enhancement by improved SOS material processes continued from page 53
1020
m
~
m
m
m
~
m
Si REFERENCE %=m
~ - = e.= m
m
m
= . m = . ~ = m m.~
I
1019
r
1018 O Z
o FZ
uJ (J
r,,3
1017
1016
AS-GROWN
1015
I
0.2
"
I
0.4
0.6
DEPTH (pM)
Fig. 4 SIMS data for aluminum concentration vs depth in as-grown and DSPE SOS material at the conclusion of MOS processing. The SIMS data was taken by Charles Evans Associates, San Mateo, CA.
54
1019
~1018 O
1017
B
1016 -
1015
I
I
0.20
0
0.40
0.60
DEPTH (MICRONS)
Fig. 5 SIMS data for MOSFET channel boron concentration at the conclusion of MOS processing. The value/profile of NA used was designed for near micron channel length. Data measured by Charles Evans Associates.
2.0
2.0
AS-DEPOSITE~::~
1.8
1.8 >
.....:/:ii::~
>~ 1.6 1.4
y
RECRYSTALLIZED
f
1.2~
,
.
,
,
. ~. ~ ! ~
1.4 tsi =
w = 5.1~tm
1.2-,t
I d = 1 laA
tsi= 0.46 lam 133 .0
~
"~ 1.6
>
I 1
I 2
I 3
I 4
I 5
1.0
0.46 ltm
RECRYSTALLIZED
=2.51am
Id = 1 laA I I 0 2 4
l(/Jm)
I 6 w(~tm)
I 8
I 10
12
Fig. 6 MOSFET threshold voltage as a function of channel length and width for as-deposited and DSPE material. This data was taken on a curve tracer at Ins = lgtA, VDs --- 3 V. Extrapolated threshold voltage data is presented in Table V (from g-V curves).
55
MOSFET performance enhancemeflt by improved SOS material ~
continued from page 55
T A B L E IV Final s h e e t resistance g,(n/
)
WRF NO 1
2 3 4 5 11
Control
DSPE
11.8E3 15.4E3 11.2E3 14.2E3 10.5E3 11.7E3
4.66E.3 5.50E3 6.10E3 5.74E3 4.95E3 6.07E3
TABLE V T h r e s h o l d v o l t a g e e x t r a p o l a t e d f r o m c o n d u c t a n c e curves: V n s 0 . 1 V , L = 2 . 5 # m , W = 5.1/zm, N ^ ~ 1.8E17, an d tox = 290,~. V~l(V)
WFR NO Control
DSPE
1
1.95 --- .02
2 3 4 5 11
1.91 --- .04 1.88 -+ .03 1.95 ~ .03 1.81 • .04 1.86 • .04
1.80 --- .07 1.76 • .01 1.64 • .03 1.64 __..01 1.63 • .09 1.61 • .04
T A B L E VI S u m m a r y o f g a t e d H a l l b a r m e a s u r e m e n t s f o r h o l e s at flat b a n d c o n d i t i o n Control Device No.
DSPE
PGH (• cm)
#GH (an'/V-s)
No:~ll (an-~)
PGH (~ an)
/aGtt (an'N-s)
NGH (an-~)
0.312
114
1.75E17
0.168
145
2.5E17
0.276
116
1.93E17
0.162
138
1.78W 17
0.304
113
1.82E17
0.142
133
3.30E17
0.313
115
1.73E17
TABLE VIII S u m m a r y o f a v e r a g e free h o l e m o b i l i t y Drift Mobility (cm'/V-s) Device Number
IIall Mobility (cm'/V-s)
Control
DSPE
Control
DSPE
188
227
113
133
197
246
115
145
193
223
114
138
116 56
3.
Discussion of results
The behaviour of the threshold voltage with respect to MOSFET W and L is shown in Fig. 6. This data was taken on a curve tracer and follows closely the trends expected for short channel devices and also the data of ref. 10 except that VTH is larger due to the increased gate oxide thickness. Threshold voltage data extrapolated from conductance curves is of more utility to the device analysis and a subgroup of that body of data is given in Table V. The threshold voltage of the DSPE material is about 0.2 volts smaller than that of the control material even though the dopant concentration measured by sheet resistance is greater and the gate oxide thickness and flatband conditions are equal. This effect was reported by other researchers on DSPE material recently as well 1~19. The dopant concentration profile measured by CV analysis of gated Hall bars supports the sheet resistance data of Table III as shown in Fig. 7. In addition, the Hall effect measurements, Table VI, support the data. 6
4.5
~-
3 DSaE ZX 1.5
0
0
I
I
I
.02
.04
.06
.0e
DISTANCE FROM 52/5iC)2 INTERFACE (/~M)
Fig. 7 Free carder concentration profiles (for holes) taken by pulsed CV measurements at the conclusion of MOS processing. 3OO
225
~"c
sn i
75
0
0
I
.02
I "
.04 OISTANCE F ROM ~ i O
I
.0G
.08
2 INTE R FACE, (HM)
Fig. 8 Drift mobility (holes) as a function of SOS film thickness by Hsu's method (at the ~onelusion of MOS processing).
Four separate techniques were used to evaluate the mobility improvement of the DSPE material. All data on these devices reported a 10-30% improvement in mobility. Table VII compares the average majority carder (holes) mobility of control devices to that of DSPE devices measured by the gated Hall technique at flat band conditions, as well as by the I-V~ 57
MOSRET perfom~ance =mhancement by improved SOS m=tmial ~
continued from page 57
techniques. Drift mobility profiles reduced by Hsu's method 18for control and DSPE devices are shown in Fig. 8. The effective channel mobility,/zw, extracted from the conductance curves o f N M O S F E T ' S (minority carriers) is shown as a function of channel width, W, in Fig. 9. T h e decrease i n / z w with decreasing W is a short channel effect explainable by the increase in effect of the electric field density component at small geometries. This, and other effects that would be correction factors to t t ~ data for short channel devices are discussed in refs. 20 and 23. The behaviour of # r e as a function of transverse (gate) electric field density is shown in Fig. 10. The absolute value of mobility in this report is not as large as is commonly r e p o r t e d for NMOS/SOS devices due to the large N^ and thin gate oxide required for short channel avoidance.
400 350 -
~ D O U B L Y ~ RECRYSTALLIZED
F
"-" 3oo
,.,~.~~
AS-DEPOSTED
i11
,T ~ 250 ~ 200
/:i::i~ i~i::'~-
tsi = 0.46_pm
//I
t,
~/
,s ..c2.5 .um NA~1.5 X 1017h/cm3
-003 .m
150 0
I
2
I
4
I
I
I
I
6 8 10 12 CHANNELWIDTH, w (pm)
Fig. 9 Effective channel mobility for NMOS devices as a functionof channel width (electrons). This data was obtained from analysisofg-V curvessupplementedby CV and SEM data for the gate oxide thickness and the dimensions, W by L, of the device. The reduction in # ~ for small W is a short channel effect aused mainlyby excessivetransversefieldstrength. Edgeless FET's were used to evalute the backchannel leakage for the NMOS/SOS devices process so that edge effects which can confuse the interpretation of the data are eliminated. O n the average, a factor of 10 improvement was achieved as sh.own in the log los vs Vg data of a group o f >20 devices in Fig. 1 la. In addition to the average value of back channel leakage being reduced, the distribution of the values of leakage current was reduced as well. It is our opinion that the reduction in back channel leakage is a result of the reduction in mlcrotwin content 9 and is also a feature of the increase in net P type dopant concentration adjacent to th~ silicon-sapphire (back channel) interface as was shown in Figs. 2 and 4, even though the free carrier concentration was shown to drop slightly in that region as shown in Fig. 7 and as discussed in ref. 2. The effect of varying drain bias is shown in Fig. l l b . A noticeable short channel effect is seen in Fig. l l b due to the relaxation of short channel avoidance parameterst~ e.g., the gate oxide thickness used in this work. T h e subthreshold current slope for edgeless FETs, under the conditions of Fig. 11 a, was 60 to 65 mV/decade of current for the DSPE sampling and 70 to 80 mV/decade for the control sampling: This data represents a 15 to 25% improvement and agrees with that published in ref. 10. T h e subthreshold current slope appears to decrease with increasing Vos as shown in Fig. l l b . 58
~" 320 1
> 300 - / r / 5 >- 280
DOUBLYRECRYSTALLIZED
~
/
_J
o 260 - ~ ;E f"'-" I-o UJ 240 It.
~
w/J{ = 3.0/2.5 (lam/pm) tsi = 0.46 ttm tsi02 = 0.03 lam
~.\\\ ~%=o.1 v ~
LL
9 LLI
220 --
m LL
AS-DEPOSITED Vth = 1.9 V
~
- ~
2o01d 0
I
I
I
1
2
3
I
I
4 5 IVg- Vthl (v)
I
I
I
6
7
8
Fig. 10 Effective channel mobility as a function of gate field strength. 4.
Conclusion
The material characteristics of as-deposited and DSPE improved SOS wafers were compared before and after MOS device processing. A significant redu~:tion of microtwin content (factor of 100) resulted for DSPE improved material, and is assumed to be the primary reason for all other improvements measured. Aluminum diffused from the sapphire was positively identified and its concentration profile determined. The mobility of both majority and minority carriers was improved by greater than 20%. The performance of NMOSFETs was also shown to be improved by the DSPE process e.g., factor of 5 to 10 reduction in back channel leakage and >15% increase in subthreshold current slope. 5.
Acknowledgements
The authors would like to acknowledge the help of Nancy Casey and Frieda Kinoshita for assistance in wafer processing, Gene Whitcomb for dry etch consultation, Rich Johnson for SEM, and Mollie Glowna and Edie Dodd for some of the parametric testing. We would also like to acknowledgement the support of Jack Mee. 96.
References
[1] Manasevit, H. M., Simpson, W. I., J. Appl. Phys. 35, 1349 (1964). [2] Abrahams, M. S., Buiocchi, C. J., AppL Phys. Lett. 27, 325 (1975). [3] Golecki, I., "The Current Status of Silicon On Sapphire and other Heteroepitaxial Silicon on Insulator Technologies," Proceedings of the symposium on Comparison of Thin Film Transistors a/ad SOl Techologies, M. J. Thompson and H. W. Lam, eds., 1984 Spring Meeting of Material Research Society, Feb. 1984 Albuquerque, MN, USA. [4] Yoshii, T., et al, Japan. J. Appl. Phys 21 Suppl. 21-1, 175, 1982, also 23rd Electronic Material, Conference, Santa Barbara, CA. No. 0-8, June 1981. [5] Amano, J., Carey, K. W., Appl. Phys. Lett. 39, 163 (1981). [6] Golecki, I., Glass, tI. L., Kinoshita, G.,Appl. Phys. Lett. 40,670(1982). 59
MOSFET performance enhancement by improved SOS material processes continued from page 59
10-4
10-6
E
tsi = 0.44 IJm Vds = 0.5 V w / l = 72/2 (!um/IJm)
10-s
Z LU rr I1-
/,f
r
10 -6
EDGELESS, n-CHANNELTRANSlSTORS
10-7
------[AS-DEPOS,TED]
10-7
-10-8
<~ :ff ~D _.J
I DouBLY-REcRYsTALuzED
I
10 .9
u.I
z z
(.) ,< r'r" Q
~
10-8
109
10 11 O
_z < 10-10
10_12 r~
I0-" I -5
I -4
I -3
I -2
1 -1
I 0
I 1
I
2
a
GATE VOLTAGE, Vg (V)
[a] 10"4
10-5
(i/h'
10~
Ill'
10-7
10~
---
-"=--.
IJIl
10-g
10-10
10-11 -5
I
-4
I
-3
I
-2
I
-1
I
0
[
1
I
2
I 3
I 4
vGw)
[H Fig. 11 a) Transfer characteristic of NMOSFET (IDs VS. Vg at fixed VDS) from which the backchannel leakage and subthreshold current slope are obtained. Note the reduced magnitude and distribution of leakage for devices fabricated on DSPE material, b) NMOSFET transfer characteristics at VDS = 0.5, 2.0, and 5.0 volts. The leakage current near Vg = 0 is less at all values of Vos for DSPE material than for as-deposited material. 60
[7] Golecki, I., Maddox, R. L., Stika, K. M., J. Electron. Matl. 13, 373 (1984); also 25th Electronic Matls. Conf., Burlington, VT, No. N-4, June 1983. [8] Lau, S. S., etal, AppL I'hys. Lett. 34, 76 (1979). [9] Roulet, M. E., etal, Electronics Lett. 15,527 (1979). [10] Maddox, R. L., Microelctron. J. 14 No. 6, 33 (1983). [I I] Duffy, M. H., et al, J. Crystal Growth, 58; 10 (1982). [12] Putley, E. H., 'The Hall Effect and Semiconductor Physics', Dover Publications, Inc., New York, 1960, p. 125. [13] Taguchi, S., etal, Electrochem Soc. Ext. Abstr. Vol. 38-1,643 (1983). [ 14] Yoshida, M., et al, 1983 IEDM, Wash. D.C. Tech. Digest No. 14.7, p. 372. [15] Richmond, E. D., etal, J. Vac. Sci. TechnoL (in press 1984). [16] Mayer, D. C., et al, 1EEE Electron Device, Lett., EDL-5, 156 (1984). [17] Lin, A..L., Maddox, R. L., Mee, J. E., Microelectron J. 14 No. 6, 22, (1983). [18] Hsu, S. T. and Scott, J. II., Jr., RCA Review36, 240 (1975). [19] Lee, J. Y., et al, Microelectron J. 14 No. 6, 5, (1983). [20] Risch, L. IEEE Trans, ED-30 No. 8,959 (1983). [2 I] Smith, D. J., et al, Inst. Phys. Conf. Ser. No. 67, Section 2, p. 83 (1983). [22] Blakemore, J. S., 'Semiconductor Statistics', Pergammon Press, New York 1964, p. 169. [23] Baccarani, G., etal, I E E E Trans. Vol. ED-31, No. 4,452 (1984).
APPENDIX TABLE A U V R data at each step of DSPE process AR
WFR NO I
2 3 4 5 11
Initial Cond.
1st Si lmpl.
+1 to +2 --lto
0
0 -2to+l 0to - 1 --2 to - 3
m
183
1st Rextal 7 -3 -4 -2 +1 -3
2nd Si Impl.
2nd Rextal
310
38 48 46 63 46 43
61
The performance of NMOS/SOS devices designed for near micron geometries is shown to be enhanced markedly by pre-process SOS material improvements. A description of the double solid phase epitaxial regrowth technique, DSPE, is presented including the results of several materials evaluation, techniques: Rutherford backscattering and channeling spectrometry, X-ray twin content, sheet resistance, spreading resistance, ultraviolet reflectivity, and Hall data vs. temperature. Post-MOS process evaluation data of materials and device properties is also presented, which includes: gated Hall data, SIMS, sheet resistance, majority and minority carrier mobility, threshold voltage, subthreshold current slope, back channel leakage current, and electrical carrier density profiles. Significantly enhanced device performance is reported, such as --- 20% improvement in all mobilities, factor of 100 reduction in twin content, factor of 5 to 10 reduction in backchannel leakage, and 15 to 25% improvement in subthreshold current slope. 1.
Introduction
The performance of any solid state microelectronic device is closely related to the crystalline quality of the material used. This is particularly true of CMOS on sapphire structures. Silicon on sapphire technology (SOS) utilizes an insulating substrate of sapphire to provide "ideal" isolation between devices made from a thin film of silicon deposited heteroepitaxially on the sapphire t. These devices are isolated electrically by sapphire in the vertical direction and laterally by silicon dioxide. The thickness of the silicon film is in the range 0.2 < t > 1.0/xm. The quality of the film improves substantially with film thickness. For example, 0.5 p.m film has very good crystalline quality at the top surface of the etailayer and substantially poorer quality at the silicon-sapphire interface. The distribution of defects is exponential, with the peak at the silicon-sapphire interface on the order of 4 x 10I - 106 planar faults/cm2~and -- 109 line defects/cm~-, as discussed in ref. 2. There are several means of improving the crystalline quality throughout the SOS film3. Most of these are based on one form or the other of solid phase epitaxial regrowth of the Si epilayer4 - a. The subject matter of this work describes the device and material improvement aspects of NMOS/SOS devices whose performance was enhanced by the double solid phase epitaxial regrowth technique, DSPE. NMOS devices were chosen because of their sensitivity to material properties, e.g., mobility and leakage, and due to the fact that the PMOS devices were of the buried channel type and not as straightforward to interpret. The process used to fabricate devices on the improved SOS miaterial is identical to that published and characterized earlier l~ except that the gate oxide was increased from 160/~ (for a 1 pm technology) to 300/~, to facilitate pulsed C-V measurements, 48
MICROELECTRONICS JOURNAL Vo115 No 5 9 1984 Benn Electronics Publications Ltd, Luton
1.5 MeV 4He + ANALYSIS ,x 12"
~m)
Si DEPTH SCALE
0.4
~" z:::) 0
1
0.2
1
0
I
0
I
I
I
.~.~.~.~^ ,,~ '
t. A
13d >-
t.
:~:'L':- a: 9 o J
:.
q'o~z %-
'~ ~.
.;'..~. ~..
|
,u)~ v
o
":~.::.,"?:" G ':'~ ....
/
m
"H'" " "';""":'::"...-.,~: "o','-~"
0
T '~ '?'-",
]
0.6
0.8
EACKSCATTERED ENERGY (MeV)
Fig. 1 Rutherford backscattering and axial channeling spectra of 0.48p.m thick, (100) SOS films. G (aligned): 400 keV, 2x10 '5 Si/cm~ + 2.5h, 560"C N,, + (80 keV, 2x10 ts Si/cm~ + 200 keV, 2.5 • I0 t5 Si/cm2) + 2h, 560"C, N2; H (aligned): same as G + 3h, 925~ N2; J (aligned): as-deposited (unimplanted) + 4.5h, 560"C; R (rotating random). See Table I for the values of the channeling yields and dechanneling rates.
TABLE I Channeling yields and average dechanneling rates for doubly recrystallized (G,H) and unimplanted control (J) SOS films. The corresponding spectra and detailed description of the samples are given in Fig. 1. Sample
Si Thickness, t (~m)
X
X
o
i
dx dz
Xt-Xo -
(#mx')
t
J
0.48
0.I0
0.58
1.0
G
0.48
0.060
0.20
0.29 (0.21)"
H
0.48
0.051
0.18
0.28
"Measured above and below buried, defective transition region.
2.
Experimental
2.1 DSPE Process Threeinch diameter SOS wafers with 0.5 ~m -+10% nominal silicon film thickness supplied by Union Carbide were used as the starting material. The films were deposited undoped at 910~ at a deposition rate of 1.1/zm/min. Initially the films were n type with a sheet resistance of -- 2 • 10a 1"//O. Half of each wafer was masked with 1.0/zm of densified silox such that, with the wafer flat at the bottom, the left side (pos.2) was the control sample and the right side (pos.4) was the DSPE sample. This system of control sampling was necessary due to the lack 40
MOSFET performance enhancement by improv~l SOS material proce==escontinued from page 49
of adequate wafer-to-wafer uniformity with respect to device performance experienced with SOS, as compared to bulk silicon. The DSPE process followed the following steps: a) The silicon film was amor~hized by a low current, high dose silicon implant with the 9 exception of the top 700 A of the film. The implant conditions were 400 keV, 2x 10 ~5 28Si/cm2, current density < 0.5 I.tA/cm 2, and 7~ angle of incidence from the wafer's surface. b) The top 700/~ of the silicon film, being of the best crystalline quality, was used as a seed to recrystallize the remainder of the film at 560~ in nitrogen. The recrystallized defect profile was verified by RBS measurements. c) The top of the silicon film was then similarly amorphized by a silicon implant; 80 keV, 2x 10~ 28Si/cm2 plus 200 keV, 2.5 x 10~ 2sSi/cm2 under the same current and angle conditions. d) Finally, the top portion of the silicon film was recrystallized using the previously recrystallized bottom portion of the film as a seed, at 560~ in nitrogen and a sample was checked by RBS. Typical RBS data is presented in Table I and Fig. 1. The material was characterized at each major step of the DSPE and MOS process by use of a blank drop-in chip at positions 2 and 4 described earlier. The difference, AR, between the ultraviolet reflectivity (UVR) at wave lengths of 280nm and 400rim has been suggested as an incoming SOS wafer acceptance criterion I~. In practice, a value of AR < 15 has been observed to provide adequate device results. The UVR data was taken at each of the four steps of the DSPE process as well as at the initial conditions. This is shown in the Appendix, Table A. The data presented this table is not straightforward to interpret except for the fact that values of AR->300 indicate amorphous surfaces as expected for the second Si implant. The volume fraction of twins was determined from measurements of the diffracted X-ray intensity of twin relections relative to parent reflections. The twin content, shown in Table II, documented the earliest observable results of the material improvements generated by the DSPE process. The data for the control (non-recrystaIlized) side of the wafers in Table II are a result of only the 560~ furnace operation. Note that a twin density of 0.03% is equal to the signal background level of the apparatus. By the end of MOS processing a reduction of 9 greater than a factor of 100 was observed. TABLE II X-ray twin content Step InitialCond. Ist Rextal 2nd Rextal End MOS Process
% Control (POS. 2) DSPE (POS. 4) 2.9
3.6
1.3
1.2
2.1 0.8
0.03 <0.03
The sheet resistance of the DSPE material will necessarily be smaller than that of the control sample due to the diffusion of aluminum that was released by the amorphization process from the sapphire substrate. This data is shown in Table III. This difference in sheet resistance was observable throughout the MOS process which includes the p type channel doping, -- 10~rcm-3. The reduction in sheet resistance of the DSPEmaterial, following the 925~ annealing, is related to the 'dissolution' of the band of extended line defects, (probably dislocation loops) present after 560~ recrystallization at a depth of ---0.3/.tm, at the original 50
TABLE III DSPE material sheet resistance (I//[]) WFR No
Initial Condition
Ist
925~ +
Rextal
2nd Rextal (All p type)
(n Type)
Test
Isol.* Oxidation
End of** MOS Process
I
i .9E8
2.7E4
3.5E7
5.1E4
5.0E3
4.7E3
2
1.6E8
3.0E4
3.7E7
8.9E4
6.5E3
5.5E3
3
2.5E8
2.8E4
1.7E8
7.3E4
6.7E3
6.1E3
4
1.6E8
2.5E4
1.2E8
I.IE5
6.5E3
5.7E3
5
2.0E8
2.6E4
3.6E7
6.0E4
5.9E3
5.0E3
11
4.1E8
2.2E4
3.6E7
9.8E4
7.1E3
6.1E3
+ 925"C, 60 min. in N2 * I l a d ~ 10trcm -s Boron doping, 250 keV, 5 x 10ncm -2 + 170 keV, 6 x 1011cm-~ + 1000~ 150 rain. N2 * * Had Boron V-m implant, 26 keV, 2 x 101Zcm-2 through 425~ sacrificial oxide.
amorphous/crystalline boundary (see RBS spectrum G in Fig. 1). Spreading resistance profiles of the net dopant concentration for the DSPE process are given in Fig. 2. The difference in dopant concentration due to diffusion of alluminum from the sapphire substrate can be demonstrated by an Arrhenius plot of the p type dopant concentration (after the first silicon implant and anneal) taken from Hall bar data as shown in Fig. 3. The Hall factor is assumed to be unity. The mobility and resistivity data versus temperature taken from the Hall bar data are also shown in this figure for DSE material. The slope of log N^ versus 1/T gives the accepted aluminum energy level in silicon, n SIMS data of the aluminum concentrationdepth profile in DSPE and control material at the end of MOS processing shown in Fig. 4. Although the particular control film shown in Fig. 4 had a mass 27 signal level of -~3 x 1015/cm3, other control samples yielded levels of (1-3) x 1016/cma. We believe these correspond to the instrumental background level, and not to real aluminum in the films. The origin of the increase in A1 signal in the near-interface region, as well as other instrumental aspects have been discussed in ref. 7. Note that the increase in A1 concentration after many high temperature steps corresponds to the 925~ data in Table III. The leveling off of the free carder concentration shown in Fig. 3a at temperatures below about 50~ indicates that impurity band conduction is dominant near the Si-Sapphire interface for dopant concentrations greater than 10~Scm-a approximately, zz Other studies describing results obtained by the DSPE process are given in references 13 through 16. A gated Hall bar structure ~7was used to measure the majority carder mobility by analysis of I-V characteristics (average drift mobility) and by Hsu's technique ta (drift mobility profile), in addidion to the Hall mobility on finished devices. These results will be dompared in the discussion. 2.2 MOS Process The NMOS/SOS process Used in this work I~was optimized for near-micron channel lengths. Basically, it has a grown oxide isolation structure (LOCOS), with polycide gates and N^ 2• 1017cm-z, as shown in the SIMS data of Fig. 5 for the DSPE material. The final sheet resistances of control and DSPE sampling are given in Table III. The gate oxide thickness was verified to be 300-+ 15.~, over the entire wafer. The shapes of the test device CoV curves showed no significant differences in fiat band voltage or surface state density. The drainsource breakdown voltage was 11.4 • 0.2 volts for all devices with L >- 2ptm. The molybdenum polycide gate sheet resistance was 11.5 • 0.7 f l / [ ] and the n § and p+ sheet resistances were 51
MOSFET performanceenhancementby improvedSOS material processes continued from page 51
105
I
n
1o4
lo3
Z
r (3 Z
t0
P 1.o
0.1 0
I
I
1
I
0.1
0.2
0.3
0.4
0.5
Si EPI THICKNESS (pm)
Fig. 2 Spreading resistance profiles on SOS test wafer a) as-deposited, b) after first Si implant and anneal, c) at conclusion of DSPE process. The spreading resistance data Was taken by Solecon, Inc., Costa Mesa, Ca.
120 and 165 f l / [ ] for phosphorus and boron doping respectively. The n § diffusio~ extended through the entire film thickness away from the gates with approximately 0.25/.tm junction depth adjacent to the gates. This structure retained the short channel otpimised structure while still reducing the junction capacitance to the minimum value possible. Source follower conductance measurements were used to determine the (extrapolated) threshold voltages and effective channel mobilities of the MOSFETs. Measurements of the logarithm of the source-drain current versus gate voltage were used to determine the leakage and the subthreshold current slope. The gate oxide thickness was obtained from 60 x 60/zm FET capacitance and SEM measurements. A curve tracer was used for initial device screening as well as breakdown voltage, some threshold voltage, and sheet resistance measurements. A test device yield exceeding 75% was obtained on all wafers processed. All device length and width measurements were obtained from SEM. 52
103/'1 ` ( ~ I0 IB
FOR PH 40 I
i
t~0
1017
~
1016
z~IO 15
'L
102 --
1014
10
101
I
10
20
30
lo3/r i% -I) FOa N8
[a]
I
~1o2
10
I 10
t
I
1
I Illl
IO2
t
I
t
t
t
ttw
IO*
103/T, I~
[b] Fig. 3 a) Hall bar resistivity and carrier concentration versus reciprocal temperature for SOS wafers that received only the 400 keV Si implant and first rect3'stallization anneal. The presence of aluminum diffused from the sapphire is indicated by the energy level obtained from the slope of the linear portion of the curve, b) Hall mobility versus reciprocal temperature for the devices in part a). 53
MOSFET performance enhancement by improved SOS material processes continued from page 53
1020
m
~
m
m
m
~
m
Si REFERENCE %=m
~ - = e.= m
m
m
= . m = . ~ = m m.~
I
1019
r
1018 O Z
o FZ
uJ (J
r,,3
1017
1016
AS-GROWN
1015
I
0.2
"
I
0.4
0.6
DEPTH (pM)
Fig. 4 SIMS data for aluminum concentration vs depth in as-grown and DSPE SOS material at the conclusion of MOS processing. The SIMS data was taken by Charles Evans Associates, San Mateo, CA.
54
1019
~1018 O
1017
B
1016 -
1015
I
I
0.20
0
0.40
0.60
DEPTH (MICRONS)
Fig. 5 SIMS data for MOSFET channel boron concentration at the conclusion of MOS processing. The value/profile of NA used was designed for near micron channel length. Data measured by Charles Evans Associates.
2.0
2.0
AS-DEPOSITE~::~
1.8
1.8 >
.....:/:ii::~
>~ 1.6 1.4
y
RECRYSTALLIZED
f
1.2~
,
.
,
,
. ~. ~ ! ~
1.4 tsi =
w = 5.1~tm
1.2-,t
I d = 1 laA
tsi= 0.46 lam 133 .0
~
"~ 1.6
>
I 1
I 2
I 3
I 4
I 5
1.0
0.46 ltm
RECRYSTALLIZED
=2.51am
Id = 1 laA I I 0 2 4
l(/Jm)
I 6 w(~tm)
I 8
I 10
12
Fig. 6 MOSFET threshold voltage as a function of channel length and width for as-deposited and DSPE material. This data was taken on a curve tracer at Ins = lgtA, VDs --- 3 V. Extrapolated threshold voltage data is presented in Table V (from g-V curves).
55
MOSFET performance enhancemeflt by improved SOS material ~
continued from page 55
T A B L E IV Final s h e e t resistance g,(n/
)
WRF NO 1
2 3 4 5 11
Control
DSPE
11.8E3 15.4E3 11.2E3 14.2E3 10.5E3 11.7E3
4.66E.3 5.50E3 6.10E3 5.74E3 4.95E3 6.07E3
TABLE V T h r e s h o l d v o l t a g e e x t r a p o l a t e d f r o m c o n d u c t a n c e curves: V n s 0 . 1 V , L = 2 . 5 # m , W = 5.1/zm, N ^ ~ 1.8E17, an d tox = 290,~. V~l(V)
WFR NO Control
DSPE
1
1.95 --- .02
2 3 4 5 11
1.91 --- .04 1.88 -+ .03 1.95 ~ .03 1.81 • .04 1.86 • .04
1.80 --- .07 1.76 • .01 1.64 • .03 1.64 __..01 1.63 • .09 1.61 • .04
T A B L E VI S u m m a r y o f g a t e d H a l l b a r m e a s u r e m e n t s f o r h o l e s at flat b a n d c o n d i t i o n Control Device No.
DSPE
PGH (• cm)
#GH (an'/V-s)
No:~ll (an-~)
PGH (~ an)
/aGtt (an'N-s)
NGH (an-~)
0.312
114
1.75E17
0.168
145
2.5E17
0.276
116
1.93E17
0.162
138
1.78W 17
0.304
113
1.82E17
0.142
133
3.30E17
0.313
115
1.73E17
TABLE VIII S u m m a r y o f a v e r a g e free h o l e m o b i l i t y Drift Mobility (cm'/V-s) Device Number
IIall Mobility (cm'/V-s)
Control
DSPE
Control
DSPE
188
227
113
133
197
246
115
145
193
223
114
138
116 56
3.
Discussion of results
The behaviour of the threshold voltage with respect to MOSFET W and L is shown in Fig. 6. This data was taken on a curve tracer and follows closely the trends expected for short channel devices and also the data of ref. 10 except that VTH is larger due to the increased gate oxide thickness. Threshold voltage data extrapolated from conductance curves is of more utility to the device analysis and a subgroup of that body of data is given in Table V. The threshold voltage of the DSPE material is about 0.2 volts smaller than that of the control material even though the dopant concentration measured by sheet resistance is greater and the gate oxide thickness and flatband conditions are equal. This effect was reported by other researchers on DSPE material recently as well 1~19. The dopant concentration profile measured by CV analysis of gated Hall bars supports the sheet resistance data of Table III as shown in Fig. 7. In addition, the Hall effect measurements, Table VI, support the data. 6
4.5
~-
3 DSaE ZX 1.5
0
0
I
I
I
.02
.04
.06
.0e
DISTANCE FROM 52/5iC)2 INTERFACE (/~M)
Fig. 7 Free carder concentration profiles (for holes) taken by pulsed CV measurements at the conclusion of MOS processing. 3OO
225
~"c
sn i
75
0
0
I
.02
I "
.04 OISTANCE F ROM ~ i O
I
.0G
.08
2 INTE R FACE, (HM)
Fig. 8 Drift mobility (holes) as a function of SOS film thickness by Hsu's method (at the ~onelusion of MOS processing).
Four separate techniques were used to evaluate the mobility improvement of the DSPE material. All data on these devices reported a 10-30% improvement in mobility. Table VII compares the average majority carder (holes) mobility of control devices to that of DSPE devices measured by the gated Hall technique at flat band conditions, as well as by the I-V~ 57
MOSRET perfom~ance =mhancement by improved SOS m=tmial ~
continued from page 57
techniques. Drift mobility profiles reduced by Hsu's method 18for control and DSPE devices are shown in Fig. 8. The effective channel mobility,/zw, extracted from the conductance curves o f N M O S F E T ' S (minority carriers) is shown as a function of channel width, W, in Fig. 9. T h e decrease i n / z w with decreasing W is a short channel effect explainable by the increase in effect of the electric field density component at small geometries. This, and other effects that would be correction factors to t t ~ data for short channel devices are discussed in refs. 20 and 23. The behaviour of # r e as a function of transverse (gate) electric field density is shown in Fig. 10. The absolute value of mobility in this report is not as large as is commonly r e p o r t e d for NMOS/SOS devices due to the large N^ and thin gate oxide required for short channel avoidance.
400 350 -
~ D O U B L Y ~ RECRYSTALLIZED
F
"-" 3oo
,.,~.~~
AS-DEPOSTED
i11
,T ~ 250 ~ 200
/:i::i~ i~i::'~-
tsi = 0.46_pm
//I
t,
~/
,s ..c2.5 .um NA~1.5 X 1017h/cm3
-003 .m
150 0
I
2
I
4
I
I
I
I
6 8 10 12 CHANNELWIDTH, w (pm)
Fig. 9 Effective channel mobility for NMOS devices as a functionof channel width (electrons). This data was obtained from analysisofg-V curvessupplementedby CV and SEM data for the gate oxide thickness and the dimensions, W by L, of the device. The reduction in # ~ for small W is a short channel effect aused mainlyby excessivetransversefieldstrength. Edgeless FET's were used to evalute the backchannel leakage for the NMOS/SOS devices process so that edge effects which can confuse the interpretation of the data are eliminated. O n the average, a factor of 10 improvement was achieved as sh.own in the log los vs Vg data of a group o f >20 devices in Fig. 1 la. In addition to the average value of back channel leakage being reduced, the distribution of the values of leakage current was reduced as well. It is our opinion that the reduction in back channel leakage is a result of the reduction in mlcrotwin content 9 and is also a feature of the increase in net P type dopant concentration adjacent to th~ silicon-sapphire (back channel) interface as was shown in Figs. 2 and 4, even though the free carrier concentration was shown to drop slightly in that region as shown in Fig. 7 and as discussed in ref. 2. The effect of varying drain bias is shown in Fig. l l b . A noticeable short channel effect is seen in Fig. l l b due to the relaxation of short channel avoidance parameterst~ e.g., the gate oxide thickness used in this work. T h e subthreshold current slope for edgeless FETs, under the conditions of Fig. 11 a, was 60 to 65 mV/decade of current for the DSPE sampling and 70 to 80 mV/decade for the control sampling: This data represents a 15 to 25% improvement and agrees with that published in ref. 10. T h e subthreshold current slope appears to decrease with increasing Vos as shown in Fig. l l b . 58
~" 320 1
> 300 - / r / 5 >- 280
DOUBLYRECRYSTALLIZED
~
/
_J
o 260 - ~ ;E f"'-" I-o UJ 240 It.
~
w/J{ = 3.0/2.5 (lam/pm) tsi = 0.46 ttm tsi02 = 0.03 lam
~.\\\ ~%=o.1 v ~
LL
9 LLI
220 --
m LL
AS-DEPOSITED Vth = 1.9 V
~
- ~
2o01d 0
I
I
I
1
2
3
I
I
4 5 IVg- Vthl (v)
I
I
I
6
7
8
Fig. 10 Effective channel mobility as a function of gate field strength. 4.
Conclusion
The material characteristics of as-deposited and DSPE improved SOS wafers were compared before and after MOS device processing. A significant redu~:tion of microtwin content (factor of 100) resulted for DSPE improved material, and is assumed to be the primary reason for all other improvements measured. Aluminum diffused from the sapphire was positively identified and its concentration profile determined. The mobility of both majority and minority carriers was improved by greater than 20%. The performance of NMOSFETs was also shown to be improved by the DSPE process e.g., factor of 5 to 10 reduction in back channel leakage and >15% increase in subthreshold current slope. 5.
Acknowledgements
The authors would like to acknowledge the help of Nancy Casey and Frieda Kinoshita for assistance in wafer processing, Gene Whitcomb for dry etch consultation, Rich Johnson for SEM, and Mollie Glowna and Edie Dodd for some of the parametric testing. We would also like to acknowledgement the support of Jack Mee. 96.
References
[1] Manasevit, H. M., Simpson, W. I., J. Appl. Phys. 35, 1349 (1964). [2] Abrahams, M. S., Buiocchi, C. J., AppL Phys. Lett. 27, 325 (1975). [3] Golecki, I., "The Current Status of Silicon On Sapphire and other Heteroepitaxial Silicon on Insulator Technologies," Proceedings of the symposium on Comparison of Thin Film Transistors a/ad SOl Techologies, M. J. Thompson and H. W. Lam, eds., 1984 Spring Meeting of Material Research Society, Feb. 1984 Albuquerque, MN, USA. [4] Yoshii, T., et al, Japan. J. Appl. Phys 21 Suppl. 21-1, 175, 1982, also 23rd Electronic Material, Conference, Santa Barbara, CA. No. 0-8, June 1981. [5] Amano, J., Carey, K. W., Appl. Phys. Lett. 39, 163 (1981). [6] Golecki, I., Glass, tI. L., Kinoshita, G.,Appl. Phys. Lett. 40,670(1982). 59
MOSFET performance enhancement by improved SOS material processes continued from page 59
10-4
10-6
E
tsi = 0.44 IJm Vds = 0.5 V w / l = 72/2 (!um/IJm)
10-s
Z LU rr I1-
/,f
r
10 -6
EDGELESS, n-CHANNELTRANSlSTORS
10-7
------[AS-DEPOS,TED]
10-7
-10-8
<~ :ff ~D _.J
I DouBLY-REcRYsTALuzED
I
10 .9
u.I
z z
(.) ,< r'r" Q
~
10-8
109
10 11 O
_z < 10-10
10_12 r~
I0-" I -5
I -4
I -3
I -2
1 -1
I 0
I 1
I
2
a
GATE VOLTAGE, Vg (V)
[a] 10"4
10-5
(i/h'
10~
Ill'
10-7
10~
---
-"=--.
IJIl
10-g
10-10
10-11 -5
I
-4
I
-3
I
-2
I
-1
I
0
[
1
I
2
I 3
I 4
vGw)
[H Fig. 11 a) Transfer characteristic of NMOSFET (IDs VS. Vg at fixed VDS) from which the backchannel leakage and subthreshold current slope are obtained. Note the reduced magnitude and distribution of leakage for devices fabricated on DSPE material, b) NMOSFET transfer characteristics at VDS = 0.5, 2.0, and 5.0 volts. The leakage current near Vg = 0 is less at all values of Vos for DSPE material than for as-deposited material. 60
[7] Golecki, I., Maddox, R. L., Stika, K. M., J. Electron. Matl. 13, 373 (1984); also 25th Electronic Matls. Conf., Burlington, VT, No. N-4, June 1983. [8] Lau, S. S., etal, AppL I'hys. Lett. 34, 76 (1979). [9] Roulet, M. E., etal, Electronics Lett. 15,527 (1979). [10] Maddox, R. L., Microelctron. J. 14 No. 6, 33 (1983). [I I] Duffy, M. H., et al, J. Crystal Growth, 58; 10 (1982). [12] Putley, E. H., 'The Hall Effect and Semiconductor Physics', Dover Publications, Inc., New York, 1960, p. 125. [13] Taguchi, S., etal, Electrochem Soc. Ext. Abstr. Vol. 38-1,643 (1983). [ 14] Yoshida, M., et al, 1983 IEDM, Wash. D.C. Tech. Digest No. 14.7, p. 372. [15] Richmond, E. D., etal, J. Vac. Sci. TechnoL (in press 1984). [16] Mayer, D. C., et al, 1EEE Electron Device, Lett., EDL-5, 156 (1984). [17] Lin, A..L., Maddox, R. L., Mee, J. E., Microelectron J. 14 No. 6, 22, (1983). [18] Hsu, S. T. and Scott, J. II., Jr., RCA Review36, 240 (1975). [19] Lee, J. Y., et al, Microelectron J. 14 No. 6, 5, (1983). [20] Risch, L. IEEE Trans, ED-30 No. 8,959 (1983). [2 I] Smith, D. J., et al, Inst. Phys. Conf. Ser. No. 67, Section 2, p. 83 (1983). [22] Blakemore, J. S., 'Semiconductor Statistics', Pergammon Press, New York 1964, p. 169. [23] Baccarani, G., etal, I E E E Trans. Vol. ED-31, No. 4,452 (1984).
APPENDIX TABLE A U V R data at each step of DSPE process AR
WFR NO I
2 3 4 5 11
Initial Cond.
1st Si lmpl.
+1 to +2 --lto
0
0 -2to+l 0to - 1 --2 to - 3
m
183
1st Rextal 7 -3 -4 -2 +1 -3
2nd Si Impl.
2nd Rextal
310
38 48 46 63 46 43
61