- Email: [email protected]
Motorola MCMs
Microelectronics Journal, Vol. 24, No. 3
Motorola MCMs Motorola's Application Specific Integrated Circuits Division, Chandler, AZ, USA, has introduced the MCML T M Series of multichip modules (MCMs). Aimed at costsensitive, low to medium power applications,the modules use laminate PCB type substrates to achieve the next level of semiconductor integration.
Motorola is offering a complete application specific MCM product solution that includes design support,
manufacturing, and test. The MCML Series MCM combines multiple ICs such as ASICs, microprocessor and memory on a small PCB substrate. The combination of ICs and substrate is moulded with a plastic compound into standard EIAJ plastic quad flat pack (QFP) body sizes and lead counts. Potential system advantages, Motorola says, are smaller physical size, better performance and lower assembly costs.
Fig. 1.
0026-2692/93/$6.00 © 1993, Elsevier Science Publishers Ltd
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Fig. 2. The MCML Series allows customers using single-chip QFP packages to take advantage of MCM packaging density while staying with existing high-volume manufacturing and test equipment. Modules fit into a PCB assembly flow exactly like a single chip QFP. Motorola encapsulates the multichip substrates in the same moulding equipment used for cost-effective single chip packages.
Potential advantages According to Steve Bowen, MCM product development manager, "Potential advantages are easy to visualize. Surface area is reduced five to ten times over single chip packages and chip-to-chip signal delays are cut in half."
Bowen noted that his module organization has been producing M C M - L types substrates for Motorola equipment divisions since the beginning of 1992. "Our customers estimate system cost savings due to lower assembly costs and simplified PCB construction," he said. A typical power rating of 2-5W makes the series suitable for high speed CMOS applications. Motorola offers the MCML Series as an enhancement to Motorola's standard semiconductor products and ASICs. O f course, the company strongly recommends that the MCML modules contain all-Motorola semiconductors to ensure chip-set availability. The use of non-Motorola ICs will be evaluated on a case-by-case basis.
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The MCML Series module CAD is an extension of the Motorola Open Architecture CAD System (OACS) used for ASIC gate array development. Motorola's CAD strategy for both ASICs and modules is to use the best available industry software, supported with Motorola developed programs, to provide a complete CAD package. It is recommended that customers do schematic capture, module simulation, and performance analysis on engineering workstations. Motorola normally performs physical design place and route, transmission line analysis, thermal analysis, and conversion to tester compatible final test programs. All MCML Series modules are tested for
Microelectronics Journal, Vol. 24, No. 3
functionality, parametrics, and performance on the same test systems used for ASIC products.
Base NRE charge According to Motorola, the base N R E charge is $75k per module design. Within the base charge Motorola performs physical design and procures all prototype die. Motorola also does thermal analysis, electromagnetic analysis and test p r o g r a m generation. T h e customer performs schematic capture, functional and performance simulation and develops test vectors. Unit pricing varies widely with chipset cost. For example, a typical 28 m m module containing two 8k SRAMs and one 64k gate C M O S array would cost less than $100.00 each in production volumes. Two substrate sizes including a 28 m m body size with 128, 160, or 208 leads, and a 40 m m body size with 232 or 304 leads are available for prototyping now. Prototype leadtime is typically 14 weeks from release of design, the company claims. Manufacturing of the M C M L Series modules will take place at Motorola's ASIC headquarters facility in Chandler, Arizona.
Contact: Steve Bowen, Motorola Inc, kiD CH290, 1300 N. Alma School Road, Chandler, A Z 85224 USA. Tel~fax: [1] (602) 821-4497 / 4963.
AT&T DIAMOND SUB-MOUNTS FOR POWER ASSEMBLIES AT&T has announced what it claims to be the world's first commercial application of a novel synthetic diamond material c o m b i n e d with an advanced metallisation bonding technique developed at AT&T Bell Labs. The company will use the new technology to make microelectronic heatsinks as sub-mounts for high power semiconductor lasers, which will shortly be in production at AT&T Microelectronics. The sub-mounts, made o f chemically vapour-deposited (CVD) films o f synthetic diamond, combine high functionality and maximum heat-extraction capability. C V D diamond sub-mounts have been fabricated to AT&T's specification by a number o f vendors worldwide selected by AT&T as the leading edge suppliers in CVD diamond technology. AT&T has worked closely with these
vendors in marrying its sub-mount design and processing technology with its diamond growth and processing technology to develop both a product and a market to their mutual benefit. Making usable laser sub-mounts from CVD diamond, h o w e v e r , requires a d v a n c e d thin film b o n d i n g metallisation compatible with diamond processing. Use o f this technology enables efficient heat removal from lasers, w h i c h is the key to achieving both h i g h - p o w e r performance and the reliability necessary in high power laser applications. T h e d e v e l o p m e n t t e a m is p u r s u i n g f u r t h e r optoelectronics applications and envisions much broader applications within AT&T Microelectronics, in the area o f silicon and gallium arsenide high performance ICs and in high density interconnects.
TOSHIBA ASIC PACKAGES REDUCE BOARD SPACE BY UP TO 60% Toshiba Electronics (UK) Ltd has announced that its entire range of ASIC products is now available in a new SM package option known as the Small-outline Very-thin Flat Pack (SVFP). The new package not only results in a PCB area reduction of 60% on the conventional plastic flat packs but also offers a reduced profile. The package is 1.4 m m thick and, when mounted, has a total height of less than 2 mm. This compares to a mounted height of over 4 m m for standard flat packs. Featuring a lead pitch of 0.5 mm, the package is available in a variety of configurations with between 48 and 176 I / O pads.
Contact: Angela Murphy, Toshiba (UK) Ltd, Tel: [44] (0)276 694 600.
EUROPEAN CONTRACT ASSEMBLY BEATS THE RECESSION According to a new report, the contract electronics assembly industry in Europe is confounding the general industry doom and gloom with an estimated value o f $1.8bn in 1992. It will continue to thrive and beat the recession with growth up to $3.67bn by 1997. The new report, from the Elsevier Advanced Technology m a r k e t research division, is called EUROPEAN
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CONTRACT ELECTRONICS ASSEMBLY M A R K E T S 1993-1997. It investigates the emerging and rapidly growing contract electronics assembly industry in Europe, w h i c h provides the service o f assembling electronic components onto PCBs, design and test. The report uncovers the basic reasons for this impressive growth o f this industry and reveals an unusual geographic bias within the industry. The recession-proof growth is apparently due to not one but, several factors: the complexity o f mixed technology assemblies, i.e., SMT and C T H assembly; the increased investment necessary to cope with both technologies; the increased technical know-how necessary to cope with the various process and design requirements, (particularly with regard to fine pitch technology and high pin count devices) and the fact that in the current economic climate it is often more economical to cope with increased demand by contracting-out the excess work rather than to invest further. The report shows that current levels o f activity in the industry vary considerably in each individual country, especially in relation to the general economic activity o f each country. Indeed, there is much more activity in the U K than in Germany, in absolute terms, which is quite unusual. The report evaluates the major factors leading to this development and takes a look at where the future areas of increased activity will be.
The report is available now priced £1250 ($2250). Further details from: Robin George, Elsevier Advanced Technology, Mayfield House, 256 Banbury Rd, Oxford OX2 7DH. Tel~fax: [44] (0)865 512242 / 310981.
are close behind with 78% gains from $385M in 1991 to $688M by 1996. O f the 10 user groups analyzed, passive component consumption growth will be the weakest, rising only 18% from $16M in 1991 to reach $19M by 1996. Development of an appropriate and cost-effective test strategy is now becoming recognised as a key element in the long term success o f electronics manufacture. Frost & Sullivan believes that the distributed test concept will gain increasing acceptance as an alternative means o f lowering overall test costs and improving test throughput rates. Distributed test strategies include a variety of process test configurations aimed at finding the most common process related faults and thereby improving the throughput o f expensive diagnostic ATE systems. The ideal functional tester o f the future will meet program development and life-cycle goals through a variety of software tools. The four leading suppliers o f the ATE market - Advantest, Teradyne, Schlumberger and LTX currently account for about half of the US market. Foreign competitors are expected to become major players. Price of the report # A2567 is $3,200.
US Contact: Frost & Sullivan Inc. Tel [ 1] (212) 233-1080. In Europe, tel: [44] (0)71 730-3438.
SMT IMPACTS ASSEMBLY TO TUNE OF $3.7BN SAYS REPORT
50% JUMP IN US ATE MARKET
A new report from Decision resources estimates that the worldwide market for SMT assembly equipment will grow from $1.5bn in 1992 to $3.7bn in 1996. The report,
A new report from Frost & Sullivan forecasts a 50% or more j u m p in ATE sales from $1.51bn in 1991 to $2.43bn in 1996.
S M T in Electronics Packaging, 1992-1996: Industry Impact of New S M T Generations and Alternative Technologies, is
A T E is d e f i n e d as c o m m e r c i a l l y available computer-controlled programmable systems used to test and diagnose faults in PCBs and the components mounted on them. In terms o f end users, telecommunication industry demand is forecast to grow most sharply, up 80% from $263M in 1991 to $476M in 1996. Semiconductors
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intended to define and forecast current and future markets for SMT, TAB, C O B and other assembly processing techniques. The report is priced $2800 and is available now.
Contact: Decision Resources. Tel~fax: [1] 617 270-1222 / 273-3048.
Microelectronics Journal, Vol. 24, No. 3
FACTS AND FIGURES ON JAPANESE ELECTRONICS The 1992 English edition of Facts & Figures recently published by the EIA of Japan gives almost a ten year history on the performance of this energetic industry. Contrary to common belief the consumer section is the worst performer.Japan's total production in electronics for 1991 is given as 46% industrial, 35% components and 19% consumer. The export breakdown is given as 45% components, 31% industrial and 24% consumer. The Walkman and TV sets are only the tip of the iceberg.
MOTOROLA 10ns PLD DEBUT IN 24-PIN SOIC PACKAGE Motorola's Logic IC Division has made its debut in the programmable logic device (PLD) market with several e n h a n c e d versions o f the popular 22V10 device. Motomla's ultra low power MC22V10S family maintains all important industry standard features, while offering advanced features and functionality. Motorola claims that its entrance into the 22V10 market gives customers many advantages over current leaders in the field. These include: 10ns and 15ns speed devices with drastically reduced power consumption of 30mA, 3.0/3/3V operation for low voltage applications with even lower power consumption. In particular, Motorola claims significantly reduced circuit board area with availability of the industry's first 10ns 24-pin SOIC package. It is the low power consumption of the MC22V10S family which permits Motorola to offer the MC22V10S devices in popular, industry standard packages including the 24-pin DIP and 28-pin PLCC packages,as well as a 24-pin wide body SOIC package. Additional customer benefits include zero power in standby mode and easy migration from existing system designs to emerging low power, low voltage portable applications. Samples will be available early second quarter 1993, and production quantities are scheduled for the end of the first half of 1993. Lead time will vary fi'om 7 to 9 weeks depending on quantity and package type. Suggested resale
pricing in 100-piece quantities is $8.70 for the 10ns MC22V10S devices. Pricing is in US dollars for US delivery only.
Contact: Patrick Holly, Motorola Inc, MD 235, 2200 W. Broadway, Mesa, A Z 85202 USA. Tel~fax: [1] (602) 898-5119 / 962-2090.
VHDL GOES AHEAD - - WARP2 Cypress distributor Ambar Components has launched a state-of-the-art V H D L (VHSIC Hardware Description Language) compiler for designing with Cypress PLDs and PROMs. Called WARP2 the new compiler utilises a proper subset of IEEE 1076 V H D L as its Hardware Description Language (HDL) for design entry. V H D L provides a number of significant benefits for the design engineer. WARP2 accepts V H D L input,synthesises and optimises the entered design and outputs a J E D E C map for the desired device. For simulation, Warp2 provides the graphical waveform simulator from the PLD Toolkit. Warp2's V H D L syntax also includes support for intermediate level entry modes such as state table and boolean entry. At the lowest level, designs can be described using gate-level RTL (Register Transfer Language). Warp2 is claimed to give the designer the flexibility to intermix all of these entry modes. Because V H D L is an IEEE standard, multiple vendors offer tools for design entry, simulation at both high and low levels, and synthesis of designs to different silicon targets. The use of device independent behavioural design entry gives users the freedom to retarget designs to different devices. The wide availability of V H D L tools provides complete vendor independence as well. Designers can begin their project using Warp2 for Cypress PLDs and convert to high volume gate arrays using the same V H D L behavioural description with industry-standard synthesis tools. Apparently the decision of offer VHDL based tools was not an arbitrary one. The languages's inherent power and universal acceptance together with the ability to offer device and vendor independent design are powerful arguments in VHDL's favour. Add to these VHDL's chip and system level simulation capabilities plus the broad
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platform of industry standard VHDL tools and for the first time the designer has an obvious choice.
Contact: Ralph Thomson, Ambar Components Ltd. Tel: 144] (0)844 261144. Fax:J44] (0)844 261789.
SYNOPSYS' TWO NEW SYNTHESIS PRODUCTS Synopsys Inc, a supplier of high-level design automation (HLDA) software, has introduced two new synthesis products: DC Professional TMand DC Expert TM.The new products make the productivity gains of logic synthesis possible for a broader range of ASIC designs, from standard to high performance applications, claims the company. Both tools incorporates Synopsys' advanced timing analysis technology as well as the new synthesis-to-layout solution reported below. DC Professional provides ASIC designers with a complete, easy-to-use synthesis solution, making synthesis practical for virtually all ASIC design in industries from computer and telecoms to consumer electronics and military /aerospace. DC Professional is based on Synopsys' original Design Compiler TM, which is production-proven on thousands of designs. "As the gate counts for all ASICs continue to increase, companies are looking for ways to increase their designers' productivity," said Penny Herscher, director of product marketing at Synopsys. "DC Professional offers designers an easy-to-use, low-risk synthesis solution." The tool's ease-of-use features include automatically generated constraints, point-to-point timing constraint support, and detailed timing analysis. At a high level, DC Professional's timing-driven arithmetic optimisation and other sequential optimisation techniques can significantly reduce area and increase performance. DC Professional also includes Synopsys' new synthesis-to-layout solution, balanced buffer trees, I/O pad synthesis, which further simplify the design process.
in-place optimisation. Critical path re-synthesis improves performance by as much as 15 percent by restructuring and re-optimising along the critical path. In-place optimisation reduces layout-related design iterations by correcting post-layout paths that are five to ten percent out of specification. This is achieved by intelligently swapping cells to improve performance, without affecting the netlist. DC Expert also includes high-end design-style support such as arbitrarily complex clocking schemes, pipeline retiming, and latch-based time borrowing, previously announced with Version 3.0. DC Expert and DC Professional will replace Synopsy's Design Compiler Version 3.0. I)C Expert and DC Professional are fully compatible with Synopsys' entire hi~h-level design automation (HLDA) product line including HDL Comlmler family the Test TM Compiler family, and the VHDL System Simulator , including previous versions of Synopsys' HLDA tools. •
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The new products are also compatible with over 100 certified libraries offered by more than 40 semiconductor vendors. DC Expert is U.S. priced at $65,000 and DC Professional at $45,000 (the same price as Design Compiler Version 2.2). Synopsys will ship I)C Expert to all customers currently under maintenance agreements at no additional charge, automatically upgrading the entire installed customer base to DC Expert, including those who have already ordered Version 3.0 simulation and test products have already started. DC Expert will be available at a discounted price of $45,000 until June 1993, when DC Professional is expected to begin shipping.
SYNOPSYS INTEGRATED SYNTHESIS-TO-LAYOUT SOLUTION Synopsys Inc. has also introduced the first high-level design synthesis-to-layout solution, eliminating the need to manually optimise designs at the layout level. The new solution was co-developed with technology partner SGS-Thomson and will be incorporated into Synopsys' '. • TM family o f synthesis complete Design Compiler p r o d u c t s , i n c l u d i n g D C E x p e r t TN and DC Professional TM. .
DC Expert is the most powerful synthesis tool on the market today, the company believes, providing new features that are not available in any synthesis product• DC Expert specifically addresses the high-performance requirements of designs by including two new powerful optimisation approaches: critical path re-synthesis and
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"Our customers are seeking ways to extend their high-level design methodology to a larger portion of the design process", said Aart de Geus, president and chief
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operating officer at Synopys. "Our synthesis-to-layout solution does exactly that, further enhancing quality of results." Synopsys' synthesis-to-layout solution automatically iterates a layout tool, converging towards a higher performance design. After an initial synthesis compile using new non-linear delay modelling, synthesis automatically drives layout, passing it critical constraint information. After a layout pass, the design is resynthesized based on the latest timing information. The technique keeps the designer interacting at high level in the design process, preserving technology independence while automatically optimising the design. The new synthesis-to-layout solution includes three new features: •
synthesis-driven constraints to layout,
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SDF back annotation,
• non-linear delay modelling. The synthesis-driven constraints use a generic format w h i c h can drive a wide v a r i e t y o f the new constraint-driven layout tools. The back annotation used the Standard Delay File (SDF), which is rapidly being adopted by layout tool and delay calculator vendors. Synopsys is working closely with several o f its semiconductor partners to deliver a vendor-definable non-linear delay modelling capability that has superior accuracy and fast compile times. Vendors will have the option of using the new non-linear modelling or Synopsys' current delay modelling, making all current libraries compatible with the new solution. Synopsys' synthesis-to-layout solution if fully integrated into the Design Compiler family, including DC Expert and DC Professional products, as well as the ECL CompilerTM.The solution is also fully compatible with the company's newly announced in-place optimisation feature, part of DC Expert and ECL Compiler. Both the synthesis-driven constraints and the SDF back annotation capabilities are included with Version 3.0 synthesis products, which are already shipping. The non-linear delay modelling will ship with version 3.0b synthesis which is scheduled for June 1993.
SYNOPSYS ARCHITECTURESPECIFIC FPGA SYNTHESIS In the third of its sequence of recent releases, Synopsys Inc., has announced a new synthesis product, FPGA CompilerTM,for designers of field-programmable gate arrays (FPGAs) who need to adopt a high-level design m e t h o d o l o g y to develop h i g h - c o m p l e x i t y , high-performance FPGA designs while meeting demanding time-to-market requirements. FPGA Compiler was developed by Synopsys in close cooperation with leading FPGA chip vendors Xilinx and Actel and FPGA tool vendor NeoCAD. FPGA Compiler extends Synopsys' line of synthesis products to a wider range of electronic designs, from FPGAs to high performance ICs and ASICs. Faster time to market and reducing the risk and cost associated with ASIC design are the forces driving more designers to use FPGAs, and the same forces are driving FPGA users to adopt a high-level design methodology. Synopsys' high-level design methodology had enabled the successful design of more than 3,000 chips since 1988. Now in its third generation, the methodology involves simulation, synthesis, and test. After describing the design in VHDL or Verilog, designers analyse and debug the description, then synthesise and optimise for performance and area into technology-specific architectures. FPGA Compiler offers architecture-specific logic optimisation and mapping, as well as state machine optimisation, to increase the performance of FPGA designs. Using the recently announced synthesis-to-layout capabilities of Synopsys' Version 3.0 tools, designers can send critical path timing information to FPGA layout tools such as NeoCAD, back annotate their designs, and confirm timing results with Synopsys' embedded timing analyser. An added benefit of FPGA Compiler is the migration path it offers FPGA designers who may eventually migrate to ASIC devices as production volume increases. FPGA designs specified in a hardware description language such as VHDL or Verilog~ may be directly translated by
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Synopsys' synthesis tools into one or more of 162 different ASIC technologies from more than 40 ASIC vendors. FPGA Compiler is supported by leading FPGA vendors, including Actel, Altera, AT&T, Crosspoint, QuickLogic, Texas Instruments, and Xilinx. Synopsys has focused first on improved optimisation o f architectures from both Xilinx and Actel, with optimisation for additional architectures to follow. For example, FPGA Compiler had the ability to map to configurable logic blocks and hard macros which are the basis o f the Xilinx 4000 series architecture, as well as the multiplexed flip-flop structures of the Actel FPGA architectures. FPGA Compiler may be purchased as a stand-alone product; as an add-on to the company's ASIC and IC synthesis products, D C Professional'rM; or as part o f the "FPGA High-level Design" package which includes PFGA Compiler HDL Compaler Designer TM ' • ' TM Analyser , and V H D L System Simulator . As a stand-alone product, FPGA Compiler is priced at $25,000; as an add-on, $15,000. The FPGA High-level Design package is priced at $60,000 (all prices U.S.). The FPGA Compiler is available immediately from Synopsys. •
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The difference between the CY7C258 and the CY7C259 is in the packaging. The CY7C258 is available in 28-pin packages because half the data lines are fed back and do not appear at the external outputs. With the CY7C259, all 16 array outputs are available at the pins. To make it easier to use the CY7C258 and the CY7C259, the devices are fully supported in the CYPRESS PLD toolkit, including the Waveform simulator. Several third party programmers also feature support for P R O M s as state machines, including Data I / O (ABEL) and ISDATA (LOG/IC).
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CYPRESS PROMs OUST PLDs FOR LARGE STATE MACHINES PLDs have dominated the field o f programmable state machines in recent years. Earlier designs utilised P R O M technology by these solutions tended to be slow. Because P R O M S are basically look-up tables their use in state machines - - as a state look-up table - - makes perfect sense. In addition large P R O M densities allow very large state machines to be constructed. The major disadvantage of this approach however is the lack o f feedback terms which then have to be provided externally. The Cypress Semiconductor CY7C258 and CY7C259 are registered P R O M s w h i c h feature internal state feedback capable of supporting 83 M H z state machines with as many as 2048 distinct states. Note that a P R O M is only limited by the number o f array inputs. If a given state machine can be implemented in the number o f inputs and feedbacks available, then it will always fit in the device! There is no need for software minimisation. These new devices feature individually bypassable input and output registers which run offthe same clock thereby adding a pipeline capability.
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Since the CY7C258/259 contain a 2k array, 11 inputs are required. Each o f these inputs can come from an input pin or from an internal output register feedback. Eleven individually programmable address multiplexers allow the user to select the ratio o f pin input and state feedback.
Applications i n f o r m a t i o n is available from A m b a r Components which will allow source code to be written in C.
UK Contact: Ralph Thomson, Ambar Components Ltd. Tel: (0)844 26I 144. Fax: (0)844 261789.
ATMEL RF IDENTIFICATION ASICs CAPABILITY Atmel has announced its R F Identification Capability which features a single chip solution with no need for any external components, customised security and optimised analogue cells. Atmel's non-volatile, mixed signal ASIC capability is said to be ideally suited for the emerging radio frequency (RF) identification (ID) market place. This capability combines non-volatile memory, digital logic and analogue circuitry on a single chip in wafer, die or standard package options, to meet the requirements o f contactless, non-volatile data storage and retrieval devices. Devices include smart cards, electronic keys, and electronic tags for a variety of applications, including toll usage parking, mass transit, I1) tags and vending machines. T h e u n i q u e silicon design c a p a b i l i t y p r o d u c e s a m o n o l i t h i c R F device that contains no e x t e r n a l components such as batteries, capacitors, coils, etc. An advanced level o f integration and miniaturisation provides the optimal single, low cost solution that is required by R F ID applications.
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Manufactured using Atmel's advanced two-level, metal, 1.8 Bm, low power CMOS process, the non-volatile, mixed signal ASICs comprise three distinct components: non-volatile memory; digital logic; and analogue circuitry. The non-volatile memory is available in OTP, EEPROM, or flash memories. The memories feature an internal high voltage pump for a single voltage operation, and are guaranteed to 100,000 erase/write cycles and up to 100 years data retention, depending on which memory type is used. The EEPROM and flash memories also support applications that have low power and low voltage requirements, with supply voltages ranging from 1,0.8 V to 5 V, depending on the memory type and circuit design. Several analogue cells have been designed and optimised to meet the needs of RF ID applications. Atmel designs and manufactures non-volatile, mixed signal ASICs that cover a variety of modulation techniques, operating frequencies and operating ranges using these cells. Atmel supports two primary design flows and a third is under development. In a turnkey design the customer provides a firm product specification and schematics, and Atmel performs the design in conjunction with third party design houses loc,ted throughout the world. The third design flow entails the development of a mixed signal, non-volatile library is currently available on Mentor Graphics, Cadence and Autologic workstations. The library supports boundary scan and includes 96 gates, muxes, latches, flip-flops and buffers, as well as several logic macro cells and an 80C31 microcontroller cell.
Contact: Bob Henderson, Atmel. Tel: [44] (0)276 68667.
WIND RIVER BSP PORTING KIT STREAMLINES VXWORKS Wind River Systems, a manufacturer of real-time operating systems and development environments, has released a Board Support Package (BSP) Porting Kit which real-time developers can use to port Wind River's VxWorks development environment to custom hardware platforms. Wind River also announces that VxWorks will support evaluation boards from Fujitsu, LSI-Logic and Performance Semiconductor. The VxWorks open-architecture, real-time operating system networks a U N I X development platform with the real-time target in an integrated environment. Its full-featured development e n v i r o n m e n t included
complete facilities for networking, multiprocessing, debugging, distributed processing, and performance monitoring. Using the BSP Porting Kit, developers can take advantage of VxWorks on any target hardware that incorporates Motorola 680x0 and 683xx, SPARClite family of microprocessors. "Both the BSP Porting Kit and the new hardware support allow developers to take VxWorks into a range of new environments" said Robert Wheaton,WRS Vice President of Sales, Marketing and Services. "Embedded systems developers, in particular, will benefit from these enhancements. The evaluation board support gives them a plug-in capability to begin developing software while their custom hardware is still in the design phase, while the Porting Kit enables them to then migrate easily from the evaluation board onto the completed custom board".
BSP porting kit All the hardware-specific functionality of the VxWorks development system is isolated into a Board Support Package (BSP), which serves as the software "glue"j oining the architecture-specific runtime system to the hardware platform. While VxWorks already supports many commercial boards, no explicit methodology had been outlined for users seeking to integrate VxWorks into custom designs, or third-party board vendors attempting to incorporate VxWorks support into additional products. With the new BSP Porting Kit, developers can easily construct their own BSPs for any VxWorks-supported p r o c e s s o r . T h e P o r t i n g Kit includes detailed documentation, a validation test suite to verify the functionality of a new port, and template software to provide a convenient starting point. Additional templates, source code for SCSI and Ethernet drivers, and assistance by WRS Engineering is available for more complex development efforts.
New hardware support W o r k i n g closely w i t h Fujitsu, L S I - L o g i c , and Performance Semiconductor, Wind River has developed BSPs enabling VxWorks compatibility with evaluation boards from these leading silicon manufacturers. Evaluation boards give developers quicker access to complex, powerful new chipsets, providing them with a temporary hardware platform for designing software while they concurrently design their own custom boards.
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The VxWorks operating system helps developers speed time-to-market even further by providing a turnkey solution to the initial development effort. Using the BSP Kit developers can then port the software onto their completed custom hardware.
UK Contact: Steven Harris, Wind River Systems, Aston Science Park, Aston Triangle, Birmingham B7 4BJ, UK. Teh [44] (0)21 359 0981. Fax: [44] (0)21 628 1889.
IC FAB OF THE FUTURE FROM TI Breakthroughs being achieved by Texas Instruments in the Microelectronics Manufacturing Science and Technology (MMST) program may provide the answer to the complexities of manufacturing single IC wafers. The goal of the MMST program is to develop and demonstrate technologies for cost-effectively manufacturing small orders of diverse ICs in fast cycle items and with greater flexibility. The problems of producing small quantities o f smaller, yet more complex, circuits that contain millions of transistors and have line widths one-hundred times smaller than a human hair on a tiny piece of silicon are monumental. Add to this the fact that IC manufacturing requires several hundred steps, each of which must be carried out in a near particle-free environment to exacting tolerances. Process modifications in today's IC factories are time-consuming and costly. These challenges will be met in the prototype single-wafer manufacturing system that TI's engineers are developing for the M M S T program. Consisting o f integrated object-oriented software for real-time factory and process control, distributed workstations, a database server, modular process systems, and unique single-wafer process technology, this IC factory of the future will bring new flexibility to wafer fabrication. T h e M M S T p r o g r a m i n c o r p o r a t e s several new approaches to traditional IC manufacturing operations. They include single-wafer processing, elimination of ultra-clean rooms, real-time process control, user-friendly s m a r t e q u i p m e n t , and a c o m p u t e r - i n t e g r a t e d manufacturing environment. Traditionally, ICs are manufactured in large volumes. Once the process is started, it cannot be easily stopped and modified. The wafers are moved between stand-alone,
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single-process machines in clean rooms. In today's fabs, the machines possess little intelligence and are not connected to each other. This results in poor material handling between machines. The MMST-approach uses "cluster" equipment, putting the clean room inside the machines. Wafers, even single ones, are processed in cluster machines (or "modular process system") that "host" at least three process modules. Wafers are contained in a sealed vacuum carrier for transport between cluster systems and are transported from m o d u l e to m o d u l e via a r o b o t arm. This cluster/vacuum-carrier approach frees up space and eliminates the need for the external environment to be ultra-clean. Managing the MMST wafer factory is a fully-integrated, object-orientated software system that allows real-time control o f production process modifications. This improved process control is based on information collected from individual wafers as they are processed in each module. The use real-time data, provided by in-situ sensors located in the process modules, reduces the likelihood of scrapping wafers that contain valuable custom circuits. The sophisticated, built-in sensors detect errors faster and save processing time, improving both quality and yield. Tying the wafer lab together via computers and integrated software brings the equivalent of a standard operating system to the factory floor. Every operator and engineer has access to a workstation that is connected to each host machine and process chamber. Communicating with the factory via Ethernet, the software unifies, monitors and controls and all production functions. The CIM-system factory-floor scheduler controls all operations, basing its decisions on the instantaneous state o f the factory, the capabilities and performance of factory resources, and projected workload. An on-line database and report-generating feature provide the lab personnel with a continual, up-to-date status of the lab's operations. A large amount of knowledge embedded in the software eliminates previously manual operations and builds more precision and quality control into the manufacturing process.
Update continues on page 287
Motorola MCMs Motorola's Application Specific Integrated Circuits Division, Chandler, AZ, USA, has introduced the MCML T M Series of multichip modules (MCMs). Aimed at costsensitive, low to medium power applications,the modules use laminate PCB type substrates to achieve the next level of semiconductor integration.
Motorola is offering a complete application specific MCM product solution that includes design support,
manufacturing, and test. The MCML Series MCM combines multiple ICs such as ASICs, microprocessor and memory on a small PCB substrate. The combination of ICs and substrate is moulded with a plastic compound into standard EIAJ plastic quad flat pack (QFP) body sizes and lead counts. Potential system advantages, Motorola says, are smaller physical size, better performance and lower assembly costs.
Fig. 1.
0026-2692/93/$6.00 © 1993, Elsevier Science Publishers Ltd
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Fig. 2. The MCML Series allows customers using single-chip QFP packages to take advantage of MCM packaging density while staying with existing high-volume manufacturing and test equipment. Modules fit into a PCB assembly flow exactly like a single chip QFP. Motorola encapsulates the multichip substrates in the same moulding equipment used for cost-effective single chip packages.
Potential advantages According to Steve Bowen, MCM product development manager, "Potential advantages are easy to visualize. Surface area is reduced five to ten times over single chip packages and chip-to-chip signal delays are cut in half."
Bowen noted that his module organization has been producing M C M - L types substrates for Motorola equipment divisions since the beginning of 1992. "Our customers estimate system cost savings due to lower assembly costs and simplified PCB construction," he said. A typical power rating of 2-5W makes the series suitable for high speed CMOS applications. Motorola offers the MCML Series as an enhancement to Motorola's standard semiconductor products and ASICs. O f course, the company strongly recommends that the MCML modules contain all-Motorola semiconductors to ensure chip-set availability. The use of non-Motorola ICs will be evaluated on a case-by-case basis.
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The MCML Series module CAD is an extension of the Motorola Open Architecture CAD System (OACS) used for ASIC gate array development. Motorola's CAD strategy for both ASICs and modules is to use the best available industry software, supported with Motorola developed programs, to provide a complete CAD package. It is recommended that customers do schematic capture, module simulation, and performance analysis on engineering workstations. Motorola normally performs physical design place and route, transmission line analysis, thermal analysis, and conversion to tester compatible final test programs. All MCML Series modules are tested for
Microelectronics Journal, Vol. 24, No. 3
functionality, parametrics, and performance on the same test systems used for ASIC products.
Base NRE charge According to Motorola, the base N R E charge is $75k per module design. Within the base charge Motorola performs physical design and procures all prototype die. Motorola also does thermal analysis, electromagnetic analysis and test p r o g r a m generation. T h e customer performs schematic capture, functional and performance simulation and develops test vectors. Unit pricing varies widely with chipset cost. For example, a typical 28 m m module containing two 8k SRAMs and one 64k gate C M O S array would cost less than $100.00 each in production volumes. Two substrate sizes including a 28 m m body size with 128, 160, or 208 leads, and a 40 m m body size with 232 or 304 leads are available for prototyping now. Prototype leadtime is typically 14 weeks from release of design, the company claims. Manufacturing of the M C M L Series modules will take place at Motorola's ASIC headquarters facility in Chandler, Arizona.
Contact: Steve Bowen, Motorola Inc, kiD CH290, 1300 N. Alma School Road, Chandler, A Z 85224 USA. Tel~fax: [1] (602) 821-4497 / 4963.
AT&T DIAMOND SUB-MOUNTS FOR POWER ASSEMBLIES AT&T has announced what it claims to be the world's first commercial application of a novel synthetic diamond material c o m b i n e d with an advanced metallisation bonding technique developed at AT&T Bell Labs. The company will use the new technology to make microelectronic heatsinks as sub-mounts for high power semiconductor lasers, which will shortly be in production at AT&T Microelectronics. The sub-mounts, made o f chemically vapour-deposited (CVD) films o f synthetic diamond, combine high functionality and maximum heat-extraction capability. C V D diamond sub-mounts have been fabricated to AT&T's specification by a number o f vendors worldwide selected by AT&T as the leading edge suppliers in CVD diamond technology. AT&T has worked closely with these
vendors in marrying its sub-mount design and processing technology with its diamond growth and processing technology to develop both a product and a market to their mutual benefit. Making usable laser sub-mounts from CVD diamond, h o w e v e r , requires a d v a n c e d thin film b o n d i n g metallisation compatible with diamond processing. Use o f this technology enables efficient heat removal from lasers, w h i c h is the key to achieving both h i g h - p o w e r performance and the reliability necessary in high power laser applications. T h e d e v e l o p m e n t t e a m is p u r s u i n g f u r t h e r optoelectronics applications and envisions much broader applications within AT&T Microelectronics, in the area o f silicon and gallium arsenide high performance ICs and in high density interconnects.
TOSHIBA ASIC PACKAGES REDUCE BOARD SPACE BY UP TO 60% Toshiba Electronics (UK) Ltd has announced that its entire range of ASIC products is now available in a new SM package option known as the Small-outline Very-thin Flat Pack (SVFP). The new package not only results in a PCB area reduction of 60% on the conventional plastic flat packs but also offers a reduced profile. The package is 1.4 m m thick and, when mounted, has a total height of less than 2 mm. This compares to a mounted height of over 4 m m for standard flat packs. Featuring a lead pitch of 0.5 mm, the package is available in a variety of configurations with between 48 and 176 I / O pads.
Contact: Angela Murphy, Toshiba (UK) Ltd, Tel: [44] (0)276 694 600.
EUROPEAN CONTRACT ASSEMBLY BEATS THE RECESSION According to a new report, the contract electronics assembly industry in Europe is confounding the general industry doom and gloom with an estimated value o f $1.8bn in 1992. It will continue to thrive and beat the recession with growth up to $3.67bn by 1997. The new report, from the Elsevier Advanced Technology m a r k e t research division, is called EUROPEAN
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CONTRACT ELECTRONICS ASSEMBLY M A R K E T S 1993-1997. It investigates the emerging and rapidly growing contract electronics assembly industry in Europe, w h i c h provides the service o f assembling electronic components onto PCBs, design and test. The report uncovers the basic reasons for this impressive growth o f this industry and reveals an unusual geographic bias within the industry. The recession-proof growth is apparently due to not one but, several factors: the complexity o f mixed technology assemblies, i.e., SMT and C T H assembly; the increased investment necessary to cope with both technologies; the increased technical know-how necessary to cope with the various process and design requirements, (particularly with regard to fine pitch technology and high pin count devices) and the fact that in the current economic climate it is often more economical to cope with increased demand by contracting-out the excess work rather than to invest further. The report shows that current levels o f activity in the industry vary considerably in each individual country, especially in relation to the general economic activity o f each country. Indeed, there is much more activity in the U K than in Germany, in absolute terms, which is quite unusual. The report evaluates the major factors leading to this development and takes a look at where the future areas of increased activity will be.
The report is available now priced £1250 ($2250). Further details from: Robin George, Elsevier Advanced Technology, Mayfield House, 256 Banbury Rd, Oxford OX2 7DH. Tel~fax: [44] (0)865 512242 / 310981.
are close behind with 78% gains from $385M in 1991 to $688M by 1996. O f the 10 user groups analyzed, passive component consumption growth will be the weakest, rising only 18% from $16M in 1991 to reach $19M by 1996. Development of an appropriate and cost-effective test strategy is now becoming recognised as a key element in the long term success o f electronics manufacture. Frost & Sullivan believes that the distributed test concept will gain increasing acceptance as an alternative means o f lowering overall test costs and improving test throughput rates. Distributed test strategies include a variety of process test configurations aimed at finding the most common process related faults and thereby improving the throughput o f expensive diagnostic ATE systems. The ideal functional tester o f the future will meet program development and life-cycle goals through a variety of software tools. The four leading suppliers o f the ATE market - Advantest, Teradyne, Schlumberger and LTX currently account for about half of the US market. Foreign competitors are expected to become major players. Price of the report # A2567 is $3,200.
US Contact: Frost & Sullivan Inc. Tel [ 1] (212) 233-1080. In Europe, tel: [44] (0)71 730-3438.
SMT IMPACTS ASSEMBLY TO TUNE OF $3.7BN SAYS REPORT
50% JUMP IN US ATE MARKET
A new report from Decision resources estimates that the worldwide market for SMT assembly equipment will grow from $1.5bn in 1992 to $3.7bn in 1996. The report,
A new report from Frost & Sullivan forecasts a 50% or more j u m p in ATE sales from $1.51bn in 1991 to $2.43bn in 1996.
S M T in Electronics Packaging, 1992-1996: Industry Impact of New S M T Generations and Alternative Technologies, is
A T E is d e f i n e d as c o m m e r c i a l l y available computer-controlled programmable systems used to test and diagnose faults in PCBs and the components mounted on them. In terms o f end users, telecommunication industry demand is forecast to grow most sharply, up 80% from $263M in 1991 to $476M in 1996. Semiconductors
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intended to define and forecast current and future markets for SMT, TAB, C O B and other assembly processing techniques. The report is priced $2800 and is available now.
Contact: Decision Resources. Tel~fax: [1] 617 270-1222 / 273-3048.
Microelectronics Journal, Vol. 24, No. 3
FACTS AND FIGURES ON JAPANESE ELECTRONICS The 1992 English edition of Facts & Figures recently published by the EIA of Japan gives almost a ten year history on the performance of this energetic industry. Contrary to common belief the consumer section is the worst performer.Japan's total production in electronics for 1991 is given as 46% industrial, 35% components and 19% consumer. The export breakdown is given as 45% components, 31% industrial and 24% consumer. The Walkman and TV sets are only the tip of the iceberg.
MOTOROLA 10ns PLD DEBUT IN 24-PIN SOIC PACKAGE Motorola's Logic IC Division has made its debut in the programmable logic device (PLD) market with several e n h a n c e d versions o f the popular 22V10 device. Motomla's ultra low power MC22V10S family maintains all important industry standard features, while offering advanced features and functionality. Motorola claims that its entrance into the 22V10 market gives customers many advantages over current leaders in the field. These include: 10ns and 15ns speed devices with drastically reduced power consumption of 30mA, 3.0/3/3V operation for low voltage applications with even lower power consumption. In particular, Motorola claims significantly reduced circuit board area with availability of the industry's first 10ns 24-pin SOIC package. It is the low power consumption of the MC22V10S family which permits Motorola to offer the MC22V10S devices in popular, industry standard packages including the 24-pin DIP and 28-pin PLCC packages,as well as a 24-pin wide body SOIC package. Additional customer benefits include zero power in standby mode and easy migration from existing system designs to emerging low power, low voltage portable applications. Samples will be available early second quarter 1993, and production quantities are scheduled for the end of the first half of 1993. Lead time will vary fi'om 7 to 9 weeks depending on quantity and package type. Suggested resale
pricing in 100-piece quantities is $8.70 for the 10ns MC22V10S devices. Pricing is in US dollars for US delivery only.
Contact: Patrick Holly, Motorola Inc, MD 235, 2200 W. Broadway, Mesa, A Z 85202 USA. Tel~fax: [1] (602) 898-5119 / 962-2090.
VHDL GOES AHEAD - - WARP2 Cypress distributor Ambar Components has launched a state-of-the-art V H D L (VHSIC Hardware Description Language) compiler for designing with Cypress PLDs and PROMs. Called WARP2 the new compiler utilises a proper subset of IEEE 1076 V H D L as its Hardware Description Language (HDL) for design entry. V H D L provides a number of significant benefits for the design engineer. WARP2 accepts V H D L input,synthesises and optimises the entered design and outputs a J E D E C map for the desired device. For simulation, Warp2 provides the graphical waveform simulator from the PLD Toolkit. Warp2's V H D L syntax also includes support for intermediate level entry modes such as state table and boolean entry. At the lowest level, designs can be described using gate-level RTL (Register Transfer Language). Warp2 is claimed to give the designer the flexibility to intermix all of these entry modes. Because V H D L is an IEEE standard, multiple vendors offer tools for design entry, simulation at both high and low levels, and synthesis of designs to different silicon targets. The use of device independent behavioural design entry gives users the freedom to retarget designs to different devices. The wide availability of V H D L tools provides complete vendor independence as well. Designers can begin their project using Warp2 for Cypress PLDs and convert to high volume gate arrays using the same V H D L behavioural description with industry-standard synthesis tools. Apparently the decision of offer VHDL based tools was not an arbitrary one. The languages's inherent power and universal acceptance together with the ability to offer device and vendor independent design are powerful arguments in VHDL's favour. Add to these VHDL's chip and system level simulation capabilities plus the broad
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platform of industry standard VHDL tools and for the first time the designer has an obvious choice.
Contact: Ralph Thomson, Ambar Components Ltd. Tel: 144] (0)844 261144. Fax:J44] (0)844 261789.
SYNOPSYS' TWO NEW SYNTHESIS PRODUCTS Synopsys Inc, a supplier of high-level design automation (HLDA) software, has introduced two new synthesis products: DC Professional TMand DC Expert TM.The new products make the productivity gains of logic synthesis possible for a broader range of ASIC designs, from standard to high performance applications, claims the company. Both tools incorporates Synopsys' advanced timing analysis technology as well as the new synthesis-to-layout solution reported below. DC Professional provides ASIC designers with a complete, easy-to-use synthesis solution, making synthesis practical for virtually all ASIC design in industries from computer and telecoms to consumer electronics and military /aerospace. DC Professional is based on Synopsys' original Design Compiler TM, which is production-proven on thousands of designs. "As the gate counts for all ASICs continue to increase, companies are looking for ways to increase their designers' productivity," said Penny Herscher, director of product marketing at Synopsys. "DC Professional offers designers an easy-to-use, low-risk synthesis solution." The tool's ease-of-use features include automatically generated constraints, point-to-point timing constraint support, and detailed timing analysis. At a high level, DC Professional's timing-driven arithmetic optimisation and other sequential optimisation techniques can significantly reduce area and increase performance. DC Professional also includes Synopsys' new synthesis-to-layout solution, balanced buffer trees, I/O pad synthesis, which further simplify the design process.
in-place optimisation. Critical path re-synthesis improves performance by as much as 15 percent by restructuring and re-optimising along the critical path. In-place optimisation reduces layout-related design iterations by correcting post-layout paths that are five to ten percent out of specification. This is achieved by intelligently swapping cells to improve performance, without affecting the netlist. DC Expert also includes high-end design-style support such as arbitrarily complex clocking schemes, pipeline retiming, and latch-based time borrowing, previously announced with Version 3.0. DC Expert and DC Professional will replace Synopsy's Design Compiler Version 3.0. I)C Expert and DC Professional are fully compatible with Synopsys' entire hi~h-level design automation (HLDA) product line including HDL Comlmler family the Test TM Compiler family, and the VHDL System Simulator , including previous versions of Synopsys' HLDA tools. •
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The new products are also compatible with over 100 certified libraries offered by more than 40 semiconductor vendors. DC Expert is U.S. priced at $65,000 and DC Professional at $45,000 (the same price as Design Compiler Version 2.2). Synopsys will ship I)C Expert to all customers currently under maintenance agreements at no additional charge, automatically upgrading the entire installed customer base to DC Expert, including those who have already ordered Version 3.0 simulation and test products have already started. DC Expert will be available at a discounted price of $45,000 until June 1993, when DC Professional is expected to begin shipping.
SYNOPSYS INTEGRATED SYNTHESIS-TO-LAYOUT SOLUTION Synopsys Inc. has also introduced the first high-level design synthesis-to-layout solution, eliminating the need to manually optimise designs at the layout level. The new solution was co-developed with technology partner SGS-Thomson and will be incorporated into Synopsys' '. • TM family o f synthesis complete Design Compiler p r o d u c t s , i n c l u d i n g D C E x p e r t TN and DC Professional TM. .
DC Expert is the most powerful synthesis tool on the market today, the company believes, providing new features that are not available in any synthesis product• DC Expert specifically addresses the high-performance requirements of designs by including two new powerful optimisation approaches: critical path re-synthesis and
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"Our customers are seeking ways to extend their high-level design methodology to a larger portion of the design process", said Aart de Geus, president and chief
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operating officer at Synopys. "Our synthesis-to-layout solution does exactly that, further enhancing quality of results." Synopsys' synthesis-to-layout solution automatically iterates a layout tool, converging towards a higher performance design. After an initial synthesis compile using new non-linear delay modelling, synthesis automatically drives layout, passing it critical constraint information. After a layout pass, the design is resynthesized based on the latest timing information. The technique keeps the designer interacting at high level in the design process, preserving technology independence while automatically optimising the design. The new synthesis-to-layout solution includes three new features: •
synthesis-driven constraints to layout,
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SDF back annotation,
• non-linear delay modelling. The synthesis-driven constraints use a generic format w h i c h can drive a wide v a r i e t y o f the new constraint-driven layout tools. The back annotation used the Standard Delay File (SDF), which is rapidly being adopted by layout tool and delay calculator vendors. Synopsys is working closely with several o f its semiconductor partners to deliver a vendor-definable non-linear delay modelling capability that has superior accuracy and fast compile times. Vendors will have the option of using the new non-linear modelling or Synopsys' current delay modelling, making all current libraries compatible with the new solution. Synopsys' synthesis-to-layout solution if fully integrated into the Design Compiler family, including DC Expert and DC Professional products, as well as the ECL CompilerTM.The solution is also fully compatible with the company's newly announced in-place optimisation feature, part of DC Expert and ECL Compiler. Both the synthesis-driven constraints and the SDF back annotation capabilities are included with Version 3.0 synthesis products, which are already shipping. The non-linear delay modelling will ship with version 3.0b synthesis which is scheduled for June 1993.
SYNOPSYS ARCHITECTURESPECIFIC FPGA SYNTHESIS In the third of its sequence of recent releases, Synopsys Inc., has announced a new synthesis product, FPGA CompilerTM,for designers of field-programmable gate arrays (FPGAs) who need to adopt a high-level design m e t h o d o l o g y to develop h i g h - c o m p l e x i t y , high-performance FPGA designs while meeting demanding time-to-market requirements. FPGA Compiler was developed by Synopsys in close cooperation with leading FPGA chip vendors Xilinx and Actel and FPGA tool vendor NeoCAD. FPGA Compiler extends Synopsys' line of synthesis products to a wider range of electronic designs, from FPGAs to high performance ICs and ASICs. Faster time to market and reducing the risk and cost associated with ASIC design are the forces driving more designers to use FPGAs, and the same forces are driving FPGA users to adopt a high-level design methodology. Synopsys' high-level design methodology had enabled the successful design of more than 3,000 chips since 1988. Now in its third generation, the methodology involves simulation, synthesis, and test. After describing the design in VHDL or Verilog, designers analyse and debug the description, then synthesise and optimise for performance and area into technology-specific architectures. FPGA Compiler offers architecture-specific logic optimisation and mapping, as well as state machine optimisation, to increase the performance of FPGA designs. Using the recently announced synthesis-to-layout capabilities of Synopsys' Version 3.0 tools, designers can send critical path timing information to FPGA layout tools such as NeoCAD, back annotate their designs, and confirm timing results with Synopsys' embedded timing analyser. An added benefit of FPGA Compiler is the migration path it offers FPGA designers who may eventually migrate to ASIC devices as production volume increases. FPGA designs specified in a hardware description language such as VHDL or Verilog~ may be directly translated by
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Synopsys' synthesis tools into one or more of 162 different ASIC technologies from more than 40 ASIC vendors. FPGA Compiler is supported by leading FPGA vendors, including Actel, Altera, AT&T, Crosspoint, QuickLogic, Texas Instruments, and Xilinx. Synopsys has focused first on improved optimisation o f architectures from both Xilinx and Actel, with optimisation for additional architectures to follow. For example, FPGA Compiler had the ability to map to configurable logic blocks and hard macros which are the basis o f the Xilinx 4000 series architecture, as well as the multiplexed flip-flop structures of the Actel FPGA architectures. FPGA Compiler may be purchased as a stand-alone product; as an add-on to the company's ASIC and IC synthesis products, D C Professional'rM; or as part o f the "FPGA High-level Design" package which includes PFGA Compiler HDL Compaler Designer TM ' • ' TM Analyser , and V H D L System Simulator . As a stand-alone product, FPGA Compiler is priced at $25,000; as an add-on, $15,000. The FPGA High-level Design package is priced at $60,000 (all prices U.S.). The FPGA Compiler is available immediately from Synopsys. •
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The difference between the CY7C258 and the CY7C259 is in the packaging. The CY7C258 is available in 28-pin packages because half the data lines are fed back and do not appear at the external outputs. With the CY7C259, all 16 array outputs are available at the pins. To make it easier to use the CY7C258 and the CY7C259, the devices are fully supported in the CYPRESS PLD toolkit, including the Waveform simulator. Several third party programmers also feature support for P R O M s as state machines, including Data I / O (ABEL) and ISDATA (LOG/IC).
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CYPRESS PROMs OUST PLDs FOR LARGE STATE MACHINES PLDs have dominated the field o f programmable state machines in recent years. Earlier designs utilised P R O M technology by these solutions tended to be slow. Because P R O M S are basically look-up tables their use in state machines - - as a state look-up table - - makes perfect sense. In addition large P R O M densities allow very large state machines to be constructed. The major disadvantage of this approach however is the lack o f feedback terms which then have to be provided externally. The Cypress Semiconductor CY7C258 and CY7C259 are registered P R O M s w h i c h feature internal state feedback capable of supporting 83 M H z state machines with as many as 2048 distinct states. Note that a P R O M is only limited by the number o f array inputs. If a given state machine can be implemented in the number o f inputs and feedbacks available, then it will always fit in the device! There is no need for software minimisation. These new devices feature individually bypassable input and output registers which run offthe same clock thereby adding a pipeline capability.
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Since the CY7C258/259 contain a 2k array, 11 inputs are required. Each o f these inputs can come from an input pin or from an internal output register feedback. Eleven individually programmable address multiplexers allow the user to select the ratio o f pin input and state feedback.
Applications i n f o r m a t i o n is available from A m b a r Components which will allow source code to be written in C.
UK Contact: Ralph Thomson, Ambar Components Ltd. Tel: (0)844 26I 144. Fax: (0)844 261789.
ATMEL RF IDENTIFICATION ASICs CAPABILITY Atmel has announced its R F Identification Capability which features a single chip solution with no need for any external components, customised security and optimised analogue cells. Atmel's non-volatile, mixed signal ASIC capability is said to be ideally suited for the emerging radio frequency (RF) identification (ID) market place. This capability combines non-volatile memory, digital logic and analogue circuitry on a single chip in wafer, die or standard package options, to meet the requirements o f contactless, non-volatile data storage and retrieval devices. Devices include smart cards, electronic keys, and electronic tags for a variety of applications, including toll usage parking, mass transit, I1) tags and vending machines. T h e u n i q u e silicon design c a p a b i l i t y p r o d u c e s a m o n o l i t h i c R F device that contains no e x t e r n a l components such as batteries, capacitors, coils, etc. An advanced level o f integration and miniaturisation provides the optimal single, low cost solution that is required by R F ID applications.
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Manufactured using Atmel's advanced two-level, metal, 1.8 Bm, low power CMOS process, the non-volatile, mixed signal ASICs comprise three distinct components: non-volatile memory; digital logic; and analogue circuitry. The non-volatile memory is available in OTP, EEPROM, or flash memories. The memories feature an internal high voltage pump for a single voltage operation, and are guaranteed to 100,000 erase/write cycles and up to 100 years data retention, depending on which memory type is used. The EEPROM and flash memories also support applications that have low power and low voltage requirements, with supply voltages ranging from 1,0.8 V to 5 V, depending on the memory type and circuit design. Several analogue cells have been designed and optimised to meet the needs of RF ID applications. Atmel designs and manufactures non-volatile, mixed signal ASICs that cover a variety of modulation techniques, operating frequencies and operating ranges using these cells. Atmel supports two primary design flows and a third is under development. In a turnkey design the customer provides a firm product specification and schematics, and Atmel performs the design in conjunction with third party design houses loc,ted throughout the world. The third design flow entails the development of a mixed signal, non-volatile library is currently available on Mentor Graphics, Cadence and Autologic workstations. The library supports boundary scan and includes 96 gates, muxes, latches, flip-flops and buffers, as well as several logic macro cells and an 80C31 microcontroller cell.
Contact: Bob Henderson, Atmel. Tel: [44] (0)276 68667.
WIND RIVER BSP PORTING KIT STREAMLINES VXWORKS Wind River Systems, a manufacturer of real-time operating systems and development environments, has released a Board Support Package (BSP) Porting Kit which real-time developers can use to port Wind River's VxWorks development environment to custom hardware platforms. Wind River also announces that VxWorks will support evaluation boards from Fujitsu, LSI-Logic and Performance Semiconductor. The VxWorks open-architecture, real-time operating system networks a U N I X development platform with the real-time target in an integrated environment. Its full-featured development e n v i r o n m e n t included
complete facilities for networking, multiprocessing, debugging, distributed processing, and performance monitoring. Using the BSP Porting Kit, developers can take advantage of VxWorks on any target hardware that incorporates Motorola 680x0 and 683xx, SPARClite family of microprocessors. "Both the BSP Porting Kit and the new hardware support allow developers to take VxWorks into a range of new environments" said Robert Wheaton,WRS Vice President of Sales, Marketing and Services. "Embedded systems developers, in particular, will benefit from these enhancements. The evaluation board support gives them a plug-in capability to begin developing software while their custom hardware is still in the design phase, while the Porting Kit enables them to then migrate easily from the evaluation board onto the completed custom board".
BSP porting kit All the hardware-specific functionality of the VxWorks development system is isolated into a Board Support Package (BSP), which serves as the software "glue"j oining the architecture-specific runtime system to the hardware platform. While VxWorks already supports many commercial boards, no explicit methodology had been outlined for users seeking to integrate VxWorks into custom designs, or third-party board vendors attempting to incorporate VxWorks support into additional products. With the new BSP Porting Kit, developers can easily construct their own BSPs for any VxWorks-supported p r o c e s s o r . T h e P o r t i n g Kit includes detailed documentation, a validation test suite to verify the functionality of a new port, and template software to provide a convenient starting point. Additional templates, source code for SCSI and Ethernet drivers, and assistance by WRS Engineering is available for more complex development efforts.
New hardware support W o r k i n g closely w i t h Fujitsu, L S I - L o g i c , and Performance Semiconductor, Wind River has developed BSPs enabling VxWorks compatibility with evaluation boards from these leading silicon manufacturers. Evaluation boards give developers quicker access to complex, powerful new chipsets, providing them with a temporary hardware platform for designing software while they concurrently design their own custom boards.
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The VxWorks operating system helps developers speed time-to-market even further by providing a turnkey solution to the initial development effort. Using the BSP Kit developers can then port the software onto their completed custom hardware.
UK Contact: Steven Harris, Wind River Systems, Aston Science Park, Aston Triangle, Birmingham B7 4BJ, UK. Teh [44] (0)21 359 0981. Fax: [44] (0)21 628 1889.
IC FAB OF THE FUTURE FROM TI Breakthroughs being achieved by Texas Instruments in the Microelectronics Manufacturing Science and Technology (MMST) program may provide the answer to the complexities of manufacturing single IC wafers. The goal of the MMST program is to develop and demonstrate technologies for cost-effectively manufacturing small orders of diverse ICs in fast cycle items and with greater flexibility. The problems of producing small quantities o f smaller, yet more complex, circuits that contain millions of transistors and have line widths one-hundred times smaller than a human hair on a tiny piece of silicon are monumental. Add to this the fact that IC manufacturing requires several hundred steps, each of which must be carried out in a near particle-free environment to exacting tolerances. Process modifications in today's IC factories are time-consuming and costly. These challenges will be met in the prototype single-wafer manufacturing system that TI's engineers are developing for the M M S T program. Consisting o f integrated object-oriented software for real-time factory and process control, distributed workstations, a database server, modular process systems, and unique single-wafer process technology, this IC factory of the future will bring new flexibility to wafer fabrication. T h e M M S T p r o g r a m i n c o r p o r a t e s several new approaches to traditional IC manufacturing operations. They include single-wafer processing, elimination of ultra-clean rooms, real-time process control, user-friendly s m a r t e q u i p m e n t , and a c o m p u t e r - i n t e g r a t e d manufacturing environment. Traditionally, ICs are manufactured in large volumes. Once the process is started, it cannot be easily stopped and modified. The wafers are moved between stand-alone,
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single-process machines in clean rooms. In today's fabs, the machines possess little intelligence and are not connected to each other. This results in poor material handling between machines. The MMST-approach uses "cluster" equipment, putting the clean room inside the machines. Wafers, even single ones, are processed in cluster machines (or "modular process system") that "host" at least three process modules. Wafers are contained in a sealed vacuum carrier for transport between cluster systems and are transported from m o d u l e to m o d u l e via a r o b o t arm. This cluster/vacuum-carrier approach frees up space and eliminates the need for the external environment to be ultra-clean. Managing the MMST wafer factory is a fully-integrated, object-orientated software system that allows real-time control o f production process modifications. This improved process control is based on information collected from individual wafers as they are processed in each module. The use real-time data, provided by in-situ sensors located in the process modules, reduces the likelihood of scrapping wafers that contain valuable custom circuits. The sophisticated, built-in sensors detect errors faster and save processing time, improving both quality and yield. Tying the wafer lab together via computers and integrated software brings the equivalent of a standard operating system to the factory floor. Every operator and engineer has access to a workstation that is connected to each host machine and process chamber. Communicating with the factory via Ethernet, the software unifies, monitors and controls and all production functions. The CIM-system factory-floor scheduler controls all operations, basing its decisions on the instantaneous state o f the factory, the capabilities and performance of factory resources, and projected workload. An on-line database and report-generating feature provide the lab personnel with a continual, up-to-date status of the lab's operations. A large amount of knowledge embedded in the software eliminates previously manual operations and builds more precision and quality control into the manufacturing process.
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