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Multichannel mixed-mode IC for digital readout of silicon strip detectors
Microelectronics Reliability 42 (2002) 427–436 www.elsevier.com/locate/microrel
Multichannel mixed-mode IC for digital readout of silicon strip detectors wientek a, P. Grybos a,*, W. Daz browski a,*, P. Hottowy a, R. Szczygieł b, K. S P. Wiaz cek a a
Faculty of Physics and Nuclear Techniques, University of Mining and Metallurgy, al. Mickiewicza 30, 30-059 Krak ow, Poland b Institute of Nuclear Physics, ul. Kawiory 26A, 30-065 Krak ow, Poland Received 26 October 2001; received in revised form 26 November 2001
Abstract The design of a mixed mode 64-channel ASIC for digital readout of silicon strip detectors used in X-ray imaging applications is presented. The design is implemented in a 0.8 lm CMOS n-well epi-type substrate technology. The single channel consists of a charge sensitive preamplifier, a shaping amplifier, a discriminator and a pseudo-random 20-bit counter. In addition to the 64-channel core which is responsible for signal processing and data storage, the IC comprises additional blocks like an internal calibration circuit, internal DACs and a command decoder which governs communication of the IC with the external world. Those blocks have been designed keeping in mind testability features and using the chips for building multi-chip modules. The equivalent input noise charge measured at room temperature for a detector capacitance of 2.5 pF and signal integration time of 0.7 ls is 167 e rms. The average power dissipation is 2.5 mW/channel. The channel-to-channel offset spread referred to the input is only 28 e rms, while the standard deviation of gain spread is 0.5% of the mean value. The chip occupies area of 2:8 6:5 mm2 . 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction Semiconductor position sensitive detectors working in the single photon counting mode are widely used for X-ray imaging in physics, biology and medicine. An advantage of single photon counting detectors is essentially an infinite dynamic range contrary to integrationtype detectors, which usually have problems with a limited dynamic range and so a low contrast of the image. Among various types of position sensitive detectors the most commonly used are silicon detectors built as matrixes of reverse biased diodes on common highresistivity substrate. The sensitive area can be easily divided into individual diodes of the shapes as required by the experiment. For direct detection of X-rays of energy
* Corresponding authors. Tel.: +48-12-617-2959; fax: +4812-634-0010. E-mail addresses: [email protected] (P. Grybos), [email protected] (W. Daz browski).
in the range up to 20 keV, a high resistivity substrate is needed in order to obtain sufficiently thick depletion regions at relatively low bias voltages, of few tens of volts. A photon absorbed in the depletion region generates charge which then is collected within 10–30 ns depending on the actual position at which the photon is absorbed and on the detector bias. The charge moving in the depletion region induces short current pulses in the electrodes which are connected to the front-end electronics. In order use such detectors effectively in digital imaging each sensitive element (diode) has to be served by an individual electronic readout channel. The developed ASIC is dedicated for applications in X-ray diffractometry where the interesting energy of Xrays is limited to a range from about 5–20 keV. There are diffraction techniques widely used for which onedimensional position sensitive detection systems are sufficient. For such applications silicon microstrip detectors with a strip pitch of 100 lm suit very well. There are basically two possible schemes for readout of silicon strip detectors: analogue and binary. In the analogue
0026-2714/02/$ - see front matter 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 2 6 0 - 8
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scheme one measures the amplitudes of the signals and calculates the centre of gravity of the signal cluster. This method allows one to improve the accuracy of position measurement, especially for small strip pitch where significant fraction of events results in charge being shared between neighbouring strips. It requires, however, either an ADC connected to each channel of the front-end electronics or multiplexing signals from some number of channels into a single ADC. In the first case one faces limitations due to complexity of the system and power consumption. The second solution results in limitations on the maximum rate of X-rays which can be measured. Preserving analogue information gives more flexibility for off-line data processing. In particular, since in many cases digital noise and external interference result in common mode noise in multi-channel systems one can think of measuring and subtracting this noise in the offline analysis. In the binary scheme each channel of the front-end electronics is equipped with an amplitude discriminator which generates 1-bit information in response to each signal above given threshold. Binary information can be easily stored on the IC separately for each channel, which allows to cope with high rates of X-rays as each channel works independently. The binary scheme requires, however, a good signal-to-noise ratio in order to keep sufficient separation between the noise and the signal level. In addition, it requires very good uniformity of analogue parameters (gain, offset and noise) in multichannel ICs, and immunity to digital noise and external interference. The second aspect is of particular importance as due to very small signals from silicon strip detectors the circuit has to be optimised to reduce the intrinsic noise sources to possible minimum and the digital noise has to be kept much below the intrinsic noise in order to make the IC useful for real applications. In this paper we present the RX64 IC which is dedicated for readout of silicon strip detectors in X-ray diffractometers. The IC comprises 64 front-end channels following the concept of binary architecture and digital circuitry required for controlling operation of the chip and for communication with an external data acquisition system. The chip has been designed and fabricated in a standard CMOS 0.8 lm n-well technology, which from the point of view of analogue design is quite adequate for such an application [1]. The system comprising up to 128 readout channels is expected work without cooling which puts a strong constraint on the maximum power dissipation in a single channel. In order to make a multi-channel system practical for use one requires that a common discriminator threshold is applied to all channels. Therefore low noise performance with good matching of the gain and offset for all channels in the multi-channel chip is an absolutely critical issue for such systems. These requirements are contradictory to small
silicon area and high speed requirements. In order to improve functionality and reliability of the detector modules using RX64 chips it is required that low noise high performance analogue circuits and digital blocks are integrated in a single die. The design follows well known general rules for mixed-mode designs, like: quieting digital blocks, lowering sensitivity of analogue circuits to switching noise and implementing proper for given technology isolation techniques [2,3]. In the following sections we present an overview of the IC architecture, some aspects of optimisation of the front-end circuit for low power, low noise and matching, design of digital blocks, layout techniques, testability features and some test results.
2. Design overview The block diagram of the complete RX64 IC is shown in Fig. 1. The chip comprises five basic blocks: 64 analogue front-end channels, 64 counters, input–output block, control block, calibration circuit and bias generators. Each channel of the analogue front-end electronics is equipped with a comparator providing discrimination of the analogue signal at a given level. Due to statistical nature of X-rays the signals at the output of the discriminator appear completely randomly in time and are stored in 20-bit asynchronous counters. The counters are grouped in the blocks of eight channels each and the data from each block are read out via 8-bit bus with tristate outputs. In a single chip we have integrated 64 channels which can simultaneously process signals and store data from 64 sensor elements of a silicon strip detector. Such architecture provides fully parallel signal processing, including data storage from all strips. It is suitable for high counting rate applications since the amount of data to be handled is minimised already in the front-end part. In addition to the basic functions which control the data storage and readout, the control block provides settings
Fig. 1. Block diagram of RX64 IC.
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of the DACs which are used in the front-end block for biasing the analogue circuits and controlling the internal calibration circuit. The control block receives the commands via an external serial link, decodes them and executes by sending the control signals and data to other blocks.
ters and all digital control logic on the same die without compromising analogue performance. Thus, we have focused on two problems, which are absolutely critical in such a multi-channel mixed-mode chip, namely:
3. Front-end circuit
Due to statistical nature of X-rays the signals appear in the strips of the detector, and so in the electronic channels, completely randomly in time. This feature requires using a continuous time comparator for discrimination on the signal amplitude and excludes possibility of applying an auto-zero-technique. Since we have decided to use a common threshold applied to all 64 channels in the chip special attention has been paid to minimise channel-to-channel variation of gain and offset. At this point one should note that another possible solution of the problem by implementing individual offset correction in every channel has been tried successfully in another design [5]. In order to reduce the channel-to-channel offset spread we have implemented AC coupling between the preamplifier and the shaping amplifier as well as in front of the discriminator. Furthermore, the circuit following the shaping amplifier is designed in fully differential mode. The differential pair in front of the discriminator has a gain close to 1 and its main function is to generate a differential threshold for the comparator. Increasing area of devices is always a good option for better matching but it is contradictory to the requirements of high speed and small die area. In our design the requirement concerning the speed of the comparator is rather relaxed because the counting rate of the overall channel is limited by the pulse duration time in the shaping amplifier, which is in the range of microseconds. Therefore we can use rather large devices in the matching sensitive circuits. The differential sections in the discriminator have been laid out in the common centroid geometry, with symmetrical surrounding and no metal layer overlaps. Provided the gain in the preamplifier and the shaper stage is high enough the chosen solution allows us to keep the rms value of the channel-to-channel offset spread much lower than the rms value of noise at the input of the comparator. The gain of the preamplifier and the shaper is determined by the components of the feedback loop circuits (see Fig. 2). The capacitors Cfed and Cfedsh of value 200 and 100 fF respectively are realised as poly–poly capacitors following the layout rules recommended for precision capacitors [6]. The tuneable feedback resistors Rfed and Rfedsh of the order of tens of megaohms are realised as long PMOS transistors working in the linear region. The dimensions of these feedback transistor are W =L ¼ 2=384 lm for the preamplifier and W =L ¼ 2=84 lm for the shaper and their gate-source bias voltages are controlled by the internal DACs implemented
The circuitry responsible for extracting and processing the signals from silicon strip detectors is called the front-end electronics. The block diagram of the frontend channel of the RX64 chip is shown in Fig. 2. The channel is built of three basic circuits: a charge sensitive preamplifier, a shaper and a discriminator. Current pulses induced in strips of the detector are integrated in the preamplifiers and shaped in the second stage shaping amplifiers. The shaping amplifier plays the role of a band pass filter, which has two functions: shaping short pulses and optimisation of signal to noise ratio by proper limitation the band pass. Then the pulses above the threshold level fire the discriminator, which in response produces digital pulses. For such a system we define the charge gain as ratio of the signal amplitude at the output of the shaping amplifier to the total input charge generated in the detector. For direct comparison of the signal level and the noise at the input of the preamplifier the noise performance of the system is described by the equivalent noise charge (ENC). The ENC is defined as the charge injected to the input of the preamplifier in the form of a d-like current pulse, which gives at the output of the shaper a signal of amplitude equal to the rms value of noise. The front-end circuit in the RX64 IC is based on the previous design RX32N [4] being prototyped as a 32channel version comprising only analogue circuitry. The ENC measured for the RX32N chip at room temperature for a detector capacitance of 2.5 pF and signal integration time 0.7 ls was 155 e rms. The power consumption was 2.5 mW per channel. In the present design we have increased the number of front-end channels up to 64. A main challenge from the point of view of the front-end design was to integrate the coun-
Fig. 2. Block diagram of single front-end channel.
• gain and offset matching for all channels, • immunity to digital noise.
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in the chip. Using such large transistors in parallel with small capacitors in the feedback circuits requires proper simulation of the circuit. In order to evaluate correctly the effect of distributed channel-to-well capacitance of such long PMOS transistors in simulation we have split the long transistors for a series of N, up to 6, shorter transistors. Although in an n-well process matching performance of PMOS transistors is usually worse than of NMOS ones [7], we have used PMOS devices as the feedback resistors for their lower 1/f noise [8], larger small signal drain-source resistance and higher immunity to switching noise [9,10]. In addition to the core part of the front-end block comprising 64 channels (see Fig. 1), two additional dummy channels have been added on each side of the chip in order to guarantee good matching for the active channel 0 and 63 at each edge of the chip. Distribution of the power supplies and reference signals is another important issue for matching in multi-channel systems. Voltage drops along the power supply busses and reference signal lines can be devastating for channelto-channel matching of critical analogue parameters. Distribution of the power supplies is discussed in detail in Section 5. The analogue part of the chip may work satisfactorily when fabricated as a separate die, however, some decrease of analogue performance is usually observed when digital blocks are added [2]. The substrate of the technology used is composed of epitaxial layer grown on heavily doped bulk substrate. Low resistivity substrate is a very good conductor for distribution of substrate noise and isolation techniques by guard rings are not so effective as for a lightly doped substrate [3]. A remedy for the problem could be fully differential front-end with sufficiently high CMRR and good PSRR, however, in our case the driving requirement of low noise prohibits such a solution in the input stage of the front-end channel. The preamplifier and the shaper have been designed as a single ended stages using folded cascode configuration. Obviously, the most sensitive component is the input transistor. In order to reduce possible injection of substrate noise to the input of the preamplifier a PMOS transistor is used as an active device in the input stage. With this configuration the n-well can be used as a shield from the substrate. In order to ensure effective functioning of such shield rings of contacts are placed around the transistors and the contacts are tied to the analogue high power supply voltage VDDA. The load current sources have been made as NMOS transistors referred to the substrate potential VSSA. Each group of the NMOS transistors is surrounded by a local guard ring tied to the VSSA. Special attention has been paid to proper contacting the substrate which is a critical issue for mixed-mode systems on an epitaxial layer. The goal is to keep the substrate near the sensitive analogue part quiet even in expense of larger chip area due to
additional substrate contacts and wide power supply lines. The immunity of the discriminator to digital noise is increased by implementing a fully differential architecture of the comparator and by careful design for matching. On the other side, the comparator itself is a source of switching noise placed in immediate vicinity of the sensitive single ended analogue stages. Due to large transistors used, the comparator has relatively slow transient response which limits to some degree generation of the switching noise while the implemented hysteresis prevents multiple response of the comparator to noisy input signals. The first stage of the discriminator, which converts the single ended signal into a differential one, is powered from the same power lines as the preamplifier and the shaper while the comparator with hysteresis has separate power supply lines VDDD and VSSD connected via dedicated bond pads.
4. Data storage and back-end circuit 4.1. Counters Considering possible options for data storage one has to keep in mind that due to statistical nature of X-ray sources the digital signals at the discriminator outputs appear completely randomly in time. An obvious solution is to use asynchronous counters to count the incoming pulses and that is the technique commonly used for radiation measurements in nuclear physics. In most imaging applications one has to deal with a large range of radiation intensity in various detector elements. In order to reduce the effect of statistical fluctuation on the image quality it is necessary to collect a certain minimum number of counts in the areas of low intensity, while at the same time the number of counts in the areas of high intensity can be higher by several orders of magnitude. The counter capacity in the RX64 chip has been specified as 20 bits, which allows measuring images with a large dynamic range. The counters are connected to the outputs of the front-end channels via Schmitt triggers which provide regeneration of relatively slow signals from the discriminators and help for rejection of noisy signals. The counters in the RX64 chip are based on the concept of a pseudo-random shift register [11,12]. A 20bit shift register is configured with a single XOR gate to generate a pseudo-random state sequence. As each state in such a scheme corresponds to a unique number of clock pulses that circuit can be used as a counter. The schematic of the counter structure is shown in Fig. 3. The 17th and the 20th bit of the shift register are XOR-ed and fed back to the register input, so that the period of the pseudo-random sequence is 220 –1.
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Fig. 3. Block diagram of the group of eight counters.
Such a concept of the counter circuit has two advantages which are particularly attractive for our multichannel chip, namely simplicity and small area. In the RX64 chip the counting shift register has been designed using semi-dynamic logic which allowed us to achieve a very compact layout. For comparison, in the earlier prototype the counter block has been implemented as a separate chip [13]. The very standard counter structure based on T flip–flops was used resulting in 30 transistors per bit while in the present structure implemented in the RX64 chip we need only eight transistors per bit. Required counting period depends on the intensity of the measured X-rays and must be programmable. The operation of the counters is controlled by four signals: Gate, ClkEx, A/R and Dest/NonDest. The Gate signal is used to open or close the inputs of the counters. When the counter inputs are closed it is possible to set the counters to the readout mode by setting ‘‘1’’ on the A/R (Accumulation/Read) line. There are two possible modes of the readout operation, which are controlled by the Dest/NonDest signal. In the destructive mode, after reading out the content of the counter, all bits in the shift register are set to ‘‘1’’, while in the non-destructive mode the configuration of bits in the shift register remains unchanged. The readout of the counters is performed synchronously with rate determined by the clock signal ClkEx which is applied externally. The ClkEx signal can be also used for test purposes by setting the chip in the accumulation mode. In this mode the external clock signal is routed to the counter inputs. Using this configuration one can perform functionality tests of the counters and the readout controller as well as evaluate the speed performance of the circuit. A drawback of the scheme based on the pseudorandom shift register is that in order to read out the content of the register one has to stop collecting the data. In a continuously running experiment this will generate so-called dead time, which is a fraction of time over which the data from the detector will be lost. In
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order to minimise the dead time 64 counters are grouped in eight blocks of eight counters each and the data from each block are read out via a separate link. In order to send the data off the chip the eight 20-bit shift registers are configured into a single 160-bit long shift register. The nominal readout clock frequency has been specified to be at least 10 MHz. This number ensures that for all foreseen measurement configurations the dead time introduced by the readout will be negligible. The RX64 chip has eight tristate data outputs which allow to connect several RX64 chips to a common external data bus and read them out sequentially. During the period of data taking the outputs of the chips are set to the high impedance state so that other chips can send the data to the external bus at the same time. While sending the data, the chip issues the clock signal which can be used to synchronise the data in the external data receiver. 4.2. Control logic In order to minimise the number of external control signals to be delivered to the chip we have implemented a control block which functions as a command decoder. The control block receives the commands from an external controller (typically a PC I/O card) via a serial link, decodes them, and generates the control signals to the other blocks in the chip. The list of commands is shown in Table 1. In addition to the commands used to control the readout of the counters there are three other commands implemented: CounterPulse, CalibrationPulse and LoadDac. These commands, in addition to normal operation, can be used for test purposes and allow to test the digital part of the chip, starting from the counter inputs. In the response to the CounterPulse command a single pulse is send to all counters simultaneously through the ClkEx line. Another command, which has been implemented for test purpose, is the CalibrationPulse. In response to this command a trigger pulse is send to the internal calibration circuit implemented in the front-end block. Then a current pulse, which simulates the detector signal, is injected into the preamplifier Table 1 List of commands Command code
Action
000 001 010 011 100 101 110 111
OpenGate CloseGate ReadoutDestructive ReadoutNonDestructive CalibrationPulse CounterPulse LoadDac Unused code
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input. This feature allows testing the overall functionality including the analogue and the digital part as well as performing detail measurements of the analogue parameters. The front-end block contains four different DACs which are used for setting the bias currents, the amplitude of the calibration signal and the threshold level in the discriminator. The command LoadDac contains, in addition to the command code, 10 bits which define the address of the DAC and the value to be loaded. 4.3. I/O circuits In order to minimise injection of parasitic digital signals to the substrate we have assumed that incoming digital clock and command signals must be differential ones following to the LVDS standard [14]. The input buffers which can receive correctly the LVDS signals have been implemented in the chip. On the other hand, 8-bit data output bus is designed in standard tristate single ended configuration while each chip has 2-bit address set during bonding procedure. A primary reason for that solution is to allow connecting outputs of up to four chips to a common external bus. This configuration allows one to transmit the data to a computer via a single 8-bit bus from up to four chips, i.e. up to 256 channels. As the time required for transmitting the data off the chip is usually negligible compared to the time of data collecting, it is assumed that during reading out the data the input gates will be closed. In this way we avoid a potential problem of analogue signals in the front-end being deteriorated by injection of parasitic signals from single-ended digital outputs.
5. Layout design The RX64 IC has been designed for the 0.8 lm CMOS technology process by AMS. As the chip contains analogue and digital circuits placed on common epi-type substrate, particular attention has been paid to the layout. A photograph of the chip with the major blocks marked is shown in Fig. 4. The total area of the die is 2800 6500 lm2 with a major part occupied by the analogue front-end circuits. The counters and the control block occupy only an area about 770 5400 lm2 . The floor plan of the chip is driven by the layout of the front-end channels which have to match the strip pitch of silicon sensors. This particular floor plan imposes some constraints on the layout of power and ground paths. For all critical paths the extracted resistances of the power supply paths have been taken into account in the simulation. The RX64 chip requires two single-ended supply voltages: 3.0 V for the analogue part and 4.0 V for the digital part. The average current
Fig. 4. Photograph of the RX64 IC.
consumption per chip is 45 mA for the analogue and 5 mA for the digital power supply. These numbers result in an average power consumption of 2.5 mW per channel, which is quite low given the functionality and complexity of the design. Due to matching concerns discussed earlier special attention has been paid to minimise channel-to-channel variation of the power supply voltages. The analogue power supply lines VDDA and VSSA run across all channels and are nearly 6500 lm long and 250 lm wide. The lines are connected via triple bonding pads placed symmetrically on each sides of the chip. These lines have been drawn using the metal 2 layer that has nearly twice lower resistance than the metal 1 layer. In order to avoid metal over the matched components (components of the feedback loops, differential pairs) and fit such wide lines close to the single ended stages we have added extra area inside the frontend channels. These regions are filled with substrate or well contacts tied to appropriate lines. The digital power supply lines are only 80 lm wide, however, they are stacked of the metal 1 and metal 2 layers with double bonding pads. In additions to local guard rings surrounding PMOS and NMOS devices in the preamplifier and the shaper as described in Section 3, there are two sets of global guard rings. One set of guard rings surrounds the whole analogue part while the second one encloses the whole digital part of the circuit. Guard rings for the analogue and the digital block have separate bonding pads. Different part of RX64 has been designed using different techniques. The analogue part of the chip has been designed using full custom techniques, following the layout rules for good matching [15]. Full custom technique was also used for design of the counter block, with a main goal to minimise the area of this block. The SPICE simulations have been performed on the transistor level and the layout has been optimised manually. After layout extraction SPICE simulations have been repeated again using the extracted netlist, including the parasitics. In order to cover variation of the process parameters we have requested that the circuit should pass the simulation for the nominal parameters at a
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frequency by a factor 2.5 higher compared to the nominal, i.e. at 25 MHz. Given a very regular structure of the counter block this approach has appeared to be very effective since the area of this block has been reduced by a factor of 2 compared to what could be achieved using the standard cells and automatic place and route technique. The control block, on the other hand, has a rather complicated logical structure while the total area of this block is small. Therefore, the only effective way to design such block is to generate the schematic from the behavioural description and then use the standard cell place and route technique to generate the layout. The functional code for the control block has been written in the Verilog HDL language and then the schematic and the layout of the circuit have been generated automatically by the special parameterised procedures. Functional analysis of this block has been performed using Verilog simulation. The timing performance has been ensured by proper parameterisation of the standard cell delays.
6. Tests and results 6.1. Testability features The functionality and complexity of the RX64 design require that advanced testability functions are implemented on the chip. Given the architecture of the chip some aspects related to testability are very specific for this design. First, for full evaluation of analogue performance we require detail measurements of analogue parameters for each of the 64 channels in the chip. These measurements allow one to determine whether channelto-channel matching performance is satisfactory. In principle, the input pads are not available to supply the input signals for such measurements as the naked chips are mounted of a PCB and the input pads are bonded directly to the strips of silicon sensors. Furthermore, the preamplifier is sensitive to the total charge injected to the input so this charge must be controlled very well. Any connection to the input pads by a probe card would introduce significant stray capacitance so it would be very difficult, or even impossible, to control the amount of charge injected to the input. Therefore we have implemented in the chip an internal calibration circuit which can generate precise charge pulses at the preamplifier inputs. Another issue very specific for the RX64 design is due to the fact the outputs from the analogue front-end channels are not accessible directly at all. The analogue parameters can be, however, extracted from multiple scans of the discriminator thresholds for various input charges. Using the internal DAC which controls the discriminator threshold and the internal
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calibration circuit we can perform these tests automatically. A standard procedure for testing analogue circuits with architecture as implemented in the RX64 design is to send a series of calibration pulses of a given amplitude to the test input and to count the pulses at the output of the comparator. By scanning the comparator threshold and repeating this test for various amplitudes of the calibration signal we can extract the gain and noise of the analogue part of the front-end circuit as well as the offset of the comparator for each channel (see Section 6.3). A significant improvement in the testing procedures has been achieved by implementing two DACs, one to control the amplitude of the internal calibration signals (in the range from 1 to 30 mV), and second to control the threshold of the comparator. Both of these DACs are set through the control block. It is worth to note that we can measure precisely the analogue parameters of the front-end circuit while sending to the chip only digital command signals and receiving from the chip digital data. This aspect becomes very important if one remembers that we need analogue calibration signals of amplitudes in the range of few millivolts and bringing such low signals to the chip working in digital environment is not an easy task. Thus, all we need to test fully the chip is a PC I/O card which generates the clock signal and command sequences, and receives the data. As typically the I/O cards generate the TTL signals, a TTL to LVDS signal translator needs to be implemented in the test set-up. At this point it is also worth to note that the internal calibration circuit allows one to repeat analogue measurements for the chips assembled into multi-chip modules together with silicon strip detectors using the same readout system as used for normal data taking in an experiment.
6.2. Basic functionality tests A first basic test, called as Readout Test, which checks the functionality of the digital part of the chip, is a sequence of two commands: ReadoutNonDestructive and ReadoutDestructive. The result of this test is a random pattern of the counter content as set after powering the chip as no power-up reset is implemented in the design. Response to the two above commands sent sequentially should be identical. Next step is to repeat the ReadoutDestructive command and in response we should receive now all zero values. The next test, which allows one to verify the functionality of the counters, is the Counting Test. In this test the command CounterPulse is sent and the contents of the counters are checked each time using the ReadoutNonDestructive command. The RX64 prototype has passed both, the Readout Test and the Counting Test, successfully.
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An important function of the control block is loading the DACs. For all DACs the analogue output values can be measured on the dedicated probe pads. Thus, in the same test we can verify the functionality of that part of the control block which is responsible for DAC loading and check the interface circuit between the control block and the DACs. All this circuitry works correctly and the response characteristics of each DAC can be measured. While the absolute accuracy and linearity of the DACs which set the bias currents in the front-end circuits are not critical at all, the DACs which set the amplitude of the calibration pulse and the threshold of the discriminator need to be measured precisely as they determine accuracy of analogue measurements. 6.3. Full analogue measurements Full functionality of the chip is verified when measuring analogue parameters. In addition to the functions and circuits discussed before, the calibration circuit and the command CalibrationPulse are exercised in these measurements. In response to the CalibrationPulse command the control block issues a pulse which triggers a chopper circuit in the calibration block. As the result, a voltage step of amplitude Vcal , defined by setting of the calibration DAC, is sent to the inputs of the front-end channels via test capacitors Ct (see Fig. 2). Current pulses carrying charges equal to Qinj ¼ Vcal Ct are injected to the preamplifiers connected to given calibration line. Combining this procedure with the scan of the comparator threshold allows one to measure analogue parameters. Typical results of the threshold scan are shown in Fig. 5a. The plot shows the total number of counts as a function of the comparator threshold measured for five different values of the input charges injected to the preamplifier. The rapid increase of the number of counts below 50 mV in Fig. 5 is due to the noise pulses. If the distribution of noise amplitudes is Gaussian the mea-
sured number of counts vs. threshold is described by the error function. By differentiating the measured error function one obtains a Gaussian distribution of signal amplitudes at the discriminator input as shown in Fig. 5b. The centre of each distribution corresponds to the amplitude of the signal at the discriminator input (i.e. output of the shaping amplifier) and the standard deviation of these distribution is equal to the rms value of noise at the discriminator input. Plotting the centres of the distributions as a function of the input charges one obtains the response curve of the analogue linear part of the circuit, up to the input of the discriminator for each channel. From these response curves one can extract the gain of the linear part of the circuit and the discriminator offset for each channel. The accuracy of measurements of the amplifier gain and the discriminator offset using the internal calibration circuit and the method described above depends on the precision of the calibration circuit, i.e. the value of the test capacitor in given channel and the accuracy of the calibration DAC. The actual values of the test capacitors and the response characteristics of the calibration DAC can be measured, however, measurements of the small test capacitors of the nominal value equal to 75 fF on naked chips are rather time consuming and require additional hardware. Therefore, we use physical signals generated by X-rays in a silicon strip detector read out by the RX64 IC for cross calibration of the internal calibration circuit. 6.4. Matching measurements As discussed earlier in the paper, a very critical issue for the RX64 IC is the channel-to-channel matching of the analogue parameters. The measurements of the gain matching using the internal calibration circuit may depend on matching of relatively small test capacitor Ct ¼ 75 fF placed at the input of each front-end channel (see Fig. 2). In order to eliminate this uncertainty on the
Fig. 5. Results of threshold scans for five different input charges: (a) integral distributions and (b) amplitude distributions obtained by differentiating integral distributions.
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amount of injected charge we have measured the matching performance employing physical signals from a silicon strip detector. By combining a radioactive source and fluorescence radiation from an iron foil we have obtained an X-ray source with four distinct energy lines: 6.4, 13.6, 17.2 and 20.1 keV. For this energy range the average energy needed for generation of one electron-hole pair in silicon is equal to 3.65 eV [16] so we obtain four distinct charge signals: 1753, 3726, 4712 and 5506 e . Of course, generation of free charge carriers by X-rays in silicon is a statistical process and the above numbers are the averages of statistical distributions. The standard deviation of such a distribution with average p charge Q is given as F Q, where F is the so-called Fano factor equal to 0.15 for the considered energy range [16]. For our measurements it is important to note that the statistical spread of the charge generated in the silicon strip detector for each of the four X-ray energy lines is much lower compared to the equivalent input noise charge of the front-end electronics, which is typically about 150 e rms. Employing the method based on scanning the discriminator threshold for measuring the distribution of signal amplitudes at the discriminator inputs we can obtain distribution of critical analogue parameters, offset, gain and ENC, for 64 channels in one chip. All three parameters are obtained now from a single threshold scan as the four input charge signals are generated in the silicon strip detectors randomly all the time. Typical distributions these parameters measured for one RX64 IC are shown in Fig. 6. The spread of the discriminator offset is equal to 2.2 mV rms and, when referred to the input, is equal to 28 e rms. This number is negligible compared to the
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equivalent input noise of 167 e rms measured for this particular set of an RX64 IC and a silicon strip detector. The spread of gain is small, about 0.5% on one sigma level. This is important as the effective threshold of the discriminator in terms of X-ray energy or input charge to be discriminated depends on the offset of the discriminator itself and on the gain of the amplifier. The contribution from the gain spread to the effective threshold spread is about 2.3 mV rms for the X-ray energy of 20 keV, which the upper limit of the range foreseen in various applications. Thus, in the worst case p the spread of the effective threshold will be 2 28 e rms, and it is still negligible compared to the ENC. For the ENC itself we observe quite good uniformity across the chip.
7. Conclusions A fully integrated multi-channel chip for readout of signals from silicon strip detectors has been designed and manufactured in the AMS 0.8 lm CMOS technology. The two blocks, analogue and digital, which had been prototyped separately before, have been integrated successfully in a single mixed-mode IC. The most significant advantages of this integration are: • functionality and bias conditions of the analogue circuits is now controlled by digital commands via a simple serial link, which simplifies the design and operation of modules comprising several RX64 ICs, • possibility of implementing internal calibration circuit which is controlled digitally and allows for complete analogue testing of the front end,
Fig. 6. Distributions of analogue parameters in 64 channels of one RX64 IC: (a) discriminator offset, (b) gain and (c) equivalent noise charge.
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• with increased functionality average area per channel is reduced by about 20% compared to the two chip options, • assembly of modules comprising silicon strip detectors and RX64 ICs is simplified and mechanical robustness of such modules is improved. In the RX64 design we have demonstrated that possible drawbacks of integration of very sensitive analogue circuits and digital blocks in a single IC can be successfully omitted by proper design. The prototype chip has been tested and proved to be fully functional. The measurements of analogue parameters for all 64 channels in the RX64 IC demonstrate good matching performance and confirm that analogue parameters have not been compromised by integration with digital circuitry on common silicon substrate.
[5]
[6] [7]
[8]
[9]
[10]
References [11] [1] Pelgrom M, Vertreget M. CMOS technology for mixed signal ICs. Solid-State Electron 1997;41(7):967–74. [2] Blalack T. Design techniques to reduce substrate noise. In: Huijsing J, van de Plassche R, Sansen W, editors. Analog circuit design Volt electronics; mixed-mode systems; lownoise and RF power amplifiers for telecommunication. Boston: Kluwer Academic Publishers; 1999. [3] Su D, Loinaz M, Masui S, Wooley B. Experimental results and modeling techniques for substrate noise in mixedsignal integrated circuits. IEEE J Solid-State Circuits 1993;28(4):420–30. [4] Grybos P, Daz browski W. Development of fully integrated readout system for high count rate position sensitive
[12] [13]
[14]
[15] [16]
measurements of X-rays using silicon strip detectors. IEEE Trans Nucl Sci 2001;48(3):466–72. Dabrowski W et al. Progress in development of the readout chip for the ATLAS semiconductor tracker, CERN/LHC/2000-041, Proceedings from Sixth Workshop on Electronics for LHC Experiments, Cracow, Poland, 2000. Johns M, Martin K. Analog integrated circuit design. New York: John Wiley and Sons; 1997. Pelgrom M, Duinmaijer A, Welbers A. Matching properties of MOS transistors. IEEE J Solid-State Circuits 1989;24(5):1433–40. Bertails J. Low-frequency noise consideration for MOS amplifier design. IEEE J Solid-State Circuits 1979;14(4): 773–6. Nauta B, Hoogzaad G. Substrate bounce in mixed-mode. In: Huijsing J, van de Plassche R, Sansen W, editors. Analog circuit design Volt electronics; mixed-mode systems; low-noise and RF power amplifiers for telecommunication. Boston: Kluwer Academic Publishers; 1999. Razavi B. Design of analog CMOS integrated circuits. New York: McGraw-Hill; 2001. Horowitz P, Hill W. The art of electronics. New York: Cambridge University Press; 1993. Fisher P et al. A counting pixel readout chip for imaging applications. Nucl Instr and Meth A 1998;405:53–9. Grybos P et al. Characterisation of silicon strip detectors with a binary readout chip for imaging. Nucl Instr and Meth A 2000;454:214–20. IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), IEEE Std 1596.3-1996. Laker K, Sansen W. Design of analog integrated circuits and systems. New York: McGraw-Hill; 1994. Owens A et al. The X-ray energy response of silicon (B): measurements. Nucl Instr and Meth A 1998;382:53–9.
Multichannel mixed-mode IC for digital readout of silicon strip detectors wientek a, P. Grybos a,*, W. Daz browski a,*, P. Hottowy a, R. Szczygieł b, K. S P. Wiaz cek a a
Faculty of Physics and Nuclear Techniques, University of Mining and Metallurgy, al. Mickiewicza 30, 30-059 Krak ow, Poland b Institute of Nuclear Physics, ul. Kawiory 26A, 30-065 Krak ow, Poland Received 26 October 2001; received in revised form 26 November 2001
Abstract The design of a mixed mode 64-channel ASIC for digital readout of silicon strip detectors used in X-ray imaging applications is presented. The design is implemented in a 0.8 lm CMOS n-well epi-type substrate technology. The single channel consists of a charge sensitive preamplifier, a shaping amplifier, a discriminator and a pseudo-random 20-bit counter. In addition to the 64-channel core which is responsible for signal processing and data storage, the IC comprises additional blocks like an internal calibration circuit, internal DACs and a command decoder which governs communication of the IC with the external world. Those blocks have been designed keeping in mind testability features and using the chips for building multi-chip modules. The equivalent input noise charge measured at room temperature for a detector capacitance of 2.5 pF and signal integration time of 0.7 ls is 167 e rms. The average power dissipation is 2.5 mW/channel. The channel-to-channel offset spread referred to the input is only 28 e rms, while the standard deviation of gain spread is 0.5% of the mean value. The chip occupies area of 2:8 6:5 mm2 . 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction Semiconductor position sensitive detectors working in the single photon counting mode are widely used for X-ray imaging in physics, biology and medicine. An advantage of single photon counting detectors is essentially an infinite dynamic range contrary to integrationtype detectors, which usually have problems with a limited dynamic range and so a low contrast of the image. Among various types of position sensitive detectors the most commonly used are silicon detectors built as matrixes of reverse biased diodes on common highresistivity substrate. The sensitive area can be easily divided into individual diodes of the shapes as required by the experiment. For direct detection of X-rays of energy
* Corresponding authors. Tel.: +48-12-617-2959; fax: +4812-634-0010. E-mail addresses: [email protected] (P. Grybos), [email protected] (W. Daz browski).
in the range up to 20 keV, a high resistivity substrate is needed in order to obtain sufficiently thick depletion regions at relatively low bias voltages, of few tens of volts. A photon absorbed in the depletion region generates charge which then is collected within 10–30 ns depending on the actual position at which the photon is absorbed and on the detector bias. The charge moving in the depletion region induces short current pulses in the electrodes which are connected to the front-end electronics. In order use such detectors effectively in digital imaging each sensitive element (diode) has to be served by an individual electronic readout channel. The developed ASIC is dedicated for applications in X-ray diffractometry where the interesting energy of Xrays is limited to a range from about 5–20 keV. There are diffraction techniques widely used for which onedimensional position sensitive detection systems are sufficient. For such applications silicon microstrip detectors with a strip pitch of 100 lm suit very well. There are basically two possible schemes for readout of silicon strip detectors: analogue and binary. In the analogue
0026-2714/02/$ - see front matter 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 2 6 0 - 8
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scheme one measures the amplitudes of the signals and calculates the centre of gravity of the signal cluster. This method allows one to improve the accuracy of position measurement, especially for small strip pitch where significant fraction of events results in charge being shared between neighbouring strips. It requires, however, either an ADC connected to each channel of the front-end electronics or multiplexing signals from some number of channels into a single ADC. In the first case one faces limitations due to complexity of the system and power consumption. The second solution results in limitations on the maximum rate of X-rays which can be measured. Preserving analogue information gives more flexibility for off-line data processing. In particular, since in many cases digital noise and external interference result in common mode noise in multi-channel systems one can think of measuring and subtracting this noise in the offline analysis. In the binary scheme each channel of the front-end electronics is equipped with an amplitude discriminator which generates 1-bit information in response to each signal above given threshold. Binary information can be easily stored on the IC separately for each channel, which allows to cope with high rates of X-rays as each channel works independently. The binary scheme requires, however, a good signal-to-noise ratio in order to keep sufficient separation between the noise and the signal level. In addition, it requires very good uniformity of analogue parameters (gain, offset and noise) in multichannel ICs, and immunity to digital noise and external interference. The second aspect is of particular importance as due to very small signals from silicon strip detectors the circuit has to be optimised to reduce the intrinsic noise sources to possible minimum and the digital noise has to be kept much below the intrinsic noise in order to make the IC useful for real applications. In this paper we present the RX64 IC which is dedicated for readout of silicon strip detectors in X-ray diffractometers. The IC comprises 64 front-end channels following the concept of binary architecture and digital circuitry required for controlling operation of the chip and for communication with an external data acquisition system. The chip has been designed and fabricated in a standard CMOS 0.8 lm n-well technology, which from the point of view of analogue design is quite adequate for such an application [1]. The system comprising up to 128 readout channels is expected work without cooling which puts a strong constraint on the maximum power dissipation in a single channel. In order to make a multi-channel system practical for use one requires that a common discriminator threshold is applied to all channels. Therefore low noise performance with good matching of the gain and offset for all channels in the multi-channel chip is an absolutely critical issue for such systems. These requirements are contradictory to small
silicon area and high speed requirements. In order to improve functionality and reliability of the detector modules using RX64 chips it is required that low noise high performance analogue circuits and digital blocks are integrated in a single die. The design follows well known general rules for mixed-mode designs, like: quieting digital blocks, lowering sensitivity of analogue circuits to switching noise and implementing proper for given technology isolation techniques [2,3]. In the following sections we present an overview of the IC architecture, some aspects of optimisation of the front-end circuit for low power, low noise and matching, design of digital blocks, layout techniques, testability features and some test results.
2. Design overview The block diagram of the complete RX64 IC is shown in Fig. 1. The chip comprises five basic blocks: 64 analogue front-end channels, 64 counters, input–output block, control block, calibration circuit and bias generators. Each channel of the analogue front-end electronics is equipped with a comparator providing discrimination of the analogue signal at a given level. Due to statistical nature of X-rays the signals at the output of the discriminator appear completely randomly in time and are stored in 20-bit asynchronous counters. The counters are grouped in the blocks of eight channels each and the data from each block are read out via 8-bit bus with tristate outputs. In a single chip we have integrated 64 channels which can simultaneously process signals and store data from 64 sensor elements of a silicon strip detector. Such architecture provides fully parallel signal processing, including data storage from all strips. It is suitable for high counting rate applications since the amount of data to be handled is minimised already in the front-end part. In addition to the basic functions which control the data storage and readout, the control block provides settings
Fig. 1. Block diagram of RX64 IC.
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of the DACs which are used in the front-end block for biasing the analogue circuits and controlling the internal calibration circuit. The control block receives the commands via an external serial link, decodes them and executes by sending the control signals and data to other blocks.
ters and all digital control logic on the same die without compromising analogue performance. Thus, we have focused on two problems, which are absolutely critical in such a multi-channel mixed-mode chip, namely:
3. Front-end circuit
Due to statistical nature of X-rays the signals appear in the strips of the detector, and so in the electronic channels, completely randomly in time. This feature requires using a continuous time comparator for discrimination on the signal amplitude and excludes possibility of applying an auto-zero-technique. Since we have decided to use a common threshold applied to all 64 channels in the chip special attention has been paid to minimise channel-to-channel variation of gain and offset. At this point one should note that another possible solution of the problem by implementing individual offset correction in every channel has been tried successfully in another design [5]. In order to reduce the channel-to-channel offset spread we have implemented AC coupling between the preamplifier and the shaping amplifier as well as in front of the discriminator. Furthermore, the circuit following the shaping amplifier is designed in fully differential mode. The differential pair in front of the discriminator has a gain close to 1 and its main function is to generate a differential threshold for the comparator. Increasing area of devices is always a good option for better matching but it is contradictory to the requirements of high speed and small die area. In our design the requirement concerning the speed of the comparator is rather relaxed because the counting rate of the overall channel is limited by the pulse duration time in the shaping amplifier, which is in the range of microseconds. Therefore we can use rather large devices in the matching sensitive circuits. The differential sections in the discriminator have been laid out in the common centroid geometry, with symmetrical surrounding and no metal layer overlaps. Provided the gain in the preamplifier and the shaper stage is high enough the chosen solution allows us to keep the rms value of the channel-to-channel offset spread much lower than the rms value of noise at the input of the comparator. The gain of the preamplifier and the shaper is determined by the components of the feedback loop circuits (see Fig. 2). The capacitors Cfed and Cfedsh of value 200 and 100 fF respectively are realised as poly–poly capacitors following the layout rules recommended for precision capacitors [6]. The tuneable feedback resistors Rfed and Rfedsh of the order of tens of megaohms are realised as long PMOS transistors working in the linear region. The dimensions of these feedback transistor are W =L ¼ 2=384 lm for the preamplifier and W =L ¼ 2=84 lm for the shaper and their gate-source bias voltages are controlled by the internal DACs implemented
The circuitry responsible for extracting and processing the signals from silicon strip detectors is called the front-end electronics. The block diagram of the frontend channel of the RX64 chip is shown in Fig. 2. The channel is built of three basic circuits: a charge sensitive preamplifier, a shaper and a discriminator. Current pulses induced in strips of the detector are integrated in the preamplifiers and shaped in the second stage shaping amplifiers. The shaping amplifier plays the role of a band pass filter, which has two functions: shaping short pulses and optimisation of signal to noise ratio by proper limitation the band pass. Then the pulses above the threshold level fire the discriminator, which in response produces digital pulses. For such a system we define the charge gain as ratio of the signal amplitude at the output of the shaping amplifier to the total input charge generated in the detector. For direct comparison of the signal level and the noise at the input of the preamplifier the noise performance of the system is described by the equivalent noise charge (ENC). The ENC is defined as the charge injected to the input of the preamplifier in the form of a d-like current pulse, which gives at the output of the shaper a signal of amplitude equal to the rms value of noise. The front-end circuit in the RX64 IC is based on the previous design RX32N [4] being prototyped as a 32channel version comprising only analogue circuitry. The ENC measured for the RX32N chip at room temperature for a detector capacitance of 2.5 pF and signal integration time 0.7 ls was 155 e rms. The power consumption was 2.5 mW per channel. In the present design we have increased the number of front-end channels up to 64. A main challenge from the point of view of the front-end design was to integrate the coun-
Fig. 2. Block diagram of single front-end channel.
• gain and offset matching for all channels, • immunity to digital noise.
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in the chip. Using such large transistors in parallel with small capacitors in the feedback circuits requires proper simulation of the circuit. In order to evaluate correctly the effect of distributed channel-to-well capacitance of such long PMOS transistors in simulation we have split the long transistors for a series of N, up to 6, shorter transistors. Although in an n-well process matching performance of PMOS transistors is usually worse than of NMOS ones [7], we have used PMOS devices as the feedback resistors for their lower 1/f noise [8], larger small signal drain-source resistance and higher immunity to switching noise [9,10]. In addition to the core part of the front-end block comprising 64 channels (see Fig. 1), two additional dummy channels have been added on each side of the chip in order to guarantee good matching for the active channel 0 and 63 at each edge of the chip. Distribution of the power supplies and reference signals is another important issue for matching in multi-channel systems. Voltage drops along the power supply busses and reference signal lines can be devastating for channelto-channel matching of critical analogue parameters. Distribution of the power supplies is discussed in detail in Section 5. The analogue part of the chip may work satisfactorily when fabricated as a separate die, however, some decrease of analogue performance is usually observed when digital blocks are added [2]. The substrate of the technology used is composed of epitaxial layer grown on heavily doped bulk substrate. Low resistivity substrate is a very good conductor for distribution of substrate noise and isolation techniques by guard rings are not so effective as for a lightly doped substrate [3]. A remedy for the problem could be fully differential front-end with sufficiently high CMRR and good PSRR, however, in our case the driving requirement of low noise prohibits such a solution in the input stage of the front-end channel. The preamplifier and the shaper have been designed as a single ended stages using folded cascode configuration. Obviously, the most sensitive component is the input transistor. In order to reduce possible injection of substrate noise to the input of the preamplifier a PMOS transistor is used as an active device in the input stage. With this configuration the n-well can be used as a shield from the substrate. In order to ensure effective functioning of such shield rings of contacts are placed around the transistors and the contacts are tied to the analogue high power supply voltage VDDA. The load current sources have been made as NMOS transistors referred to the substrate potential VSSA. Each group of the NMOS transistors is surrounded by a local guard ring tied to the VSSA. Special attention has been paid to proper contacting the substrate which is a critical issue for mixed-mode systems on an epitaxial layer. The goal is to keep the substrate near the sensitive analogue part quiet even in expense of larger chip area due to
additional substrate contacts and wide power supply lines. The immunity of the discriminator to digital noise is increased by implementing a fully differential architecture of the comparator and by careful design for matching. On the other side, the comparator itself is a source of switching noise placed in immediate vicinity of the sensitive single ended analogue stages. Due to large transistors used, the comparator has relatively slow transient response which limits to some degree generation of the switching noise while the implemented hysteresis prevents multiple response of the comparator to noisy input signals. The first stage of the discriminator, which converts the single ended signal into a differential one, is powered from the same power lines as the preamplifier and the shaper while the comparator with hysteresis has separate power supply lines VDDD and VSSD connected via dedicated bond pads.
4. Data storage and back-end circuit 4.1. Counters Considering possible options for data storage one has to keep in mind that due to statistical nature of X-ray sources the digital signals at the discriminator outputs appear completely randomly in time. An obvious solution is to use asynchronous counters to count the incoming pulses and that is the technique commonly used for radiation measurements in nuclear physics. In most imaging applications one has to deal with a large range of radiation intensity in various detector elements. In order to reduce the effect of statistical fluctuation on the image quality it is necessary to collect a certain minimum number of counts in the areas of low intensity, while at the same time the number of counts in the areas of high intensity can be higher by several orders of magnitude. The counter capacity in the RX64 chip has been specified as 20 bits, which allows measuring images with a large dynamic range. The counters are connected to the outputs of the front-end channels via Schmitt triggers which provide regeneration of relatively slow signals from the discriminators and help for rejection of noisy signals. The counters in the RX64 chip are based on the concept of a pseudo-random shift register [11,12]. A 20bit shift register is configured with a single XOR gate to generate a pseudo-random state sequence. As each state in such a scheme corresponds to a unique number of clock pulses that circuit can be used as a counter. The schematic of the counter structure is shown in Fig. 3. The 17th and the 20th bit of the shift register are XOR-ed and fed back to the register input, so that the period of the pseudo-random sequence is 220 –1.
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Fig. 3. Block diagram of the group of eight counters.
Such a concept of the counter circuit has two advantages which are particularly attractive for our multichannel chip, namely simplicity and small area. In the RX64 chip the counting shift register has been designed using semi-dynamic logic which allowed us to achieve a very compact layout. For comparison, in the earlier prototype the counter block has been implemented as a separate chip [13]. The very standard counter structure based on T flip–flops was used resulting in 30 transistors per bit while in the present structure implemented in the RX64 chip we need only eight transistors per bit. Required counting period depends on the intensity of the measured X-rays and must be programmable. The operation of the counters is controlled by four signals: Gate, ClkEx, A/R and Dest/NonDest. The Gate signal is used to open or close the inputs of the counters. When the counter inputs are closed it is possible to set the counters to the readout mode by setting ‘‘1’’ on the A/R (Accumulation/Read) line. There are two possible modes of the readout operation, which are controlled by the Dest/NonDest signal. In the destructive mode, after reading out the content of the counter, all bits in the shift register are set to ‘‘1’’, while in the non-destructive mode the configuration of bits in the shift register remains unchanged. The readout of the counters is performed synchronously with rate determined by the clock signal ClkEx which is applied externally. The ClkEx signal can be also used for test purposes by setting the chip in the accumulation mode. In this mode the external clock signal is routed to the counter inputs. Using this configuration one can perform functionality tests of the counters and the readout controller as well as evaluate the speed performance of the circuit. A drawback of the scheme based on the pseudorandom shift register is that in order to read out the content of the register one has to stop collecting the data. In a continuously running experiment this will generate so-called dead time, which is a fraction of time over which the data from the detector will be lost. In
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order to minimise the dead time 64 counters are grouped in eight blocks of eight counters each and the data from each block are read out via a separate link. In order to send the data off the chip the eight 20-bit shift registers are configured into a single 160-bit long shift register. The nominal readout clock frequency has been specified to be at least 10 MHz. This number ensures that for all foreseen measurement configurations the dead time introduced by the readout will be negligible. The RX64 chip has eight tristate data outputs which allow to connect several RX64 chips to a common external data bus and read them out sequentially. During the period of data taking the outputs of the chips are set to the high impedance state so that other chips can send the data to the external bus at the same time. While sending the data, the chip issues the clock signal which can be used to synchronise the data in the external data receiver. 4.2. Control logic In order to minimise the number of external control signals to be delivered to the chip we have implemented a control block which functions as a command decoder. The control block receives the commands from an external controller (typically a PC I/O card) via a serial link, decodes them, and generates the control signals to the other blocks in the chip. The list of commands is shown in Table 1. In addition to the commands used to control the readout of the counters there are three other commands implemented: CounterPulse, CalibrationPulse and LoadDac. These commands, in addition to normal operation, can be used for test purposes and allow to test the digital part of the chip, starting from the counter inputs. In the response to the CounterPulse command a single pulse is send to all counters simultaneously through the ClkEx line. Another command, which has been implemented for test purpose, is the CalibrationPulse. In response to this command a trigger pulse is send to the internal calibration circuit implemented in the front-end block. Then a current pulse, which simulates the detector signal, is injected into the preamplifier Table 1 List of commands Command code
Action
000 001 010 011 100 101 110 111
OpenGate CloseGate ReadoutDestructive ReadoutNonDestructive CalibrationPulse CounterPulse LoadDac Unused code
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input. This feature allows testing the overall functionality including the analogue and the digital part as well as performing detail measurements of the analogue parameters. The front-end block contains four different DACs which are used for setting the bias currents, the amplitude of the calibration signal and the threshold level in the discriminator. The command LoadDac contains, in addition to the command code, 10 bits which define the address of the DAC and the value to be loaded. 4.3. I/O circuits In order to minimise injection of parasitic digital signals to the substrate we have assumed that incoming digital clock and command signals must be differential ones following to the LVDS standard [14]. The input buffers which can receive correctly the LVDS signals have been implemented in the chip. On the other hand, 8-bit data output bus is designed in standard tristate single ended configuration while each chip has 2-bit address set during bonding procedure. A primary reason for that solution is to allow connecting outputs of up to four chips to a common external bus. This configuration allows one to transmit the data to a computer via a single 8-bit bus from up to four chips, i.e. up to 256 channels. As the time required for transmitting the data off the chip is usually negligible compared to the time of data collecting, it is assumed that during reading out the data the input gates will be closed. In this way we avoid a potential problem of analogue signals in the front-end being deteriorated by injection of parasitic signals from single-ended digital outputs.
5. Layout design The RX64 IC has been designed for the 0.8 lm CMOS technology process by AMS. As the chip contains analogue and digital circuits placed on common epi-type substrate, particular attention has been paid to the layout. A photograph of the chip with the major blocks marked is shown in Fig. 4. The total area of the die is 2800 6500 lm2 with a major part occupied by the analogue front-end circuits. The counters and the control block occupy only an area about 770 5400 lm2 . The floor plan of the chip is driven by the layout of the front-end channels which have to match the strip pitch of silicon sensors. This particular floor plan imposes some constraints on the layout of power and ground paths. For all critical paths the extracted resistances of the power supply paths have been taken into account in the simulation. The RX64 chip requires two single-ended supply voltages: 3.0 V for the analogue part and 4.0 V for the digital part. The average current
Fig. 4. Photograph of the RX64 IC.
consumption per chip is 45 mA for the analogue and 5 mA for the digital power supply. These numbers result in an average power consumption of 2.5 mW per channel, which is quite low given the functionality and complexity of the design. Due to matching concerns discussed earlier special attention has been paid to minimise channel-to-channel variation of the power supply voltages. The analogue power supply lines VDDA and VSSA run across all channels and are nearly 6500 lm long and 250 lm wide. The lines are connected via triple bonding pads placed symmetrically on each sides of the chip. These lines have been drawn using the metal 2 layer that has nearly twice lower resistance than the metal 1 layer. In order to avoid metal over the matched components (components of the feedback loops, differential pairs) and fit such wide lines close to the single ended stages we have added extra area inside the frontend channels. These regions are filled with substrate or well contacts tied to appropriate lines. The digital power supply lines are only 80 lm wide, however, they are stacked of the metal 1 and metal 2 layers with double bonding pads. In additions to local guard rings surrounding PMOS and NMOS devices in the preamplifier and the shaper as described in Section 3, there are two sets of global guard rings. One set of guard rings surrounds the whole analogue part while the second one encloses the whole digital part of the circuit. Guard rings for the analogue and the digital block have separate bonding pads. Different part of RX64 has been designed using different techniques. The analogue part of the chip has been designed using full custom techniques, following the layout rules for good matching [15]. Full custom technique was also used for design of the counter block, with a main goal to minimise the area of this block. The SPICE simulations have been performed on the transistor level and the layout has been optimised manually. After layout extraction SPICE simulations have been repeated again using the extracted netlist, including the parasitics. In order to cover variation of the process parameters we have requested that the circuit should pass the simulation for the nominal parameters at a
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frequency by a factor 2.5 higher compared to the nominal, i.e. at 25 MHz. Given a very regular structure of the counter block this approach has appeared to be very effective since the area of this block has been reduced by a factor of 2 compared to what could be achieved using the standard cells and automatic place and route technique. The control block, on the other hand, has a rather complicated logical structure while the total area of this block is small. Therefore, the only effective way to design such block is to generate the schematic from the behavioural description and then use the standard cell place and route technique to generate the layout. The functional code for the control block has been written in the Verilog HDL language and then the schematic and the layout of the circuit have been generated automatically by the special parameterised procedures. Functional analysis of this block has been performed using Verilog simulation. The timing performance has been ensured by proper parameterisation of the standard cell delays.
6. Tests and results 6.1. Testability features The functionality and complexity of the RX64 design require that advanced testability functions are implemented on the chip. Given the architecture of the chip some aspects related to testability are very specific for this design. First, for full evaluation of analogue performance we require detail measurements of analogue parameters for each of the 64 channels in the chip. These measurements allow one to determine whether channelto-channel matching performance is satisfactory. In principle, the input pads are not available to supply the input signals for such measurements as the naked chips are mounted of a PCB and the input pads are bonded directly to the strips of silicon sensors. Furthermore, the preamplifier is sensitive to the total charge injected to the input so this charge must be controlled very well. Any connection to the input pads by a probe card would introduce significant stray capacitance so it would be very difficult, or even impossible, to control the amount of charge injected to the input. Therefore we have implemented in the chip an internal calibration circuit which can generate precise charge pulses at the preamplifier inputs. Another issue very specific for the RX64 design is due to the fact the outputs from the analogue front-end channels are not accessible directly at all. The analogue parameters can be, however, extracted from multiple scans of the discriminator thresholds for various input charges. Using the internal DAC which controls the discriminator threshold and the internal
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calibration circuit we can perform these tests automatically. A standard procedure for testing analogue circuits with architecture as implemented in the RX64 design is to send a series of calibration pulses of a given amplitude to the test input and to count the pulses at the output of the comparator. By scanning the comparator threshold and repeating this test for various amplitudes of the calibration signal we can extract the gain and noise of the analogue part of the front-end circuit as well as the offset of the comparator for each channel (see Section 6.3). A significant improvement in the testing procedures has been achieved by implementing two DACs, one to control the amplitude of the internal calibration signals (in the range from 1 to 30 mV), and second to control the threshold of the comparator. Both of these DACs are set through the control block. It is worth to note that we can measure precisely the analogue parameters of the front-end circuit while sending to the chip only digital command signals and receiving from the chip digital data. This aspect becomes very important if one remembers that we need analogue calibration signals of amplitudes in the range of few millivolts and bringing such low signals to the chip working in digital environment is not an easy task. Thus, all we need to test fully the chip is a PC I/O card which generates the clock signal and command sequences, and receives the data. As typically the I/O cards generate the TTL signals, a TTL to LVDS signal translator needs to be implemented in the test set-up. At this point it is also worth to note that the internal calibration circuit allows one to repeat analogue measurements for the chips assembled into multi-chip modules together with silicon strip detectors using the same readout system as used for normal data taking in an experiment.
6.2. Basic functionality tests A first basic test, called as Readout Test, which checks the functionality of the digital part of the chip, is a sequence of two commands: ReadoutNonDestructive and ReadoutDestructive. The result of this test is a random pattern of the counter content as set after powering the chip as no power-up reset is implemented in the design. Response to the two above commands sent sequentially should be identical. Next step is to repeat the ReadoutDestructive command and in response we should receive now all zero values. The next test, which allows one to verify the functionality of the counters, is the Counting Test. In this test the command CounterPulse is sent and the contents of the counters are checked each time using the ReadoutNonDestructive command. The RX64 prototype has passed both, the Readout Test and the Counting Test, successfully.
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An important function of the control block is loading the DACs. For all DACs the analogue output values can be measured on the dedicated probe pads. Thus, in the same test we can verify the functionality of that part of the control block which is responsible for DAC loading and check the interface circuit between the control block and the DACs. All this circuitry works correctly and the response characteristics of each DAC can be measured. While the absolute accuracy and linearity of the DACs which set the bias currents in the front-end circuits are not critical at all, the DACs which set the amplitude of the calibration pulse and the threshold of the discriminator need to be measured precisely as they determine accuracy of analogue measurements. 6.3. Full analogue measurements Full functionality of the chip is verified when measuring analogue parameters. In addition to the functions and circuits discussed before, the calibration circuit and the command CalibrationPulse are exercised in these measurements. In response to the CalibrationPulse command the control block issues a pulse which triggers a chopper circuit in the calibration block. As the result, a voltage step of amplitude Vcal , defined by setting of the calibration DAC, is sent to the inputs of the front-end channels via test capacitors Ct (see Fig. 2). Current pulses carrying charges equal to Qinj ¼ Vcal Ct are injected to the preamplifiers connected to given calibration line. Combining this procedure with the scan of the comparator threshold allows one to measure analogue parameters. Typical results of the threshold scan are shown in Fig. 5a. The plot shows the total number of counts as a function of the comparator threshold measured for five different values of the input charges injected to the preamplifier. The rapid increase of the number of counts below 50 mV in Fig. 5 is due to the noise pulses. If the distribution of noise amplitudes is Gaussian the mea-
sured number of counts vs. threshold is described by the error function. By differentiating the measured error function one obtains a Gaussian distribution of signal amplitudes at the discriminator input as shown in Fig. 5b. The centre of each distribution corresponds to the amplitude of the signal at the discriminator input (i.e. output of the shaping amplifier) and the standard deviation of these distribution is equal to the rms value of noise at the discriminator input. Plotting the centres of the distributions as a function of the input charges one obtains the response curve of the analogue linear part of the circuit, up to the input of the discriminator for each channel. From these response curves one can extract the gain of the linear part of the circuit and the discriminator offset for each channel. The accuracy of measurements of the amplifier gain and the discriminator offset using the internal calibration circuit and the method described above depends on the precision of the calibration circuit, i.e. the value of the test capacitor in given channel and the accuracy of the calibration DAC. The actual values of the test capacitors and the response characteristics of the calibration DAC can be measured, however, measurements of the small test capacitors of the nominal value equal to 75 fF on naked chips are rather time consuming and require additional hardware. Therefore, we use physical signals generated by X-rays in a silicon strip detector read out by the RX64 IC for cross calibration of the internal calibration circuit. 6.4. Matching measurements As discussed earlier in the paper, a very critical issue for the RX64 IC is the channel-to-channel matching of the analogue parameters. The measurements of the gain matching using the internal calibration circuit may depend on matching of relatively small test capacitor Ct ¼ 75 fF placed at the input of each front-end channel (see Fig. 2). In order to eliminate this uncertainty on the
Fig. 5. Results of threshold scans for five different input charges: (a) integral distributions and (b) amplitude distributions obtained by differentiating integral distributions.
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amount of injected charge we have measured the matching performance employing physical signals from a silicon strip detector. By combining a radioactive source and fluorescence radiation from an iron foil we have obtained an X-ray source with four distinct energy lines: 6.4, 13.6, 17.2 and 20.1 keV. For this energy range the average energy needed for generation of one electron-hole pair in silicon is equal to 3.65 eV [16] so we obtain four distinct charge signals: 1753, 3726, 4712 and 5506 e . Of course, generation of free charge carriers by X-rays in silicon is a statistical process and the above numbers are the averages of statistical distributions. The standard deviation of such a distribution with average p charge Q is given as F Q, where F is the so-called Fano factor equal to 0.15 for the considered energy range [16]. For our measurements it is important to note that the statistical spread of the charge generated in the silicon strip detector for each of the four X-ray energy lines is much lower compared to the equivalent input noise charge of the front-end electronics, which is typically about 150 e rms. Employing the method based on scanning the discriminator threshold for measuring the distribution of signal amplitudes at the discriminator inputs we can obtain distribution of critical analogue parameters, offset, gain and ENC, for 64 channels in one chip. All three parameters are obtained now from a single threshold scan as the four input charge signals are generated in the silicon strip detectors randomly all the time. Typical distributions these parameters measured for one RX64 IC are shown in Fig. 6. The spread of the discriminator offset is equal to 2.2 mV rms and, when referred to the input, is equal to 28 e rms. This number is negligible compared to the
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equivalent input noise of 167 e rms measured for this particular set of an RX64 IC and a silicon strip detector. The spread of gain is small, about 0.5% on one sigma level. This is important as the effective threshold of the discriminator in terms of X-ray energy or input charge to be discriminated depends on the offset of the discriminator itself and on the gain of the amplifier. The contribution from the gain spread to the effective threshold spread is about 2.3 mV rms for the X-ray energy of 20 keV, which the upper limit of the range foreseen in various applications. Thus, in the worst case p the spread of the effective threshold will be 2 28 e rms, and it is still negligible compared to the ENC. For the ENC itself we observe quite good uniformity across the chip.
7. Conclusions A fully integrated multi-channel chip for readout of signals from silicon strip detectors has been designed and manufactured in the AMS 0.8 lm CMOS technology. The two blocks, analogue and digital, which had been prototyped separately before, have been integrated successfully in a single mixed-mode IC. The most significant advantages of this integration are: • functionality and bias conditions of the analogue circuits is now controlled by digital commands via a simple serial link, which simplifies the design and operation of modules comprising several RX64 ICs, • possibility of implementing internal calibration circuit which is controlled digitally and allows for complete analogue testing of the front end,
Fig. 6. Distributions of analogue parameters in 64 channels of one RX64 IC: (a) discriminator offset, (b) gain and (c) equivalent noise charge.
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• with increased functionality average area per channel is reduced by about 20% compared to the two chip options, • assembly of modules comprising silicon strip detectors and RX64 ICs is simplified and mechanical robustness of such modules is improved. In the RX64 design we have demonstrated that possible drawbacks of integration of very sensitive analogue circuits and digital blocks in a single IC can be successfully omitted by proper design. The prototype chip has been tested and proved to be fully functional. The measurements of analogue parameters for all 64 channels in the RX64 IC demonstrate good matching performance and confirm that analogue parameters have not been compromised by integration with digital circuitry on common silicon substrate.
[5]
[6] [7]
[8]
[9]
[10]
References [11] [1] Pelgrom M, Vertreget M. CMOS technology for mixed signal ICs. Solid-State Electron 1997;41(7):967–74. [2] Blalack T. Design techniques to reduce substrate noise. In: Huijsing J, van de Plassche R, Sansen W, editors. Analog circuit design Volt electronics; mixed-mode systems; lownoise and RF power amplifiers for telecommunication. Boston: Kluwer Academic Publishers; 1999. [3] Su D, Loinaz M, Masui S, Wooley B. Experimental results and modeling techniques for substrate noise in mixedsignal integrated circuits. IEEE J Solid-State Circuits 1993;28(4):420–30. [4] Grybos P, Daz browski W. Development of fully integrated readout system for high count rate position sensitive
[12] [13]
[14]
[15] [16]
measurements of X-rays using silicon strip detectors. IEEE Trans Nucl Sci 2001;48(3):466–72. Dabrowski W et al. Progress in development of the readout chip for the ATLAS semiconductor tracker, CERN/LHC/2000-041, Proceedings from Sixth Workshop on Electronics for LHC Experiments, Cracow, Poland, 2000. Johns M, Martin K. Analog integrated circuit design. New York: John Wiley and Sons; 1997. Pelgrom M, Duinmaijer A, Welbers A. Matching properties of MOS transistors. IEEE J Solid-State Circuits 1989;24(5):1433–40. Bertails J. Low-frequency noise consideration for MOS amplifier design. IEEE J Solid-State Circuits 1979;14(4): 773–6. Nauta B, Hoogzaad G. Substrate bounce in mixed-mode. In: Huijsing J, van de Plassche R, Sansen W, editors. Analog circuit design Volt electronics; mixed-mode systems; low-noise and RF power amplifiers for telecommunication. Boston: Kluwer Academic Publishers; 1999. Razavi B. Design of analog CMOS integrated circuits. New York: McGraw-Hill; 2001. Horowitz P, Hill W. The art of electronics. New York: Cambridge University Press; 1993. Fisher P et al. A counting pixel readout chip for imaging applications. Nucl Instr and Meth A 1998;405:53–9. Grybos P et al. Characterisation of silicon strip detectors with a binary readout chip for imaging. Nucl Instr and Meth A 2000;454:214–20. IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), IEEE Std 1596.3-1996. Laker K, Sansen W. Design of analog integrated circuits and systems. New York: McGraw-Hill; 1994. Owens A et al. The X-ray energy response of silicon (B): measurements. Nucl Instr and Meth A 1998;382:53–9.