- Email: [email protected]
Readout of silicon strip detectors
Nuclear Instruments and Methods in Physics Research A 501 (2003) 167–174
Readout of silicon strip detectors W. Da- browski* Faculty of Physics and Nuclear Techniques, University of Mining and Metallurgy, al. Mickiewicza 30, Krakow 23 30-059, Poland
Abstract Various architectural and technological options of readout electronics for silicon strip detectors in vertex and tracking applications are discussed briefly. The ABCD3T ASIC for the readout of silicon strip detectors in the ATLAS semiconductor tracker is presented. The architecture of the chip, some design issues and radiation effects are discussed. r 2002 Elsevier Science B.V. All rights reserved. PACS: 07.50.Qx; 29.40.Gx; 80.40. e Keywords: Front-end electronics; Silicon strip detectors; ASICs; Radiation effects; Radiation hardened technology
1. Introduction A new generation of vertex and tracking detectors built of silicon microstrip detectors represents new challenges for the readout electronics. Some basic parameters discussed usually as critical for the front-end electronics are: noise, speed, power consumption and radiation tolerance. Because of the speed and radiation tolerance, the projects of readout electronics for the LHC experiments represent front line development in this field. There are two numbers which set the boundaries for the front-end electronics in the LHC experiments: ATLAS, CMS and LHCb, namely the bunch crossing period of 25 ns and the radiation levels which are of the order of 10 Mrad of total ionising dose and 1 1014 n=cm2 of 1 MeV neutron equivalent fluence of hadrons. An exception is the heavy ion experiment ALICE, for which the requirements are relaxed compared *Tel.: +48-12-617-2959; fax: +48-12-634-0010. E-mail address: [email protected] (W. Da- browski).
to the proton–proton experiments. With respect to these two parameters, speed and radiation levels, the LHC proton–proton experiments require definitely a new generation of electronics compared to the electronics used in presently running experiments. There are two experiments, CDF and HERA-B, which represent some kind of intermediate steps between the LEP experiments, which required slow and not radiation tolerant electronics, and the LHC experiments, which require fast and radiation hard electronics. Other aspects, which are new in the detectors for the LHC experiments, are the system aspects, which are mainly driven by the large scale of these detectors. Power consumption is a very critical parameter and there are two equally important reasons for that: difficulties associated with supplying the power to the electronics on the detector over a large distance, of about 100 m; and difficulties associated with cooling the electronics and taking the heat off the sensitive volume of the detector. Both issues become very difficult due to constraints on the amount of material which can
0168-9002/02/$ - see front matter r 2002 Elsevier Science B.V. All rights reserved. doi:10.1016/S0168-9002(02)02028-4
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be used in the sensitive volume of the detector. The space for the electronics and its mass is limited too, since, contrary to most of the vertex detectors built so far, in the detectors for the LHC experiments, the hybrids with the readout electronics are located entirely in the sensitive volume of the detector and they overlap fully with the sensors. A further consequence of such a detector construction will be very limited access to the detector modules once the entire detector is assembled. Therefore, the system issues like testability, diagnostic tools, reliability, redundancy, failure immunity, etc. become far more critical than in the past. Finally, there are numerous problems related to radiation effects. Obviously, one has to use radiation tolerant technologies for building electronics for the radiation environment as expected in the LHC experiments. The required radiation resistance can be achieved by using proper technology and proper design techniques. In most cases, paying attention to both aspects is needed to meet the requirements. One cannot assume that using a radiation resistant process will solve all the problems. For a radiation tolerant process it is guaranteed that the post-radiation changes of device parameters will not exceed some limits. It does not mean, however, that these changes can be ignored at the design level. One has to take them into account from the very beginning and look for robust circuit solutions, which are not very sensitive to variations of device or process parameters. The experience from operation of silicon strip vertex detectors in the LEP or other experiments shows that the signal-to-noise ratio achievable in a running experiment is usually significantly lower compared to what is measured in bench tests [1]. We can expect that in the LHC experiments these issues will become even more critical, especially because of simultaneous analogue signal processing and digital activity in the front-end chips. Therefore, equally important as the signal-to-noise ratio achievable in the bench tests or beam test are other parameters, which decide about robustness of the design. The two most critical parameters are: the Power Supply Rejection Ratio (PSRR), which defines circuit immunity to variation of
supply voltages and noise of the power supply systems, and Common Mode Rejection Ratio (CMRR), which defines immunity of the circuit to external and internal interference. It is worth noting that all Application Specific Integrated Circuits (ASICs), being developed for the readout of silicon strip detectors in the LHC experiments, are of mixed-mode type and comprise fast digital electronics integrated with very sensitive analogue circuits on a common silicon substrate.
2. Architectural and technological options There are several possible schemes for the readout of silicon strip detectors which result from combinations of signal processing schemes, readout architectures, and technologies used. Signals from the silicon strips in tracking and vertex detectors have to provide information about the amount of charge collected in the strips and the time of signal generation. The requirements for timing precision are not very demanding. It is required that each event is associated uniquely with a given beam collision so the required time resolution is given by the bunch crossing period. In experiments with a low bunch crossing rate, like for example the LEP experiments, the timing requirements could be ignored completely. In faster experiments with a bunch crossing period of the order of 100 ns; and especially in the LHC experiments with 25 ns bunch crossing period, the timing requirements impose serious constraints on the signal processing. The requirements for the precision of the amplitude measurements are rather moderate compared, for example, to electronics for calorimeters. For a given strip pitch one can improve the spatial resolution by using information about signal amplitudes. However, for a strip pitch of about 100 mm the gain in spatial resolution is very limited since most of the particles generate single strip events. In addition, the achievable signal-tonoise ratio is limited. Thus, from the point of view of spatial resolution, binary readout is sufficient for many applications. Preserving and storing analogue information about the signal amplitudes provides more flexibility for off-line analysis and,
W. Da- browski / Nuclear Instruments and Methods in Physics Research A 501 (2003) 167–174
in particular, the possibility to correct the data for common mode noise if such appears in the system. In order to meet timing requirements the simplest solution is to shape short pulses in the front-end circuits but this is usually contradictory to requirements for optimisation of the signal-tonoise ratio. Short shaping requires minimising the series noise in the front-end circuit, which can be done in expense of increasing power consumption. On the other hand, the contribution of the parallel noise to the ENC is limited for short shaping times and one can allow for much higher parallel noise. For the above reasons it is worth considering an option of the front-end circuit based on a bipolar input transistor. For slower electronics such an option would be ruled out immediately by the parallel noise due to shot noise of the base current in bipolar devices. Various schemes of the front-end electronics for the LHC experiments can be divided into two basic categories: fast circuits with a peaking time of 25 ns and slower circuits with a longer peaking time, 50 or 75 ns: The peaking time of 25 ns guarantees unique association of a given signal with the bunch crossing. However, in the best case of semi-gaussian shaping it allows for double pulse resolution of 50 ns: For longer shaping of 50 or 75 ns a deconvolution method can be used to recover time information from slow pulses. Using slower shaping in the front-end circuit simplifies two problems in the design, namely, the contribution of the series noise to the ENC is reduced and it is easier to achieve appropriate rise time in the input stage. For CMOS processes with minimum feature size of 0:8 mm it is not straight forward to obtain a rise time about 10 ns in the input stage. The limitation is due to the fact that for long strips with total capacitance of about 20 pF; large input transistors have to be used in order to optimise the noise performance. The required speed of the input stage can be easily achieved using bipolar devices with unity gain frequency ft in the range of 5–10 GHz: At the same time bipolar devices offer the possibility of achieving the required noise using significantly less power compared to CMOS transistors. These issues have changed significantly for CMOS deep submicron technologies, like for
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example a 0:25 mm one, being now commonly used. First of all, this process is sufficiently fast so that it allows to build fast input stages using MOS transistors. The transconductance parameter is now significantly better compared to 0:8 mm processes because of thinner gate oxides but still the current required to obtain a given transconductance, and therefore a given voltage noise, is about two times higher compared to a bipolar transistor. In terms of power consumption, higher currents needed for circuits realised in deep submicron processes are partially compensated by the lower supply voltage of 2:5 V which is defined by a technology limit. One can try to reduce the supply voltage even further but for many analogue circuits 2:5 V is already a difficult limitation. Requirements concerning radiation resistance of readout electronics reduce significantly the number of technological options. Many radiation hardened CMOS processes considered and explored by the particle physics community at the beginning of the 1990s [2] are not available any more. Essentially the only process available these days is the DMILL one [3], which offers radiation hardened CMOS devices and fast bipolar devices. This process suits quite well to designs employing bipolar transistors in the front-end as it allows to integrate fast front-end circuits optimised for low noise with CMOS digital circuitry. Another way of solving the problem of radiation hardness is to use a deep submicron CMOS process and improve its radiation hardness by special design and layout techniques [4]. Thus, all readout chips for silicon microstrips detectors, being developed for the LHC experiments, use one of the two technological options mentioned above. The list of projects, which are either in advanced prototyping stage or in production stages includes: *
*
ABCD3T: binary readout chip for the ATLAS semiconductor tracker, fast bipolar front-end realised in the DMILL process [5,6]. SCTA: general purpose analogue readout chip, fast bipolar front-end realised in the DMILL process [7].
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APV25: analogue readout chip for the CMS silicon tracker, slow front-end with deconvolution circuit realised in a 0:25 mm CMOS process [8]. BEETLE: analogue readout chip for silicon strip vertex detector in the LHCb experiment, fast front-end realised in a 0:25 mm CMOS process [9].
3. Binary readout for the ATLAS semiconductor tracker The readout of the silicon strip detectors in the ATLAS semiconductor tracker is based on the binary architecture. The readout ASIC, ABCD3T, is realised in the DMILL process and employs a front-end circuit using a bipolar input transistor. Some issues concerning noise optimisation and shaping in the front-end circuits and radiation effects are representative for other designs using the same technology. For example, the SCTA design, being developed in parallel with the ABCD3T, employs the same concept of the frontend circuit. Some other aspects of the ABCD3T design are very specific for the binary readout architecture. 3.1. Architecture of the ABCD3T ASIC The ABCD3T ASIC comprises in a single chip all blocks of the binary readout architecture: the front-end circuit, discriminator, binary pipeline, derandomising buffer, data compression logic, and the readout control logic, as required for the ATLAS SCT off detector readout electronics. The block diagram of the ABCD3T design is shown in Fig. 1. An overview of the ABCD3T architecture and of the performance of the ABCD2T prototype can be found in earlier publications [5,6]. In this paper we focus only on some selected issues. For the binary architecture an absolutely critical issue is the uniformity of parameters, gain, noise, peaking time of the front-end circuit and matching of the discriminator thresholds. The project was started with an assumption that sufficiently good matching could be obtained to allow for a common threshold applied to all 128 channels in
the chip. After extensive radiation testing we have learned that matching degrades significantly after irradiation. The target concerning threshold uniformity has been eventually achieved by implementing individual threshold correction in every channel using a 4-bit digital-to-analogue converter (TrimDAC) per channel. It is worth noting that the chosen architecture of the ABCD3T ASIC provides maximum possible reduction of data to be transferred off the detector. The front-end circuit is equipped with an amplitude discriminator and only one bit of information from each channel is stored in the pipeline for a period of a trigger latency. Then, after pipeline and derandomising buffer, the data are compressed and only addresses of channels with hits are transferred off the detector. This readout scheme allows one to read out six chips (768 channels) via a single 40 MHz binary optical link for an average trigger rate of 100 kHz and strip occupancy up to 2%. On the module the data are transferred via a serial token ring including six chips. All the circuitry responsible for controlling the data transfer is implemented in the back-end of the ABCD3T chip so that no additional chips are needed on the module. Mechanisms responsible for recovery from transmission errors are built into the ABCD3T design. In order to make the module immune to single point failures a bypassing scheme has been implemented in the ABCD3T and in the hybrid design. 3.2. Testability Testability of ASICs for the readout of silicon strip detectors in the LHC experiments is equally important as basic parameters responsible for signal processing. The testability features are foreseen to be used at various steps of building, commissioning and running the experiments. They have to provide effective means for testing the chips on wafers before dicing, testing hybrids equipped with the chips and testing fully assembled modules as well as monitoring module performance in the experiment. Analogue testability of the ABCD3T chip has been achieved by implementation of an internal calibration circuit, which allows measuring
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Fig. 1. Block diagram of the ABCD3T ASIC.
analogue parameters of the front-end without accessing the input pads. This is a very important feature for testing the chips on wafers as well as for testing the chips assembled into modules since it allows to perform full analogue measurements by sending to the chips digital commands and reading from the chip digital data only. In response to digital commands sent to the chip through a serial link, the calibration circuit generates precise analogue signals which simulate current pulses from the strips. This scheme allows one to measure the analogue parameters of the front-end and the TrimDAC characteristics for every channel without the necessity of supplying precise analogue signals to the chips. All important analogue parameters, gain, noise, time walk and comparator offset, are extracted from scans of the discriminator threshold for various amplitudes of the calibration signal. The discriminator threshold voltage and the amplitude of the calibration signal are controlled by internal 8-bit DACs. The results of such measurements are converted into a stream of digital data and are read out through the data
path. These measurements are then repeated for the chips assembled onto hybrids and later for full modules with the silicon strip detectors connected to the front-end electronics. The internal calibration circuit is used also for trimming the discriminator thresholds. A starting point for the trimming procedure is measurements of the response curve for every channel. An example of such measurements is shown in Fig. 2. The effective threshold of the discriminator for each individual channel, expressed in terms of an equivalent input charge, depends on the actual gain and actual comparator offset for a given channel. From the plot shown in Fig. 2 one can see that for the nominal operation threshold of 1 fC the channel-to-channel spread of the effective threshold is mostly due to comparator offset spread and the contribution due to the gain spread is negligible. For a given target value of the threshold, the offset value is calculated for each channel and the point nearest to the offset is found on the measured response curve of the correction TrimDAC in that channel.
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Fig. 2. Response curves of 128 channels in one ABCD3T chip before threshold correction.
The performance of the TrimDACs is illustrated in Fig. 3, which shows the distribution of the effective offset for 1 fC input charge for 128 channels in one ABCD3T chip before trimming (a) and after trimming (b). The offset spread of 7:4 mV rms before trimming is reduced to 1:5 mV rms after trimming, which is close to the expected value given the TrimDAC step of 4 mV: The spread of the threshold is equivalent to ENC of 180 e rms, which is negligible compared to the typical noise of 1400 e rms for a module with long silicon strips as designed for the ATLAS SCT. 3.3. Radiation effects The radiation effects in the DMILL technology and in the ABCD3T design have been discussed in a previous paper [10]. The DMILL technology is qualified as radiation resistant. However, the radiation levels expected for the SCT detector in the ATLAS experiments exceed the upper limits specified for the DMILL process, i.e. 10 Mrad of total ionising dose and 1 1014 n=cm2 of 1 MeV neutron equivalent fluence. In addition, if one takes into account very advanced requirements regarding the noise, speed and power consumption of the ABCD3T chip, it becomes obvious that radiation effects in the basic devices, although limited, cannot be ignored. Some radiation effects in basic devices, like for example degradation of the current gain factor b in
Fig. 3. Distribution of thresholds for 128 channels in one ABCD3T chip before threshold correction (a) and after threshold correction (b).
bipolar transistors or threshold voltage shifts in MOS devices, have been taken into account from the beginning of the project. The radiation hardness of the ABCD3T design has been evaluated in numerous tests performed in various radiation environments, including high-energy proton and pion beams, neutrons, gamma radiation and Xrays. The main expected radiation effects in the ABCD3T circuits have been confirmed in these tests. We observe systematic slowing down of the digital CMOS circuits due to the threshold voltage shifts in MOS transistors. The performance of the front-end circuit is affected by degradation of the current gain factor b: As a result, the parallel noise in the front-end increases. Fig. 4 shows the typical evolution of the parallel noise vs. particle fluence during irradiation of a hybrid with six ABCD3T chips in 24 GeV proton beam. Each curve represents the average for 128 channels in one chip. We observe an increase of the parallel noise,
W. Da- browski / Nuclear Instruments and Methods in Physics Research A 501 (2003) 167–174
Fig. 4. Increase of the parallel noise vs. proton fluence.
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irradiation and slightly less, by a factor of about 2, after neutron irradiation. This is an example when radiation effects force particular design solutions. As mentioned before, the project has been started with an assumption that satisfactory matching of the discriminator thresholds can be achieved by proper scaling of device areas. In the course of prototyping and irradiation testing we have learned about the effect mentioned above and in order to cope with it we have implemented individual threshold correction employing a 4-bit TrimDAC in every channel. The TrimDACs have, in addition, four selectable ranges, which allow one to adjust the range according to the actual range of the threshold spread.
4. Summary
Fig. 5. Increase of the discriminator offset spread vs. proton fluence.
which is due to the increase of the shot noise of the base current when the input stage is biased with a constant collector current. Very similar behaviour of the parallel noise is observed after neutron irradiation. As discussed earlier, the increase of the parallel noise has a small effect on the total noise when the chips are connected to long strips and the ENC is dominated by the series noise. An effect, which was not expected from the beginning but has been observed systematically in all radiation tests, is the increase of the offset spread in the discriminator. The source of this effect has been identified as the worsening of resistor matching. The evolution of the offset spread vs. proton fluence for six irradiated ABCD3T chips is shown in Fig. 5. The offset spread increases by a factor of 3–4 after proton
Several different solutions of readout electronics for silicon strip detectors to be used in the LHC experiments have been developed and can be considered now as very matured projects. It has been demonstrated that the basic LHC requirements concerning noise, speed and radiation hardness can be achieved for various architectural and technological options. The system tests employing some numbers of silicon strip modules, being designed and prototyped for the LHC experiments, are continued in order to evaluate performance of the readout electronics relevant for operation of large systems. Some system issues are new in the tracking detectors for the LHC experiments compared to vertex detectors built in the past for other experiments and efforts need to be continued to understand fully those issues.
References [1] D. Amidei, et al., Nucl. Instr. and Meth. A 342 (1994) 251. [2] W. Da- browski, Nucl. Phys. B Proc. Suppl. 44 (1995) 463. [3] P. Abbon, et al., RD29 Status Report, DMILL, a mixed analog–digital radiation hard technology for high energy physics electronics, CERN/LHCC/97-15, March 1997. [4] G. Anelli, et al., IEEE Trans. Nucl. Sci. NS-46 (6) (1999) 1690.
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[5] W. Da- browski, et al., IEEE Trans. Nucl. Sci. NS-47 (6) (2000) 1843. [6] W. Da- browski, et al., Progress in development of the readout chip for the ATLAS semiconductor tracker, Proceedings of the Sixth Workshop on Electronics for LHC Experiments, Cracow, Poland, 11–15 September 1999, CERN/LHCC/2000-041, October 2000, p. 115. [7] E. Chesi, et al., IEEE Trans. Nucl. Sci. NS-47 (4) (2000) 1434. [8] M. Raymond, et al., The CMS tracker APV25 0:25 mm CMOS readout chips, Proceedings of the Sixth Workshop on Electronics for LHC Experiments, Cracow, Poland,
11–15 September 1999, CERN/LHCC/2000-041, October 2000, p. 130. [9] N. van Bakel, et al., Design of a readout chip for LHCb, Proceedings of the Sixth Workshop on Electronics for LHC Experiments, Cracow, Poland, 11–15 September 1999, CERN/LHCC/2000-041, October 2000, p. 157. [10] W. Da- browski, et al., Radiation hardness of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker, Proceedings of the Fifth Workshop on Electronics for LHC Experiments, Snowmass, Colorado, USA, 20–24 September, 1999, CERN/LHCC/99-03, October 1999, p. 113.
Readout of silicon strip detectors W. Da- browski* Faculty of Physics and Nuclear Techniques, University of Mining and Metallurgy, al. Mickiewicza 30, Krakow 23 30-059, Poland
Abstract Various architectural and technological options of readout electronics for silicon strip detectors in vertex and tracking applications are discussed briefly. The ABCD3T ASIC for the readout of silicon strip detectors in the ATLAS semiconductor tracker is presented. The architecture of the chip, some design issues and radiation effects are discussed. r 2002 Elsevier Science B.V. All rights reserved. PACS: 07.50.Qx; 29.40.Gx; 80.40. e Keywords: Front-end electronics; Silicon strip detectors; ASICs; Radiation effects; Radiation hardened technology
1. Introduction A new generation of vertex and tracking detectors built of silicon microstrip detectors represents new challenges for the readout electronics. Some basic parameters discussed usually as critical for the front-end electronics are: noise, speed, power consumption and radiation tolerance. Because of the speed and radiation tolerance, the projects of readout electronics for the LHC experiments represent front line development in this field. There are two numbers which set the boundaries for the front-end electronics in the LHC experiments: ATLAS, CMS and LHCb, namely the bunch crossing period of 25 ns and the radiation levels which are of the order of 10 Mrad of total ionising dose and 1 1014 n=cm2 of 1 MeV neutron equivalent fluence of hadrons. An exception is the heavy ion experiment ALICE, for which the requirements are relaxed compared *Tel.: +48-12-617-2959; fax: +48-12-634-0010. E-mail address: [email protected] (W. Da- browski).
to the proton–proton experiments. With respect to these two parameters, speed and radiation levels, the LHC proton–proton experiments require definitely a new generation of electronics compared to the electronics used in presently running experiments. There are two experiments, CDF and HERA-B, which represent some kind of intermediate steps between the LEP experiments, which required slow and not radiation tolerant electronics, and the LHC experiments, which require fast and radiation hard electronics. Other aspects, which are new in the detectors for the LHC experiments, are the system aspects, which are mainly driven by the large scale of these detectors. Power consumption is a very critical parameter and there are two equally important reasons for that: difficulties associated with supplying the power to the electronics on the detector over a large distance, of about 100 m; and difficulties associated with cooling the electronics and taking the heat off the sensitive volume of the detector. Both issues become very difficult due to constraints on the amount of material which can
0168-9002/02/$ - see front matter r 2002 Elsevier Science B.V. All rights reserved. doi:10.1016/S0168-9002(02)02028-4
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be used in the sensitive volume of the detector. The space for the electronics and its mass is limited too, since, contrary to most of the vertex detectors built so far, in the detectors for the LHC experiments, the hybrids with the readout electronics are located entirely in the sensitive volume of the detector and they overlap fully with the sensors. A further consequence of such a detector construction will be very limited access to the detector modules once the entire detector is assembled. Therefore, the system issues like testability, diagnostic tools, reliability, redundancy, failure immunity, etc. become far more critical than in the past. Finally, there are numerous problems related to radiation effects. Obviously, one has to use radiation tolerant technologies for building electronics for the radiation environment as expected in the LHC experiments. The required radiation resistance can be achieved by using proper technology and proper design techniques. In most cases, paying attention to both aspects is needed to meet the requirements. One cannot assume that using a radiation resistant process will solve all the problems. For a radiation tolerant process it is guaranteed that the post-radiation changes of device parameters will not exceed some limits. It does not mean, however, that these changes can be ignored at the design level. One has to take them into account from the very beginning and look for robust circuit solutions, which are not very sensitive to variations of device or process parameters. The experience from operation of silicon strip vertex detectors in the LEP or other experiments shows that the signal-to-noise ratio achievable in a running experiment is usually significantly lower compared to what is measured in bench tests [1]. We can expect that in the LHC experiments these issues will become even more critical, especially because of simultaneous analogue signal processing and digital activity in the front-end chips. Therefore, equally important as the signal-to-noise ratio achievable in the bench tests or beam test are other parameters, which decide about robustness of the design. The two most critical parameters are: the Power Supply Rejection Ratio (PSRR), which defines circuit immunity to variation of
supply voltages and noise of the power supply systems, and Common Mode Rejection Ratio (CMRR), which defines immunity of the circuit to external and internal interference. It is worth noting that all Application Specific Integrated Circuits (ASICs), being developed for the readout of silicon strip detectors in the LHC experiments, are of mixed-mode type and comprise fast digital electronics integrated with very sensitive analogue circuits on a common silicon substrate.
2. Architectural and technological options There are several possible schemes for the readout of silicon strip detectors which result from combinations of signal processing schemes, readout architectures, and technologies used. Signals from the silicon strips in tracking and vertex detectors have to provide information about the amount of charge collected in the strips and the time of signal generation. The requirements for timing precision are not very demanding. It is required that each event is associated uniquely with a given beam collision so the required time resolution is given by the bunch crossing period. In experiments with a low bunch crossing rate, like for example the LEP experiments, the timing requirements could be ignored completely. In faster experiments with a bunch crossing period of the order of 100 ns; and especially in the LHC experiments with 25 ns bunch crossing period, the timing requirements impose serious constraints on the signal processing. The requirements for the precision of the amplitude measurements are rather moderate compared, for example, to electronics for calorimeters. For a given strip pitch one can improve the spatial resolution by using information about signal amplitudes. However, for a strip pitch of about 100 mm the gain in spatial resolution is very limited since most of the particles generate single strip events. In addition, the achievable signal-tonoise ratio is limited. Thus, from the point of view of spatial resolution, binary readout is sufficient for many applications. Preserving and storing analogue information about the signal amplitudes provides more flexibility for off-line analysis and,
W. Da- browski / Nuclear Instruments and Methods in Physics Research A 501 (2003) 167–174
in particular, the possibility to correct the data for common mode noise if such appears in the system. In order to meet timing requirements the simplest solution is to shape short pulses in the front-end circuits but this is usually contradictory to requirements for optimisation of the signal-tonoise ratio. Short shaping requires minimising the series noise in the front-end circuit, which can be done in expense of increasing power consumption. On the other hand, the contribution of the parallel noise to the ENC is limited for short shaping times and one can allow for much higher parallel noise. For the above reasons it is worth considering an option of the front-end circuit based on a bipolar input transistor. For slower electronics such an option would be ruled out immediately by the parallel noise due to shot noise of the base current in bipolar devices. Various schemes of the front-end electronics for the LHC experiments can be divided into two basic categories: fast circuits with a peaking time of 25 ns and slower circuits with a longer peaking time, 50 or 75 ns: The peaking time of 25 ns guarantees unique association of a given signal with the bunch crossing. However, in the best case of semi-gaussian shaping it allows for double pulse resolution of 50 ns: For longer shaping of 50 or 75 ns a deconvolution method can be used to recover time information from slow pulses. Using slower shaping in the front-end circuit simplifies two problems in the design, namely, the contribution of the series noise to the ENC is reduced and it is easier to achieve appropriate rise time in the input stage. For CMOS processes with minimum feature size of 0:8 mm it is not straight forward to obtain a rise time about 10 ns in the input stage. The limitation is due to the fact that for long strips with total capacitance of about 20 pF; large input transistors have to be used in order to optimise the noise performance. The required speed of the input stage can be easily achieved using bipolar devices with unity gain frequency ft in the range of 5–10 GHz: At the same time bipolar devices offer the possibility of achieving the required noise using significantly less power compared to CMOS transistors. These issues have changed significantly for CMOS deep submicron technologies, like for
169
example a 0:25 mm one, being now commonly used. First of all, this process is sufficiently fast so that it allows to build fast input stages using MOS transistors. The transconductance parameter is now significantly better compared to 0:8 mm processes because of thinner gate oxides but still the current required to obtain a given transconductance, and therefore a given voltage noise, is about two times higher compared to a bipolar transistor. In terms of power consumption, higher currents needed for circuits realised in deep submicron processes are partially compensated by the lower supply voltage of 2:5 V which is defined by a technology limit. One can try to reduce the supply voltage even further but for many analogue circuits 2:5 V is already a difficult limitation. Requirements concerning radiation resistance of readout electronics reduce significantly the number of technological options. Many radiation hardened CMOS processes considered and explored by the particle physics community at the beginning of the 1990s [2] are not available any more. Essentially the only process available these days is the DMILL one [3], which offers radiation hardened CMOS devices and fast bipolar devices. This process suits quite well to designs employing bipolar transistors in the front-end as it allows to integrate fast front-end circuits optimised for low noise with CMOS digital circuitry. Another way of solving the problem of radiation hardness is to use a deep submicron CMOS process and improve its radiation hardness by special design and layout techniques [4]. Thus, all readout chips for silicon microstrips detectors, being developed for the LHC experiments, use one of the two technological options mentioned above. The list of projects, which are either in advanced prototyping stage or in production stages includes: *
*
ABCD3T: binary readout chip for the ATLAS semiconductor tracker, fast bipolar front-end realised in the DMILL process [5,6]. SCTA: general purpose analogue readout chip, fast bipolar front-end realised in the DMILL process [7].
170 *
*
W. Da- browski / Nuclear Instruments and Methods in Physics Research A 501 (2003) 167–174
APV25: analogue readout chip for the CMS silicon tracker, slow front-end with deconvolution circuit realised in a 0:25 mm CMOS process [8]. BEETLE: analogue readout chip for silicon strip vertex detector in the LHCb experiment, fast front-end realised in a 0:25 mm CMOS process [9].
3. Binary readout for the ATLAS semiconductor tracker The readout of the silicon strip detectors in the ATLAS semiconductor tracker is based on the binary architecture. The readout ASIC, ABCD3T, is realised in the DMILL process and employs a front-end circuit using a bipolar input transistor. Some issues concerning noise optimisation and shaping in the front-end circuits and radiation effects are representative for other designs using the same technology. For example, the SCTA design, being developed in parallel with the ABCD3T, employs the same concept of the frontend circuit. Some other aspects of the ABCD3T design are very specific for the binary readout architecture. 3.1. Architecture of the ABCD3T ASIC The ABCD3T ASIC comprises in a single chip all blocks of the binary readout architecture: the front-end circuit, discriminator, binary pipeline, derandomising buffer, data compression logic, and the readout control logic, as required for the ATLAS SCT off detector readout electronics. The block diagram of the ABCD3T design is shown in Fig. 1. An overview of the ABCD3T architecture and of the performance of the ABCD2T prototype can be found in earlier publications [5,6]. In this paper we focus only on some selected issues. For the binary architecture an absolutely critical issue is the uniformity of parameters, gain, noise, peaking time of the front-end circuit and matching of the discriminator thresholds. The project was started with an assumption that sufficiently good matching could be obtained to allow for a common threshold applied to all 128 channels in
the chip. After extensive radiation testing we have learned that matching degrades significantly after irradiation. The target concerning threshold uniformity has been eventually achieved by implementing individual threshold correction in every channel using a 4-bit digital-to-analogue converter (TrimDAC) per channel. It is worth noting that the chosen architecture of the ABCD3T ASIC provides maximum possible reduction of data to be transferred off the detector. The front-end circuit is equipped with an amplitude discriminator and only one bit of information from each channel is stored in the pipeline for a period of a trigger latency. Then, after pipeline and derandomising buffer, the data are compressed and only addresses of channels with hits are transferred off the detector. This readout scheme allows one to read out six chips (768 channels) via a single 40 MHz binary optical link for an average trigger rate of 100 kHz and strip occupancy up to 2%. On the module the data are transferred via a serial token ring including six chips. All the circuitry responsible for controlling the data transfer is implemented in the back-end of the ABCD3T chip so that no additional chips are needed on the module. Mechanisms responsible for recovery from transmission errors are built into the ABCD3T design. In order to make the module immune to single point failures a bypassing scheme has been implemented in the ABCD3T and in the hybrid design. 3.2. Testability Testability of ASICs for the readout of silicon strip detectors in the LHC experiments is equally important as basic parameters responsible for signal processing. The testability features are foreseen to be used at various steps of building, commissioning and running the experiments. They have to provide effective means for testing the chips on wafers before dicing, testing hybrids equipped with the chips and testing fully assembled modules as well as monitoring module performance in the experiment. Analogue testability of the ABCD3T chip has been achieved by implementation of an internal calibration circuit, which allows measuring
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Fig. 1. Block diagram of the ABCD3T ASIC.
analogue parameters of the front-end without accessing the input pads. This is a very important feature for testing the chips on wafers as well as for testing the chips assembled into modules since it allows to perform full analogue measurements by sending to the chips digital commands and reading from the chip digital data only. In response to digital commands sent to the chip through a serial link, the calibration circuit generates precise analogue signals which simulate current pulses from the strips. This scheme allows one to measure the analogue parameters of the front-end and the TrimDAC characteristics for every channel without the necessity of supplying precise analogue signals to the chips. All important analogue parameters, gain, noise, time walk and comparator offset, are extracted from scans of the discriminator threshold for various amplitudes of the calibration signal. The discriminator threshold voltage and the amplitude of the calibration signal are controlled by internal 8-bit DACs. The results of such measurements are converted into a stream of digital data and are read out through the data
path. These measurements are then repeated for the chips assembled onto hybrids and later for full modules with the silicon strip detectors connected to the front-end electronics. The internal calibration circuit is used also for trimming the discriminator thresholds. A starting point for the trimming procedure is measurements of the response curve for every channel. An example of such measurements is shown in Fig. 2. The effective threshold of the discriminator for each individual channel, expressed in terms of an equivalent input charge, depends on the actual gain and actual comparator offset for a given channel. From the plot shown in Fig. 2 one can see that for the nominal operation threshold of 1 fC the channel-to-channel spread of the effective threshold is mostly due to comparator offset spread and the contribution due to the gain spread is negligible. For a given target value of the threshold, the offset value is calculated for each channel and the point nearest to the offset is found on the measured response curve of the correction TrimDAC in that channel.
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Fig. 2. Response curves of 128 channels in one ABCD3T chip before threshold correction.
The performance of the TrimDACs is illustrated in Fig. 3, which shows the distribution of the effective offset for 1 fC input charge for 128 channels in one ABCD3T chip before trimming (a) and after trimming (b). The offset spread of 7:4 mV rms before trimming is reduced to 1:5 mV rms after trimming, which is close to the expected value given the TrimDAC step of 4 mV: The spread of the threshold is equivalent to ENC of 180 e rms, which is negligible compared to the typical noise of 1400 e rms for a module with long silicon strips as designed for the ATLAS SCT. 3.3. Radiation effects The radiation effects in the DMILL technology and in the ABCD3T design have been discussed in a previous paper [10]. The DMILL technology is qualified as radiation resistant. However, the radiation levels expected for the SCT detector in the ATLAS experiments exceed the upper limits specified for the DMILL process, i.e. 10 Mrad of total ionising dose and 1 1014 n=cm2 of 1 MeV neutron equivalent fluence. In addition, if one takes into account very advanced requirements regarding the noise, speed and power consumption of the ABCD3T chip, it becomes obvious that radiation effects in the basic devices, although limited, cannot be ignored. Some radiation effects in basic devices, like for example degradation of the current gain factor b in
Fig. 3. Distribution of thresholds for 128 channels in one ABCD3T chip before threshold correction (a) and after threshold correction (b).
bipolar transistors or threshold voltage shifts in MOS devices, have been taken into account from the beginning of the project. The radiation hardness of the ABCD3T design has been evaluated in numerous tests performed in various radiation environments, including high-energy proton and pion beams, neutrons, gamma radiation and Xrays. The main expected radiation effects in the ABCD3T circuits have been confirmed in these tests. We observe systematic slowing down of the digital CMOS circuits due to the threshold voltage shifts in MOS transistors. The performance of the front-end circuit is affected by degradation of the current gain factor b: As a result, the parallel noise in the front-end increases. Fig. 4 shows the typical evolution of the parallel noise vs. particle fluence during irradiation of a hybrid with six ABCD3T chips in 24 GeV proton beam. Each curve represents the average for 128 channels in one chip. We observe an increase of the parallel noise,
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Fig. 4. Increase of the parallel noise vs. proton fluence.
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irradiation and slightly less, by a factor of about 2, after neutron irradiation. This is an example when radiation effects force particular design solutions. As mentioned before, the project has been started with an assumption that satisfactory matching of the discriminator thresholds can be achieved by proper scaling of device areas. In the course of prototyping and irradiation testing we have learned about the effect mentioned above and in order to cope with it we have implemented individual threshold correction employing a 4-bit TrimDAC in every channel. The TrimDACs have, in addition, four selectable ranges, which allow one to adjust the range according to the actual range of the threshold spread.
4. Summary
Fig. 5. Increase of the discriminator offset spread vs. proton fluence.
which is due to the increase of the shot noise of the base current when the input stage is biased with a constant collector current. Very similar behaviour of the parallel noise is observed after neutron irradiation. As discussed earlier, the increase of the parallel noise has a small effect on the total noise when the chips are connected to long strips and the ENC is dominated by the series noise. An effect, which was not expected from the beginning but has been observed systematically in all radiation tests, is the increase of the offset spread in the discriminator. The source of this effect has been identified as the worsening of resistor matching. The evolution of the offset spread vs. proton fluence for six irradiated ABCD3T chips is shown in Fig. 5. The offset spread increases by a factor of 3–4 after proton
Several different solutions of readout electronics for silicon strip detectors to be used in the LHC experiments have been developed and can be considered now as very matured projects. It has been demonstrated that the basic LHC requirements concerning noise, speed and radiation hardness can be achieved for various architectural and technological options. The system tests employing some numbers of silicon strip modules, being designed and prototyped for the LHC experiments, are continued in order to evaluate performance of the readout electronics relevant for operation of large systems. Some system issues are new in the tracking detectors for the LHC experiments compared to vertex detectors built in the past for other experiments and efforts need to be continued to understand fully those issues.
References [1] D. Amidei, et al., Nucl. Instr. and Meth. A 342 (1994) 251. [2] W. Da- browski, Nucl. Phys. B Proc. Suppl. 44 (1995) 463. [3] P. Abbon, et al., RD29 Status Report, DMILL, a mixed analog–digital radiation hard technology for high energy physics electronics, CERN/LHCC/97-15, March 1997. [4] G. Anelli, et al., IEEE Trans. Nucl. Sci. NS-46 (6) (1999) 1690.
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[5] W. Da- browski, et al., IEEE Trans. Nucl. Sci. NS-47 (6) (2000) 1843. [6] W. Da- browski, et al., Progress in development of the readout chip for the ATLAS semiconductor tracker, Proceedings of the Sixth Workshop on Electronics for LHC Experiments, Cracow, Poland, 11–15 September 1999, CERN/LHCC/2000-041, October 2000, p. 115. [7] E. Chesi, et al., IEEE Trans. Nucl. Sci. NS-47 (4) (2000) 1434. [8] M. Raymond, et al., The CMS tracker APV25 0:25 mm CMOS readout chips, Proceedings of the Sixth Workshop on Electronics for LHC Experiments, Cracow, Poland,
11–15 September 1999, CERN/LHCC/2000-041, October 2000, p. 130. [9] N. van Bakel, et al., Design of a readout chip for LHCb, Proceedings of the Sixth Workshop on Electronics for LHC Experiments, Cracow, Poland, 11–15 September 1999, CERN/LHCC/2000-041, October 2000, p. 157. [10] W. Da- browski, et al., Radiation hardness of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker, Proceedings of the Fifth Workshop on Electronics for LHC Experiments, Snowmass, Colorado, USA, 20–24 September, 1999, CERN/LHCC/99-03, October 1999, p. 113.