Multichip modules for high performance computer applications

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Multichip module packaging is ew)lving to become the dominant packaging approach for high performance computer applications in order to take full advantage of the improvements in speed and level of integration of advanced verylarge-scale integrated circuits. This technology uses chip-on-board assembly on very high density interconnect and achieves reduced interconnect length and elimination of one packaging level. In this paper we present the development efforts at Microelectronics and Computer Technology Corporation in this area which include the following: wafer bumping, multilaycr copper/polyimide interconnect, high I O tape automated bonding, high density connector, and cooling technology.

I. IN'I'R()I)U("I I()N

In applications where performance is the primary consideration, the traditional method of interconnecting single-chip packages on multilayer printed-circuit boards is being replaced by the more modern technology of multichip modules. The transition offers the potential advantage of higher integrated circuit (IC) chip density, smaller interconnect delays, improved electrical performance and reliability. The use of multichip modules, which consist of unpackagcd IC chips bonded to a high density interconnect substrate, results in a dramatic reduction in overall size and weight, and is important for many applications including both consumer electronics and military systems. The technology is especially important for high lead count devices, which may have many hundreds of I"Os and which tvould otherwise require a large footprint for each single-chip package. As an example, a 1 cm chip with 400 bondpads spaced at a 0. I mm pitch around thc periphery, of the chip would rcquirc a package 5cm on a side for leads on a 0.5 mm pitch. A system constructed of such packages would require 25 times the area ofa multichip module just to accommodate the chips. * (.'urrent ~ddrcss: T a n d e m ( ' o l l l p u l e r s lilt:. 1~333 \"allco Parkv, a.,,. 1.O(" 3-0N. ( ' u p e r t l n o . ('.,\ t)Yl)14. t i.S.A

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The trend to larger chips with higher I/O count and the placement of these unpackaged chips closer together necessitates the use of a high density interconnect substrate. Typical high quality printed-circuit boards achieve the line widths of 0.1 mm and line pitches of 0.2mm. By contrast, wiring densities of 400cm of interconnect per square centimeter ofsubstrate are achievable on multichip modules using a high density copper/polyimide interconnect substrate. This can be accomplished on one pair ofx and y signal interconnect levels with a wiring pitch of 50 p.m each, providing a wiring density about 33~o higher than that provided by a 44layer printed-circuit board'. Even more important than line width, the large pad size required for through-board vias with many layers of interconnect further limits how close packages can be placed on printed-circuit boards. A typical multichip module would use vias as small as 20 p,m with pad landings of 30-40 p.m. Consequently the chip die can be essentially "brick walled" on a multichip module, whereas silicon coverage for typical printed-circuit boards may range from 5~o to 10~. Size reduction also improves the electrical performance by shrinking the length of the chip-to-chip interconnect, thereby decreasing delay and lowering noise levels in the signal and power distribution system. Furthermore, the short lead lengths and beam geometries used for connecting the inner lead bonds on the chip to the outer lead bonds on the substrate with tape automated bonding (TAB) result in smaller lead inductance, which is important for reducing power disturbance and cross-talk. For flip chip of controlled collapse chip connection (C4) bonding, the improvement is even more dramatic. Since only two layers of interconnect are required, the interconnect layers may be sandwiched between a single pair of reference layers to provide controlled impedance interconnections as well as an efficient power distribution scheme. A typical custom substrate used with a multichip module would contain two signal layers, two reference layers, and a top bondpad layer. A copper/polyimide system using this configuration with a line pitch of 50 lam and 15 p.m line width and dielectric thickness would produce lines with a characteristic impedance of about 50 ~, saturated cross-talk levels below 5'Yo,and nominal series resistance of about 2.5 f~ cm - 1. A multichip module with these electrical characteristics would be useful for a variety of different circuit families, including complementary metal-oxide-semiconductor (CMOS), emitter-coupled logic, and GaAs. A typical multichip module consisting of 6 custom very-large-scale integration (VLSi) chips and 12 programmable read-only memory (PROMI devices on a 5.72 cm square substrate is shown in Fig. 1. The module incorporates TAB-bonded CMOS/silicon-on sapphire (SOS) devices and implements a dual processor 1750 computing system. The chip bumping and TAB bonding as well as the substrate design and fabrication were performed at Microelectronics and Computer Technology Corporation (MCC). Multichip modules require the convergence of a set of individual technologies including fabrication of high yield interconnect substrates with good electrical properties, availability of unpackaged chips from semiconductor houses in the required format, methods of testing prior to assembly, appropriate means of bonding active devices to the substrate, thermal management techniques, high density connectors for interfacing the module to the next level of packaging, repair and rework strategies, and protective coating. When these technologies become

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established and in widespread use. multichip modules should offer higher performance and reliability at a lower manufacturing cost than thc cquivalent multilayer printed-circuit board bccause of miniaturization, the elimination of one lcvel of packaging, and the use of fewer layers of interconncct. 2.

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The high density interconnects (or substrates for multichip module assemblyl for interconnecting a multiple of high i.;O VLSI chips can be multilayer ceramics 2. thick film substrates 3, or thin film substrates'*. Comparison of thcse competing technologies has been made 5, with the thin tilm approach expected to be the dominant technology in high performance systems ~'. Many different approaches and different materials can be used for fabrication of thin film interconnects and multichip modules. Examples ofthesc and references can be found in literature ~' ~ A thin tilm substrate typically consists of multilaycrs of power, ground, and signal conductors, isolated by dielectric layers, and is fabricatcd on either a passive or an active substratc. For applications where the conductor and dielectric layers are relatively thin, silicon substratc material can be used. Silicon offers thc advantagc of high thermal conductivity and perfect match of thermal expansion coetficient to silicon chips. It also offers the opportunity to havc built-in capacitors or even active devices. The drawback is its relatively poor mcchanical strength and toughness. Fracturing and cracking occur casily during sawing and assembly, especially with thick layers of thin tilm fabricated on top of it. Other suitablc substrate materials arc

MULTICI-IIP MODULES FOR HIGH PERFORMANCE COMPUTERS

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alumina, silicon carbide, aluminum nitride, and various metallic materials. For modules with high thermal dissipation and with cooling through the substrate, aluminum nitride and metallic materials (pure metal, alloy, or clad metals) offer good thermal conductivity. Two common choices of conductor material in interconnects are aluminum and copper. Aluminum is used because it is widely used as the metallization material in IC fabrication. The deposition and patterning technology is relatively mature. It is especially suitable where low line resistance is not a requirement and the conductor thickness is no more than a few microns. At MCC, copper was selected because of its low resistance, high thermal conductivity, and low cost. In addition, it can be pattern plated to form high density and high aspect ratio conductors and pillars, in order to achieve higher density and lower line resistivity. Polyimide is a commonly used interlayer dielectric and is used at MCC. The advantages are its low dielectric constant, high thermal and chemical stability, good planarization characteristics, and ease of processing for achieving the required dielectric thickness range for controlled impedance. The recently introduced low thermal coefficient of expansion (TCE) polyimide is especially beneficial for lowering the overall stress in the interconnect 9 to achieve better reliability. The MCC approach for interconnect fabrication has been presented elsewhere ~0. In addition to pattern plating of copper as mentioned earlier, this approach uses mechanical polishing to achieve true planarization and nickel overcoat to protect copper. Stacked pillars are able to be implemented due to the good planarization achieved by the polishing method. The stacked pillars not only enhance the interconnect density, but also serve as thermal pillars and anchors for bonding pads. Nickel overcoat around the plated copper together with the adhesion layer (chromium layer) under copper totally isolate the copper from polyimide and protect the copper from corrosion, oxidation, and interdiffusion. This greatly enhances the overall adhesion and reliability, and improves the conductor line resistance stability. Figure 2 shows part of a pillar string test structure after copper pattern plating

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and nickel overcoat. Pillars 18 pm tall and 18 tam square in size are plated on slightly larger pillar pads which arc connected to each other through 15 lam wide and 5 Bm thick conductor. After formation of this conductor and pillar pair. polyimide dielectric is spin coated over the substrate, and polishing is carried out to planarize the surface and to expose the top of pillars to connect to next layer of conductor. This process sequence is repeated to form the multilayer interconnect, l-igurc 3 shows a cross-sectional micrograph of a typical MCC interconnect fabricated on an alumina substratc. Electrical characterization of these interconnects has been carried out and is reported elsewhere ~~. The typical copper conductor lines are 15 Bm wide, 5 lain thick with a pitch of 50 I.tm and a dielectric thickness of 15 Bin. [ h e interconnect is measured to have less than 2 . 5 ~ c m ~ d.c. resistance, less than 70 pscm propagation delay, approximately 52 f2 characteristic impedance, and a saturated near-end cross-talk of 2.8"o for coupled strip lines.

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The three main bonding technologies appropriate for multichip modules are wire bonding, llip chip, and TAB. Each technology has certain advantages and disadvantages. Wire bonding is very flexible, easily adaptable and no chip-specific tooling is needed, ttowever, the achievable pitch for conventional wire bonding is limited to approximately 0.15mm and the wires add extra inductance to the interconnect. From an electrical point of view, flip chip offers superior performance. This is because mutual coupling between the interconnects is small owing to the very short electrical paths involved. There are several approaches to flip chip bonding. With C4 bonding, solder bumps on the chip align with appropriate metallic pads on the substrate and all connections are reflowed simultaneously. It is also possible to make use of conductive adhesives or gold bumps in a flip chip approach. Another advantage of flip chip is that the connections are not necessarily restricted to the periphery, and thus a large number of bonding pads can be placed under the chip,

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MULTICHIP MODULES FOR HIGH PERFORMANCE COMPUTERS

allowing chips to be placed side by side with very little gap. The main disadvantages with flip chip are possible fracturing of the chip resulting from differences in the TCE between the chip and substrate, and the difficulty with test and inspection. A key attribute of TAB is that it allows the devices to be tested and burned in prior to bonding on the substrate. That is, the devices are first inner lead bonded to tape frames which fan the leads out to large test points. After testing, the leads are excised and formed for the outer lead bonding operation. A second advantage of TAB is that the expected yield per bond is high, since the entire process can be automated and the beam leads have better mechanical integrity than conventional wire bonds. This is especially critical, since a multichip module may have 5000 or more individual bonds. TAB can be used with devices either face up or face down. An advantage of face-up TAB is that the devices can be cooled through the substrate. On the contrary, face-down TAB allows shorter TAB leads. It is important to minimize the lead length in order to reduce self- and mutual inductance which can adversely affect signal fidelity and cause power supply noise with simultaneously switched drivers. It is also possible to reduce lead inductance by using two-metallayer tape, by placing the outer lead bondpads on the same pitch as the inner lead pads to avoid fanout, or by using additional reference leads. The latter also reduces noise due to simultaneous switching. TAB, whether face up or face down, has significant performance advantages over wire bonding and allows reliable operation with signal rise time faster than 60-100 ps. Figure 4 shows a schematic drawing of a face-up TABed device on a copper polyimide interconnect.

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SYSTEM A S P E ( ' T S

Cooling, module connectors, environmental protection and module package are all application-dependent system issues. Workstations, supercomputers and avionics will require different solutions to these problems. Connection requirements for multichip modules can vary by at least an order of magnitude from 200 to 2000 l/Os. Conventional connector technologies are not easily adapted for use with high density multichip modules. Requirements include the need to transmit very fast signal rise times and to keep cross-talk amplitudes between neighboring lines small. Depending on the number of l/Os required and the general system configuration, either peripheral or array connections can be used. For two-dimensional packaging of multichip modules on a mother board high l ( ) numbers can be achieved by area connectors which consist of up to about 2000 pins brazed to the bottom side of the module. This is the approach chosen for instance in the IBM 3081 Thermal Conduction Module 2 and the NEC SX2 Liquid Conduction Module ~z, which uses 2177 pins per module. For a 2.5-dimensional card cage type packaging scheme, which allows a smaller system volume, edge connectors need to be used. M C C has developed a flexible tape edge connector. f h i s connector is an extension of TAB technology using multilayer tape for impedance control and raised vias in the form ofgold-plated pads that serve as a demountable connection at one end. The other end of the tape can be permanently attached to the substrate by thermosonic or laser bonding. Environmental protection of the multichip module also depends on the system application. Military Standard type reliability can be demonstrated by sealing the multichip module into hermetic packages. ]'his additional packaging level will, however, contribute additional stress problems if the substrate has to be die attached to a different material, because of the large areas and the potential differences in TCEs. For instance, for silicon substrates static stresses have to be kept below 10 0(X) Ibfin 2 to avoid fracture, and the strain range needs to be less than 0.0005 to reduce fatigue s. For silicon-based substratcs aluminum nitride packages can provide a good match in TCE, for alumina-based modules Kovar packages are suitable candidates even though the glass feed-throughs are susceptible to thermal and mechanical shock damage. For commercial applications environmental protection can be provided by protective thin coatings such as silicone gels, epoxies, polyimides, or paralene. M C C has demonstrated the reliability of TAB on FR4 board using live parametric C M O S parts. The environmental and mechanical stress tests used included air-to-air temperature cyclcs (- 55 to + 125 C). liquid-to-liquid thermal shock ( 55 to + 125 C ) , high temperature s t o r a g e ( + 150 CI, biased parts at 85"o relative humidity at 85 C. moisture resistance ( -- 10 to + 65 C, 3". 100",, relative humidity), autoclave (121 C and 10ft',, relative humidity), random vibration (MilStd-883C, Method 2026-1A), mechanical shock (Mil-Std-883C. Method 2(X)2.3-A) and salt atmosphere (MiI-Std-883C, Method 1009.5A). Similar environmental stress tests are being carried out on fully fabricated multilayer interconnect. After the stress tests these parts were analyzed through visual inspection, parametric electrical testing, and cross-sectional examination. No degradation has been detected so far.

MULTICHIP MODULES FOR HIGH PERFORMANCE COMPUTERS

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The parts have been proven reliable even through thermal shocks to liquid nitrogen temperature. Given the reliability of the TAB process and the substrates, we expect the assembled multichip modules to exhibit excellent reliability. The approach to thermal management of multichip modules is a function of the overall system requirements and configuration. There are three basic approaches to removing the heat from a dense multichip module. (1) Thermal conduction through a high thermal conductivity substrate or a heat pipe to a remote location where the cooling system does not impact the circuit density. This can be done for instance through an edge connector to a cooled frame and is generally the preferred approach in avionics. (2) Natural or forced air convection across finned heat exchangers attached to the chips or the substrate. This approach is suitable for low and medium power modules. (3) Liquid-cooled cold plates. This method is necessary for high performance modules dissipating in excess of ! kW. This is the approach chosen in the IBM Thermal Conduction Module 2 and the NEC Liquid Conduction Module 12. In each case the heat can be taken out directly from the chips. The advantages of removing the heat directly from the chips include a reduced number of thermal interfaces. However, ifa single cold plate is to be used, a compliant interface between the individual chips and the cold plate needs to be devised in order to account for assembly tolerances. Through-substrate cooling eliminates the need for this compliant interface and also offers the advantage that hermetic protection of the chips is easier to achieve. Thermal vias through the interconnect structures can reduce the additional thermal resistance due to the substrate. The MCC planar approach to high density substrate fabrication allows the use of stacked vias to enhance the efficiency of the thermal vias.

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MCC has developed a family of efficient, compact air-cooled heat exchangers j 3. The principles of laminar flow were combined with novel heat sink designs to extend the range of applicability of air cooling. The resulting cooling systems rival the performance of liquid-cooled multichip modules. Figure 5 shows a photograph of one example of such a heat sink. The heat sink consists of a multitude of thin fins spaced by narrow channels. The dimensions at the top are approximately I cm by 3.5 cm. The air flow enters tit the top and exits through the lateral openings. The cooling air can be supplied by a plenum or impingemenl. This particular type of heat sink achieves a thermal resistance of less than 2 C W ~ power dissipated at an air flow rate of 2 ft "~min ~ and a pressure of().17 inH zO. With the help of such heat sinks a typical tubeaxial fan can remove about 500 W from a multichip module. This type of heat sink can be optimized either for single chips or for multichip modules. 5. ('()N('I.USI()N

Multichip modules using chip-on-board technology on very high density interconnects can improve the performance and the reliability of computer systems as a result of reduced interconnect length and elimination of one packaging level (single chip package). This technology requires the development of a multitude of packaging technologies and the integration of them. Through the last few years MCC has developed these technologies which include wafer bumping, multilayer copper/polyimide interconnect, high I/O TAB, high density connector, and cooling technology. High performance, good reliability, and manufacturability have been taken into account through the development process. Technology integration and reliability testing on test vehicles are being carried out. Results so far have been very encouraging. RIiFEREN('ES I 2 3 4 5 6 7 8 9 10 I[ 12 [3

D . R . Rcsnick. Proc. 2rid hst. C'm!L on .5"upcrc,,mputing, 1~87, Vol. 1. p. 153. A.J. Blodgett and I). R. Barbour, I B M J. Res./)er.. 26 (1982) 30. D.E. Pitkancn. J. P. Cummings and R. E. Acosta. SolidState Technol., 23 IOclober 1980), p. 141. R.J. Jenscn. J. P. Cummings and H. Vora, Proc. 34th Eh,ctronic Component Con/i. 1984, p. 73. M. Terasa'.~a, S. Minami and J. Rubin, Proceedings o / ' l S l t M .~vmp. on Microeh,ctronic,v. October 1983. p. 607. C" W. Ho. I'L.S'l Eh'ctronics Microslructure Science, Vol. 5. Academic Press, New York, 1982. p. 103. R . W . John,,on. Prin. Technical Program, N E P ( ' O N H/e,vt 89. Anaheim. (',4. March 6 ~. 1989, p. 655. J. l-'Iaggc, lEE Trans. Compon.. ttyhrids'. Manu/i Technol., 12 (2) (1989) 170. J, T. Pan and S. Pooh, Eh, ctronic Packaging Materials Science IV. Materials Research Society, Pittsburgh. PA, 1989, p. 27. J T. Pan, S. Poon and B. Nelson, Proc. 8th dnnu. hit. Electronics Packaging ConL. November 1987¢, p. 174. 1. C. Wang, S. Sommerfeld! and L. Smith, Proc. 6th VI,SI Multilevel hlterconnect Con/i, 1988, p. 252. T, Watari and H. Murano. Proc. IEEE Eh,ctronics Components C'onL. 1985, p. 192. C. Hilbert, S. Sommerfeldt. O. Gupta and D. Herrelt, Proc. 6th ,4nnu. IEEE Semiconductor l'hermal and Temperature Meast~remcnt ,~ymp. C~emitherm VII, 1990, p. 108.