- Email: [email protected]
Testability guidelines for multichip modules
Testability guidelines for muitichip modules Kenneth E Posse
Because of the advantages that they offer in clock rates, real-estate savings, power dissipation savings, weight etc., multichip modules are rapidly becoming a reality in commercial electronics. Solutions to the problems of handling and testing module components and to the fabrication of the modules themselves have pretty much been solved. However, before MCMs can become a reality, it will be necessary to solve the problems associated with the testing and repairing of modules. This article suggests a set of design guidelines which will minimize the probability of undetectable defects and maximize the probability of diagnosin# detectable defects. The guidelines revolve mainly around the IEEE 1149.1-1990 Test Access Port and Boundary-Scan Architecture standard as adopted by the IEEE. multichip modules IEEE 1149.1-1990 boundary scan design for testability digital testing
Multichip modules (MCMs, Figure 1) are rapidly becoming a reality in commercial electronics. Most of the design and manufacturing problems have been solved, and now it is only a matter of time before products built on this architecture begin to appear. Solutions to the construction of silicon and ceramic substrates in reasonable quantities - one of the difficulties which plagued the MCM process have pretty much been solved. New techniques for the handling and testing of bare dice (a requirement for achieving adequate MCM yields) appear very promising. Mounting technologies, such as wirebond, tape automated bonding (TAB) and flip-chip, have been perfected to the extent that is necessary to begin production of high quality modules (Figures 2 and 3). There is, however, one problem that has yet to be adequately explored: how to test the assembled modules. Multichip modules present a more or less unique set of difficulties to the test engineer: • Unless it is specifically provided for, access to the internal nodes of the module is not possible. Hewlett Packard (ompany, Manufacturing Test Division, PO Box 301, Loveland, ( o[olado 80537, USA. E~mail: posse(,, hpmtlx.lvld.hp.com Paper received: July 1992. Revised: 14 December 1 992
• Many of the module components will be quite expensive. Therefore, very accurate diagnosis of failures is necessary to preclude the possibility of damaging non-faulty components removed due to an inaccurate diagnostic. • Approximately 50% of the manufacturers considering the use of MCMs are doing so to achieve an improvement in performance (the goal of the other 50% is a reduction in the size, weight or power consumption of a product). Those designs attempting to achieve the ultimate in performance will require high-quality highspeed margin testing with diagnostics to verify that the module will function within its specifications, These three problems appear in virtually every discussion having to do with the testing of multichip modules. Unfortunately, there is no single, allencompassing test methodology which will solve these problems. There are, however, a number of test tools which are currently available, or which will soon be available, which a test engineer can employ and which, if properly used, will produce very high quality module yields. Most of these tools, however, require that the modules (and their components) adhere to architectural guidelines which have two goals: • Minimizing the probability of the occurrence of defects which cannot be adequately diagnosed given the restrictions imposed by MCMs • Maximizing the probability of the detection and accurate diagnosis of those defects which can be isolated. This paper will explore the guidelines and test techniques aimed at achieving these goals.
MODULE
TESTING
- AT SPEED
'Should my module be tested at-speed? Can I achieve good yields without having to go to the expense of a highspeed functional tester?'. These questions are asked of me at every conference and every presentation. Unfortunately, there are no easy answers. Whether it is possible to meet the yield requirements of a particular manufacturer without testing at-speed will depend on such things as the quality of the test of the MCM
0141-9331/93/050281-07 © 1993 Butterworth-Heinemann Ltd Vol "/7 No 5 7993
281
Figure 1. Photograph of a multichip module showing test pads around the edge of the substrate to provide testability access. (Photograph compliments of Hewlett Packard)
i Figure2. Photograph of an experimental multichip module. The device pictured alongside the module is a standard 20 pin DIP for size comparison. Note that there are no test pads provided on this module. (Photograph compliments of Hewlett Packard)
components, how well the destgn was margined, a~c~ other characteristics which are not under tile control oi the test engineer. It is possible, however, to present some guidelines which may be used in determining whether o~ not at-speed tests will solve a particular test problem. First, what is the purpose of an at-speed test? It is NO~ to determine whether or not a module produces the correct vector response; this can be done much more easily and inexpensively using i:ur~ctional test techniques which do not require high speed vector rates. It shcxHd also not be relied upon to detect spot defects (such a~ gate-oxide shorts, transistor sizing defects, particle defects etc.) which may be present on an individual ASI(. These should be caught at chip test, not at the module final tes~ Performance testing of a module is intended to determ me that the module will functiof~ within the design margirts (specifications) set by the designek rhis type of test, offer-~ termed 'margin testing', calls for file device t,:~ be nm a~ ~ome vector rate higher than wr ~uht be normally expel, te~i ~o as to detect and diagnose rho~e modules which ar~ marginal in their capability. To adequately achieve tilese goals requires th( following: • Fully descriptive simulation models for all devices ou the module. These provide a basis for the automatic creation of fault-isolation trees and fault dictionaries. For many ASICS, creating these models may prove to be a formidable task. • A pattern set which will uncover and propagate to an I/O pin a high percentage of stuck-at, bridging and delay faults. This will require a simulator capable (.ff resolving faults in these categories. Additionally, it should be pointed out that experience has shown that achieving a reasonable fault coverage (i.e., above 80% to 90%) under these circumstances is extremely difficult. • An at-speed functional test mechanism which i~ capable of monitoring the nodal activity o~1 the module and accurately diagnosing defects when they oc cur. This may be in the form of a tester utilizing some sort of probing mechanism ~s~c:h as a mi~ ro-probe, u~possibly a'sample-mode' prob( discussed later- ~)r,~ 'special silicon' device ~apable of monitoring ttr~-~ activity of internal nodes). It is important to point out here that not all performan(:{~ faults can be traced to a specific: defect. There is some finite probability that the manufacturing of a module will result in the selection of a die such that the accumulation of propagation delays through the dice will result in a failure. In this case, the problem will not be traceable to a single location. However, the solution to the problem may be as simple as replacing one of the ASICs in the offending path, but this cannot be guaranteed. The result, therefore, may be an inaccurate diagnosis coupled with an ineffective repair. This problem wili not occtm however, if the 'design margin' guideline discussed later in this paper is adhered to.
Figure 3. Close-up photograph of a portion of the previously pictured MCM showing the die attachment methods used on this module (wirebond and TAB). Note the difficulty in identifying and probing these nodes even using a microprobe. (Photograph compliments of Hewlett
Packard) 282
T I M I N G CONSTRAINTS FOR AT-SPEED DIAGNOSTICS At-speed defect accumulation of internal nodes. It algorithms which
diagnosis depends on the accurate data from the module outputs and is not appropriate here to discuss the perform the defect analysis beyond
&,licroptocessors and ,~icrosystems
noting that it requires the determination of PASS/FAIL on each node at a particular point in time for each vector. Therefore, it is necessary to specify exactly when each node (including the module outputs) should be probed. Some simulators are capable of providingthis information. However, there are accuracy problems associated with using this data. The simulator predicts at what point in time each node in a circuit will have 'good' data. The designer uses this information in determining when to apply a clock to latch this information into a device. The amount of time between the latest point in time at which a node's data becomes valid and when it is expected at a device's input is the timing margin for that node (Figure 4). This timing margin is very important in at-speed fault isolation because the exact point in time at which a node is strobed by the tester should be (more or less) in the middle of this margin. However, inaccuracies such as vector skew, clock synchronization, tester calibration etc., mean that the exact point at which the data is actually sampled is unknown. All that can be said is that it will occur at some time in a'window' of plus or minus some amount of time from the requested strobe point. If either edge of the window occurs outside of the timing margin, then an inaccurate diagnosis is possible (Figure 5). For this reason, if high-speed tests are required for a module, the timing margins for nodes should be designed with the probe model in mind. Incidentally, this argument holds true for any type of probing: hand-held, samplemode, E-beam etc. If the accuracy of the probe can be calculated, then the minimum timing margin for a node can be determined. Of course, in many cases, the required margin may not be acceptable to the design engineer, in which case it should be expected that an accurate diagnosis of at-speed tests will not be possible.
MODULE TESTING - MANUFACTURING
• Trace opens - these generally occur due to faulty
/ /
I
Figure 4. l he node timing margin is the time between the latest time at which the node data become valid until the earliest point at which the node data must be valid. Usually, this earliest point is determined by the setup time of the receivers connected to the node, and will be earlier than the clock edge
Vol 17 No 5 1992,
I I
~"
li
~ t rl r
I F t ill=tv
~vlrilc
~'j
Figure 5. The probe uncertainty window represents the uncertainty of exactly where the selected probe actually latched data. The uncertainty may be due to a number of system-dependent characteristics and may not be straightforward in its determination. For example, in addition to the maximum + / - skew of the probe clock, the system clock jitter and the system-to-probe clocking skew will also play a part in the calculation
•
DEFECTS
Besides the functional testing of modules at high vector rates, it will also be necessary to verify the module against typical manufacturing defects. The faults which are induced at module fabrication will be easier to diagnose than performance defects since this type of failure is static in nature. Typical defects in this category are:
I
I
•
•
•
attachment of the die (or encapsulated die) to the substrate. Trace shorts - if the substrate has been adequately designed and tested prior to its use, these defects will typically result from a faulty attachment of the die (cr encapsulated die) to the substrate. Typical shorts are due to solder bridges between pads, (ross bonding of a wirebond, etc. Improper device orientation - frequently dice are symmetrical; therefore, it is possible to insert them into a circuit in two or more orientations. Damaged die - the handling of unpackaged or encapsulated dice may result in electrical or mechanical damage to the device. Wrong component - since many dice look alike and are typically not marked, the insertion of an improper component will, from time to time, occur.
Therefore, it will be the responsibility of the tester to properly detect and diagnose these conditions whenever they occur. The traditional method for diagnosing these problems calls for access to all nodes by the tester. However, providing physical access to all internal nodes of a multichip module is not practical. Even if it were practical, the expense of doing so and the effects on performance of pads large enough to grant simultaneous access to all nodes would be undesirable. Therefore, it will be necessary to provide nodal 'access' through some other mechanism. The most usable and practical of these mechanisms is the IEEE 1149-1990 Boundary-Scan and Test Access Port Standard (boundary-scan for short). This standard, adopted by the IEFEin 1990, calls for the incorporation of a state machine (called the test access port, or TAP for short) and certain shift-register type latches into the designs of ASICs. These shift-register latches grant access to, among other things, the device's
28?,
input and output pins through the use of four pins on the device. Since the standard allows all devices so equipped to be 'chained' together, it is possible to gain visibility into the internal nodes of a module via four module I/O pins ", If all of the devices on a module are provided with the boundary-scan capability, it is possible to accurately diagnose all shorts and opens which might occur. Additionally, if the components are provided with two ot the optional requirements of the standard (IDCODE and RUNBIST), it is possible to verify that the circuit is free from defects in any of the five categories listed abow~.
TESTABILITY FOR NON-BOUNDARY-SCAN DEVICES
i............ ] ........
i
i
i
•
!............ ]
If it is not practical to expect every component of a module to contain boundary-scan, it is still possible to provide tests for the scan-less devices. To see how this is possible, consider the following classifications of circuitry: I. A category I circuit (or sub-circuit) is one whose node connections are only to boundary-scan devices. II. A category II circuit (or sub-circuit) is one whose nodes are either directly accessible (via a module I/O or test point) OR whose nodes contain at least one boundary-scan connection and one or more nonboundary-scan connections (Figure 6). Ill. A category III circuit (or sub-circuit) is one whose nodes are not directly accessible AND have only nonboundary-scan connections (Figure 7).
TDO M C M Substrate
Figure 6. Illustration of a Category II circuit: the non boundary-scan device has inputs and outputs which are all directly accessible or accessible via the boundary-scan chain. If the test vectors are properly serialized, the device may be tested even though all of its circuit nodes are not accessible * I t is n o t p r a c t i c a l
t o d i s c u s s t h e IEEE 1 1 4 9 . 1 - 1 9 9 0
standard
in this article.
Readersunfamiliar with the capability of this standard are referred to the references section for suggested reading.
284
....
I
Figure 7. Illustration of a Category III circuit. Note thai the centre device has nodes which are not accessible via either the primary M C M I / 0 pins or a boundary-scan chain. However, this device is a component in a larger circuit which is, itself, a Category, I1 circuit. By using the means for testing category II circuits, the inaccessible device may be indirectly verified. In these cases, it is appropriate to utilize a simulator to predict the fault coverage for the internal (Category 111)nodes [ h e testing of category I circuits has already been carefully considered in the preceding section. Here, the testing of category II and category III circuits will b~~ discussed. All of the nodes in a category II circuit are accessible either directly, or from a boundary-scan device. Therefore, it is possible to develop a test for the structure (device or subcircuit) whose inputs and outputs are in category II. For those nodes which are directly accessible, the appropriate vector information may be applied directly to the node. For those nodes whose access is only via a boundary register, the bit pattern for each vector may be shifted in via the shift register chain to the appropriate cell in the chain and then applied, together with the directly accessible nodes, as the YAP is passed through the UPDATE-DR state. In this manner, a test may be constructed which will verify the proper functioning of the circuit. The absence of any defect in the five categories may be inferred from the proper operation of the circuit assuming an appropriate pattern set is chosen. Category III circuits seem to pose a unique problem until one realizes that several category Ill subcircuits may be combined to form a single category II circuit. The single category II circuit so constructed may then be simulated using stuck-at and bridging fault models to verify against the defects listed in the preceding section.
MODULE ARCHITECTURAL GUIDELINES Now, in order to make use ot the testability method~ discussed earlier, it is necessary to construct the module and its components according to the following guidelines:
Micropr(~( essors and Microsystem~
I. The substrate should have been previously tested for shorts and opens. Additionally, the interconnections should be kept at a reasonable width. While most of today's substrates utilize line widths of 25/~m or larger, there is some experimentation being done with line widths on the order of 5 pm or less. With widths in this range, spot defects which are not detectable may occur. This may induce failures which cannot be adequately diagnosed at final assembly. The 25/Jm and 5 pm limits are somewhat arbitrary, however. The frequency and size of spot defects is process-dependent, but, in virtually all cases, the greater the trace widths, the lower is the probability that such a defect will affect circuit performance. Spot defects in narrow-width interconnections may cause an increase in trace resistance which will be undetectable by all but the most sophisticated substrate tests in use for production testing today. Additionally, wider traces are more resistant to mechanical stresses caused by differences in the thermal coefficients of trace and substrate material. II. ASIC gate counts should be kept as low as is practicable. Recent evidence suggests that, no matter how thorough the chip test may be, the more complicated the ASIC circuitry, the more the likelihood of undetected defects occurring. Therefore, it may be appropriate to utilize chip sets rather than attempting extremely complex circuits on a single die. On a module, the performance of chip sets should be comparable to that of the same circuit integrated onto a single piece of silicon, but the improvement in chip quality levels will result in better module testability and fewer module failures. III. ASIC pad drivers should be well margined and should be designed to accommodate the capacitance of any tester probing which is planned without a degradation in propagation delay. This is especially important in those situations where test pads are provided for internal node probing during high-speed (margin) testing. A failure to adhere to this guideline may mean that probe-induced failures may occur.
VII. All ASIC outputs which are to be connected to category II nodes or which are to be connected to nodes containing only one boundary-scan input should be designed with the two-cell bidirectional boundary-scan capability. The addition of the input cell will cost little in propagation delay, but will greatly enhance the diagnostic accuracy. The extra receiver cell provides a means for performing a shorts test on category II nodes. It also provides a means for verifying driver activity on those nodes connected to only one device input. The ability to perform this verification gives the diagnostic system the ability to differentiate between a short to power (or ground) and an open in the interconnection between the pins. VIII. All ASICs with bused outputs should be provided with three-state control cells in the boundary register. Additionally, multiple control cells should be provided to disable drivers which are in separate logical pin groups. For example, providing a single cell which disables both the address and data buses of a microprocessor is not as desirable as providing a single cell for each of the logical groups (one cell for address, one cell for data). A failure to do this may result in some potential faults not being detectable. For example, if two outputs on a single device are bused together and cannot be independently disabled, then an open circuit on either output cannot be detected (Figure 8). IX. All module primary I/O pins should have boundaryscan access. This requirement does not actually affect module testability, but will provide for an easy method of determining if the module has been properly inserted into the circuit for which it was designed.
TDO MCM Subst.~'~.te
IV. All ASICs should have performance and parametric tests performed on them at chip test. This should include IDDQ testing (where possible). It is very important to ensure that the quality levels of ASICs destined for MCM fabrication be very high (S00 ppm or better has been suggested by a number of MCM manufacturers as being a minimum requirement). V. All designs should be well margined with probe windowing requirements accounted for where required. All designs should utilize worst-case timing simulations for specifying design margins. VI. All ASICs should be designed with the IEEE 1149.1-1990 standard and should include the optional IDCODE (USERCODE where appropriate) and RUNBIST capability. These features will allow for the verification of interconnections between devices, the verification that the correct devices have been inserted into the circuit, and the verification of basic device functionality without requiring access to the internal circuit nodes of the module. Studies have shown that the additional realestate and costs are well offset by the savings in testability for these designs.
Vol / 7 No 5 1993
TDI
Figure 8. This figure illustrates the 'disable dilema'. If the two devices connected to the boundary-scan device are to be tested, the boundary-scan device must have two of its outputs disabled while the others are in use providing input stimulus to the circuit under test. This will not be possible if all of the boundary-scan device's outputs are disabled by the same control cell
285
X. If a backtrace-style fault isolation method is to be used for the isolation of performance defects, all devices on the module should respond to a single system clock. That clock should not pass through any on-module logic save a clock distribution network if one is required. All devices should be clocked from the same phase of the system clock (i.e. if the clock is distributed, the design should provide that all of the clock lines go through the same number of stages in the network). The detection of delay defects in assembled circuits requires that the test system be capable of very precise positioning of the datacapture strobe with respect to the system clock. While it is possible to calibrate out any deterministic skew between the system clock and the sample clock used for capturing node data, it is not possible to calibrate out phase noise. Therefore, anything which affects the uncertainty in the relationship between the system clock and the data capture strobe should be avoided. If these guidelines are followed, and if the module designers will work with the test engineering departments in providing testability for MCMs, then it is possible to achieve a high module yield with the test equipment and methodologies available today. In the preceding sections, discussions of performance and manufacturing defect testing and module architectures have been presented. The remainder of this article will be dedicated to a discussion of two performance test methodologies which are currently under investigation. These hold some promise, but the reader is cautioned that a full analysis of each is not yet available.
S A M P L E - M O D E FAULT ISOLATION One of the requirements of the IEEE 1149.1-1990 standard calls for a SAMPLE instruction to be provided. This instruction will cause the inputs and outputs of all devices in the chain to latch the node data without interfering with the normal operation of the ASIC. This means that the state of all nodes which are boundary-scan accessible could be determined at any given point in time by latching the node state using the SAMPLE instruction. The implication is that a high-speed test could utilize this 'sample-mode probe' in place of a physical micro-probe in the determination of node state information. The most accurate method of isolating defects during the functional testing of a circuit is the backtrace fault isolation technique. This method requires that the state of all of the nodes in the circuit be determined for each vector executed during a functional test. This is most often accomplished using a probe placed on each node in turn as requested by the backtracing software. In the case of multichip modules, however, the nodes internal to the module may not be physically accessible. Additionally, even if access is available, the capacitance of the probe may alter the circuit performance in an undesirable manner. Both of these problems can be solved through the use of a boundary-scan sample-mode probe. There are two difficulties with this approach, however. The first is that in order to get the information, the functional test must be repeated N times, where N is the number of vectors to be applied. For example, if there are 20 000 vectors in the test, it will be necessary to repeat the test 20 000 times for each node to be accessed in this way. This is due to the fact that a complete node state picture must be had for all 20 000 vectors, but the chain is
286
capable of storing only 1 bit per SAMPLE before then being scanned out. Therefore, to get a picture of 20 000 vectors, the test must be re-executed 20 000 times. This must be done for every node which is to be examined in this manner. The time required to perform this task for a test running at 50 MHz is relatively insignificant and is certainly less than the amount of time required for manual probing (especially using a microprobe). The second problem, however, is much more significant. The TAP clock (TCK) does not go directly to the boundary-register cells. Instead, it goes to the TAP which, in turn, redistributes it to the boundary register in the CAPTURE state. Therefore, there is a delay between when the TCK is presented to the test access port and when the boundary register actually latches the data. This delay cannot be directly calibrated out (as can the delay associated with a physical probe) since this strobe delay will vary from ASIC to ASIC (and therefore, from node to node). Therefore, it is extremely important that this delay be specified by the chip designer so that it can be accounted for by adjusting the calibration timing constants. It is equally important that the tolerances for the strobe be very tight so as not to add too much uncertainty to the data strobe. This is because this 'latch uncertainty' must be added to the other sources of strobe error, but the total probe window must not become too wide to be effective.
SPECIAL SILICON NODE STATE MONITOR For those systems with a microprocessor controller on the module, it is possible to create a self-diagnosing test using the processor to perform the tests. This requires an on-module ASIC designed to accumulate node state data from all of the nodes in the MCM and to make this data available to the controller. This can be done using an ASIC designed to accumulate CRC information. The controller can, after executing a special 'TEST' program, scan out this information and examine it for failing nodes. In this way, a reasonably accurate diagnosis can be had for the entire circuit which is accessible by the 'Special Silicon Monitor' (Figure 9). However, as with sample mode probing, there are problems with this technique. First, CRC accumulation can provide an accurate diagnosis only if there are no feedback loops in the circuit. Therefore, if fault isolation is desired in addition to fault detection, either the feedback loops must be broken or else a less accurate diagnosis must be accepted. Additionally, the problem associated with timing of the latch exists here; in fact, it is amplified by the fact that it is not practical to provide separate timing for each node. Therefore, it may not be possible to detect performance defects accurately using this method. Nevertheless, because of the advantages of a selfdiagnosing module, this technique is under investigation and may prove to be very useful in the future.
SUMMARY Testability is always a problem, but the multichip module takes these difficulties to the extreme. It is now clear that in order to provide adequately for MCM testing, it will be necessary to coordinate the MCM design with the
Microprocessors and Microsystems
TDO
FASTRACE' Hewlett PackardJ. (March 1979) pp 8-13 3 Andrews, M 'Building infrastructure for commodi W multichip modules' Hybrid Circ. Technol. (October 1990) pp 58-61
4 Kessler, J, Kreisl, F, Pflug, G, Rauh, H and Tannhauser, R 'Multichip module testing' Siemens Forsch. Entwickl.-Ber. Vo117 No 5 (1988) pp 259-262
5 Fritzemeier, R R, Nagle, H T and Hawkins, C F 'Fundamentals of testability - a tutorial' IEEE Trans. Indust. Electron. Vo136 No 2 (May 1989) pp 117-128 6 Soden, I M and Hawkins, F 'Electrical properties and detection methods for CMOS IC defects' Proc. IEEE 1st European Test Conference (1989) pp 159-167 7 Syrzycki, M 'Modeling of spot defects in MOS transistors' Proc. IEEE International Test Conference (1989) pp 148-157
8 Maxwell, P C, Aitken, R C, lahansen, V and Chiang, I
TD!
~t~b[Uty
Device
Figure 9. The lower device in the centre of this circuit is designed to provide visibility into the interior of Category III circuits. It contains nothing more than CRC accumulators which can be read out upon command. In this illustration, the accumulators are readable via the boundary-scan chain and thus are accessible by a tester connected to the M C M primary I / 0 pins. However, it is just as likely that such a device would be used to provide node state information to an on-board microprocessor for the purpose of providing self-diagnostic ability
selected tester capabilities so as to architect a proper module test. In the long run, this should not seem so strange, but the tendency to place the responsibility for circuit test entirely on the shoulders of the test engineer must now be replaced with a cooperative effort between the product designers and testers. If this close cooperation exists, and a few simple guidelines are followed, testable MCMs can be produced with little difficulty. This will require design compromises, however. The MCM holds a great deal of promise for yielding faster, smaller and lighter products which require less power to operate. The promise will not be realized, though, unless adequate testing technology is applied to the development of these devices.
REFERENCES 1 Maxwell, P C, Aitken, R C, Johansen, Vand Chiang, I 'The effectiveness of IDDQ, functional and scan tests: how many fault coverages do we need?' Proc. IEEE International Test Conference (1992) pp 168-177 2 Groves, W A 'Rapid digital fault isolation with
Vol 17 N o 5 1993
9
10
11
12
13
14
'The effect of different test sets on quality level prediction: when is 80% better than 90%' Proc. IEEE International Test Conference (1991) Hilla, S C 'Boundary scan testing for multichip modules' Proc. IEEE International Test Conference (1992) pp 224-231 IEEE Standard Test Access Port and Boundary-Scan Architecture, Institute of Electrical and Electronic Engineers (21 May 1990) Maunder, C M and Tulloss, R E The Test Access Port and Boundary Scan Architecture, IEEE Computer Society Press (1990) Parker, K P and Oresja, $ 'A language for describing boundary-scan devices' Proc. IEEE International Test Conference (1990) pp 222-234 Wagner, P T 'Interconnect testing with boundaryscan' Proc. IEEE International Test Conference (1987) pp 52-57 Ballew, W g and $treb, L M 'Board-level boundaryscan, regaining observability with an additional IC' Proc. IEEE International Test Conference (1989) pp 182-189
15 Bula, O, Maser, J, Trinka, J, Weissman, M and Woytowich, F 'Gross delay defect evaluation for a CMOS logic design system product' IBM J. Res. Dev. Vol 34 No 2/3 (March/May 1990) pp 325-338 16 Parker, K P The Boundary-Scan Handbook, Kluwer Academic Publishers, Boston (1992)
Ken Posseis currentlyan R&D engineerwith the Hewlett PackardManufacturing Test Division in Loveland, Colorado, USA.He has been with HP for 20 years,the last 10 of which havebeenat the Loveland facility. Ken is ( urrenrly involved in researching the design of test equipment associated with diagnosing MCM faults. Ken received his BS in aerospace engineering from the University of Michigan and his MS in computer science and engineering from the National Technological University.
287
Because of the advantages that they offer in clock rates, real-estate savings, power dissipation savings, weight etc., multichip modules are rapidly becoming a reality in commercial electronics. Solutions to the problems of handling and testing module components and to the fabrication of the modules themselves have pretty much been solved. However, before MCMs can become a reality, it will be necessary to solve the problems associated with the testing and repairing of modules. This article suggests a set of design guidelines which will minimize the probability of undetectable defects and maximize the probability of diagnosin# detectable defects. The guidelines revolve mainly around the IEEE 1149.1-1990 Test Access Port and Boundary-Scan Architecture standard as adopted by the IEEE. multichip modules IEEE 1149.1-1990 boundary scan design for testability digital testing
Multichip modules (MCMs, Figure 1) are rapidly becoming a reality in commercial electronics. Most of the design and manufacturing problems have been solved, and now it is only a matter of time before products built on this architecture begin to appear. Solutions to the construction of silicon and ceramic substrates in reasonable quantities - one of the difficulties which plagued the MCM process have pretty much been solved. New techniques for the handling and testing of bare dice (a requirement for achieving adequate MCM yields) appear very promising. Mounting technologies, such as wirebond, tape automated bonding (TAB) and flip-chip, have been perfected to the extent that is necessary to begin production of high quality modules (Figures 2 and 3). There is, however, one problem that has yet to be adequately explored: how to test the assembled modules. Multichip modules present a more or less unique set of difficulties to the test engineer: • Unless it is specifically provided for, access to the internal nodes of the module is not possible. Hewlett Packard (ompany, Manufacturing Test Division, PO Box 301, Loveland, ( o[olado 80537, USA. E~mail: posse(,, hpmtlx.lvld.hp.com Paper received: July 1992. Revised: 14 December 1 992
• Many of the module components will be quite expensive. Therefore, very accurate diagnosis of failures is necessary to preclude the possibility of damaging non-faulty components removed due to an inaccurate diagnostic. • Approximately 50% of the manufacturers considering the use of MCMs are doing so to achieve an improvement in performance (the goal of the other 50% is a reduction in the size, weight or power consumption of a product). Those designs attempting to achieve the ultimate in performance will require high-quality highspeed margin testing with diagnostics to verify that the module will function within its specifications, These three problems appear in virtually every discussion having to do with the testing of multichip modules. Unfortunately, there is no single, allencompassing test methodology which will solve these problems. There are, however, a number of test tools which are currently available, or which will soon be available, which a test engineer can employ and which, if properly used, will produce very high quality module yields. Most of these tools, however, require that the modules (and their components) adhere to architectural guidelines which have two goals: • Minimizing the probability of the occurrence of defects which cannot be adequately diagnosed given the restrictions imposed by MCMs • Maximizing the probability of the detection and accurate diagnosis of those defects which can be isolated. This paper will explore the guidelines and test techniques aimed at achieving these goals.
MODULE
TESTING
- AT SPEED
'Should my module be tested at-speed? Can I achieve good yields without having to go to the expense of a highspeed functional tester?'. These questions are asked of me at every conference and every presentation. Unfortunately, there are no easy answers. Whether it is possible to meet the yield requirements of a particular manufacturer without testing at-speed will depend on such things as the quality of the test of the MCM
0141-9331/93/050281-07 © 1993 Butterworth-Heinemann Ltd Vol "/7 No 5 7993
281
Figure 1. Photograph of a multichip module showing test pads around the edge of the substrate to provide testability access. (Photograph compliments of Hewlett Packard)
i Figure2. Photograph of an experimental multichip module. The device pictured alongside the module is a standard 20 pin DIP for size comparison. Note that there are no test pads provided on this module. (Photograph compliments of Hewlett Packard)
components, how well the destgn was margined, a~c~ other characteristics which are not under tile control oi the test engineer. It is possible, however, to present some guidelines which may be used in determining whether o~ not at-speed tests will solve a particular test problem. First, what is the purpose of an at-speed test? It is NO~ to determine whether or not a module produces the correct vector response; this can be done much more easily and inexpensively using i:ur~ctional test techniques which do not require high speed vector rates. It shcxHd also not be relied upon to detect spot defects (such a~ gate-oxide shorts, transistor sizing defects, particle defects etc.) which may be present on an individual ASI(. These should be caught at chip test, not at the module final tes~ Performance testing of a module is intended to determ me that the module will functiof~ within the design margirts (specifications) set by the designek rhis type of test, offer-~ termed 'margin testing', calls for file device t,:~ be nm a~ ~ome vector rate higher than wr ~uht be normally expel, te~i ~o as to detect and diagnose rho~e modules which ar~ marginal in their capability. To adequately achieve tilese goals requires th( following: • Fully descriptive simulation models for all devices ou the module. These provide a basis for the automatic creation of fault-isolation trees and fault dictionaries. For many ASICS, creating these models may prove to be a formidable task. • A pattern set which will uncover and propagate to an I/O pin a high percentage of stuck-at, bridging and delay faults. This will require a simulator capable (.ff resolving faults in these categories. Additionally, it should be pointed out that experience has shown that achieving a reasonable fault coverage (i.e., above 80% to 90%) under these circumstances is extremely difficult. • An at-speed functional test mechanism which i~ capable of monitoring the nodal activity o~1 the module and accurately diagnosing defects when they oc cur. This may be in the form of a tester utilizing some sort of probing mechanism ~s~c:h as a mi~ ro-probe, u~possibly a'sample-mode' prob( discussed later- ~)r,~ 'special silicon' device ~apable of monitoring ttr~-~ activity of internal nodes). It is important to point out here that not all performan(:{~ faults can be traced to a specific: defect. There is some finite probability that the manufacturing of a module will result in the selection of a die such that the accumulation of propagation delays through the dice will result in a failure. In this case, the problem will not be traceable to a single location. However, the solution to the problem may be as simple as replacing one of the ASICs in the offending path, but this cannot be guaranteed. The result, therefore, may be an inaccurate diagnosis coupled with an ineffective repair. This problem wili not occtm however, if the 'design margin' guideline discussed later in this paper is adhered to.
Figure 3. Close-up photograph of a portion of the previously pictured MCM showing the die attachment methods used on this module (wirebond and TAB). Note the difficulty in identifying and probing these nodes even using a microprobe. (Photograph compliments of Hewlett
Packard) 282
T I M I N G CONSTRAINTS FOR AT-SPEED DIAGNOSTICS At-speed defect accumulation of internal nodes. It algorithms which
diagnosis depends on the accurate data from the module outputs and is not appropriate here to discuss the perform the defect analysis beyond
&,licroptocessors and ,~icrosystems
noting that it requires the determination of PASS/FAIL on each node at a particular point in time for each vector. Therefore, it is necessary to specify exactly when each node (including the module outputs) should be probed. Some simulators are capable of providingthis information. However, there are accuracy problems associated with using this data. The simulator predicts at what point in time each node in a circuit will have 'good' data. The designer uses this information in determining when to apply a clock to latch this information into a device. The amount of time between the latest point in time at which a node's data becomes valid and when it is expected at a device's input is the timing margin for that node (Figure 4). This timing margin is very important in at-speed fault isolation because the exact point in time at which a node is strobed by the tester should be (more or less) in the middle of this margin. However, inaccuracies such as vector skew, clock synchronization, tester calibration etc., mean that the exact point at which the data is actually sampled is unknown. All that can be said is that it will occur at some time in a'window' of plus or minus some amount of time from the requested strobe point. If either edge of the window occurs outside of the timing margin, then an inaccurate diagnosis is possible (Figure 5). For this reason, if high-speed tests are required for a module, the timing margins for nodes should be designed with the probe model in mind. Incidentally, this argument holds true for any type of probing: hand-held, samplemode, E-beam etc. If the accuracy of the probe can be calculated, then the minimum timing margin for a node can be determined. Of course, in many cases, the required margin may not be acceptable to the design engineer, in which case it should be expected that an accurate diagnosis of at-speed tests will not be possible.
MODULE TESTING - MANUFACTURING
• Trace opens - these generally occur due to faulty
/ /
I
Figure 4. l he node timing margin is the time between the latest time at which the node data become valid until the earliest point at which the node data must be valid. Usually, this earliest point is determined by the setup time of the receivers connected to the node, and will be earlier than the clock edge
Vol 17 No 5 1992,
I I
~"
li
~ t rl r
I F t ill=tv
~vlrilc
~'j
Figure 5. The probe uncertainty window represents the uncertainty of exactly where the selected probe actually latched data. The uncertainty may be due to a number of system-dependent characteristics and may not be straightforward in its determination. For example, in addition to the maximum + / - skew of the probe clock, the system clock jitter and the system-to-probe clocking skew will also play a part in the calculation
•
DEFECTS
Besides the functional testing of modules at high vector rates, it will also be necessary to verify the module against typical manufacturing defects. The faults which are induced at module fabrication will be easier to diagnose than performance defects since this type of failure is static in nature. Typical defects in this category are:
I
I
•
•
•
attachment of the die (or encapsulated die) to the substrate. Trace shorts - if the substrate has been adequately designed and tested prior to its use, these defects will typically result from a faulty attachment of the die (cr encapsulated die) to the substrate. Typical shorts are due to solder bridges between pads, (ross bonding of a wirebond, etc. Improper device orientation - frequently dice are symmetrical; therefore, it is possible to insert them into a circuit in two or more orientations. Damaged die - the handling of unpackaged or encapsulated dice may result in electrical or mechanical damage to the device. Wrong component - since many dice look alike and are typically not marked, the insertion of an improper component will, from time to time, occur.
Therefore, it will be the responsibility of the tester to properly detect and diagnose these conditions whenever they occur. The traditional method for diagnosing these problems calls for access to all nodes by the tester. However, providing physical access to all internal nodes of a multichip module is not practical. Even if it were practical, the expense of doing so and the effects on performance of pads large enough to grant simultaneous access to all nodes would be undesirable. Therefore, it will be necessary to provide nodal 'access' through some other mechanism. The most usable and practical of these mechanisms is the IEEE 1149-1990 Boundary-Scan and Test Access Port Standard (boundary-scan for short). This standard, adopted by the IEFEin 1990, calls for the incorporation of a state machine (called the test access port, or TAP for short) and certain shift-register type latches into the designs of ASICs. These shift-register latches grant access to, among other things, the device's
28?,
input and output pins through the use of four pins on the device. Since the standard allows all devices so equipped to be 'chained' together, it is possible to gain visibility into the internal nodes of a module via four module I/O pins ", If all of the devices on a module are provided with the boundary-scan capability, it is possible to accurately diagnose all shorts and opens which might occur. Additionally, if the components are provided with two ot the optional requirements of the standard (IDCODE and RUNBIST), it is possible to verify that the circuit is free from defects in any of the five categories listed abow~.
TESTABILITY FOR NON-BOUNDARY-SCAN DEVICES
i............ ] ........
i
i
i
•
!............ ]
If it is not practical to expect every component of a module to contain boundary-scan, it is still possible to provide tests for the scan-less devices. To see how this is possible, consider the following classifications of circuitry: I. A category I circuit (or sub-circuit) is one whose node connections are only to boundary-scan devices. II. A category II circuit (or sub-circuit) is one whose nodes are either directly accessible (via a module I/O or test point) OR whose nodes contain at least one boundary-scan connection and one or more nonboundary-scan connections (Figure 6). Ill. A category III circuit (or sub-circuit) is one whose nodes are not directly accessible AND have only nonboundary-scan connections (Figure 7).
TDO M C M Substrate
Figure 6. Illustration of a Category II circuit: the non boundary-scan device has inputs and outputs which are all directly accessible or accessible via the boundary-scan chain. If the test vectors are properly serialized, the device may be tested even though all of its circuit nodes are not accessible * I t is n o t p r a c t i c a l
t o d i s c u s s t h e IEEE 1 1 4 9 . 1 - 1 9 9 0
standard
in this article.
Readersunfamiliar with the capability of this standard are referred to the references section for suggested reading.
284
....
I
Figure 7. Illustration of a Category III circuit. Note thai the centre device has nodes which are not accessible via either the primary M C M I / 0 pins or a boundary-scan chain. However, this device is a component in a larger circuit which is, itself, a Category, I1 circuit. By using the means for testing category II circuits, the inaccessible device may be indirectly verified. In these cases, it is appropriate to utilize a simulator to predict the fault coverage for the internal (Category 111)nodes [ h e testing of category I circuits has already been carefully considered in the preceding section. Here, the testing of category II and category III circuits will b~~ discussed. All of the nodes in a category II circuit are accessible either directly, or from a boundary-scan device. Therefore, it is possible to develop a test for the structure (device or subcircuit) whose inputs and outputs are in category II. For those nodes which are directly accessible, the appropriate vector information may be applied directly to the node. For those nodes whose access is only via a boundary register, the bit pattern for each vector may be shifted in via the shift register chain to the appropriate cell in the chain and then applied, together with the directly accessible nodes, as the YAP is passed through the UPDATE-DR state. In this manner, a test may be constructed which will verify the proper functioning of the circuit. The absence of any defect in the five categories may be inferred from the proper operation of the circuit assuming an appropriate pattern set is chosen. Category III circuits seem to pose a unique problem until one realizes that several category Ill subcircuits may be combined to form a single category II circuit. The single category II circuit so constructed may then be simulated using stuck-at and bridging fault models to verify against the defects listed in the preceding section.
MODULE ARCHITECTURAL GUIDELINES Now, in order to make use ot the testability method~ discussed earlier, it is necessary to construct the module and its components according to the following guidelines:
Micropr(~( essors and Microsystem~
I. The substrate should have been previously tested for shorts and opens. Additionally, the interconnections should be kept at a reasonable width. While most of today's substrates utilize line widths of 25/~m or larger, there is some experimentation being done with line widths on the order of 5 pm or less. With widths in this range, spot defects which are not detectable may occur. This may induce failures which cannot be adequately diagnosed at final assembly. The 25/Jm and 5 pm limits are somewhat arbitrary, however. The frequency and size of spot defects is process-dependent, but, in virtually all cases, the greater the trace widths, the lower is the probability that such a defect will affect circuit performance. Spot defects in narrow-width interconnections may cause an increase in trace resistance which will be undetectable by all but the most sophisticated substrate tests in use for production testing today. Additionally, wider traces are more resistant to mechanical stresses caused by differences in the thermal coefficients of trace and substrate material. II. ASIC gate counts should be kept as low as is practicable. Recent evidence suggests that, no matter how thorough the chip test may be, the more complicated the ASIC circuitry, the more the likelihood of undetected defects occurring. Therefore, it may be appropriate to utilize chip sets rather than attempting extremely complex circuits on a single die. On a module, the performance of chip sets should be comparable to that of the same circuit integrated onto a single piece of silicon, but the improvement in chip quality levels will result in better module testability and fewer module failures. III. ASIC pad drivers should be well margined and should be designed to accommodate the capacitance of any tester probing which is planned without a degradation in propagation delay. This is especially important in those situations where test pads are provided for internal node probing during high-speed (margin) testing. A failure to adhere to this guideline may mean that probe-induced failures may occur.
VII. All ASIC outputs which are to be connected to category II nodes or which are to be connected to nodes containing only one boundary-scan input should be designed with the two-cell bidirectional boundary-scan capability. The addition of the input cell will cost little in propagation delay, but will greatly enhance the diagnostic accuracy. The extra receiver cell provides a means for performing a shorts test on category II nodes. It also provides a means for verifying driver activity on those nodes connected to only one device input. The ability to perform this verification gives the diagnostic system the ability to differentiate between a short to power (or ground) and an open in the interconnection between the pins. VIII. All ASICs with bused outputs should be provided with three-state control cells in the boundary register. Additionally, multiple control cells should be provided to disable drivers which are in separate logical pin groups. For example, providing a single cell which disables both the address and data buses of a microprocessor is not as desirable as providing a single cell for each of the logical groups (one cell for address, one cell for data). A failure to do this may result in some potential faults not being detectable. For example, if two outputs on a single device are bused together and cannot be independently disabled, then an open circuit on either output cannot be detected (Figure 8). IX. All module primary I/O pins should have boundaryscan access. This requirement does not actually affect module testability, but will provide for an easy method of determining if the module has been properly inserted into the circuit for which it was designed.
TDO MCM Subst.~'~.te
IV. All ASICs should have performance and parametric tests performed on them at chip test. This should include IDDQ testing (where possible). It is very important to ensure that the quality levels of ASICs destined for MCM fabrication be very high (S00 ppm or better has been suggested by a number of MCM manufacturers as being a minimum requirement). V. All designs should be well margined with probe windowing requirements accounted for where required. All designs should utilize worst-case timing simulations for specifying design margins. VI. All ASICs should be designed with the IEEE 1149.1-1990 standard and should include the optional IDCODE (USERCODE where appropriate) and RUNBIST capability. These features will allow for the verification of interconnections between devices, the verification that the correct devices have been inserted into the circuit, and the verification of basic device functionality without requiring access to the internal circuit nodes of the module. Studies have shown that the additional realestate and costs are well offset by the savings in testability for these designs.
Vol / 7 No 5 1993
TDI
Figure 8. This figure illustrates the 'disable dilema'. If the two devices connected to the boundary-scan device are to be tested, the boundary-scan device must have two of its outputs disabled while the others are in use providing input stimulus to the circuit under test. This will not be possible if all of the boundary-scan device's outputs are disabled by the same control cell
285
X. If a backtrace-style fault isolation method is to be used for the isolation of performance defects, all devices on the module should respond to a single system clock. That clock should not pass through any on-module logic save a clock distribution network if one is required. All devices should be clocked from the same phase of the system clock (i.e. if the clock is distributed, the design should provide that all of the clock lines go through the same number of stages in the network). The detection of delay defects in assembled circuits requires that the test system be capable of very precise positioning of the datacapture strobe with respect to the system clock. While it is possible to calibrate out any deterministic skew between the system clock and the sample clock used for capturing node data, it is not possible to calibrate out phase noise. Therefore, anything which affects the uncertainty in the relationship between the system clock and the data capture strobe should be avoided. If these guidelines are followed, and if the module designers will work with the test engineering departments in providing testability for MCMs, then it is possible to achieve a high module yield with the test equipment and methodologies available today. In the preceding sections, discussions of performance and manufacturing defect testing and module architectures have been presented. The remainder of this article will be dedicated to a discussion of two performance test methodologies which are currently under investigation. These hold some promise, but the reader is cautioned that a full analysis of each is not yet available.
S A M P L E - M O D E FAULT ISOLATION One of the requirements of the IEEE 1149.1-1990 standard calls for a SAMPLE instruction to be provided. This instruction will cause the inputs and outputs of all devices in the chain to latch the node data without interfering with the normal operation of the ASIC. This means that the state of all nodes which are boundary-scan accessible could be determined at any given point in time by latching the node state using the SAMPLE instruction. The implication is that a high-speed test could utilize this 'sample-mode probe' in place of a physical micro-probe in the determination of node state information. The most accurate method of isolating defects during the functional testing of a circuit is the backtrace fault isolation technique. This method requires that the state of all of the nodes in the circuit be determined for each vector executed during a functional test. This is most often accomplished using a probe placed on each node in turn as requested by the backtracing software. In the case of multichip modules, however, the nodes internal to the module may not be physically accessible. Additionally, even if access is available, the capacitance of the probe may alter the circuit performance in an undesirable manner. Both of these problems can be solved through the use of a boundary-scan sample-mode probe. There are two difficulties with this approach, however. The first is that in order to get the information, the functional test must be repeated N times, where N is the number of vectors to be applied. For example, if there are 20 000 vectors in the test, it will be necessary to repeat the test 20 000 times for each node to be accessed in this way. This is due to the fact that a complete node state picture must be had for all 20 000 vectors, but the chain is
286
capable of storing only 1 bit per SAMPLE before then being scanned out. Therefore, to get a picture of 20 000 vectors, the test must be re-executed 20 000 times. This must be done for every node which is to be examined in this manner. The time required to perform this task for a test running at 50 MHz is relatively insignificant and is certainly less than the amount of time required for manual probing (especially using a microprobe). The second problem, however, is much more significant. The TAP clock (TCK) does not go directly to the boundary-register cells. Instead, it goes to the TAP which, in turn, redistributes it to the boundary register in the CAPTURE state. Therefore, there is a delay between when the TCK is presented to the test access port and when the boundary register actually latches the data. This delay cannot be directly calibrated out (as can the delay associated with a physical probe) since this strobe delay will vary from ASIC to ASIC (and therefore, from node to node). Therefore, it is extremely important that this delay be specified by the chip designer so that it can be accounted for by adjusting the calibration timing constants. It is equally important that the tolerances for the strobe be very tight so as not to add too much uncertainty to the data strobe. This is because this 'latch uncertainty' must be added to the other sources of strobe error, but the total probe window must not become too wide to be effective.
SPECIAL SILICON NODE STATE MONITOR For those systems with a microprocessor controller on the module, it is possible to create a self-diagnosing test using the processor to perform the tests. This requires an on-module ASIC designed to accumulate node state data from all of the nodes in the MCM and to make this data available to the controller. This can be done using an ASIC designed to accumulate CRC information. The controller can, after executing a special 'TEST' program, scan out this information and examine it for failing nodes. In this way, a reasonably accurate diagnosis can be had for the entire circuit which is accessible by the 'Special Silicon Monitor' (Figure 9). However, as with sample mode probing, there are problems with this technique. First, CRC accumulation can provide an accurate diagnosis only if there are no feedback loops in the circuit. Therefore, if fault isolation is desired in addition to fault detection, either the feedback loops must be broken or else a less accurate diagnosis must be accepted. Additionally, the problem associated with timing of the latch exists here; in fact, it is amplified by the fact that it is not practical to provide separate timing for each node. Therefore, it may not be possible to detect performance defects accurately using this method. Nevertheless, because of the advantages of a selfdiagnosing module, this technique is under investigation and may prove to be very useful in the future.
SUMMARY Testability is always a problem, but the multichip module takes these difficulties to the extreme. It is now clear that in order to provide adequately for MCM testing, it will be necessary to coordinate the MCM design with the
Microprocessors and Microsystems
TDO
FASTRACE' Hewlett PackardJ. (March 1979) pp 8-13 3 Andrews, M 'Building infrastructure for commodi W multichip modules' Hybrid Circ. Technol. (October 1990) pp 58-61
4 Kessler, J, Kreisl, F, Pflug, G, Rauh, H and Tannhauser, R 'Multichip module testing' Siemens Forsch. Entwickl.-Ber. Vo117 No 5 (1988) pp 259-262
5 Fritzemeier, R R, Nagle, H T and Hawkins, C F 'Fundamentals of testability - a tutorial' IEEE Trans. Indust. Electron. Vo136 No 2 (May 1989) pp 117-128 6 Soden, I M and Hawkins, F 'Electrical properties and detection methods for CMOS IC defects' Proc. IEEE 1st European Test Conference (1989) pp 159-167 7 Syrzycki, M 'Modeling of spot defects in MOS transistors' Proc. IEEE International Test Conference (1989) pp 148-157
8 Maxwell, P C, Aitken, R C, lahansen, V and Chiang, I
TD!
~t~b[Uty
Device
Figure 9. The lower device in the centre of this circuit is designed to provide visibility into the interior of Category III circuits. It contains nothing more than CRC accumulators which can be read out upon command. In this illustration, the accumulators are readable via the boundary-scan chain and thus are accessible by a tester connected to the M C M primary I / 0 pins. However, it is just as likely that such a device would be used to provide node state information to an on-board microprocessor for the purpose of providing self-diagnostic ability
selected tester capabilities so as to architect a proper module test. In the long run, this should not seem so strange, but the tendency to place the responsibility for circuit test entirely on the shoulders of the test engineer must now be replaced with a cooperative effort between the product designers and testers. If this close cooperation exists, and a few simple guidelines are followed, testable MCMs can be produced with little difficulty. This will require design compromises, however. The MCM holds a great deal of promise for yielding faster, smaller and lighter products which require less power to operate. The promise will not be realized, though, unless adequate testing technology is applied to the development of these devices.
REFERENCES 1 Maxwell, P C, Aitken, R C, Johansen, Vand Chiang, I 'The effectiveness of IDDQ, functional and scan tests: how many fault coverages do we need?' Proc. IEEE International Test Conference (1992) pp 168-177 2 Groves, W A 'Rapid digital fault isolation with
Vol 17 N o 5 1993
9
10
11
12
13
14
'The effect of different test sets on quality level prediction: when is 80% better than 90%' Proc. IEEE International Test Conference (1991) Hilla, S C 'Boundary scan testing for multichip modules' Proc. IEEE International Test Conference (1992) pp 224-231 IEEE Standard Test Access Port and Boundary-Scan Architecture, Institute of Electrical and Electronic Engineers (21 May 1990) Maunder, C M and Tulloss, R E The Test Access Port and Boundary Scan Architecture, IEEE Computer Society Press (1990) Parker, K P and Oresja, $ 'A language for describing boundary-scan devices' Proc. IEEE International Test Conference (1990) pp 222-234 Wagner, P T 'Interconnect testing with boundaryscan' Proc. IEEE International Test Conference (1987) pp 52-57 Ballew, W g and $treb, L M 'Board-level boundaryscan, regaining observability with an additional IC' Proc. IEEE International Test Conference (1989) pp 182-189
15 Bula, O, Maser, J, Trinka, J, Weissman, M and Woytowich, F 'Gross delay defect evaluation for a CMOS logic design system product' IBM J. Res. Dev. Vol 34 No 2/3 (March/May 1990) pp 325-338 16 Parker, K P The Boundary-Scan Handbook, Kluwer Academic Publishers, Boston (1992)
Ken Posseis currentlyan R&D engineerwith the Hewlett PackardManufacturing Test Division in Loveland, Colorado, USA.He has been with HP for 20 years,the last 10 of which havebeenat the Loveland facility. Ken is ( urrenrly involved in researching the design of test equipment associated with diagnosing MCM faults. Ken received his BS in aerospace engineering from the University of Michigan and his MS in computer science and engineering from the National Technological University.
287