Nano-electromechanical random access memory (RAM) devices

13 Nano- electromechanical random access memory (RAM) devices W. KWON, University of California Berkeley, USA DOI: 10.1533/9780857098092.3.415 Abstract: Historically, our society requires computational memory media to support the development of our civilization. It is likely that our society will keep demanding larger capacity memory. However, conventional memory technologies are facing many challenges such as difficulties of miniaturization and guarantee of good reliability. Therefore, alternative memory device designs are proposed to overcome these challenges. As a new concept of non-volatile memory technology, a nano-electro-mechanical (NEM) diode non-volatile memory cell design is proposed. This design eliminates the need of a selector device to form a cross-point array, by leveraging the gap closing actuator. The electro-mechanical diode cell design can be scaled to 20 nm minimum lateral dimension by following an appropriate scaling methodology in consideration of various practical and fundamental limits. Low-voltage (<2 V) and high-speed (sub-nanosecond) operation are projected using a calibrated analytical model as well as 3-D finite-element method simulation. These findings indicate that electro-mechanical diode technology is promising for high density storage beyond the limits of conventional flash memory technology. Key words: MEMS, non-volatile memory, cross-point memory array.

13.1

Introduction

As a non-volatile memory, Flash memory technology has evolved greatly over the past few decades. In the last ten years, lithography enabled a significant size reduction, going down from 100 nm to 19 nm half pitch and the memory capacity has doubled every generation. The memory cell size reduction has been key to increasing storage capacity while lowering cost per bit. To date, 128 Gbit density NAND Flash memory with 170 mm2 chip size is available1 and the price per GigaBite (GB) is lower than $1.2 The achievements in Flash memory technology have helped to enable a revolution in information technology applications, such as smartphones and Tablet PCs. However, fundamental scaling limitations for Flash memory cell operating voltages and the physical thickness of the tunneling dielectric layer pose a significant challenge for continued scaling in the sub-20-nm regime.3

415 © 2014 Elsevier Ltd

416

Advances in Non-volatile Memory and Storage Technology

A lot of alternative memory device designs and new materials have been proposed to overcome the scaling limits in conventional Flash memory technology. Various cross-point memory architectures appear as one of the most attractive successors to the current Flash technology, because they not only allow for the most compact storage with 4F2 cell layout size (where F is the minimum half-pitch), but also can be fabricated using a relatively simple process that is more amenable to 3D integration. Programmable resistance devices such as phase-change memory4 and resistive RAM5 have been explored for cross-point memory application. However, there are intrinsic drawbacks of purely passive cross-point architecture, such as parasitic leakage paths in unselected cells and series resistance of the interconnections. These drawbacks hinder achieving the high density array of the cross-point due to requiring large sensing circuits, lowering the memory-array efficiency and reducing the maximum allowable array size. To resolve these issues, integrating with a selection device such as diodes or transistors in series with the memory cell has been investigated. However, these approaches demand additional complicated process steps and lower sensing current. Recently, a nano-electro-mechanical (NEM) non-volatile memory cell design that eliminates the need for a selector device by leveraging the hysteretic behavior of a mechanical gap-closing actuator, was recently proposed and demonstrated.6 Although this design is well suited for a cross-point array architecture, it requires separate read and write word lines as well as an initial ‘forming’ step (charging of a dielectric layer) to achieve non-volatile operation. To overcome these disadvantages, a simpler electro-mechanical memory cell design is proposed and demonstrated.7,8

13.2

Device structure and cell operation

Figures 13.1(a and b) illustrate the cell structure and the array layout of electromechanical diode memory. The bit lines (BLs) are formed on the insulating substrate and the word lines (WLs) are formed over the bit lines. The WLs and BLs are formed in different types (n-type or p-type) of semiconductor layer. Initially, the WLs are physically separated from the BLs by an air gap at each cross-point, so that no current can flow between these lines through the cell initially. This array conFiguration can achieve the most efficient cell layout area of 4F2. The circuit schematic of an electro-mechanical diode memory array is shown in Fig. 13.2. When the selected cell (in the dashed circle) is in the Set state and all other cells are in the Reset state, the Set state cell forms a p-n diode and provides a rectifying current-vs-voltage characteristic, while the Reset state cells are in an electrically-open-state. Exemplary operating voltage conditions for Set, Reset and Read operations are listed in Table 13.1. Figure 13.3(a) illustrates the Set operation; the pull-in voltage (Vpull-in) is the minimum voltage for actuating the WL into contact with the BL. Thus, to cause a memory cell to be programmed into the Set state, a voltage pulse (Vset) is applied

Nano- electromechanical random access memory devices

417

13.1 (a) Schematic cross- section of the electro- mechanical diode cell (parallel to the word line); (b) schematic plan view of the electromechanical diode memory array.

Table 13.1 Exemplary voltage conditions for Set, Reset and Read operations. The selected word line (WL’) and selected bit line (BL’) are biased to achieve Set, Reset and Read operations

WL’ (selected) BL’ (selected) WL (unselected) BL (unselected)

Set

Reset

Read

0V VSet > Vpull-in (Floating) 0V

0V VReset < Vrelease (Floating) 0V

Vread >0V 0V 0V (Floating)

418

Advances in Non-volatile Memory and Storage Technology

13.2 Circuit schematic of an electro-mechanical diode memory array.

between its WL and BL to induce an attractive electrostatic force that is sufficiently larger than the pull-in voltage (Vpull-in). In order for the Set state to be retained during a Hold operation (i.e. when no voltage is applied), the built-in electrostatic force (Felect in Fig. 13.3(b)) together with the surface adhesion force (Fadhesion in Fig. 13.3(b)) in the Set state must be larger than the spring restoring force (Fspring in Fig.13.3(b)) in the Set state. The state of a cell is determined by sensing the BL current when a Read voltage is applied between its WL and BL (Fig. 13.4(a)). If the cell is in the Reset state, no current flows through (Fig.13.4(b)); only leakage current (through parasitic paths) can flow. If the cell is in the Set state, a much larger forward diode current flows through. A Reset operation is shown in Fig. 13.5. To cause a memory cell to be erased into the Reset state, a voltage pulse (Vreset) is applied between its WL and BL to counteract the built-in electrostatic force of the p-n diode (Fig. 13.5(a)). When the sum of Felect and Fadhesion becomes smaller than Fspring, the spring restoring force of

Nano- electromechanical random access memory devices

419

13.3 (a) Illustration of the Set operation. When Vset is applied on the bit line (BL), the word line (WL) is pulled down to the BL by electrostatic force. (b) Illustration of the Hold operation. The Set state is sustained by a sum of electrostatic force (Felect ) caused by space charges in the depletion region and surface adhesion force (Fadhesion ) between WL and BL materials; Fspring < Felect + Fadhesion .

the WL beam pulls it out of contact with the BL (Fig. 13.5(b)). After a Reset operation, the cell state is maintained due to a sufficiently stiff beam.

13.3

Fabrication process for a prototype cell

The process used to fabricate the first prototype electro-mechanical memory array is illustrated in Fig. 13.6; to form an isolation layer, 100 nm Al2O3 is coated on the silicon wafer by an Atomic Layer Deposition (ALD) tool at 350 °C. A phosphorus in-situ doped poly-Si (at 550 °C, 100 nm, 85Ω/□) layer is deposited onto the insulating substrate (Al2O3), followed by a sacrificial oxide (LPCVD oxide 30 nm) deposition at 450 °C. After making photo resistor patterns of lines, the reactive ion etch (RIE) cuts into the oxide and poly-Si layer to form bit lines. A siliconnitride (SiNx) is deposited over the bit lines, and the SiNx etch process forms

420

Advances in Non-volatile Memory and Storage Technology

13.4 (a) Illustration of the Read operation in the Set state. The Read current flows through the p-n junction when a forward bias (Vread ) is applied on the word line. (b) Illustration of the Read operation in the Reset state. No current flows between the bit line (BL) and the word line (WL).

silicon-nitride spacers along the BLs; the silicon-nitride spacers provide anchor of the WLs beam and also electrical isolation between WLs and BLs. A boron in-situ-doped poly-Si0.4Ge0.6 deposition (100 nm, 300Ω/□) is deposited as the WLs material. After making photo resistor patterns of perpendicular lines to the BLs, the RIE cuts into the poly-Si0.4Ge0.6 layer and forms the WLs. Finally, the sacrificial oxide is selectively removed by vapor HF, which leaves air gaps between the BLs and WLs. Scanning electron microscopy (SEM) images are shown in Figs 13.7 and 13.8. A bird’s-eye view shows that the functional 4 μm × 4 μm cells are successfully fabricated in Fig. 13.7. The cross-sectional view shows the sacrificial oxide layer thickness (12.7 nm); the as-fabricated gap thickness between BL (n-type poly-Si) and WL (p-type poly-Si0.4Ge0.6) is approximately 13 nm.

Nano- electromechanical random access memory devices

421

13.5 (a) Illustration of the Reset operation. As a forward bias (Vreset ) is applied on the p-n junction, the built-in electrostatic force decreases. When the sum of the electrostatic force and the adhesion force is smaller than the spring restoring force, the spring restoring force pulls the WL beam out of the BL. (b) Illustration of the cell state after the Reset operation. The cell state (i.e. Reset state) is maintained due to a sufficiently stiff beam after a Reset operation.

13.3.1 Electrical measurement of the prototype cell Figure 13.9 shows the BL current changes of a prototype cell during a Set operation. A sudden increase in current at the pull-in voltage (Vpull-in = 6.2 V) is observed when the WL is pulled in to contact the BL. Since it is an applied voltage (not current) that is required to actuate the WL, the Set current can be lowered by inserting a current-limiting resistance (1 MΩ) in series with the BL driver (Fig. 13.7), to reduce the energy consumed by the Set operation. Figure 13.10 shows the transient response of the WL voltage during a Set operation. The measured set time for the prototype cell is approximately 2 μs for a Set voltage of 14 V. To ‘Hold’ the Set state without applied voltage, the attraction forces (i.e. the summation of electrostatic force (Felect) and adhesion force (Fadhesion)) between the

422

Advances in Non-volatile Memory and Storage Technology

13.6 Key process steps for fabricating the prototype electromechanical diode memory array: (a) n-type poly-Si and sacrificial oxide (LTO) layers deposition on the isolation oxide (Al2O3 ); (b) bit lines formation by photo lithography and reactive ion etch (RIE); (c) silicon nitride (PECVD SiNx) deposition; (d) spacer formation; (e) p-type poly-Si0.4Ge 0.6 deposition and WL formation; and (f) sacrificial oxide removal by vapor HF.

Nano- electromechanical random access memory devices

423

13.7 Bird’s eye SEM view of the fabricated electro-mechanical diode array. The working prototype memory cell size is 4 μm × 4 μm.

13.8 Cross- sectional SEM image of the fabricated electro- mechanical diode before sacrificial oxide removal by vapor HF. Since the oxide thickness is 12.7 nm, the gap thickness after releasing poly-Si0.4Ge 0.6 in vapor HF is ~13 nm.

424

Advances in Non-volatile Memory and Storage Technology

13.9 Measured Set operation hysteric I-V curves of a prototype electro-mechanical diode cell as the bit line voltage is swept from 0 V to 8 V and 8 V to 0 V. After inserting a current- limiting resistance (1 MΩ ), the current can be lowered to reduce the power consumption of the Set operation.

13.10 Measured transient voltages of WL and BL during Set operation of a prototype electro-mechanical diode cell. A step pulse of voltage is given on the BL and the voltage on WL is monitored by an oscilloscope. When the WL touches the BL, the WL voltage increases rapidly at 2 μ sec.

Nano- electromechanical random access memory devices

425

13.11 Simulated energy-band diagram and electric-field profile within a p-n junction in the Set state with VBL = 0 V and V WL = 0 V (Hold state). It is relevant to the prototype cell’s doping condition.

WL and the BL has to be larger than the spring restoring force (Fspring) of the WL beam. The electrostatic force is caused by built-in space charges in the deletion region of the p-n diode. Finite element method simulation9 is used for the prototype cell to calculate Felect. Figure 13.11 shows the simulated energy band diagram and electric field profile for a p-n junction of the prototype cell and it gives the value of Felect to be 70.5 μN. Since the calculate Fspring is only 4.22 μN from another finite element method simulation,10 the Set state is retained when the external voltage (i.e. the actuation voltage) is removed The state of a cell is determined by sensing the BL current when the Read bias voltage is applied between its WL and BL. If the cell is in the Reset state, no current flows through; only leakage current flows through the SiNx spacers in the cell. On the other hand, if the cell is in the Set state, a much larger current flows through the forward-biased p-n junction. Figure 13.12 shows measured I-V curves (linear scale and log scale of currents) in the Set and Reset state; a very high Set/ Reset current ratio (>106) is seen. Figure 13.13 shows how the BL current of the prototype cell changes during a Reset operation. An abrupt drop in current at the release voltage (Vrelease = −6.2 V) is seen when the WL is released from the BL and goes back to the Reset state. It should be noted that the release voltage is larger than the flat band voltage (~1 V in

426

Advances in Non-volatile Memory and Storage Technology

13.12 (a) Measured I-V curves for Read operation of a prototype electro-mechanical diode cell. A cell in the Set state shows a typical p-n diode curve (black curve), whereas only leakage current is shown in the Reset state cell (grey curve); and (b) measured log- scaled I-V curves for Read operation of a prototype electro-mechanical cell.

Nano- electromechanical random access memory devices

427

13.13 Measured I-V curve for Reset operation of a prototype electromechanical diode cell. The bit line voltage is swept from 0 V to −8 V to increase forward-bias on the p-n junction.

13.14 Measured Reset time of a prototype electro- mechanical diode cell, where the bit line voltage is −7 V and the word line voltage is 0 V (a forward bias condition on the p-n junction).

428

Advances in Non-volatile Memory and Storage Technology

13.15 Illustration of the p-n junction (contacting surfaces) of the electro-mechanical diode.

ideal case) of a p-n diode in a forward bias condition. The large release voltage is caused by the voltage drop on the WL and BL. Since the thickness of the WL beam is thin, the resistance of the WL is too large, which results in a large voltage drop on the WL rather than the p-n junction. To reduce these voltage drops on the external resistance, a metallic WL material, or shunting it with a metal layer, can be usable. From transient measurements, the reset time for the prototype cell is approximately 100 ms for a Reset voltage of −7 V (Fig. 13.14). The longer reset time possibly can be explained by the contact opening model presented in,11 the restoring spring force reduces the number of bonds between the contacting surfaces (Fig. 13.15); only when the number of bonds is sufficiently small, can contact opening occur. The contact opening time therefore depends on the number of bonds formed between the contacting surfaces, and can be reduced with scaling (to reduce the contact force and apparent contact area) and/or an appropriate surface treatment.

13.3.2 Suppression of sneak leakage currents in the cell array A key requirement for implementation of a cross-point memory array is the suppression of the unwanted ‘sneak’ leakage currents through unselected cells in the array. These leakages can sum to a sufficiently high current to result in an erroneous Read operation.12 The size of the cross-point array is therefore limited by the ratio of the selected cell current to the summation of the leakage currents of unselected cells in the Set state during a Read operation;13 the larger this ratio, the larger the array size. The sneak leakage current through unselected cell in the Set state is almost equal to the diode current in a reverse-biased condition, which is one-half the forward-bias read voltage (VWL,READ) for an optimally designed sense amplifier for a resistive cross-point memory array. Thus, the ratio of the forward-bias Set cell current at VWL,READ to the reverse-bias Set cell current at –VWL,READ/2, ‘the rectification ratio’, is a key parameter to determine cross-point array size.

Nano- electromechanical random access memory devices

429

13.16 Measured diode I-V curves of electro- mechanical diode cell of poly-Si word line case with post annealing conditions.

Table 13.2 Measured electro- mechanical diode characteristics for different p-type WL materials and post- deposition annealing conditions P-type WL material

Non-ideal factor

Rectification ratio

Poly-Si0.4 Ge 0.6 (410 °C) Poly-Si (610 °C) with 950 °C, 1 hr anneal Poly-Si (610 °C) with 1050 °C, 1 hr anneal

5~8 3.0

50 103

1.7

10 4

The rectification ratio of the prototype cell is approximately 300 for VWL,READ = 1.2 V. It can be enhanced by increasing the work-function difference between the WL and BL materials and by improving crystalline quality of the semiconductor materials. Figure 13.16 shows the demonstrated experiment results of p-type poly-Si as the WL material and adding a thermal anneal step. Table 13.2 also shows the ideal factor and rectification ratio changes of the p-n diode curves of each p-type poly-Si process condition; since the p-type poly-Si has a larger work function than p-type poly-Si0.4Ge0.6, the rectification ratio has been improved almost three times. Furthermore, the rectification ratio is improved greatly and the diode curve is getting close to the ideal diode curve, due to the thermal annealing step for increasing average grain size improving.

430

Advances in Non-volatile Memory and Storage Technology

13.17 Measured retention behavior of a prototype electro- mechanical diode cell in the Set state (circles) and the Reset state (squares) in the high temperature condition (200 °C).

13.18 Measured endurance characteristics of a prototype electromechanical diode cell in the Set state (circles) and the Reset state (squares).

Nano- electromechanical random access memory devices

13.4

431

Assessing cell reliability

In order to investigate the basic reliability of the prototype cell, data retention and endurance are measured. Since surface adhesion force and electrostatic force hold a diode memory cell in the Set state, the prototype cell shows very long retention time in Fig. 13.17; negligible changes in conductance for the Set and Reset states are seen at 200 °C, which well exceeds the normal operating temperature range for CMOS. As the electro-mechanical diode does not rely on charge storage in a floating-gate/ charge-trap layer or a material phase change to store data, it has more robust retention behavior than other NVM technologies. Moreover, it opens the possibility for new applications that demand very high (>150 °C) temperature operating. Figure 13.18 shows that the prototype cell is multi-time programmable (MTP), with endurance exceeding 104 Set/Reset cycles. The endurance of an electromechanical device can be very high if it is properly designed. For example, the endurance of a micro-electro-mechanical switch has been shown to exceed 109 on/off cycles.14 A potential reliability concern for mechanical devices is vibration or mechanical shock. But because of the extremely small mass (3.73 picogram for the prototype devices in this work) of the WL beam within a cell, a very large acceleration (108 G) would be needed to accidentally Set a cell or to overcome the attraction forces in the Set state (4 μN for the prototype devices in this work) to Reset a cell. This is far beyond the acceleration requirement (~20 000 G) for automotive environments.15

13.5

Device scaling

A shrinking device area is required for high storage density memory application. For the scaling of electrostatically actuated beams, a constant-field scaling methodology is used.16 Also, to achieve non-volatility in the Hold state (i.e. without an external bias, the built-in electrostatic force (Felect), the Set state has to be larger than the spring restoring force (Fspring) in the Set state. Following this methodology, the beam thickness and actuation gap thickness should be scaled down together with the lateral dimensions of the beam, to reduce the Set voltage (i.e. Vpull-in) and operation energy. Since there is a practical limit for beam thickness scaling, alternative structural materials with lower Young’s modulus can be used to reduce beam stiffness. Projected pull-in voltages for nanometer-scale diode memory cells are shown in Table 13.3. These were calculated using Finite-Element-Method software10 and for various conductive structural materials with lower Young’s modulus, for example TiNi alloy17 and carbon nanotube (CNT);18 note that the scaling of beam length is legged behind the beam with scaling, because the restoring force (the spring force) increases greatly. Thus, the device area becomes larger than 4F2. Table 13.4 shows the performances and cell size comparisons between the scaled electro-mechanical diode cell and the current and emerging non-volatile memory cells around 20 nm technologies.19 The electro-mechanical diode technology shows

432

Advances in Non-volatile Memory and Storage Technology

Table 13.3 Design and calculated performance characteristics of scaled electromechanical diode memory cells Technology Cell size Beam width Beam length F2 Structural material Young’s modulus Beam thickness Actual gap thickness Set voltage Set time Energy for set operation

4 μm 64 μm2 4 μm 4 μm 4 F2 Poly-SiGe 140 GPa 100 nm 35 nm (*13 nm) 7.0 V 2 us 2.6 × 10 −13 J

40 nm 0.0064 μm2 40 nm 40 nm 4 F2 TiNi 14 GPa 5 nm 3 nm

20 nm 0.0016 μm2 20 nm 30 nm 6 F2 TiNi 14 GPa 4 nm 2 nm

10 nm 0.0008 μm2 10 nm 20 nm 8 F2 CNT 5 GPa 3 nm 2 nm

3.5 V 0.38 ns 7.8 × 10 −17 J

2.4 V 0.27 ns 2.7 × 10 −17 J

2.1 V 0.12 ns 5.4 × 10 −18 J

Table 13.4 Comparison of scaled electro-mechanical diode technology with current and emerging technologies at 16 nm technology generation in reference 19 Technology

NAND Flash

PCM

Redox RRAM

Electromechanical diode device

Effective cell size (per bit)

2.5 F2

4 ~ 6F2

5 ~ 8 F2

4 ~ 6 F2

Minimum F-scaling

16 nm

5 ~ 10 nm

5 ~ 10 nm

20 nm

Write voltage

18 ~ 20 V

3V

< 0.5 V

2.4 V

Write speed

>10 nsec

50 ~ 120 nsec

<20 nsec

0.27 nsec

Retention

10 yrs at 85°C 10 yrs at 85°C 10 yrs at 85° > 10 yrs at ~ 4 days at 125°C < 1 day at 125°C ~ 2 days at 125°C 200°C

Endurance

10 4 ~ 10 5

1015

1016

>10 4

Programming > 1 fJ energy per bit

< 2pJ

1 fJ

0.03 fJ

Ease of integration

2 ~ 3 Masks to BEOL

2 ~ 3 Masks to BEOL

2 Masks

10 Masks

advantages, including compatible cell size, simplest process, good retention (even at high temperature) and lowest energy consumption for programming. Therefore the electro-mechanical diode potentially can be a good candidate for non-volatile memory solution beyond the limitations of other technologies.

13.6

Conclusion

A new electro-mechanical diode memory cell is proposed for the cross-point nonvolatile memory array application. The first prototype cell demonstrates the basic

Nano- electromechanical random access memory devices

433

idea with relatively low Set/Reset voltages. It also shows excellent retention behavior and multi-time programmable exceeding 104 cycles, so that this design shows promise for compact and low power operating non-volatile storage applications in the future.

13.7

References

1. Li, Y. et al. (2012), ‘128 Gb 3b/Cell NAND Flash memory in 19 nm technology with 18MB/s write rate and 400 Mb/s toggle mode’, Solid-State Circuits Conference Digest of Technical Papers (ISSCC). 2. 64 Giga bit NAND Flash price on: www.dramexchange.com [accessed 1/28/2013]. 3. Koh, Y. (2009), ‘NAND Flash scaling beyond 20 nm’, International Memory Workshop. 4. Wong, H.-S.P., Raoux, S., Kim, S., Liang, J., Reifenberg, J.P. et al. (2010), ‘Phase change memory’, Proc. IEEE, 98(12): 2201–27. 5. Akinaga, H. and Shima, H. (2010), ‘Resistive random access memory (ReRAM) based on metal oxides’, Proc. IEEE, 98(12): 2237–51. 6. Choi, W.Y., Kam, H., Lee, D., Lai, J. and Liu, T.-J.K. (2007), ‘Compact nano-electromechanical non-volatile memory (NEMory) for 3D integration’. IEDM Tech. Dig., 603–6. 7. Kwon, W., Jeon, J., Hutin, L. and Liu, T.K. (2012), ‘Electro-mechanical diode memory cell design for cross-point memory arrays’, IEEE Electron Device Letters, 33(2). 8. Kwon, W., Hutin, L. and Liu, T-J.K. (2012). ‘Electro-mechanical diode performance and scaling for cross-point non-volatile memory array’, International Memory Workshop (IMW). 9. Sentaurus Ver. A-2008.09, SYNOPSYS. 10. CoventorWare™ Ver. 2008. 11. Jensen, B.D., Huang, K., Chow, L.L.-W. and Kurabayashi, K. (2005), ‘Adhesion effects on contact opening dynamics in micromachined switches’, Journal of Applied Physics, 97: 103535. 12. Liang, J. and Wong, H.-S.P. (2010), ‘Cross-point memory array without cell selectors: device characteristics and data storage pattern dependencies’, IEEE Transaction on Electron Devices, 57: 2531. 13. Flocke, A. and Noll, T.G. (2007), ‘Fundamental Analysis of Resistive Nano-Crossbars for the Use in Hybrid Nano/CMOS-Memory’, International Solid-State Circuits Conference Digest, 328. 14. Kam, H., Pott, V., Nathanael, R., Jeon, J., Alon, E. et al. (2009), ‘Design and reliability of a micro-relay technology for zero-standby-power digital logic applications’, IEEE IEDM Technical Digest. 15. Automotive Electronic Council (2007), AEC-Q100-Rev-G, 14 May. 16. Chen, F., Kam, H., Markovic, D., Liu, T-J.K., Stojanovic, V. et al. (2008), ‘Integrated circuit design with NEM relays’, ICCAD, p. 750. 17. Lee, D., Osabe, T. and Liu, T-J.K. (2009), ‘Scaling limitations for flexural beams used in electromechanical devices’, IEEE Transactions on Electron Devices, 56: 688. 18. Acquavia, D. et al. (2010), ‘Capacitive nanoelectromechanical switch based on suspended carbon nanotube array’, Applied Physics Letters, 97: 233508. 19. Assessment of the Potential and Maturity of Selected Emerging Research Memory Technologies Workshop and ERD/ERM Working Group Meeting, 6–7 April, ITRS.