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GaN HEMTs: Impact on current collapse
Solid-State Electronics 137 (2017) 1–5
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Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Neutral beam process in AlGaN/GaN HEMTs: Impact on current collapse Fuyumi Hemmi a,⇑, Cedric Thomas b, Yi-Chun Lai c, Akio Higo c, Yoh Watamura a, Seiji Samukawa b,c, Taiichi Otsuji a, Tetsuya Suemitsu a,⇑ a
Research Institute of Electrical Communication, Tohoku University, Japan Institute of Fluid Science, Tohoku University, Japan c Advanced Institute for Materials Research, Tohoku University, Japan b
a r t i c l e
i n f o
Article history: Received 30 June 2017 Accepted 25 July 2017 Available online 26 July 2017 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Neutral beam GaN Gate recess Current collapse HEMTs
a b s t r a c t In this paper, we report a promising approach for the gate recess process with a suppressed current collapse in GaN-based high electron mobility transistors (HEMTs) by means of neutral beam (NB). A recessed gate structure has been widely studied as a way to realize normally-off operation in GaN, InP, and GaAsbased HEMTs. Since GaN-based materials are usually etched by dry process, plasma-induced damage is a serious concern. NB is free from electrical charges and UV photons, resulting in an accurate control of etching depth and less plasma-induced damages. In this work, we introduce NB irradiation to the gate interface and measured DC and gate-pulsed output characteristics. The results suggest that NB is applicable for the gate recess etching with suppressing the current collapse. Ó 2017 Elsevier Ltd. All rights reserved.
1. Introduction AlGaN/GaN high electron mobility transistors (HEMTs) are promising for both high-power and high-frequency applications [1–6] because their two-dimensional electron gas (2DEG) has high saturation velocity, high mobility, and high carrier concentration. Moreover GaN has a high breakdown field. Although AlGaN/GaN HEMTs have many advantages, normally-off operation for GaN HEMTs is still a challenge. Normally-on operation of AlGaN/GaN HEMTs is caused by 2DEG under the gate electrode existing at zero gate bias. While various approaches for normally-off operation have been studied, for example, gate-recess [7–13], p-doped injection gates [14], fluorine-based treatments [15–18] and selective regrowth of cap layers [19,20], many of them suffer from plasma-induced damages [21]. In the gate-recess, normally-off operation is realized by removing the barrier layer by dry etching to reduce the 2DEG concentration under the gate electrode. The p-doped injection gate is realized by removing the p-doped layer out of the gate region by dry etching. These etching are typically done by inductively-coupled-plasma reactive ion etching (ICP-RIE) [7–11]. As an improved type of gate recess structures,
⇑ Corresponding authors. E-mail addresses: [email protected] (F. Hemmi), [email protected]. ac.jp (T. Suemitsu). http://dx.doi.org/10.1016/j.sse.2017.07.015 0038-1101/Ó 2017 Elsevier Ltd. All rights reserved.
hybrid MOS-HEMTs are proposed in which 2DEG under gate region is completely removed [12,13]. Generally speaking, the gate recess is considered as a simple approach without complicate process steps compared to other approaches. To solve the problem on the plasma-induced damages caused by the gate recess etching, we introduce neutral beam (NB) etching [22]. Fig. 1 shows the NB etching system. In the conventional ICP etching, UV photons included in plasma discharge can cause damages at etched surface [22–25], which become a cause of degradation of device characteristics [26,27]. To reduce such plasma damages, the NB etching system features a carbon aperture array between the ICP chamber and the etching chamber to filter out charged particles and UV photons in plasma. Thus NB becomes almost electrically uncharged and includes few UV photons when the aspect ratio of the carbon aperture (thickness/diameter) is sufficiently large, e.g., 10. We reported a reduction of isolation leakage current in AlGaN/GaN HEMTs by applying the NB etching to the mesa isolation process [28]. In this paper, we irradiated NB and the conventional plasma beam to the gate interface to observe its impact on plasma-induced damages through the appearance of the current collapse, which reduces the drain current right after the device is turned on from the pinched-off state under high operation voltages [29,30]. The current collapse is closely related to the deep levels that capture electrons and form a virtual gate in the channel [31]. The advantage of NB etching on the gate recess process in AlGaN/GaN HEMTs is dis-
2
F. Hemmi et al. / Solid-State Electronics 137 (2017) 1–5
Fig. 1. (a) Schematic of neutral beam etching system, and (b), (c) enlarged figures of carbon aperture array existing between the ICP chamber and the etching chamber. The aspect ratio is defined as the ratio of carbon thickness and diameter. (b) In aspect ratio = 10, charged particles are neutralized and UV photons are blocked during they pass through the carbon aperture. (c) In aspect ratio = 2, a large part of charged particles and UV photons are able to pass through the carbon aperture.
cussed by comparing the current collapse on the output characteristics. Since the plasma-induced damages depend on many parameters consisting of the etching system, it is difficult to make a fair comparison between different etching systems. Therefore we tried to compare the neutral beam etching and the conventional plasma etching in the same system. The carbon aperture array with an aspect ratio of 2 was prepared for this purpose so that the conventional plasma etching condition is intentionally produced in the neutral beam etching system. 2. Device fabrication The samples have a standard AlGaN/GaN HEMT heterostructure grown on a sapphire substrate as shown in Fig. 2(a). The epitaxial structure consists of a 15.6-nm-thick AlGaN barrier layer on a 2000-nm-thick GaN channel/buffer layer grown on a c-plane sapphire substrate. The mobility and concentration of the twodimensional electron gas are 1531 cm2/V s and 9.0 1012 cm 2 at room temperature, respectively. The devices fabrication started with source and drain ohmic metallization by Ti/Al/Ni/Au (20/120/20/70 nm) lift-off followed by mesa isolation, and then a 2-min ohmic annealing with a SiO2 protection coating was performed at 780 °C in N2 ambient. The mesa isolation was carried out by the NB etching system with two conditions; (i) NB with sufficient neutralization by choosing an aspect ratio of the carbon aperture of 10 (NB10) as shown in Fig. 1(b) and (ii) NB with insufficient neutralization by choosing an aspect ratio of 2 (NB2) as shown in Fig. 1(c). The NB10 and NB2 were carried out with Cl2 gas at 0.09 Pa and an RF power of 800 W. The etching rate in each
condition is shown in Table 1. Because NB2 includes plasma ion particles and UV photons which can damage the device surface, the beam condition of NB2 is close to that of ICP etching. After isolation, gate metallization divided the samples into 3-types: (i) simply deposited the gate metal as a reference, (ii) NB10 was irradiated for 30 s to the gate surface before the deposition of the gate metal, and (iii) NB2 was irradiated for 30 s to the gate surface instead (Fig. 2(b)-(c)). After that, Ni/Au (20/160 nm) was deposited to form gate electrode and samples were passivated with 200-nmthick SiN film by plasma-enhanced chemical vapor deposition at 250 °C. Then the SiN layer on the drain and source ohmic electrodes were removed by reactive ion etching (RIE) with SF6 to open the contact holes. Finally, Ti/Ni/Au (20/20/350 nm) pad electrodes were evaporated and lifted off for all types of samples. The process flow is illustrated in Fig. 3. 3. Results and discussion The surface morphology of the samples after the gate recess etching is observed by atomic force microscopy (AFM). Fig. 4 shows the AFM images of the samples etched with NB10 and NB2 conditions and an as-grown sample for comparison. The RMS (Root Mean Square) roughness was 0.088 nm for the as-grown sample, 0.452 nm for the NB10 sample, and 1.024 nm for the NB2 sample. The smoother etched surface is achieved by the neutral beam etching. The DC and pulsed Id-Vds characteristics are measured for the devices with a gate length of 3 mm. The DC characteristics are shown in Fig. 5. Comparing to the reference sample shown in
Fig. 2. Cross sectional views of (a) epitaxial layer structure, (b) reference sample without any irradiation under the gate, and (c) NB10/NB2 sample with NB10/NB2 irradiation under gate electrode.
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F. Hemmi et al. / Solid-State Electronics 137 (2017) 1–5 Table 1 NB irradiation parameters. Sample
Plasma power
Etching rate (AlGaN)
NB exposure
Carbon aspect ratio
Reference NB10 NB2
– 800 W 800 W
– 5 nm/min 7.5 nm/min
No 30 s 30 s
– 10 2
Fig. 3. Process flow.
Fig. 5(a), the devices irradiated to NB10 or NB2 exhibit a positive shift in the threshold voltage (Vth) as shown in Fig. 5(b) and (c), respectively, and the maximum of the drain current (Id_max) for NB10 and NB2 samples are decreased. The NB10 and NB2 samples exhibit a similar gate leakage current. The threshold voltage shift and the decrease in Id_max are depicted more clearly in the transfer characteristics shown in Fig. 5(d). These results indicate that the AlGaN layer was partly etched by NB and a shallow gate recess was formed. Table 2 lists the changes in Id_max, the maximum transconductance (gm_max), and Vth of devices. Comparing NB10 and NB2 samples, NB10 exhibits a positive shift of Vth with less degradation in Id_max and gm_max after gate recessing. Since the estimated recess depth is 3–4 nm, longer NB irradiation is promising to achieve normally-off characteristics. Fig. 6 shows the pulsed Id-Vds characteristics. The pulse width and the period are 250 ms and 1 ms, respectively. Two pulse
Fig. 4. AFM images of (a) as-grown substrate before fabrication (RMS = 0.088 nm), (b) NB10 etched sample (RMS = 0.452 nm), and (c) NB2 etched sample (RMS = 1.024 nm).
Fig. 5. DC Id-Vds characteristics of AlGaN/GaN HEMTs (a) without NB irradiation as a reference, (b) with NB10 irradiation, (c) with NB2 irradiation, and (d) transfer characteristics of these samples at a drain voltage of 5 V.
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F. Hemmi et al. / Solid-State Electronics 137 (2017) 1–5
Table 2 Transconductance and threshold voltage shifts in the samples. Samples
Id_max [mA/mm]
gm_max [mS/mm]
Reference NB10 NB2
430 367 332
120 112 101
Vth [V] 2.23 1.63 1.57
conditions are tested as illustrated in Fig. 6(d). In the first condition, the quiescent bias is set at 0 V for both gate and drain, namely, Vq,g = Vq,d = 0 V. In the second condition, Vq,g is set at 5 V, which is negative enough to pinch off the channel, to observe the gate lag while Vg,d is kept at 0 V. In the first pulse condition, Vq,g = Vq, d = 0 V, the Id-Vds characteristics of the three samples represent their DC characteristics as shown by the solid circle plots in Fig. 6(a)-(c). The slope of the Id-Vds curve in the linear region gives the on-state resistance (Ron). The Ron measured at a gate voltage of 1 V is 9.1, 10.1, 10.5 Xmm for the reference, NB10, and NB2 samples, respectively. The larger Ron in the NB10 and NB2 samples in comparison to the reference sample is ascribed to the reduced 2DEG concentration in the recessed region that increases the source/drain access resistance and the intrinsic channel resistance at a fixed gate voltage. When the second pulse condition, Vq,g = 5 V and Vq,d = 0 V, was applied, the output characteristics have been changed as shown by the open circle plots in Fig. 6(a)-(c). In the all three samples, Ron increases from the ones under the pulse condition 1 (Vq,g = Vq,d = 0 V): 9.6, 10.3, and 10.6 X mm for the reference, NB10, and NB2 samples, respectively. A significant difference in the increase in Ron was not observed. However, The NB2 sample exhibits a clear decrease in the drain saturation current at around
a drain voltage of 5 V when the pulse condition 2 was applied while the NB10 sample exhibits the drain saturation current independent of the pulse condition. The decrease in the drain saturation current in the NB2 sample should be a result of the gate lag because it became smaller as the pulse width increased from 250 to 750 ms. That is, the smaller pulse width is the severer condition for the 2DEG in the intrinsic gate region to recover from the pinchoff state. These results suggest that at least two different mechanisms play roles on the increase in Ron and the decrease in the drain saturation current observed in the pulsed Id-Vds characteristics. The former is observed regardless of the gate recess technique and the latter is observed in a particular sample using NB2 in the gate recess. Because NB2 includes plasma ionized particles and UV photons like the conventional ICP etching, this result suggests that the neutral beam etching has a clear advantage over the conventional ICP etching with respect to, at least, the suppression of the gate lag by reducing the plasma-induced damages by the gate recess etching. 4. Conclusion We experimentally confirmed that the neutral beam irradiation to the gate surface helps positive shift in the threshold voltage for AlGaN/GaN HEMTs with less degradation in the transconductance. Moreover, the current collapse caused by the interface traps at the gate electrode is successfully suppressed by the neutral beam with sufficient neutralization. These results suggest that the neutral beam gate recess etching in GaN-based HEMTs is a promising approach for normally-off AlGaN/GaN HEMTs with less current collapse.
Fig. 6. Pulsed Id-Vds characteristics of AlGaN/GaN HEMTs (a) without NB irradiation as a reference, (b) with NB10 irradiation, and (c) with NB2 irradiation. Gate voltage: 1 V top, 1 V step. (d) Quiescent gate and drain biases (Vq,g and Vq,d, respectively): (1) Vq,g = Vq,d = 0 V and (2) Vq,g = –5 V, Vq,d = 0 V.
F. Hemmi et al. / Solid-State Electronics 137 (2017) 1–5
Acknowledgements This work is supported by the JSPS KAKENHI grant 15K13963 and 16H04341. The device fabrication has been carried out at the Laboratory for Nanoelectronics and Spintronics, Tohoku University.
[19] [20]
[21]
References [22] [1] Shiohara K et al. Deeply-scaled self-aligned-gate GaN DH-HEMTs with ultrahigh cut off frequency. IEDM Tech Dig 2011;453. [2] Yue Y et al. InAlN/AlN/GaN HEMTs with regrown ohmic contacts and fT of 370 GHz. IEEE Electron Device Lett 2012;33:988. [3] Wang R et al. InGaN channel high-electron mobility transistors with AlGaN barrier and fT/fmax of 260/220 GHz. Appl Phys Express 2013;6:016503. [4] Arulkumaran S et al. Demonstration of submicron-gate AlGaN/GaN highelectron-mobility transistors on silicon with complementary metal–oxide– semiconductor-compatible non-gold metal stack. Appl Phys Express 2013;6:016501. [5] Suemitsu T et al. A new process approach for slant field plates in GaN-based high-electron-mobility transistors. Jpn J Appl Phys 2016;55:01AD02. [6] Kachi T. Recent progress of GaN power devices for automotive applications. Jpn J Appl Phys 2014;53:100210. [7] Saito W et al. Recessed-gate structure approach toward normally off highvoltage AlGaN/GaN HEMT for power electronics applications. IEEE Trans Electron Devices 2006;53:356–62. [8] Chu R et al. V-gate GaN HEMTs with engineered buffer for normally off operation. IEEE Electron Device Lett 2008;29:1184–6. [9] Maroldt S et al. Gate-recessed AlGaN/GaN based enhancement-mode high electron mobility transistors for high frequency operation. Jpn J Appl Phys 2009;48:04C083. [10] Schuette ML et al. Gate-recessed integrated E/D GaN HEMT technology with fT/ fmax > 300 GHz. IEEE Electron Device Lett 2013;34:741–3. [11] Wakejima A et al. Normally off AlGaN/GaN HEMT on Si substrate with selectively dry-etched recessed gate and polarization-charge-compensation ddoped GaN cap layer. Appl Phys Express 2015;8:026502. [12] Oka T et al. AlGaN/GaN recessed MIS-gate HFET with high-threshold-voltage normally-off operation for power electronics applications. IEEE Electron Device Lett 2008;29:668–70. [13] Kim K-W et al. Effects of TMAH treatment on device performance of normally off Al2O3/GaN MOSFET. IEEE Electron Device Lett 2011;32:1376–78. [14] Uemoto Y et al. Gate Injection Transistor (GIT)—a normally-off AlGaN/GaN power transistor using conductivity modulation. IEEE Trans Electron Devices 2007;54:3393–9. [15] Song D et al. Normally off AlGaN/GaN Low-density drain HEMT (LDD-HEMT) with enhanced breakdown voltage and reduced current collapse. IEEE Electron Device Lett 2007;28:189–91. [16] Chen W et al. Single-chip boost converter using monolithically integrated AlGaN/GaN lateral field-effect rectifier and normally off HEMT. IEEE Electron Device Lett 2009;30:430–2. [17] Chu R et al. 1200-V normally off GaN-on-Si field-effect transistors with low dynamic on-resistance. IEEE Electron Device Lett 2011;32:632–4. [18] Zhang Z et al. Normally off AlGaN/GaN MIS-high-electron mobility transistors fabricated by using low pressure chemical vapor deposition Si3N4 gate
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dielectric and standard fluorine ion implantation. IEEE Electron Device Lett 2015;36:1128–31. Yao Y et al. Normally-off GaN recessed-gate MOSFET fabricated by selective area growth technique. Appl Phys Express 2014;7:016502. Yang F et al. The suppression of background doping in selective area growth technique for high performance normally-off AlGaN/GaN MOSFET. J Mater Sci: Mater Electron 2015;26:9753–8. Su M et al. Prospects for the application of GaN power devices in hybrid electric vehicle drive systems. Semicond Sci Technol 2013;28:074012. Samukawa S. Ultimate top-down etching processes for future nanoscale devices: advanced neutral-beam etching. Jpn J Appl Phys 2006;45:2395–407. Kawakami R et al. Analysis of GaN etching damage by capacitively coupled RF Ar plasma exposure. Thin Solid Films 2008;516:3478–81. Kawakami R et al. Synergy effect of particle radiation and ultraviolet radiation from capacitively coupled radio frequency argon plasmas on n-GaN etching damage. Jpn J Appl Phys 2008;47:6863–6. Minami M et al. Analysis of GaN damage induced by Cl2/SiCl4/Ar plasma. Jpn J Appl Phys 2011;50:08JE03. Chong Wang et al. Breakdown voltage and current collapse of F-plasma treated AlGaN/GaN HEMTs. J Semicond 2014;35:014008. Asubar Joel T et al. Highly reduced current collapse in AlGaN/GaN highelectron-mobility transistors by combined application of oxygen plasma treatment and field plate structures. Jpn J Appl Phys 2016;55:04EG07. Hemmi F et al. Neutral beam etching for device isolation in AlGaN/GaN HEMTs. Phys Status Solidi A 2016;1–5. Hasegawa H et al. Mechanisms of current collapse and gate leakage currents in AlGaN/GaN heterostructure field effect transistors. J Vac Sci Technol B 2003;21:1844–55. Kobayashi K et al. Current collapse suppression in AlGaN/GaN HEMTs by means of slant field plates fabricated by multi-layer SiCN. Solid State Electro 2014;101:63–9. Vetury R et al. The impact of surface states on the DC and RF characteristics of AlGaN/GaN HFETs. IEEE Trans Electron Devices 2001;48:560–6.
Tetsuya Suemitsu received the B.S., M.S., and Ph.D. degrees from Waseda University, Tokyo, Japan, in 1992, 1994, and 2000, respectively, all in electrical engineering. In 1994, he joined Nippon Telegraph and Telephone Corporation (NTT), Japan, where he conducted research on high electron mobility transistors (HEMTs) based on indium phosphide (InP) and related materials. In 2002, he was a visiting scientist of the Microsystems Technology Laboratories at Massachusetts Institute of Technology (MIT), Cambridge, MA, USA. Since 2006, he has been with the Research Institute of Electrical Communication at Tohoku University, Sendai, Japan, as an associate professor. Dr. Suemitsu is a member of the Japan Society of Applied Physics, the Physical Society of Japan, the Institute of Electrical and Electronics Engineers (IEEE) and the American Physical Society. In 2003, he received the Best Paper Award from the Institute of Electronics, Information and Communication Engineers (IEICE). In 2007, he received the Best Paper Award of the Electronics Express (ELEX) from IEICE.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Neutral beam process in AlGaN/GaN HEMTs: Impact on current collapse Fuyumi Hemmi a,⇑, Cedric Thomas b, Yi-Chun Lai c, Akio Higo c, Yoh Watamura a, Seiji Samukawa b,c, Taiichi Otsuji a, Tetsuya Suemitsu a,⇑ a
Research Institute of Electrical Communication, Tohoku University, Japan Institute of Fluid Science, Tohoku University, Japan c Advanced Institute for Materials Research, Tohoku University, Japan b
a r t i c l e
i n f o
Article history: Received 30 June 2017 Accepted 25 July 2017 Available online 26 July 2017 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Neutral beam GaN Gate recess Current collapse HEMTs
a b s t r a c t In this paper, we report a promising approach for the gate recess process with a suppressed current collapse in GaN-based high electron mobility transistors (HEMTs) by means of neutral beam (NB). A recessed gate structure has been widely studied as a way to realize normally-off operation in GaN, InP, and GaAsbased HEMTs. Since GaN-based materials are usually etched by dry process, plasma-induced damage is a serious concern. NB is free from electrical charges and UV photons, resulting in an accurate control of etching depth and less plasma-induced damages. In this work, we introduce NB irradiation to the gate interface and measured DC and gate-pulsed output characteristics. The results suggest that NB is applicable for the gate recess etching with suppressing the current collapse. Ó 2017 Elsevier Ltd. All rights reserved.
1. Introduction AlGaN/GaN high electron mobility transistors (HEMTs) are promising for both high-power and high-frequency applications [1–6] because their two-dimensional electron gas (2DEG) has high saturation velocity, high mobility, and high carrier concentration. Moreover GaN has a high breakdown field. Although AlGaN/GaN HEMTs have many advantages, normally-off operation for GaN HEMTs is still a challenge. Normally-on operation of AlGaN/GaN HEMTs is caused by 2DEG under the gate electrode existing at zero gate bias. While various approaches for normally-off operation have been studied, for example, gate-recess [7–13], p-doped injection gates [14], fluorine-based treatments [15–18] and selective regrowth of cap layers [19,20], many of them suffer from plasma-induced damages [21]. In the gate-recess, normally-off operation is realized by removing the barrier layer by dry etching to reduce the 2DEG concentration under the gate electrode. The p-doped injection gate is realized by removing the p-doped layer out of the gate region by dry etching. These etching are typically done by inductively-coupled-plasma reactive ion etching (ICP-RIE) [7–11]. As an improved type of gate recess structures,
⇑ Corresponding authors. E-mail addresses: [email protected] (F. Hemmi), [email protected]. ac.jp (T. Suemitsu). http://dx.doi.org/10.1016/j.sse.2017.07.015 0038-1101/Ó 2017 Elsevier Ltd. All rights reserved.
hybrid MOS-HEMTs are proposed in which 2DEG under gate region is completely removed [12,13]. Generally speaking, the gate recess is considered as a simple approach without complicate process steps compared to other approaches. To solve the problem on the plasma-induced damages caused by the gate recess etching, we introduce neutral beam (NB) etching [22]. Fig. 1 shows the NB etching system. In the conventional ICP etching, UV photons included in plasma discharge can cause damages at etched surface [22–25], which become a cause of degradation of device characteristics [26,27]. To reduce such plasma damages, the NB etching system features a carbon aperture array between the ICP chamber and the etching chamber to filter out charged particles and UV photons in plasma. Thus NB becomes almost electrically uncharged and includes few UV photons when the aspect ratio of the carbon aperture (thickness/diameter) is sufficiently large, e.g., 10. We reported a reduction of isolation leakage current in AlGaN/GaN HEMTs by applying the NB etching to the mesa isolation process [28]. In this paper, we irradiated NB and the conventional plasma beam to the gate interface to observe its impact on plasma-induced damages through the appearance of the current collapse, which reduces the drain current right after the device is turned on from the pinched-off state under high operation voltages [29,30]. The current collapse is closely related to the deep levels that capture electrons and form a virtual gate in the channel [31]. The advantage of NB etching on the gate recess process in AlGaN/GaN HEMTs is dis-
2
F. Hemmi et al. / Solid-State Electronics 137 (2017) 1–5
Fig. 1. (a) Schematic of neutral beam etching system, and (b), (c) enlarged figures of carbon aperture array existing between the ICP chamber and the etching chamber. The aspect ratio is defined as the ratio of carbon thickness and diameter. (b) In aspect ratio = 10, charged particles are neutralized and UV photons are blocked during they pass through the carbon aperture. (c) In aspect ratio = 2, a large part of charged particles and UV photons are able to pass through the carbon aperture.
cussed by comparing the current collapse on the output characteristics. Since the plasma-induced damages depend on many parameters consisting of the etching system, it is difficult to make a fair comparison between different etching systems. Therefore we tried to compare the neutral beam etching and the conventional plasma etching in the same system. The carbon aperture array with an aspect ratio of 2 was prepared for this purpose so that the conventional plasma etching condition is intentionally produced in the neutral beam etching system. 2. Device fabrication The samples have a standard AlGaN/GaN HEMT heterostructure grown on a sapphire substrate as shown in Fig. 2(a). The epitaxial structure consists of a 15.6-nm-thick AlGaN barrier layer on a 2000-nm-thick GaN channel/buffer layer grown on a c-plane sapphire substrate. The mobility and concentration of the twodimensional electron gas are 1531 cm2/V s and 9.0 1012 cm 2 at room temperature, respectively. The devices fabrication started with source and drain ohmic metallization by Ti/Al/Ni/Au (20/120/20/70 nm) lift-off followed by mesa isolation, and then a 2-min ohmic annealing with a SiO2 protection coating was performed at 780 °C in N2 ambient. The mesa isolation was carried out by the NB etching system with two conditions; (i) NB with sufficient neutralization by choosing an aspect ratio of the carbon aperture of 10 (NB10) as shown in Fig. 1(b) and (ii) NB with insufficient neutralization by choosing an aspect ratio of 2 (NB2) as shown in Fig. 1(c). The NB10 and NB2 were carried out with Cl2 gas at 0.09 Pa and an RF power of 800 W. The etching rate in each
condition is shown in Table 1. Because NB2 includes plasma ion particles and UV photons which can damage the device surface, the beam condition of NB2 is close to that of ICP etching. After isolation, gate metallization divided the samples into 3-types: (i) simply deposited the gate metal as a reference, (ii) NB10 was irradiated for 30 s to the gate surface before the deposition of the gate metal, and (iii) NB2 was irradiated for 30 s to the gate surface instead (Fig. 2(b)-(c)). After that, Ni/Au (20/160 nm) was deposited to form gate electrode and samples were passivated with 200-nmthick SiN film by plasma-enhanced chemical vapor deposition at 250 °C. Then the SiN layer on the drain and source ohmic electrodes were removed by reactive ion etching (RIE) with SF6 to open the contact holes. Finally, Ti/Ni/Au (20/20/350 nm) pad electrodes were evaporated and lifted off for all types of samples. The process flow is illustrated in Fig. 3. 3. Results and discussion The surface morphology of the samples after the gate recess etching is observed by atomic force microscopy (AFM). Fig. 4 shows the AFM images of the samples etched with NB10 and NB2 conditions and an as-grown sample for comparison. The RMS (Root Mean Square) roughness was 0.088 nm for the as-grown sample, 0.452 nm for the NB10 sample, and 1.024 nm for the NB2 sample. The smoother etched surface is achieved by the neutral beam etching. The DC and pulsed Id-Vds characteristics are measured for the devices with a gate length of 3 mm. The DC characteristics are shown in Fig. 5. Comparing to the reference sample shown in
Fig. 2. Cross sectional views of (a) epitaxial layer structure, (b) reference sample without any irradiation under the gate, and (c) NB10/NB2 sample with NB10/NB2 irradiation under gate electrode.
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F. Hemmi et al. / Solid-State Electronics 137 (2017) 1–5 Table 1 NB irradiation parameters. Sample
Plasma power
Etching rate (AlGaN)
NB exposure
Carbon aspect ratio
Reference NB10 NB2
– 800 W 800 W
– 5 nm/min 7.5 nm/min
No 30 s 30 s
– 10 2
Fig. 3. Process flow.
Fig. 5(a), the devices irradiated to NB10 or NB2 exhibit a positive shift in the threshold voltage (Vth) as shown in Fig. 5(b) and (c), respectively, and the maximum of the drain current (Id_max) for NB10 and NB2 samples are decreased. The NB10 and NB2 samples exhibit a similar gate leakage current. The threshold voltage shift and the decrease in Id_max are depicted more clearly in the transfer characteristics shown in Fig. 5(d). These results indicate that the AlGaN layer was partly etched by NB and a shallow gate recess was formed. Table 2 lists the changes in Id_max, the maximum transconductance (gm_max), and Vth of devices. Comparing NB10 and NB2 samples, NB10 exhibits a positive shift of Vth with less degradation in Id_max and gm_max after gate recessing. Since the estimated recess depth is 3–4 nm, longer NB irradiation is promising to achieve normally-off characteristics. Fig. 6 shows the pulsed Id-Vds characteristics. The pulse width and the period are 250 ms and 1 ms, respectively. Two pulse
Fig. 4. AFM images of (a) as-grown substrate before fabrication (RMS = 0.088 nm), (b) NB10 etched sample (RMS = 0.452 nm), and (c) NB2 etched sample (RMS = 1.024 nm).
Fig. 5. DC Id-Vds characteristics of AlGaN/GaN HEMTs (a) without NB irradiation as a reference, (b) with NB10 irradiation, (c) with NB2 irradiation, and (d) transfer characteristics of these samples at a drain voltage of 5 V.
4
F. Hemmi et al. / Solid-State Electronics 137 (2017) 1–5
Table 2 Transconductance and threshold voltage shifts in the samples. Samples
Id_max [mA/mm]
gm_max [mS/mm]
Reference NB10 NB2
430 367 332
120 112 101
Vth [V] 2.23 1.63 1.57
conditions are tested as illustrated in Fig. 6(d). In the first condition, the quiescent bias is set at 0 V for both gate and drain, namely, Vq,g = Vq,d = 0 V. In the second condition, Vq,g is set at 5 V, which is negative enough to pinch off the channel, to observe the gate lag while Vg,d is kept at 0 V. In the first pulse condition, Vq,g = Vq, d = 0 V, the Id-Vds characteristics of the three samples represent their DC characteristics as shown by the solid circle plots in Fig. 6(a)-(c). The slope of the Id-Vds curve in the linear region gives the on-state resistance (Ron). The Ron measured at a gate voltage of 1 V is 9.1, 10.1, 10.5 Xmm for the reference, NB10, and NB2 samples, respectively. The larger Ron in the NB10 and NB2 samples in comparison to the reference sample is ascribed to the reduced 2DEG concentration in the recessed region that increases the source/drain access resistance and the intrinsic channel resistance at a fixed gate voltage. When the second pulse condition, Vq,g = 5 V and Vq,d = 0 V, was applied, the output characteristics have been changed as shown by the open circle plots in Fig. 6(a)-(c). In the all three samples, Ron increases from the ones under the pulse condition 1 (Vq,g = Vq,d = 0 V): 9.6, 10.3, and 10.6 X mm for the reference, NB10, and NB2 samples, respectively. A significant difference in the increase in Ron was not observed. However, The NB2 sample exhibits a clear decrease in the drain saturation current at around
a drain voltage of 5 V when the pulse condition 2 was applied while the NB10 sample exhibits the drain saturation current independent of the pulse condition. The decrease in the drain saturation current in the NB2 sample should be a result of the gate lag because it became smaller as the pulse width increased from 250 to 750 ms. That is, the smaller pulse width is the severer condition for the 2DEG in the intrinsic gate region to recover from the pinchoff state. These results suggest that at least two different mechanisms play roles on the increase in Ron and the decrease in the drain saturation current observed in the pulsed Id-Vds characteristics. The former is observed regardless of the gate recess technique and the latter is observed in a particular sample using NB2 in the gate recess. Because NB2 includes plasma ionized particles and UV photons like the conventional ICP etching, this result suggests that the neutral beam etching has a clear advantage over the conventional ICP etching with respect to, at least, the suppression of the gate lag by reducing the plasma-induced damages by the gate recess etching. 4. Conclusion We experimentally confirmed that the neutral beam irradiation to the gate surface helps positive shift in the threshold voltage for AlGaN/GaN HEMTs with less degradation in the transconductance. Moreover, the current collapse caused by the interface traps at the gate electrode is successfully suppressed by the neutral beam with sufficient neutralization. These results suggest that the neutral beam gate recess etching in GaN-based HEMTs is a promising approach for normally-off AlGaN/GaN HEMTs with less current collapse.
Fig. 6. Pulsed Id-Vds characteristics of AlGaN/GaN HEMTs (a) without NB irradiation as a reference, (b) with NB10 irradiation, and (c) with NB2 irradiation. Gate voltage: 1 V top, 1 V step. (d) Quiescent gate and drain biases (Vq,g and Vq,d, respectively): (1) Vq,g = Vq,d = 0 V and (2) Vq,g = –5 V, Vq,d = 0 V.
F. Hemmi et al. / Solid-State Electronics 137 (2017) 1–5
Acknowledgements This work is supported by the JSPS KAKENHI grant 15K13963 and 16H04341. The device fabrication has been carried out at the Laboratory for Nanoelectronics and Spintronics, Tohoku University.
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Tetsuya Suemitsu received the B.S., M.S., and Ph.D. degrees from Waseda University, Tokyo, Japan, in 1992, 1994, and 2000, respectively, all in electrical engineering. In 1994, he joined Nippon Telegraph and Telephone Corporation (NTT), Japan, where he conducted research on high electron mobility transistors (HEMTs) based on indium phosphide (InP) and related materials. In 2002, he was a visiting scientist of the Microsystems Technology Laboratories at Massachusetts Institute of Technology (MIT), Cambridge, MA, USA. Since 2006, he has been with the Research Institute of Electrical Communication at Tohoku University, Sendai, Japan, as an associate professor. Dr. Suemitsu is a member of the Japan Society of Applied Physics, the Physical Society of Japan, the Institute of Electrical and Electronics Engineers (IEEE) and the American Physical Society. In 2003, he received the Best Paper Award from the Institute of Electronics, Information and Communication Engineers (IEICE). In 2007, he received the Best Paper Award of the Electronics Express (ELEX) from IEICE.