GaN HEMTs: Permanent leakage current increase and output current drop

Microelectronics Reliability 52 (2012) 2188–2193

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Reliability of AlGaN/GaN HEMTs: Permanent leakage current increase and output current drop D. Marcon ⇑, J. Viaene, P. Favia, H. Bender, X. Kang, S. Lenci, S. Stoffels, S. Decoutere imec, Kapeldreef 75, B-3001 Leuven, Belgium

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Article history: Received 3 June 2012 Accepted 20 June 2012 Available online 18 July 2012

a b s t r a c t In this work we report on the two most common failure modes for AlGaN/GaN-based HEMTs: the gate leakage increase and the output current drop. First, by performing step-stress experiments in function of the step-time (tSTEP) we show that the critical voltage for the increase of gate leakage current depends on the tSTEP and is not associated with a permanent drop of the output current. Consequently, identification of the critical voltage by means of step-stress is not meaningful per se since it depends on the tSTEP used. Second, we show that during high power stress at high voltage a permanent output current drop occurs. The failure analysis reveals the formation of crystallographic defects in the AlGaN layer along the whole width of the gate, in agreement with the inverse piezoelectric theory. However, in contrast to the degradation model based on the inverse piezoelectric effect, these defects do not aid the leakage of electrons from the gate toward the drain electrode since the output current drop is not associated with an increase of the gate leakage current. Therefore, combining the outcome of the two experiments, we suggest that the two most common failure modes are not correlated despite both might concur to the device degradation. Finally, an excellent stability is shown for devices with reduced Al content in the AlGaN barrier, highlighting the fundamental role of strain on reliability of AlGaN/GaN-based devices. Crown Copyright Ó 2012 Published by Elsevier Ltd. All rights reserved.

1. Introduction In recent years, the number of reliability studies of GaN-based HEMTs has significantly grown [1]. Indeed, the extraordinary performance, which has been demonstrated for these devices, needs to be combined with an excellent device reliability to guarantee the success of GaN-technology over others. To the best of our knowledge, the failure modes (i.e. how devices fail) of GaN-based HEMTs stress under DC or RF conditions can be summarized as a reduction of the output power/current and an increase of the gate/drain leakage current [1]. An important contribution to the understanding of GaN-HEMTs reliability has been given by del Alamo and Joh [2–5]. They suggested that device degradation could be induced by the inverse piezoelectric effect, i.e. beyond a certain critical voltage, hence a critical electric field [6], the total strain in the AlGaN barrier exceeds the critical value beyond which strain relaxation occurs by means of crystallographic defect formation [7]. This phenomenon happens at the gate edge where the electric field peaks, as confirmed by means of transmission electron microscopy (TEM) [8,9]. Therefore, according to the inverse piezoelectric degradation model [2–4], the output current drop observed during electrical

⇑ Corresponding author. Tel.: +32 16 28 8404. E-mail address: [email protected] (D. Marcon).

stress is a consequence of the AlGaN relaxation, which reduces the piezoelectric polarization in the material. Moreover, it is also suggested that the defects formed beyond the critical voltage assist electrons to leak from the gate toward the drain contact through the AlGaN barrier, therefore, explaining the increase in gate leakage current. In other works [1–4,6,10], the critical voltage was identified by performing reverse gate bias step-stress. Beyond this critical voltage the gate leakage current increases rapidly and the output current starts to drop. Recently, we have shown that the gate leakage current increase can also occur below the critical voltage, conventionally measured in step-stress experiments, with a voltage-accelerated degradation kinetics [11]. However, in our previous work we could not deduce if it was the same degradation phenomenon occurring below and above the critical voltage or if two different phenomena were occurring which resulted in a gate leakage current increase. In this work we focus on the two most common failure modes of AlGaN/GaN transistors: gate leakage current increase and output current drop. Recently, it has been shown that these two phenomena do not track in time for stress voltages in excess of the critical voltage; yet it is suggested they have a common origin [5]. Here, we indicate that these two failure modes are not correlated despite both might concur to the device degradation. First, we provide evidence that the identification of the critical voltage by means of step-stress is not meaningful per se. Moreover,

0026-2714/$ - see front matter Crown Copyright Ó 2012 Published by Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.052

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The heterostructure was grown by MOCVD on a 3-inch SiC substrate. The layer stack consisted of a 200 nm thick buffer layer, a 1 lm GaN channel layer and a 22 nm thick AlGaN barrier layer (i.e. devices with different AlN content in the barrier were tested. This will be indicated at the beginning of each section). Finally the heterostructure was capped with 50 nm of Si3N4 grown in situ in a MOCVD reactor. The device processing started with the ohmic contacts that were fabricated after selectively removing the in situ Si3N4 layer, deposition and lift-off of Ti/Al/Mo/Au as metallization, and a rapid thermal annealing. The device-to-device isolation was obtained by means of multiple N+ ion implantations at varying energies. Subsequently, T-gates with integrated field plates, were fabricated by selectively dry etching the thick in situ Si3N4 under the gate. Finally, the devices were covered with a 250-nm-thick Si3N4 passivation layer. All devices here investigated presented small drain-lag up to 50 V.

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we observed that the output current drop during such a test is recoverable and it does not coincide with the gate leakage current increase. Second, we confirm the formation of crystallographic defects in the AlGaN barrier as the main cause of the permanent output current drop during high power DC stress at 50 V drain bias. However, in our case this permanent reduction is not associated with an increase of the gate leakage current, and therefore, these defects do not help electrons to leak through the AlGaN barrier. Finally, we show that reliability can be significantly improved by reducing the Al content in the AlGaN barrier, confirming the fundamental role of strain in the reliability of AlGaN/GaN-based HEMTs [3,12,13].

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time (s) 3. Reverse gate bias step-stress Fig. 1. (a) Gate leakage current monitored during reverse gate bias step-stress (tSTEP = 10 s) and (b) relative drop of the output current measured at (VG = 0 V, VD = 0.1 V) after each step on four devices. Inset in (a) schematic illustration of electron flow in a percolation path formed through the AlGaN.

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In this section we focus on reverse gate bias step-stress tests performed on symmetric devices having an identical gate-source and gate-drain distance of 1.5 lm, and a gate length of 0.5 lm with an integrated field plate of 0.25 lm extending from the gate edge on both sides. In this case the AlGaN barrier contained 26% AlN. Step-stress experiments were performed at room temperature on 12 devices, located on the same die, by sweeping the gate voltage from 20 V to 100 V in steps of 5 V with the source and drain voltage set to 0 V. After each step, the transfer-characteristic of the device under test was measured. Three different step time values (tSTEP) were used: 10 s, 100 s and 1000 s (four devices per group). As already reported in [1–3,10] we have observed that during step-stress there is a voltage at which the gate leakage current starts to rapidly increase (VCRITICAL in Fig. 1a). However, this was not associated with a severe drop of the output current, which happened well beyond VCRITICAL (Fig. 1b). Therefore, in contrast to [2,4], in our case the output current drop did not coincide with the gate leakage current increase. Furthermore, we have observed that VCRITICAL strongly depends on the tSTEP used during test and it is always significantly lower than the voltage for 20% reduction of the output current (V20%ID-Drop) (Fig. 2). The value for VCRITICAL was larger when shorter times were used for tSTEP. This is in agreement with our previous investigation [11], confirming that the phenomenon of leakage current increase has a voltage-accelerated degradation kinetics i.e. the time necessary to form the first percolation path through the AlGaN (inset Fig. 1a), which we suggest is causing the first gate current increase, depends on the applied stress conditions [11]. For a longer tSTEP, there is more time at lower voltages to create defects and consequently the bias for which the device will fail during step-stress is lowered.

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Fig. 2. Average value of the gate voltage for sudden gate current increase (VCRITICAL as in Fig. 1a) and for 20% reduction of drain current (V20%ID-Drop) as a function of tSTEP used during step-stress.

Therefore, without minimizing the importance of performing step-stress for quick technology assessment, this experiment clearly indicates that the identification of the VCRITICAL is not per se meaningful since it depends on the tSTEP used. Moreover, by repeating the step-stress test after a waiting period of 200 h, we firstly confirmed that the gate leakage current increase was permanent (Fig. 3a) [8], and secondly, we observed that

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surrounding materials). This seems further exclude the inverse piezoelectric effect as root cause for the permanent gate leakage current increase. The localized and tiny nature of the parasitic paths (atom scale) compare to the whole device width (usually of at least 10–100 lm) explains also why the overall output current is negligibly influenced by their formation, as also reported in [15]. Nevertheless, it is possible that if the density of leakage paths becomes large, as shown in [10], their presence might somehow severely alter the static or the dynamic device performance, albeit we have never observed this. This might also explain the incubation time for permanent degradation in [5]. According to our best knowledge, the mechanism forming these parasitic paths is still unknown and further investigations are required. Moreover, even though above we suggested that percolation paths are formed in the AlGaN [11], it is also plausible that these paths are formed in the thin native oxide present below the Schottky contact (Fig. 4b), as suggested in [16]. However, TEM analysis at the aforementioned hot-spots did not show the oxide consumption mentioned in [16] (Fig. 4b).

4. Long-term high-power 50 V DC stress at high temperatures

Fig. 3. Reverse gate-bias step stress performed twice on the same device. Between the two tests the device was left unbiased for more than 200 h. (b) Output drain current measured at (VG = 0 V, VD = 0.1 V) before and after each test.

the output current drop was fully recoverable and it could return to the same value when the test was repeated (Fig. 3b). This indicates that the output current drop was caused by trapping phenomena, most probably in the access region, rather than due to creation of permanent macro-defects, for instance, related to the inverse piezoelectric effect as shown later. Moreover, each parasitic leakage path can be identified by a hot-spot visible with emission microscopy (Fig. 4a) [1,10,11,14]. TEM analysis performed precisely on this spot did not reveal any defects (Fig. 4b), as also commented by other authors [8,14,15]. Percolation paths are indeed formed by point defects that are not possible to visualize by TEM analysis, because they are too localized and small (unless they thermally run-away melting the

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In this section we focus on long-term DC stress performed on 1mm-wide devices packaged in a copper-based fixture. The device geometries were: a gate-source distance of 1 lm, a gate-drain distance of 4 lm and a gate length of 0.5 lm with an embedded field plate of 0.5 lm extending toward the drain side. In this case the AlGaN barrier contained 30% of AlN (ns = 1.2  1013 cm 2). Constant high-power DC stress was performed at an output current of 150 mA/mm at 50 V drain bias (7.5 W/mm) for 816 h. The gate voltage was continuously adjusted throughout the test to maintain a constant stress power level. Regularly, the stress was interrupted for device characterization. Six devices were divided in 3 temperature groups. On each group the ambient temperature was tuned to achieve a peak junction temperature (Tj) of 280 °C, 300 °C and 330 °C, respectively. These values were extracted by means of simulations based on Raman measurements. In Fig. 5 the relative variation of the output drain current during stress with respect to its initial value is reported. We observed that generally there was an initial drop within the first 24 h, which we attributed to trapping as proved in other experiments to be recoverable. This was followed by a period of stability for 100–200 h. Beyond this point, however, the output current started to severely and monotonically drop with time. We observed that this degradation was permanent since it was not recoverable after stress, nei-

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time (hrs) Fig. 4. (a) Emission microscopy on a device that shown gate degradation [11]. (b) TEM analysis performed as precise as possible at the hot-spot indicated in (a). The dashed line on the TEM pictures indicates the AlGaN/GaN interface.

Fig. 5. Relative variation of the output current during the high-power DC stress (7.5 W/mm at 50 V). Six devices divided in three peak junction temperature (Tj) groups were used. The label ‘‘recovery test’’ indicates the time (264 h) when devices were left unbiased to test if the output current drop was recoverable.

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ther spontaneously nor by shining light on devices to promote detrapping (Fig. 5). It has to be pointed out that due to the small number of samples per group, we cannot make any conclusion about the temperature dependence of the output current degradation phenomenon, even though temperature has been shown to play a crucial role [8,17]. An obvious reduction of the output current, trans-conductance and sub-threshold slope can be noticed, when comparing the device transfer-characteristic before and after stress (recovery time included) (Fig. 6). Moreover, we observed more than one order of magnitude reduction in gate leakage current after stress (recovery time included) (Fig. 7), indicating that the phenomenon of permanent output current drop, in our case, was not associated with an increase of the gate leakage current. Physical failure analysis was performed on a device stressed at Tj = 300 °C, which characteristics are shown in and Figs. 6 and 7, in the locations indicated in Fig. 8. TEM analysis in these regions showed the formation of a vertical crack in the AlGaN layer at the gate edge on the drain side, corresponding to a peak in both temperature and electric field during stress. Since the precise location of the TEM analyses were randomly chosen, it is reasonable to assume that the crack was extending all over the gate width, confirming the findings reported in [9]. Therefore, it can be concluded that the severe and permanent output current drop discussed above was due to AlGaN relaxation, which reduces the piezoelectric polarization component and consequently the 2DEG density [3], i.e. the inverse piezoelectric effect. However, as mentioned before and in contrast to [2,4], the defects formed in the AlGaN layer as a consequence of its relaxation (Fig. 8) do not provide a path for electrons to leak from the gate toward the drain contact, since the gate leakage did not increase (Fig. 7). Similar findings (i.e. output current drop due to cracks

Fig. 8. TEM analysis performed along the gate width on two different locations. The gate corner on the drain side is shown in both pictures. The dashed line on the TEM pictures indicates the AlGaN/GaN interface.

and pits however not associated with a gate leakage current increase) have also been reported in [18]. The gate leakage current decrease after stress and apparent increase of Schottky barrier height (Fig. 7) can be explained by the reduction of the 2DEG density due to the AlGaN relaxation. Indeed, a recent work has shown that the lower the 2DEG density the larger the Schottky barrier height and the lower the leakage [19]. From the high angle annular dark field (HAADF) scanning transmission electron microscopy (STEM) (not reported here), where the contrast is approximately proportional to the square of the atomic number of the material and to the thickness of the TEM specimen, we could deduce that there was no metal propagation inside the crack. Moreover, from this analysis we could infer that the cavity was either filled with SiN or it was oxidized or both as observed in [9]. The chemical analysis performed along the defective region formed in the AlGaN layer showed a strong reduction of gallium and nitrogen in the crack, whereas the aluminum concentration only slightly dropped (Fig. 9). The carbon signal was close to the

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minimum measureable level and Si was either not present or below the measurable level. As also reported by other authors [20], we observed a remarkable increase of oxygen in the crack. Therefore, this analysis indicated that most likely Al(Ga)O oxide was formed in the crack. This oxide could have been formed either during the stress or during the sample preparation for TEM analysis or both. Further investigations are required to clarify this point. Combining the findings reported in [8,9,14,17] with our experience, we indicate that the phenomenon of permanent output

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current drop linked to the AlGaN relaxation required the conjunction of three factors: high (junction) temperature, high electric field and current. Indeed, we have shown that neither long-term storage stress at high temperatures (up to 325 °C) [21] nor off-state stress at high voltages and temperatures (up to 200 V and 200 °C) [22,23] could induce such a permanent drop of the output current. Moreover, it has been reported that also the gate interface quality with AlGaN plays a significant role on this device degradation [13]. The fundamental role the strain of the AlGaN barrier plays on the reliability of AlGaN/GaN HEMTs [3,12,13] has been confirmed when new devices with AlN content reduced to 26% (ns = 9.5  1012 cm 3) were processed. Transistors with the same layout were stressed at the same conditions described above. In agreement with [12,13], we observed that by reducing the Al content it is possible to obtain excellent stability for more than 1000 h at the same high-power stress conditions (Fig. 10). Indeed, throughout this test no output current drop or other failures were observed. 5. Conclusion

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time (hrs) Fig. 10. Relative variation of the output current during the high-power DC stress (7.5 W/mm at 50 V) on devices with 26% Al content in the barrier. For reference, the degradation on an identical device with 30% Al content in the barrier is reported.

In this work we studied the gate leakage current increase and output current drop phenomena on AlGaN/GaN-based HEMTs. Firstly, by performing step-stress in function of the tSTEP, we have confirmed that the gate leakage current increase has a voltageaccelerated degradation kinetics and therefore the identification of the critical voltage is not per se meaningful, since it depends on the tSTEP used. Moreover, during such a test we observed that

D. Marcon et al. / Microelectronics Reliability 52 (2012) 2188–2193

the output current drop was not permanent and it was uncorrelated with the gate leakage current increase. These observations together with the absence of cracks or other crystallographic defects indicated that this phenomenon might not be related to the inverse piezoelectric effect as described in literature. Secondly, we performed long-term high-power DC stress at high voltage where we observed a severe and permanent output current drop. Physical failure analysis revealed the formation of crystallographic defects in the AlGaN layer all over the gate width, as a consequence of the inverse piezoelectric effect. However, in contrast to the degradation model based on the same effect, these defects did not provide a path for the electrons to leak from the gate toward the drain electrode, since the output current drop was not associated with an increase of the gate leakage current. Consequently, we suggest that the permanent leakage current increase and output current drop are two distinct degradation phenomena not obviously linked to each other, even though both might concur and affect the device reliability. Finally, the fundamental role of the elastic energy present in the AlGaN barrier on the reliability of AlGaN/GaN-based devices has been confirmed by showing the excellent stability of transistors with reduced Al content in the barrier. Acknowledgement This work is supported by the European Space Agency (ESA) within the program GREAT2 (Contract Number: 21.499/08/NL/PA). References [1] Meneghesso G, Meneghini M, Tazzoli A, Ronchi N, Stocco A, Chini A, et al. Int J Microwave Wireless Technol 2010;2:39–50. [2] del Alamo JA, Joh J. GaN HEMT reliability. Microelectron Reliab 2009;49:1200–6. [3] Joh J, Gao F, Palacios T, del Alamo JA. A model for the critical voltage for electrical degradation of GaN high electron mobility transistors. Microelectron Reliab 2010;50:767–73. [4] Joh J, del Alamo JA, Langworthy K, Xie S, Zheleva T. Role of stress voltage on structural degradation of GaN high-electron-mobility transistors. Microelectron Reliab 2011;51:201–6. [5] Joh J, del Alamo JA. Time evolution of electrical degradation under high-voltage stress in GaN high electron mobility transistors. In: IEEE international reliability physics symposium (IRPS); 2011. p. 4E.3.1–4E.3.4. [6] Chang C-Y, Douglas EA, Kim J, Lu L, Lo C-F, Chu B-H, et al. Electric-field-driven degradation in OFF-state step-stressed AlGaN/GaN high-electron mobility transistors. IEEE Trans Device Mater Reliab 2011;11:187–93.

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