New technology for the control of narrow-gap semiconductors

New technology for the control of narrow-gap semiconductors

Chaos, Solitons and Fractals 17 (2003) 219–223 www.elsevier.com/locate/chaos New technology for the control of narrow-gap semiconductors I. Antoniou,...

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Chaos, Solitons and Fractals 17 (2003) 219–223 www.elsevier.com/locate/chaos

New technology for the control of narrow-gap semiconductors I. Antoniou, V. Bozhevolnov, Yu. Melnikov *, A. Yafyasov International Solvay Institutes for Physics and Chemistry, Campus Plaine ULB, C.P. 231, Bd.du Triomphe, Brussels 1050, Belgium

Abstract We present the results of the year work in the frame of the EU ESPRIT Project 28890 NTCONGS ‘‘New technology for the control of narrow-gap semiconductors’’. This work has involved both theoretical and experimental study, as well as the development of new specific equipment, towards the creation of a new generation of nanoelectronic devices able to operate at 77 K and even at room temperature.  2002 Elsevier Science Ltd. All rights reserved.

The presented work is the result of the collaboration of several teams, namely the International Solvay Institutes (Brussels), the Aristotle University (Thessaloniki), and INTRACOM (Athens) in the frame of EU ESPRIT Project no. 28890 NTCONGS (July 1998–June 2000). Processing of narrow-gap semiconductor surfaces has essential difficulties related to the complex structure of these materials (binary or triple) and complex structure of interface boundaries, including the presence of many-component oxides on the surface. Therefore, in order to use narrow-gap semiconductor materials in nanoelectronics, one has to develop a specific technology for processing the surfaces of narrow-gap semiconductors. That is a necessary step towards the fabrication of nanowires for electronic devices. Our objectives were: • To develop the appropriate new technology for the design and control of the electrophysical properties of the surfaces of narrow-gap semiconductors and realize this technology by the construction of a new Integrated Laboratory Equipment. The equipment has been constructed, tested and evaluated. • To chose the appropriate narrow-gap semiconductor material for the fabrication of nanowires. • To fabricate several samples of nanowires and verify their switch characteristics. • To construct a pre-commercial prototype of the Profile Plotter, test and evaluate it. The Profile Plotter being a part of the Integrated Laboratory Equipment, has an added value and is considered as a by-product of the Project. • To perform general theoretical study as well as specific theoretical study with respect to the geometry of the proposed nanowires. All these objectives have been successfully achieved through the work organized in five workpackages.

1. Construction, testing and evaluation of the prototype of the Profile Plotter for the monitoring of the electrophysical properties of surfaces of semiconductors The Profile Plotter is a specialized measuring device. The measurement of electrical parameters of semiconductor surfaces is based on the method of the field effect in the electrolyte. It allows to measure:

*

Corresponding author. E-mail address: [email protected] (Yu. Melnikov).

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Bulk charge carrier concentration nI in the interval 1011 < nI < 1020 cm3 with accuracy better than 10%. Effective masses m of the charge carriers in the interval m ¼ ð0:01  0:1Þm0 with accuracy 10%. Density of surface states Nss in the interval 1010 < Nss < 1013 cm2 with accuracy 3–5%. Depth of the etching d in the interval 10 nm < d < 1000 nm with accuracy 10%. The value of x in three-compound semiconductors Mex Hg1x Te with accuracy 5%.

The operation of the Profile Plotter is based on the controlled layer-by-layer etching and simultaneous measurement of the capacitance. We have constructed all the necessary electronic circuits of the Profile Plotter, namely: • • • • •

Specific potentiostat, Current integrator, Capacitance measurement device, Thermostatic electrochemical cell, Governing programmator device.

The Profile Plotter was adapted for measurements of voltage during relaxation of the test charge through nanostructures. In fact, we have constructed a set of the devices, specialized for the specific users according to the possible fields of applications. This specialization of the Profile Plotter allows the following significant advantages: • The reduction of the required qualification of the personnel. • The reduction of the cost of every specific device. The Profile Plotter is tested with the certified samples of the following materials: Ge, Si, Mnx Hg1x Te, Cdx Hg1x Te, Znx Hg1x Te, GaAs, GaAlAs, GaN, GaP, InP, InSb, InAs, C (carbon), Te, PbTe, PbSe, PbSnTe, YBaCuO. All the tests have shown that the Profile Plotter meets all the prerequirements as stated in the EU ESPRIT contract. The measured capacitance/voltage characteristics allows to obtain the values of physical parameters like charge carrier concentration, density of surface states, flat band potential, gap width, effective mass of charge carriers, and stoichiometric composition.

2. Choice and improvement of the properties of narrow-gap semiconductors Our purpose was to select appropriate narrow-gap semiconductor materials and to improve the electrophysical properties of their surfaces in order to obtain substrates with low density of surface states Nss < 1011 cm2 . We have investigated the electrophysical and electrochemical properties of narrow-gap semiconductors Cdx Hg1x Te, Mnx Hg1x Te, Znx Hg1x Te. We confirmed that the electrophysical properties of the narrow-gap semiconductors Mex Hg1x Te are stable under the process of electrochemical etching. We have measured the following electrophysical parameters: width of the spectral gap, charge carrier concentration, and effective masses in conductivity band. We have shown that the electrophysical parameters of the semiconductor materials under investigation are sufficiently stable after electrochemical formation of their surfaces. We have chosen the basic material for the formation of ‘‘sandwich’’ structure for nanowires, namely Cdx Hg1x Te (0:32 > x > 0:10). The Aristotle University of Thessaloniki performed the independent test by electron microscope and X-ray analysis. We have studied TlBi(Sex S1x ) as an alternative narrow-gap semiconductor material for the formation of nanowires. The properties of TlBi(Sex S1x ) are determined by the layer structure of this material. An advantage of TlBi(Sex S1x ) materials is due to the natural monolayer structure of the samples, which automatically allows to obtain two-dimensional structures. However, the electrophysical properties vary essentially from sample to sample, depending on the ‘‘prehistory’’ of their synthesis. We have developed a technology for the modification of near-surface layers of CdHgTe in order to fabricate ‘‘sandwiches’’ of the type Cdx1 Hg1x1 Te–Cdx2 Hg1x2 Te. We have fabricated thin (10–100 nm) layers with modified compound parameter x. We have measured electrophysical parameters of these layers and have performed the IRcontrol measurements. The results for two samples of sandwiches Cdx1 Hg1x1 Te–Cdx2 Hg1x2 Te are shown in the following table. The accuracy of measurements is 5%. We have obtained substrates of Cdx Hg1x Te with prescribed electrophysical characteristics: • Density of surface states Nss < 5  1010 cm2 . • Effective mass of charge carriers m ¼ ð0:013  0:023Þm0 , for x varying in the interval 0:10 < x < 0:33.

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• Bulk concentration of the electrons in the substrate nI ¼ 8  1015 –7  1016 cm3 for x varying in the same interval. We have demonstrated that the maximal error in the calculation of electrophysical parameters of semiconductor substrates is due to an uncertainty of the value S of the square of a substrate. Indeed, the experimental capacitance Cex ðV Þ equals to Cex ðV Þ ¼ C0 ðV ÞS, where C0 ðV Þ is differential capacitance. Taking the logarithmic derivative of the latter formula with respect to the voltage V one gets dðlog Cex ðV ÞÞ=dV ¼ dðlog C0 ðV ÞÞ=dV , which allows the comparison of experimental and theoretical curves C0 ðV Þ and thus the determination of electrophysical parameters of substrates. We have demonstrated that the form of the experimental curve C0 ðV Þ obtained at temperature T  300 K under condition Nss ! 0 coincides with that of the theoretical curve obtained in the frame of purely quantum description of the domain of spatial charge. This curve cannot be satisfactory explained by classical approximations. This result is an experimental proof of the effect of dimensional quantization of the domain of spatial charge at room temperature for narrow-gap semiconductors.

3. Construction, testing and evaluation of the integrated laboratory equipment for the design and control of the electrophysical properties of narrow-gap semiconductors The objective was to construct new integrated laboratory equipment able to prepare substrates and create specific geometric inhomogeneities on the surfaces of narrow-gap semiconductors. The equipment includes: • • • • • • •



Specific atomic layer epitaxy device with high precision valves. Profile Plotter for the modification of semiconductor surfaces. Modified scanning tunnel microscope for the measurement of electron densities on the surfaces. Atomic force microscope for determination of the topography of the surfaces, able to operate in electrolytes and adapted to the processes of etching and passivation of the surfaces. Device for the optical monitoring of the etching processes in the electrochemical cell, including high-resolution TVcamera, blue light diode, binocular microscope, and TV-controller. Device for the measurement of electrophysical parameters of nanoelectronic structures, based on the Profile Plotter. IR-monochromator with inverted optical scheme for the control of the surfaces of single layer and multi-layer semiconductor substrates. In combination with the Profile Plotter it allows to measure photoelectric characteristics of single layer and multi-layer substrates. Service computers.

All the above mentioned devices have been assembled and tested. The Integrated Laboratory Equipment has been tested with Mex Hg1x Te (Me ¼ Mn, Zn, Cd) narrow-gap semiconductors and with a new material TlBi(Sex S1x ), wich surface electrophysical properties have not been studied so far.

4. Fabrication of the geometrical structures on the surfaces of narrow-gap semiconductors for the construction of nanowires Our previous results have demonstrated that the most appropriate geometric structure for the formation of the nanowire by the field effect in electrolyte is the ‘‘corner’’ structure. We have developed a self-consistent algorithm for the solution of Schroedinger and Poisson equations for semi-infinite crystal with fictitious boundary. The computer code for numerical simulations is adapted to real geometric parameters and may be used for the information processing during experimental formation of nanowires. We have developed technology for the creation of the appropriate geometric structures on the substrates of narrowgap semiconductors. Formation of geometric inhomogeneity for nanowires has to lead to a low density of surface states (Nss < 1010 1/cm2 ) in the vicinity of the order of de Broglie wavelength (as given in table). Fig. 1 shows the surface after electrochemical etching with simultaneous passivation by monomolecular layer of surface-active chemicals (a––long arrow shows the domain of the line of scratching; short arrow shows the domain of the biographic defect; b––short arrow shows geometric inhomogeneity formed by convection etching). Mechanical scratching leads to the increasing of the number of the surface states (Nss > 1013 cm2 ) due to very low mechanical cleavage strength of CdHgTe. Therefore the engraving has to include chemical or electrochemical etching.

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Fig. 1. Semiconductor surface after electrochemical etching with simultaneous passivation by monomolecular layer of surface-active chemicals (a) long arrow shows the domain of the line of scratching; short arrow shows the domain of the biographic defect; (b) short arrow shows geometric inhomogeneity formed by convection etching.

Fig. 2. An interval of a long geometric inhomogeneity after the elimination of the masking oxide.

Table 1 X1 (Substrate)

1 2

X2 (Modified layer)

Data from the certificate of a sample

Measurements by the Profile Plotter

Results of IR-control

Measurements by the Profile Plotter

Results of IR-control

0.29 0.23

0.30 0.23

0.28 0.23

0.24 0.20

0.25 0.20

Fig. 2 shows an interval of a long geometric inhomogeneity after the elimination of the masking oxide. The thickness of the edge of the geometric inhomogeneity varies from 0.5 to 3.0 mkm. Using the developed technological methods, we have fabricated more than 20 long (1–3 mm) geometrical inhomogeneities on CdHgTe substrates with the edges of the size from 0.5 to 1.5–3.0 mkm. For temperature 77 K (see Table 1) length of the structure ‘‘contact-nanowire-contact’’ does not exceed 55 mkm (25 þ 5 þ 25). 5. Theoretical investigation of the possibility of electronic devices based on narrow-gap semiconductor nanowires for the implementation of multi-valued logic This part of the work was devoted to theoretical investigation of the properties of a new original series of quantum electronic devices based on interference of electron waves in geometric structures created by etching and/or epitaxy on the interface of wide range narrow-gap semiconductors and special electrolyte.

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We have considered interference properties of simple model system of arrays and barriers and have discussed the capabilities for realizing new nano-devices based on the constructive interference for coding and decoding signals. We have produced the design of few variants of triadic quantum relay based on resonance scattering in simplest quantum networks constructed of quantum wires and/or quantum domains. These relays (splitters) are manipulated in different ways: by the changing of the direction of the constant electric field and by the change of the relevant Fermi level. 1. In the first case the direction of the electric field may be chosen such that the transmission of the electron from one–– incoming channel (wire) to another––outgoing channel (wire) may be controlled by turning of the electric field in the plane parallel to the network. In particular, both cases of simple and multiple resonance eigenvalues are investigated in detail. 2. In the second case the Fermi level on the network may be chosen such that potential barriers may block the entrance to the forbidden channels (wires) and open the entrance of the electron to scattering channels. 3. Another device is based on stimulated Peierls transition: metal–dielectric. For this device the geometrical design is chosen to optimize the switching parameters. The voltage–current characteristics of this device are calculated. 4. One more device is proposed for resonance manipulation of the optical waveguide using acoustic running wave. The idea of this device is close to the ideas used by the previous electronic device described above.