Next generation of Deep Trench Isolation for Smart Power technologies with 120 V high-voltage devices

Microelectronics Reliability 50 (2010) 1758–1762

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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel

Next generation of Deep Trench Isolation for Smart Power technologies with 120 V high-voltage devices R. Charavel *, J. Roig, S. Mouhoubi, P. Gassot, F. Bauwens, P. Vanmeerbeek, B. Desoete, P. Moens, E. De Backer Power Technology Centre, ON Semiconductor, Oudenaarde, Belgium

a r t i c l e

i n f o

Article history: Received 6 July 2010 Accepted 19 July 2010 Available online 11 August 2010

a b s t r a c t A new Deep Trench Isolation (DTI) structure with high-voltage capability (BV > 150 V) and latch-up suppression (log(Ic/Ie) < 2 in adjacent pockets) is experimentally demonstrated in this work. The new DTI is implemented in a Nepi/BLN/N/P+ Silicon stack by using a 0.18 lm CMOS-based platform. Moreover the advantages and design limitations of the new DTI are investigated by TCAD simulations and analytical models, being compared to its DTI predecessor in a Nepi/BLN/P/P+ stack. Ó 2010 Elsevier Ltd. All rights reserved.

1. Introduction The reliability problems related to the minority carrier injection in bulk Smart Power technologies (junction isolation between devices) have been largely reported in the past [1]. An ideal solution to overcome these issues is to provide complete dielectric isolation by using Silicon-On-Insulator (SOI) Smart Power technologies [2]. However, the high cost of the SOI wafers and the inherent thermal problems hamper the proliferation of these technologies. Contrarily, the alternative technologies with DTI techniques appear as a good compromise between cost and device isolation, thus being very performing at high-temperature for automotive electronics. As a consequence, an incessant DTI development has been carried out during the last decade giving for a widespread of possibilities. The most of the reported DTI cross-sections [3–11] match with one of the (a)–(d) structures in Fig. 1. From the DTI cross-section point of view the principal design variations are: (a) A deep trench filled with TEOS [3,10,11] or with TEOS and Polysilicon [4–9]. The latter is beneficial to avoid mechanical stress. Moreover, the existence of inner Polysilicon opens the possibility to electrically activate the DTI. (b) A deep trench filled with TEOS and Polysilicon which is electrically isolated or contacted to the substrate [11]. In the former case, the Polysilicon is highly doped and contacted to the bulk substrate by removing the oxide at the trench bottom. (c) A high resistive substrate [3,10] or a combination of high (top) with low (bottom) resistive regions in the substrate [4–9,11]. In order to provide different resistivity regions like

* Corresponding author. E-mail address: [email protected] (R. Charavel). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.117

in structures (c) and (d) in Fig. 1, there exist two techniques: a high-dose implant through the trench [7,9,11] or a multiepitaxial substrate [4–6,8]. Other types of DTI isolation based on multi-trench [12] or trench combined with junction isolation [13] are less efficient in terms of area consumption. Among the aforementioned possibilities, the DTI structure (d) in Fig. 1 shows a very good compromise between voltage capability and latch-up immunity in medium-voltage (40–80 V) applications for automotive electronics [8]. Such a structure presents a Nepi/BLN/P/P+ stack with very deep trenches (>15 lm) in order to reach the P+ region. The depth of the trenches (TD) is not only determined by the P region thickness (Dn), which limits the DTI voltage capability, but also by Nepi and BLN thickness. Actually, high-voltage technologies (>100 V) offering quasi-vertical power devices need thicker Nepi layers when comparing to lateral power devices. In a quasi-vertical device, the voltage is always sustained from the top to the BLN. For this reason, the higher is the voltage capability, the deeper is the DTI. In a recent technology targeting 100 V-rated devices (i.e., with BV  120 V), this work proves that DTI in Nepi/BLN/P/P+ fails to reach the targeted 150 V voltage capability. Hence, a new DTI in Nepi/BLN/N/P+ is successfully optimized by TCAD and processed in a 0.18 lm CMOS-based platform with DTI depths reaching 40 lm (see Fig. 2).

2. Process and test structure description The DTI pockets are created in a Nepi/BLN/N/P+ stack by firstly growing an N-epitaxial layer on a P+-substrate (4  1018 cm3). Since this layer vertically sustains the applied voltage, the Dn thickness is optimized by TCAD for N = Nepi with an optimum Dn of 17.5 lm (see Fig. 3). At the optimum Dn the planar BV in our stack is about 155 V. The remaining processes, comprising the BLN

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NWell

PWell

Nepi

Nepi

Nepi

Nepi

Nepi

Nepi

Nepi

Nepi

BLN

BLN

BLN

BLN

BLN

BLN

P-

PN-

N-

BLN

P+

P-

P-

P-

(a)

(b)

(c)

P+

P+

(d)

New DTI generation

Fig. 1. (a)–(d) Schematic cross-section of the previous DTI structures [3–11]. The new DTI structure with very deep trenches (40 lm) is shown at the right side. The replacement of the P- by N-type bottom epitaxy and the deeper trenches are the main differences of the new DTI vs. its predecessor (d).

Outer ring Straight corner

(BLN)

tox

Dn

Inner pocket Dp

tox Cut corner

TD

Fig. 2. SEM image and TCAD cross-section of the new DTI structure in a Nepi/BLN/ N/P+ stack.

implantation, the top epitaxial growth and the trench formation is identical to the reported Nepi/BLN/N/P+ one in [5]. A poly-filled trench and a TEOS oxide deposition of 750 nm is a good compromise to impede the defect formation and reduce the electric field across the oxide thickness. For thicker TEOS deposition the mechanical stress becomes very high after the densification, thus producing lattice defects that are propagated to the Silicon surface.

180 160 140

BV (V)

120

Fig. 4. Schematic view of the layout in DTI test structures with CC and SC configuration.

In order to investigate the electrical properties of the DTI isolation, special test structures are integrated. The layouts of the DTI test structure are represented in Fig. 4. Two concentric rings of DTI define an inner pocket surrounded by an external ring that can be separately biased. The Polysilicon filling the trenches remain floating. The concentric rings are designed in two layout configurations. One of them shows optimum cut corners (CC) with an angle above 90° while the other includes straight corners (SC) with an angle of 90°. As it has been reported in literature [10], the CC configuration relaxes the mechanical stress and allows a higher voltage capability. From here on, unless the contrary is specified, the presented data correspond to the CC configuration. Differently from other works [11], an investigation on the layout shapes between adjacent pockets is not included in this paper.

100 80

3. Electrical results

60

3.1. Voltage capability vs. latch-up immunity 40 Doping conc.

20

Potential lines

0 5

10

15 Dn (um)

20

Fig. 3. Simulated planar BV vs. Dn in Nepi/BLN/N/P+ stack.

25

The measured and simulated BV and Ic/Ie in the DTI test structures are plotted in Fig. 5 in function of TD and Dp, respectively. The emitter, base and collector correspond to the terminals of the parasitic bipolar along the DTI constituted by: N (inner pocket)–P+ (substrate)–N (outer ring). Both BV and Ic/Ie are measured following the biasing conditions in Fig. 5. These conditions deter-

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1.E+01

(a) 1.E-06

Gnd

200

Ic

Vin

Ie

Ic/I

1.E-07

Dint

175

Ib

1.E+00

Ic, Ie, Ib (A)

BV (V)

150 125 100

1.E-09

1.E-01

1.E-10

TCAD -- Nepi/BLN/P-/P+

1.E-02

EXP. -- Nepi/BLN/P-/P+

75

Ic/Ie

1.E-08

TCAD -- Nepi/BLN/N-/P+

1.E-11

EXP. -- Nepi/BLN/N-/P+

(a)

50 20

30

40 TD (um)

50

60

1.E-03

1.E-12 0

0.2

0.4 Vak (V)

0.6

0.8

1.E+00

(b) 1.E-06

1.E-01 EXP. -- Nepi/BLN/N-/P+

1.E-07

1.E-02

Ib

Ie

Ic/I

1.E-08

1.E-03

1.E-01

1.E-09 Ln =4.6µm

1.E-04 Ln =3.0µm

1.E-05

Eq. 1

1.E-06

1.E-02

1.E-11 1.E-12

1.E-03

1.E-13

TCAD -- Nepi/BLN/P-/P+

1.E-07

1.E-10

Ic/Ie

Ic, Ie, Ib (A)

Ic/Ie

1.E+00 Ic

EXP. -- Nepi/BLN/P-/P+

1.E-14

1.E-04

1.E-08

1.E-15 1.E-09

(b)

0

10

20 Dp (µm)

30

1.E-16

40

Fig. 5. Measured and simulated (a) BV and (b) Ic/Ie vs. TD and Dp in DTI with Nepi/ BLN/P/P+ and Nepi/BLN/N/P+ stacks. Dashed line in (b) represents the theoretical extraction of Ic/Ie from Eq. (1). Inset in (a): biasing conditions of the DTI test structure.

mine a grounded substrate, a grounded outer ring and a Vin at the inner pocket which is defined positive or negative in order to investigate BV and Ic/Ie, respectively. It is observed from Fig. 5a that a deeper DTI implies BV degradation due to the electrical coupling between the trench and the P+-substrate. More obvious is the fact that deeper DTI provide a lower Ic/Ie ratio. As a consequence, it appears the well-known trade-off between BV and Ic/Ie [6]. A TD about 40 lm is a good compromise for the new DTI in Nepi/BLN/ N/P+ exhibiting BV > 150 V and log(Ic/Ie) < 2 for adjacent pockets. An example of the measured Ic, Ib and Ie currents for adjacent and 12 lm-separated pockets is shown in Fig. 6 with log(Ic/Ie)  4 for the latter. The experimental BV values match well with the values extracted from a commercial TCAD simulator [14]. Differently, the TCAD prediction on Ic/Ie is too optimistic due to a possible discrepancy in the minority carrier diffusion length (Ln). Both TCAD and experimental data are matched by using different Ln (3.0 and 4.6 lm) in the theoretical expression

Ic 1 ¼ þC Ie coshð2  Dp =Ln Þ

1.E-05 0

ð1Þ

where the term C, accounting for the activation energy difference DEa, has been adjusted to 1e8 to match the low current level at large Dp.

0.2

0.4 Vak (V)

0.6

0.8

Fig. 6. Measured Ic, Ie and Ib in DTI test pockets: (a) adjacent and (b) 12 lm separated.

A substantial improvement on BV of Nepi/BLN/N/P+ with respect to Nepi/BLN/P/P+ is demonstrated in Fig. 5a. The new DTI design enhances BV more than 40 V for the same TD value. The reasons behind this higher voltage capability have been analyzed by TCAD. It can be inferred from Fig. 7 that for similar P and N doping concentrations the corner region between trench oxide, BLN and N or P (see blue1 circle in Fig. 7) is more critical in the P case. In the latter, a large electric field across the trench oxide produces the avalanche process in the weak corner. Under these conditions a thicker P-region does not contribute to the BV enhancement. In both Nepi/BLN/N/P+ and Nepi/BLN/P/P+ the BV is dramatically reduced 40 V and 30 V, respectively, when substituting a CC by a SC configuration. On the contrary Ic/Ie is independent from the layout configuration. The electrical properties of the new DTI isolation are finally investigated for temperatures ranging from 40 °C to 150 °C in Fig. 8. For adjacent pockets, Ic/Ie increases with temperature due to the Ln(T) dependence. In spite of this increment, Ic/Ie is still below 2.5  102 at 150 °C. Moreover, BV also increases with temperature as 0.16 V/°C, being BV  150 V the lowest value at 40 °C.

1 For interpretation of color in Fig. 7, the reader is referred to the web version of this article.

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Nepi/BLN/P-/N++

450

Nepi/BLN/N-/N++

190 180

400

1

TCAD

170

BLN

160

350 BLN

2

BV (V)

150 N-

140

300

120 1.0E+15 1 2

250 P-

200 P++

Dint=4um Dint=10um

130

2.0E+15 Nepi N-3.0E+15 Nepi =(cm-3)

4.0E+

EXP.

P++

150 Fig. 7. Equipotential lines at BV extracted by TCAD in Nepi/BLN/P/P+ and Nepi/ BLN/N/P+. The critical region showing avalanche process at BV is indicated with a circle.

1.E-01

0

10

20 Dint (um)

30

40

Fig. 9. Measured BV vs. Dint in Nepi/BLN/P/P+ DTI test structures. Inset: BV vs. Nepi for Dint = 4 and 10 lm extracted from TCAD.

200

Dint

10

190

Fixed Tox and N-

9

180

170

1.E-03

BV (V)

Ic/Ie

A

160

A'

Minimum Dint (um)

8 1.E-02

7 6 5 4 3 2 1

150

0 0

1.E-04 -60

50

100 150 Vdepl (V)

200

250

140 -30

0

30 60 90 Temperature (C)

120

150

Fig. 8. Measured Ic/Ie and BV vs. temperature (adjacent pockets).

3.2. New design rules for the test structures The DTI test structures described in Section 2 are usually minimized to reduce the area consumption. This minimization implies the use of the smallest design rules to define the distance between trenches (Dint). In this sense, Dint can be reduced down to 3 lm. Nevertheless, a BV enhancement has been observed for small-size DTI pockets thus exceeding 400 V when Dint = 3 lm pocket (see Fig. 9). These measurements are carried out by defining identical biasing conditions than in Section 3.1. The BV for short Dint is boosted due to the interaction between the depletion regions in the inner pocket. This interaction occurs when the lateral depletion originated in MOS-trench walls merge in the center of the inner pocket (see lateral arrows in Fig. 10). Similarly than in charge-balanced power devices [15], a more uniform distribution of the electric field takes place in the vertical sense and the resultant BV is higher than in the non-depleted case. The impact of Dint on BV has been corroborated by TCAD simulations. The inset of Fig. 9 shows the BV vs. N relation for Dint = 4 and 10 lm. When N = Nepi the obtained BV values, indicated by circles 1 and 2, are in accordance to the measured values for Dint = 4 and 10 lm. In Dint = 4 lm and N = Nepi the depletion of the inner pocket is complete at BV, for this reason Nepi is close

Fig. 10. Schematic representation of the depletion region contour. Minimum Dint for a required BV (from Eq. (2)).

to the optimum value. Contrarily, in Dint = 10 lm an N < Nepi is required to provide complete depletion and higher BV. Since the real pockets for power MOSFETs show large area, the BV enhancement in the test structures must be suppressed to obtain realistic BV values. In order to avoid complete inner pocket depletion before the DTI breakdown, a minimum Dint must be defined. The minimum Dint for a given DTI voltage capability can be found by solving 1D Poisson equation in the AA0 cut in Fig. 10. The required voltage to provide complete depletion (Vdepl) can be written as

V depl

 2 ! q  Nepi esi Dint ¼ Dint  tox  þ 2  eo  eox eox 2

ð2Þ

where q is the electronic charge, eo is the permittivity of free space, esi and eox are the relative dielectric permittivities of Si and SiO2. Applying this formula in our specific case we obtain the values plotted in Fig. 10. These values demonstrate that Dint = 6.5 lm is required to avoid complete depletion before a BV = 150 V. This criterion matches quite well with the data in Fig. 9 showing a relevant BV increment for Dint below 6 lm. 4. Conclusions This work presents, assesses by simulation and experimentally proves a new high-voltage Deep Trench Isolation (DTI) structure in

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a Nepi/BLN/N/P+ Silicon stack. This isolation structure is addressed to high-voltage (120 V) devices integrated in a 0.18 lm Smart Power technology. The good performance in terms of voltage capability (BV > 150 V) and minority carrier injection (log(Ic/ Ie) < 2) is demonstrated for a wide range of temperatures (40 °C to 150 °C). Acknowledgement This work is carried out in the frame of the MEDEA+ 2T205 ‘‘SPOT” project. References [1] Gonnard O, Charitat G, Lance P, Stefanov E, Suquet M, Bafleurl M, et al. Substrate current protection in smart power IC’s. In: ISDP; 2000. p. 169–72. [2] Swanenberg MJ, Ludikhuize AW, Grakist A. Applying DMOSTs, diodes and thyristors above and below substrate in thin-layer SOI. In: ISPSD; 2003. p. 232– 6. [3] Gilbert PV, Crabtree PE, Sun SW. Latch-up performance of a Sub-0.5 micron inter-well deep trench technology. In: IEDM; 1993. p. 731–4. [4] Parthasarathy V, Zhu R, Khemka V, Roggenbauer T, Bose A, Hui P, et al. A 0.25 lm CMOS based 70 V Smart Power technology with deep trench for highvoltage isolation. In: IEDM; 2002. p. 459–62.

[5] Khemka V, Roggenbauer T, Parthasarathy V, Puchades I, Zhu R, Bose A, et al. A nondestructive electrical test structure to monitor deep trench depth for automated parametric process control. IEEE Trans Semicond Manuf 2004;17(2):98–103. [6] Khemka V, Parthasarathy V, Zhu R, Bose A, Roggenbauer T. Trade-off between high-side capability and substrate minority carrier injection in deep submicron smart power technologies. In: ISPSD; 2003. p. 241–4. [7] De Pestel F, Moens P, Hakim H, De Vleeschouwer H, Reynders K, Colpaert T, et al. Development of a robust 50 V 0.35 pm based Smart Power technology. In: ISPSD; 2003. p. 182–5. [8] Desoete B, De Smet A, Moens P. A multiple deep trench isolation structure with voltage divider biasing. In: ISPSD; 2007. p. 213–6. [9] Park JN, Cha K, Lee, Jeon H, Choi H, Kim J, Kim S, et al. A BCD18 – an advanced 0.18 lm BCD technology for PMIC application. In: ISPSD; 2009. p. 231–4. [10] Kitahara H, Tsukihara T, Sakai M, Morioka J, Deguchi K, Yonemura K, et al. A deep trench isolation integrated in a 0.13 lm BiCD process technology for analog power ICs. In: BCTM; 2009. p. 206–9. [11] Knaipp M, Stueckler E, Bissmann W. Development of a high voltage deep trench environment for a smart power technology. In: EPE; 2009. p. 1–9. [12] Takahashi T, Terashima T, Moritani J. Trench-isolated high-voltage IC with reduced parasitic bipolar transistor action. In: ISPSD; 2007. p. 69–72. [13] Parthasarathy V, Khemka V, Zhu R, Puchades I, Roggenbauer T, Butner M, et al. A multi trench analog + logic protection (M-TRAP) for substrate crosstalk prevention in a 0.25 lm smart power platform with 100 V high-side capability. In: ISPSD; 2004. p. 427–30. [14] Sentaurus Z-2007.03. Synopsys. . [15] Liang YC, Gan KP, Samudra GS. Oxide-bypassed VDMOS (OBVDMOS): an alternative to superjunction high voltage MOS power devices. IEEE Electron Dev Lett 2001;22:407–9.