OLA, A low-noise bipolar amplifier for the readout of silicon drift detectors

UCLEAR PHYSICS

PROCEEDINGS SUPPLEMENTS ELSEVIER

Nuclear Physics B (Proc. Suppl.) 44 (1995) 637--641

OLA, A low-noise bipolar amplifier for the readout of Silicon Drift Detectors W. D~browski a, W. Biatasa, G. Bonazzolab, V. Bonvicinic, F. Cerettob* , P. Giubellinob, M. Idzika, M. Prest c, L. RJccatib and N. Zampa c aFaculty of Physics and Nuclear Techniques Academy of Mining and Metallurgy, Cracow, Poland blNFN, Torino, Italy CINFN, Trieste, Italy

A very low noise, 32-channel preamplifier/shaper chip has been designed for the analogue readout of silicon detectors. The circuit has been optimised in view of the operation of Silicon Drift Detectors, which have very low capacitance and produce gaussian signals of cr up to -100 ns. The chip (OLA) has been designed and manufactured using the SHPi full-custom bipolar process by Tektronix. Each channel is composed by a preamplifier, a shaper and a symmetrical line driver, which allows to drive either a positive and a negative single ended output separately on 50 F2 impedance or a differential twisted pair. The intrinsic peaking time of the circuit is --60 ns, and the noise is below 250 electrons at zero input load capacitance. The power consumption is 2 mW/channel, mostly due to the output driver.

1. INTRODUCTION

2. DESIGN DESCRIPTION

Silicon Drift Detectors (SDD) exploit the measurements of the transport time of the charge deposited by a traversing particle to the collection electrodes to localise the impact point in one of the dimensions, while the position in other dimension is determined by the positions of collecting electrodes. Therefore they are ideally suited, as twodimentional detectors, to experiments in which high track densities are coupled with relatively low event rates. The precision of the detector in both coordinates is directly linked to the noise levels, and therefore it is very important to optimise the design of the front-end electronics to best exploit of the low capacitance of the anodes. Within the DSI collaboration, which is persuing an R&D program to demonstrate the possibility of large scale use of SDDs, as foreseen for example by the ALICE experiment at the LHC [1], we decided to follow a line in which the front-end electronics is designed as a full custom integrated chip bonded directly to the detector.

A 32 channels front-end chip for silicon drift detectors has been designed for the full custom bipolar process SHPi by Tektronix [2]. A single channel contains a preamplifier, a shaper and a symmetrical line driver. The noise, shaping, power dissipation have been taken into account in this design. The block diagram of the circuit and the complete schematic diagram are shown in figure 1. The outstanding feature of silicon drift detectors is the very low capacitance of the collecting anodes, which allows to obtain a good signal-to-noise ratio provided we use an optimised low input capacitance preamplifier. From the set of devices which are available in the SHPi process, we decided for a bipolar transistor as the input device. It is not the best one as far as only noise is concerned but it gives the best noise vs. power figure of merit.

* Now at MPI Heidelberg 0920-5632/95/$09.50 © 1.995 Elsevier Science B.V. All rights reserved. SSDI 0920-5632(95)00597-8

2.1. Preamplifier For the preamplifier a transimpedance configuration is used. The input stage is formed by

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Figure 1. Block diagram (a) and schematic diagram of the circuit (b). the bipolar cascode (Q1, Q2), in which the current is set by the external reference voltage VR2 via the current mirror Q23, Q24. This way one can optimise the current in the input stage to achieve the minimum of noise for a given detector capacitance. In the preamplifier configuration which has been used there are four significant noise sources: (1) equivalent voltage input noise due to shot noise of the collector current of Q1 (proportional to 1/Ic, (2) thermal noise of the base spread resistance of Q1, (3) shot noise of the base current of Q1 (proportional to Ic), (4) thermal noise of the feedback resistors RF1-RF6. Relative contributions of the voltage noise sources (1) and (2) and the current noise sources (3) and (4) are dependent on the detector capacitance and the shaping time constant. The nominal value of the collector current of the input transistor is set at about 20 rtA which gives the minimum of noise for the detector anode capacitance of about 0.3 pF at the given

shaping. For a larger input load capacitance the collector current of the input transistor can be increased and set for another optimum value. 2.2. Shaper

The method of a quasi-gaussian shaping was chosen. The shaper is essentially a multiple integrator. The time constant of the feedback loop of the preamplifier is short enough so that additional short differentiation is not required. The integration is distributed over the circuit. The first dominant pole is already introduced by the preamplifier. The main block of the shaper is formed by the differential pair Q10, QII which introduces three other poles and the pole-zero cancellation which is realised in the circuit consisting of collector resistors R12 and R13, capacitor C2 and the parasitic capacitances at the collector nodes of Q10 and Q l l . The differential amplifier Q10, QI1 converts also the single ended signal from the preamplifier to a differential one.

W. Dqbrowski et al./Nuclear Physics B (Proc. Suppl.) 44 (1995) 63~64I

The value of shaping time constant was chosen as a compromise taking into account the following aspects of the design: (1) noise - since the current noise sources are significant in the chosen configuration of the preamplifier and the detector capacitance is low (assumed 0.3 pF), the optimum shaping time constant is relatively short, of about 20 ns, (2) ballistic deficit - the expected current signals from silicon drift detectors are of gaussian shapes with t~ typically of 30 ns so a short integration time constant introduces a significant ballistic deficit, (3) sampling rate - the output pulses are supposed to be sampled by a FADC with a sampling rate of 50 MHz and at least three samples should be taken in the region where the signal level is well above the noise level, (4) double pulse resolution - determines the spatial double track resolution and requires a short shaping time constant [3]. Finally the peaking time of the shaper was chosen to be 55 ns for the nominal process parameters. Allowing the extreme variation of the process parameters within the range guaranteed by Tektronix the value of the peaking time for the final circuit was expected to be differ by no more than 5 ns compared with the above nominal value.

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H-20% and in some cases, like the current gain 13, by +/-40% of their nominal values. The design parameters of the circuit are listed in table 1. Table 1. Expected parameters of the circuit. Supply voltages VCC = +2 V VSUB =-2 V VR2 = +0.6 V VCR = +0.35 V 2.4 mW/channel Power consumption 30 mV/fC Gain for a ~-like pulse Dynamic range at 50 f2 load: for positive output pulse 300 mV for negative output pulse 500 mV Output resistance 50 f2 Peaking time 55 ns Expected ENC 230 el

2.3. Output drivers Since the circuit is supposed to be used in different set-ups requiring different schemes for the transmission of the output signals (single-ended or differential) two output drivers delivering complementary signals have been implemented in the circuit. Each of these drivers can drive separately a single-ended 50 ~ line or both of them can be used to drive a differential line. The output offset voltage can be tuned using the VCR reference voltage.

2.5. Layout 32 channels with the pitch of 160 i.tm are laid out in one die 5.6 mm wide and 3.6 mm long. The photograph of the chip is shown in figure 2. There are two rows of output pads, for positive and negative outputs. The bonding pads for the bias, control and calibration lines are placed on both sides of the die. To avoid a non uniform distribution of the bias currents across the chip it is recommended that each bias is bonded from both sides. A test capacitor of 100 tF is placed at each channel input.The test signal is provided to each channel through one of four calibration lines so, from each calibration input every fourth channel can be pulsed.

2.4. Simulation results The ~imulations have been done for the nominal process parameters as well as for two extreme sets of parameters (UP and DOWN) which correspond to the possible extreme variation of the process from one production run to another. These simulations do not tell us anything about the channel-to-channel or chip-to-chip matching of the circuit parameters, however, they show that the circuit is reasonably insensitive to the variation of the component parameters. One has to remember that the UP and DOWN libraries correspond to the variation of the component parameters typically by

Figure 2. Photograph of OLA chip.

W. Dqbrowski et al./Nuclear Physics B (Proc. Suppl.) 44 (1995) 637-641

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Figure 3. Output pulse waveforms for positive and negative outputs. 3. MEASUREMENTS OF BASIC CIRCUIT PARAMETERS

3.1. Basic functionality In order to verify and test all circuit parameters, an adequate measurement set up has been realised. A chip was glued onto a dedicated PC board. The channels could be pulsed through the four calibration inputs and 8 output channels (4 positive and 4 negative) were wire-bonded to the output lines on the board. The power consumption measured for standard bias conditions was about 2 mW/channel, even slightly less than the foreseen value of 2.4 mW/channel. Figure 3 shows typical output pulses at two complementary outputs of the same channel. The peaking time of about 55 ns is very close to the expected one. The shapes of output signals are as they could be expected for a limited number of integrations and the output signals at both complementary outputs are fully symmetric. For the chip bonded on a PC board we measured the crosstalk between adjacent channels to be bellow 1%, value which should be considered as an upper limit, since it could still can be dominated by the crosstalk on the board.

3.2. Gain and linearity Figure 4 shows the linearity plots for the positive and the negative outputs measured at the nominal bias voltages. The output signals were measured on a 50 f) load. A good linearity has been obtained up to 8 fC of input charge for the positive output signal, and up to 10 fC of input charge for the negative output signal. The output linear dynamic ranges are 250 mV and 200 mV for the negative and positive output respectively. A small non-linearity appears for low input signals (below 3000 electrons) which is due to a nonlinear 300 f

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W Dqbrowski et al./Nuclear Physics B (Proc. Suppl.) 44 (1995) 637-641

behaviour of the output resistances of the output drivers. This nonlinearity is negligible if the circuit is loaded with a higher load, in the range of 1 k.Q. The gain obtained for the linear range is 28.8 mV/fC and 27.5 mV/fC for negative and positive output respectively which is in good agreement with the expected value of 30 mV/fC. The results shown in figure 4 represent characteristics of a typical channel. A critical issue for this kind of multichannel chip is the matching between the channels as well as the matching between chips. Measuring all the channels on a chip we obtained the gain variation of 1.9% (lo). For the output offset measured at the given value of VCR voltage we obtained an average value of -0.08 mV and a standard deviation of 1.33 mV which is 1.2% of the output signal for a MIP input signal.

3.3. Noise As mentioned above the design has been optimised for a very low input load capacitance, below 0.5 pF. This requirements together with the requirement concerning the shaping time constant (peaking time of 55 ns) results in a optimum value for the collector current of the input transistor which is of about 25 ~tA. The plot of ENC vs collector current of input transistor for zero input load capacitance is shown in figure 5. Obviously, for larger input load capacitances one needs a higher current in the input stage to reduce the series noise. In figure 6 we show, as an example, the ENC vs input load capacitance for a collector current of 75 ~A. The values of noise 300

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4. SUMMARY A 32 channel low-noise low-power front-end chip for silicon drift detectors has been designed and manufactured. The measured parameters and characteristics of the chip are very close to the design values. The obtained noise below 250 electrons at the peaking time and of 60 ns is fully adequate to the requirements of silicon drift detectors proposed for the ALICE experiment. The chip offers also good performances for higher input load capacitances and can be used as front-end chip for other detectors, like silicon strips or MSGCs. REFERENCES

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1. Letter of Intent for A Large Ion Collider Experiment, CERN/LHCC/93-16, 1993. 2. SHPi Full Custom Integrated Circuit Design Guide, Tektronix INC., Beaverton, OR 97077. 3. E. Gatti et al. Nucl. Instr. and Meth. A274, (1989), 469.

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Aekonwledgements The help and support of A.Vacchi throughout this project is gratefully acknowledged.