- Email: [email protected]
On-chip electrostatic discharge protections in advanced CMOS technologies
Microelectron. Reliab.,Vol. 32, No. 11, pp. 1545-1550, 1992. Printed in Great Britain.
0026-2714/9255.00+ .00 PergamonPress Ltd
ON-CHIP ELECTROSTATIC DISCHARGE PROTECTIONS IN ADVANCED CMOS TECHNOLOGIES N. MAENE,J. VANDENBROECKand K. ALLAERT Alcatel Bell Telephone, Francis Wellesplein 1, B-2018 Antwerpen, Belgium Abstract--In this paper several on-chip electrostatic discharge (ESD) protections for inputs, outputs and supply pins are discussed. By comparing different structures, insight has been attained in the most important parameters determining the ESD sensitivity, and optimal protections for the Human Body Model 0-IBM) which could be selected. In addition the test method as prescribed by the Mil-Std 883C Method 3015.7 is discussed more into detail, leading to the concept of using a supply protection for improving the ESD performance of inputs/outputs (I/Os). For input protections the performance of the lateral silicon controlled rectifier (SCR) structure is found to be superior to the behaviour of the classical thick oxide protection, the minimum failure voltage of the former being 6000V. Several alternatives for CMOS outputs are also presented. A comparison between the "waffle" layout and the more classical ladder layout concerning the ESD performance is made. A minimum failure voltage of 1750 V for stressing the output vs the ground for both polarities has been seen on one of our output structures. However, the output failure voltage can be increased by using a good supply protection, providing a parallel discharge path. The concept of using a supply protection for achieving a better ESD hardness is highlighted in this paper. An output of a ring oscillator with a thick oxide supply protection did not fail up to 2000 V for a worst case stress, and using a SCR supply protection with an optimised output layout still should result in a better ESD hardness.
INTRODUCTION Electrostatic discharge or ESD is the well-known problem causing VLSI chips to fail due to discharge currents during handling. This paper discusses onchip ESD protections against failures according to the Human Body Model (HBM). It is known that for advanced CMOS technologies the ESD performance becomes more critical compared to the conventional processes [1]. Due to the scaling of geometries, junctions become shallower, oxides thinner and lightly doped drain (LDD) transistors are being introduced in these processes. These features degrade the ESD performance of the circuits. In this paper some results of the HBM evaluation of on-chip ESD protections in CMOS are presented. Different types of input protections and output layouts are processed and evaluated using a 1.2gm CMOS twin-tub technology with LDD transistors and a p-type epitaxial layer on a p + substrate. The ESD performances of different input and output protections are compared, and the most important parameters are highlighted. This paper also reports on the evaluation of supply protections in this technology.
3015.7. This method requires firstly, that a test of each device pin vs the ground pin(s) and vs each different set of a combination of all the power supply pins, with the other pins open, is performed. Secondly, the IC must withstand pulses on each input and output vs a combination of all the other input and output pins, with the other pins open. Each pin combination should be tested for both polarities. Referring to the measurement method above, one should remark that stressing an input or output pin to only one of the supply pins (VDD or VSS) for both polarities, keeping the other supply pin open, is much more a "worst case" test than stressing an I/O pin with both the VSS and VDD supplies at ground. Indeed in the latter situation, a simple I/O protection with two diodes (one between the VSS and the pad, the other between the pad and the VDD, see Fig. I) can already be considered to be a satisfying structure, since it will always have one diode forwardly biased, whatever polarity is used. On the contrary, with the
7
EXPERIMENTS AND TEST STRUCTURES
Measurement method and strategy of design The protections are tested according to the Human Body Model as specified in M i l ~ t d 883C Method
Fig. 1. The simple two-diode concept. 1545
1546
N. MAENEet aL CI
//////////J/
_vs d
v5$
Fig. 3. Schematic of the thick oxide device input protection.
b
..;.)....
.
Fig. 2. The function of a supply protection (a and b). test method used here, the following pin combinations will be a problem for the two-diode concept: (1) (with (2) VDD
stressing the I/O pin negatively vs the VDD VSS open); Stressing the I/O pin positively vs the VSS (with open).
In case (1), the problem can be solved by designing an ESD protection between the VDD supply and the VSS, able to conduct positive stresses. Stressing the I/O pin negatively vs the VDD will then turn on the supply protection, and the diode between the VSS and the I/O p a d - - i n series to that protection--will be forwardly biased (see Fig. 2a). In case (2), one can select a structure that turns on for positive stresses as described below for the inputs, while for CMOS outputs the n MOS transistor can go into snapback from its own. The problem here is to make these devices robust enough. In the literature there are agreements that this is mainly a problem for the outputs [2], while in general the inputs cause fewer problems. Also, here, a supply protection able to turn on for positive pulses is useful. For positive pulses vs the VSS, the diode between the output and the VDD will conduct; in series to this diode, the supply protection will turn on (see Fig. 2b). This discharge path from the output to the VSS through the floating VDD is in parallel to the direct path through the n MOS in snapback. Therefore the supply protection can help to improve the ESD performance of the output. These concepts are now worked out below.
oxide) with the gate and the source at VSS, and a diffusion resistor limiting the current in the thin oxide n MOS. For the working principle, we refer to the paper of C. Duvvury et al. [1]. One must be careful at the layout of this TOD protection, since a bad layout can spoil the ESD performance. The TOD has been made more robust by designing a n-well around the drain, making the junction deeper, and the current density more uniform. Two versions of this protection are designed to check the influence of the drain contact: one TOD has many minimum designed drain contacts, and the other has one large contact. (2) The second input protection, shown in Fig. 4, has been proposed by L. Avery [2] and worked out by C. Duvvury et al. [3]. This protection has a lateral SCR instead of the TOD device, and again a secondary protection is used. In addition, a diode to the VDD is placed--for the positive stress vs the VDD, which will not be discussed here. The SCR will turn on at positive voltages vs VSS, after the secondary protection starts to conduct, the principle being equal as for the TOD protection. The lateral SCR is formed by a p + diffusion and a n + diffusion, both in the same n-well and both connected to the input pad, and another n + diffusion in the p-well, as shown in Fig. 5. The distance between the n-well and the p + diffusion lying in it, and between the n-well and the n + diffusion in the p-well must not be minimal, since this limits the current dissipated by the SCR. The layout of the lateral SCR input protection is in Fig. 6. Outputs
Two layouts are possible for the output buffer: one is the conventional ladder or finger layout, the alternative is the so-called "waffle" layout [4, 5] (see Figs 7 and 8). Important parameters for ESD for both types of layout are the spacing from the drain contacts to the poly gate (DS), the gate length (Lg), and the perimeter of the drain diffusions. Also, the form of the drain diffusions is important, e.g. for a finger layout
Input protections
As explained above, we designed input protections which conduct both for positive and negative stresses vs VSS. Mainly two approaches are considered. (l) The first structure is the well-known thick oxide device (TOD) protection as shown in Fig. 3. This is basically a robust field oxide n MOS transistor with the drain and metal gate connected to the pad in parallel with a secondary protection, which consists of a small gate length n MOS transistor (with gate
-
VSS
Fig. 4. Schematic of the SCR input protection.
Advanced CMOS technologies ////////////////~//,/,/,////A
• I I
I
""
1547
ox~
~
J.
Fig. 5. Intersection of the SCR input protection. it is better to have few long fingers than many short ones, because not all the fingers go into snapback, as described in [6]. For the waffle buffers three versions have been designed: (1) buffers in waffle layout with Lg = 2/tm and DS = 2.3/~m (waffle 1); (2) buffers in waffle layout with Lg = 2/~m and DS = 2.3/~m, with diodes to the VDD and VSS, and a poly resistor of 1.5 square limiting the power dissipated in the buffer (waffle 2), and (3) buffers in wffle layout with Lg = 1.2 g m and DS = 2.7 #m, with two diodes in parallel (waffle 3, see Fig. 7).
For the ladder buffers three versions have also been tested: (1) ladders with Lg = 1.2 p m and DS = 2.7/~m and two diodes in parallel (ladder 1, see Fig. 8---comparable to waffle 3); (2) ladders with Lg = 1.2/~m and DS = 5 # m and two diodes (ladder 2), and (3) ladders with Lg = 1.2 # m and DS = 5 # m and two diodes, but now with n-wells at the n MOS drain diffusion (ladder 3). It is expected that the smaller the gate length, Lg, and the larger the distance, DS, is, the better the ESD performance of the nMOS will be. This is because of the lower snapback voltage and the larger drain resistance, respectively. To compare the waffle and the ladder nMOS with the same Lg and DS, two structures with the same transistor area and a comparable electrical width are designed (Figs 7 and 8). Special test structure
Fig. 6. Layout of the SCR input protection.
A special test structure with supply protections is designed, consisting of a 40-stage ring oscillator and a buffer (see Fig. 9). The ring oscillator and the buffer have two separate power supplied V D D A and VDDB. The buffer output has a simple two-diode protection to VSS and VDDB with a small poly resistor of 30 f~ between the buffer drain and the output pad, to limit the dissipation in the buffer during ESD. As a supply protection, the same TOD structure with the small drain contacts as discussed in the input section has been used to protect VDDB for stresses vs VSS, as well as for VDDA vs VSS.
Fig. 7. Layout of the waffle output number 3.
Fig. 8. Layout of the ladder output number I.
N. MAENEet al.
1548
i...........
i.
.
.
.
.
.
.
.
.
.
VI~A .
J
n
~
i.................
VSS
I
L .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
J
Fig. 9. Special test structure with supply protection.
Experiments Since the method 3015.7 requires a whole lot of pin combinations to be stressed, the following pin combinations have been selected here to focus our attention
on.
(1) Inputs and outputs are stressed both positively and negatively vs the VSS, while the VDD is left open. The failure criterium for the proposed inputs is a current of 1/~A at + 8 V, and the invertor connected at the protection still has to be functional. For the outputs, the leakage current should be less than 1/~A at 0 V and + 5 V with the output in a tri-state, and the buffer still has to be functional as an invertor. (2) On the ring oscillator with the supply protection, the output is stressed for both polarities, not only vs the VSS, but also vs the VDD. The criterion here is that the ring oscillator should still be functional with an amplitude of at least 4 V. (3) A third kind of test consists of stressing the VDD supply of the ring oscillator itself vs the VSS bus for both polarities. The same failure criterion as above is used here.
a sample size of five devices for each kind of protection. The inputs are step stressed with a step of 500 V. The classical thick oxide device (TOD) protection gives good results with a lowest failure voltage of 3500V. Negative pulses forwardly bias the diode of the n + drain of the TOD in the p-well, so no problems are expected here. Indeed the results show that the inputs all fail for positive ESD voltages when the TOD has been turned on. Comparing the two TOD versions with the different drain contacting, shows that one large drain contact for the TOD seems to be better than many minimum contacts: the lowest failure voltage is 4500 V for the large contact, compared with 3500 V for the small contacts. Probably the current density is more uniform in the case of one large contact. The lateral SCR protection is even better than the TOD structure, giving excellent results of 6000 V minimum failure voltage. Since the secondary protection has a layout which is similar to the one of the TOD protection, this proves that the SCR is more robust once it is turned on.
Outputs
RESULTS AND DISCUSSION
Input protections The inputs are stressed vs the VSS. Table 1 shows the mean failure threshold voltages together with the standard deviation and the lowest failure voltage for
For positive voltages on the CMOS output pad vs the VSS, the n MOS transistor is the weak part of the output, since the total ESD voltage comes over the n MOS. This worst case test has been performed on the different outputs, in order to study the n MOS
Table 1. Mean failure voltage, standard deviation (sigma) and minimum failure voltage of input, output and supply protections. Mmn V Iwll
Slanclard Dwvlal~
Min. V kin1
TOG {stud conlacls)
4000 V
320V
3S00 V
TOO I k ~ e conkm)
.5100 V
49OV
450O V
sol i~t~tmmutm
7OOOv
7tov
6ooo v
1125 V
350V
750 V
1450
310V
1250V
141= 1.2p, DSffi 3.7p
1750 V
3SOV
1250 V
tliffi !.21a, DSffi 3.7p
1375 V
375V
1000 V
tg : !.2 p, DS : $1a
2200V
680V
ISOOV
ladder Lg = 1.2 p, DSffi 5la + dlod~ + n vndls
30SOV
1040V
1750V
te=Sp DS ffi 2.3 la I Waffle t0 = 2 p, DS m 2.3 la + diockn + nnlslor Waffle
+diodes Ladder
+diodes + dlodes
1549
Advanced CMOS technologies robustness for positive pulses. The outputs are step stressed with a step voltage of 250 V. A sample size of ten has been taken for the waffle 1 and 2, and five for the other outputs. The results of the ESD tests are shown in Table 1. As expected all outputs are failing for positive voltages. The waffle outputs with gate length Lg = 2 # m and spacing from drain contacts to poly gate DS = 2.3 p m seem to have very weak nMOS transistors, with the minimum failure voltage already at 750 and 1000 V. The same waffles, but now with a poly resistor of 30 t2 and two diodes, have a minimum failure voltage of 1250 V. As expected these results are slightly better than the previous ones, since the resistor limits the power dissipated in the nMOS that has gone into snapback for positive voltages vs VSS. The waffle output with a smaller gate length of 1.2 # m and a larger distance DS of 2.7/~m (and two diodes), behaves better than the first ones, although there is no resistor here: the minimum failure voltage is 1250 V. This improvement is because the smaller gate length lowers the snapback voltage of the nMOS, while a larger distance, DS, adds some drain resistance and more importantly, makes the current density more uniform over the drain perimeter. The ladder output with L g = 1.2pm and DS = 2.7 p m - - s i m i l a r to the waffle output discussed above---has a minimum failure voltage of 1000V, compared to the 1250 V for the similar waffle 3. This indicates that for these specific Lg and DS the waffle output has to be preferred over the ladder layout. However, for a larger DS (e.g. 5 #m) all the drain diffusions of a waffle layout become much larger, resulting in a much too large total transistor area. The advantage of the ladder layout here is that a DS of 5 # m results in a total transistor area which still is acceptable. The ladder layout with L g = 1.2#m and DS = 5 / ~ m gives a minimum failure voltage of 1500 V, while the same ladder with n-wells at the drain diffusions gives a minimum failure voltage of 1750 V. The n-wells at the drain diffusions should still be optimised in terms of overlap around the drain contacts, and distance from the n-well edge to the poly gate. We can conclude that positively stressing the n MOS vs the VSS gives failures at a minimum voltage of 1750 V for the best tested output. This is a ladder layout with Lg = 1.2/~m and DS = 5 # m with n-wells at the drain diffusions. This still could be optimised by adjusting the layout. However, these results do not characterise the total performance of outputs, since a supply protection can help to reduce the positive voltage on the drain of the n MOS as demonstrated below.
Supply protection and impact on I / 0 performance The output of the ring-oscillator buffer is tested vs the VSS for both polarities. Negative voltages
forwardly bias the drain diode of the n MOS (and the extra diode) and provide no problems. For positive pulses the n MOS can go into snapback, while a parallel path is present through the supply protection and the diode between the output pad and the VSS---as explained above (Fig. 2b). Positive pulses make this structure fail at a minimum failure voltage of 2000 V, as shown in Table 1. Stressing the output vs the VDD for both polarities has a similar working principle. Positive voltages bias the p M O S drain diode forwardly (together with the extra diode). For negative pulses the supply protection and the diode between the VSS and the output become a discharge path between the VDD and the output over the VSS (Fig. 2a). The minimum failure voltage of the ring oscillator is 2000 V for negative stresses. Stressing the supply pin of the ring oscillator vs the VSS for both polarities gives a failure at a minimum voltage of + 3500 V. This is comparable to the minimum failure voltage of the inputs protected by the same structure, so these results are consistent. The minimum failure voltage, for the output tests for this test structure, is lower than for the supply stress test, since there is a diode in series to the supply protection, and for positive pulses vs the VSS, the nMOS is in parallel with the protection. This supply protection can be enhanced by choosing the lateral SCR protection, as proposed for the input protection. This alternative will probably give better results for the stress of the output.
CONCLUSION We can conclude that by studying various versions of ESD protections in 1.2/~m CMOS, we gained insight into the most important parameters determining the ESD performance and which optimal protections could be selected. For the input protection, the lateral SCR protection gives the best results with a minimum failure voltage of 6000V, while the thick oxide device structure fails from 3500 V onwards. For outputs, the waffle layout has to be preferred over the ladder layout for small spacings between drain contacts and gate, but for larger spacings the ladder layout uses less area. One of the tested ladder buffers has a minimum failure voltage of 1750 V for stressing the n MOS vs the VSS. However, the output failure voltage can be increased by using a good supply protection that provides a parallel path for the discharge. An output with two diodes and a thick oxide device supply protection did not fail until 2000 V. Improving the layout of the output buffer and using the SCR structure as a supply protection should still lower the ESD sensitivity.
1550
N. MAENE et al. REFERENCES
1. C. Duvvury, R. A. McPhee, D. A. Baglee and R. N. Rountree, ESD Protection reliability in 1 p.m CMOS technologies, Proe. IRPS, pp. 199-205 (April, 1986). 2. L. Avery, Using SCRs as transient protection structures in integrated circuits, Proc. EOS/ESD Syrup. EOS-5, 177-180 (September, 1983). 3. C. Duvvury, T. Taylor, J. Lindgren, J. Morris and S. Kumar, Input protection design for overall chip reliability, Proe. EOS/ESD Syrup. EOS-11, 190-197 (September, 1989).
4. L. Baker, R. Currence, S. Law, M. Le, S. T. Lin and M. Teene, A waffle layout technique strengthens the ESD hardness of the nMOS output transistor, Proc. EOS/ESD Syrup. EOS-11, 175-181 (September, 1989). 5. N. Maene, J. Vandenbroeck and K. Allaert, 1.2#m CMOS ESD protection network optimisation for latchup and minimum area, Proc. ESREF '90, pp. 345-352. Valenzano (2-5 October, 1990). 6. T. Polgreen and A. Chatterjee, Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow, Proc. EOS/ESD Symp. EOS--ll, 167-174 (September, 1989).
0026-2714/9255.00+ .00 PergamonPress Ltd
ON-CHIP ELECTROSTATIC DISCHARGE PROTECTIONS IN ADVANCED CMOS TECHNOLOGIES N. MAENE,J. VANDENBROECKand K. ALLAERT Alcatel Bell Telephone, Francis Wellesplein 1, B-2018 Antwerpen, Belgium Abstract--In this paper several on-chip electrostatic discharge (ESD) protections for inputs, outputs and supply pins are discussed. By comparing different structures, insight has been attained in the most important parameters determining the ESD sensitivity, and optimal protections for the Human Body Model 0-IBM) which could be selected. In addition the test method as prescribed by the Mil-Std 883C Method 3015.7 is discussed more into detail, leading to the concept of using a supply protection for improving the ESD performance of inputs/outputs (I/Os). For input protections the performance of the lateral silicon controlled rectifier (SCR) structure is found to be superior to the behaviour of the classical thick oxide protection, the minimum failure voltage of the former being 6000V. Several alternatives for CMOS outputs are also presented. A comparison between the "waffle" layout and the more classical ladder layout concerning the ESD performance is made. A minimum failure voltage of 1750 V for stressing the output vs the ground for both polarities has been seen on one of our output structures. However, the output failure voltage can be increased by using a good supply protection, providing a parallel discharge path. The concept of using a supply protection for achieving a better ESD hardness is highlighted in this paper. An output of a ring oscillator with a thick oxide supply protection did not fail up to 2000 V for a worst case stress, and using a SCR supply protection with an optimised output layout still should result in a better ESD hardness.
INTRODUCTION Electrostatic discharge or ESD is the well-known problem causing VLSI chips to fail due to discharge currents during handling. This paper discusses onchip ESD protections against failures according to the Human Body Model (HBM). It is known that for advanced CMOS technologies the ESD performance becomes more critical compared to the conventional processes [1]. Due to the scaling of geometries, junctions become shallower, oxides thinner and lightly doped drain (LDD) transistors are being introduced in these processes. These features degrade the ESD performance of the circuits. In this paper some results of the HBM evaluation of on-chip ESD protections in CMOS are presented. Different types of input protections and output layouts are processed and evaluated using a 1.2gm CMOS twin-tub technology with LDD transistors and a p-type epitaxial layer on a p + substrate. The ESD performances of different input and output protections are compared, and the most important parameters are highlighted. This paper also reports on the evaluation of supply protections in this technology.
3015.7. This method requires firstly, that a test of each device pin vs the ground pin(s) and vs each different set of a combination of all the power supply pins, with the other pins open, is performed. Secondly, the IC must withstand pulses on each input and output vs a combination of all the other input and output pins, with the other pins open. Each pin combination should be tested for both polarities. Referring to the measurement method above, one should remark that stressing an input or output pin to only one of the supply pins (VDD or VSS) for both polarities, keeping the other supply pin open, is much more a "worst case" test than stressing an I/O pin with both the VSS and VDD supplies at ground. Indeed in the latter situation, a simple I/O protection with two diodes (one between the VSS and the pad, the other between the pad and the VDD, see Fig. I) can already be considered to be a satisfying structure, since it will always have one diode forwardly biased, whatever polarity is used. On the contrary, with the
7
EXPERIMENTS AND TEST STRUCTURES
Measurement method and strategy of design The protections are tested according to the Human Body Model as specified in M i l ~ t d 883C Method
Fig. 1. The simple two-diode concept. 1545
1546
N. MAENEet aL CI
//////////J/
_vs d
v5$
Fig. 3. Schematic of the thick oxide device input protection.
b
..;.)....
.
Fig. 2. The function of a supply protection (a and b). test method used here, the following pin combinations will be a problem for the two-diode concept: (1) (with (2) VDD
stressing the I/O pin negatively vs the VDD VSS open); Stressing the I/O pin positively vs the VSS (with open).
In case (1), the problem can be solved by designing an ESD protection between the VDD supply and the VSS, able to conduct positive stresses. Stressing the I/O pin negatively vs the VDD will then turn on the supply protection, and the diode between the VSS and the I/O p a d - - i n series to that protection--will be forwardly biased (see Fig. 2a). In case (2), one can select a structure that turns on for positive stresses as described below for the inputs, while for CMOS outputs the n MOS transistor can go into snapback from its own. The problem here is to make these devices robust enough. In the literature there are agreements that this is mainly a problem for the outputs [2], while in general the inputs cause fewer problems. Also, here, a supply protection able to turn on for positive pulses is useful. For positive pulses vs the VSS, the diode between the output and the VDD will conduct; in series to this diode, the supply protection will turn on (see Fig. 2b). This discharge path from the output to the VSS through the floating VDD is in parallel to the direct path through the n MOS in snapback. Therefore the supply protection can help to improve the ESD performance of the output. These concepts are now worked out below.
oxide) with the gate and the source at VSS, and a diffusion resistor limiting the current in the thin oxide n MOS. For the working principle, we refer to the paper of C. Duvvury et al. [1]. One must be careful at the layout of this TOD protection, since a bad layout can spoil the ESD performance. The TOD has been made more robust by designing a n-well around the drain, making the junction deeper, and the current density more uniform. Two versions of this protection are designed to check the influence of the drain contact: one TOD has many minimum designed drain contacts, and the other has one large contact. (2) The second input protection, shown in Fig. 4, has been proposed by L. Avery [2] and worked out by C. Duvvury et al. [3]. This protection has a lateral SCR instead of the TOD device, and again a secondary protection is used. In addition, a diode to the VDD is placed--for the positive stress vs the VDD, which will not be discussed here. The SCR will turn on at positive voltages vs VSS, after the secondary protection starts to conduct, the principle being equal as for the TOD protection. The lateral SCR is formed by a p + diffusion and a n + diffusion, both in the same n-well and both connected to the input pad, and another n + diffusion in the p-well, as shown in Fig. 5. The distance between the n-well and the p + diffusion lying in it, and between the n-well and the n + diffusion in the p-well must not be minimal, since this limits the current dissipated by the SCR. The layout of the lateral SCR input protection is in Fig. 6. Outputs
Two layouts are possible for the output buffer: one is the conventional ladder or finger layout, the alternative is the so-called "waffle" layout [4, 5] (see Figs 7 and 8). Important parameters for ESD for both types of layout are the spacing from the drain contacts to the poly gate (DS), the gate length (Lg), and the perimeter of the drain diffusions. Also, the form of the drain diffusions is important, e.g. for a finger layout
Input protections
As explained above, we designed input protections which conduct both for positive and negative stresses vs VSS. Mainly two approaches are considered. (l) The first structure is the well-known thick oxide device (TOD) protection as shown in Fig. 3. This is basically a robust field oxide n MOS transistor with the drain and metal gate connected to the pad in parallel with a secondary protection, which consists of a small gate length n MOS transistor (with gate
-
VSS
Fig. 4. Schematic of the SCR input protection.
Advanced CMOS technologies ////////////////~//,/,/,////A
• I I
I
""
1547
ox~
~
J.
Fig. 5. Intersection of the SCR input protection. it is better to have few long fingers than many short ones, because not all the fingers go into snapback, as described in [6]. For the waffle buffers three versions have been designed: (1) buffers in waffle layout with Lg = 2/tm and DS = 2.3/~m (waffle 1); (2) buffers in waffle layout with Lg = 2/~m and DS = 2.3/~m, with diodes to the VDD and VSS, and a poly resistor of 1.5 square limiting the power dissipated in the buffer (waffle 2), and (3) buffers in wffle layout with Lg = 1.2 g m and DS = 2.7 #m, with two diodes in parallel (waffle 3, see Fig. 7).
For the ladder buffers three versions have also been tested: (1) ladders with Lg = 1.2 p m and DS = 2.7/~m and two diodes in parallel (ladder 1, see Fig. 8---comparable to waffle 3); (2) ladders with Lg = 1.2/~m and DS = 5 # m and two diodes (ladder 2), and (3) ladders with Lg = 1.2 # m and DS = 5 # m and two diodes, but now with n-wells at the n MOS drain diffusion (ladder 3). It is expected that the smaller the gate length, Lg, and the larger the distance, DS, is, the better the ESD performance of the nMOS will be. This is because of the lower snapback voltage and the larger drain resistance, respectively. To compare the waffle and the ladder nMOS with the same Lg and DS, two structures with the same transistor area and a comparable electrical width are designed (Figs 7 and 8). Special test structure
Fig. 6. Layout of the SCR input protection.
A special test structure with supply protections is designed, consisting of a 40-stage ring oscillator and a buffer (see Fig. 9). The ring oscillator and the buffer have two separate power supplied V D D A and VDDB. The buffer output has a simple two-diode protection to VSS and VDDB with a small poly resistor of 30 f~ between the buffer drain and the output pad, to limit the dissipation in the buffer during ESD. As a supply protection, the same TOD structure with the small drain contacts as discussed in the input section has been used to protect VDDB for stresses vs VSS, as well as for VDDA vs VSS.
Fig. 7. Layout of the waffle output number 3.
Fig. 8. Layout of the ladder output number I.
N. MAENEet al.
1548
i...........
i.
.
.
.
.
.
.
.
.
.
VI~A .
J
n
~
i.................
VSS
I
L .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
J
Fig. 9. Special test structure with supply protection.
Experiments Since the method 3015.7 requires a whole lot of pin combinations to be stressed, the following pin combinations have been selected here to focus our attention
on.
(1) Inputs and outputs are stressed both positively and negatively vs the VSS, while the VDD is left open. The failure criterium for the proposed inputs is a current of 1/~A at + 8 V, and the invertor connected at the protection still has to be functional. For the outputs, the leakage current should be less than 1/~A at 0 V and + 5 V with the output in a tri-state, and the buffer still has to be functional as an invertor. (2) On the ring oscillator with the supply protection, the output is stressed for both polarities, not only vs the VSS, but also vs the VDD. The criterion here is that the ring oscillator should still be functional with an amplitude of at least 4 V. (3) A third kind of test consists of stressing the VDD supply of the ring oscillator itself vs the VSS bus for both polarities. The same failure criterion as above is used here.
a sample size of five devices for each kind of protection. The inputs are step stressed with a step of 500 V. The classical thick oxide device (TOD) protection gives good results with a lowest failure voltage of 3500V. Negative pulses forwardly bias the diode of the n + drain of the TOD in the p-well, so no problems are expected here. Indeed the results show that the inputs all fail for positive ESD voltages when the TOD has been turned on. Comparing the two TOD versions with the different drain contacting, shows that one large drain contact for the TOD seems to be better than many minimum contacts: the lowest failure voltage is 4500 V for the large contact, compared with 3500 V for the small contacts. Probably the current density is more uniform in the case of one large contact. The lateral SCR protection is even better than the TOD structure, giving excellent results of 6000 V minimum failure voltage. Since the secondary protection has a layout which is similar to the one of the TOD protection, this proves that the SCR is more robust once it is turned on.
Outputs
RESULTS AND DISCUSSION
Input protections The inputs are stressed vs the VSS. Table 1 shows the mean failure threshold voltages together with the standard deviation and the lowest failure voltage for
For positive voltages on the CMOS output pad vs the VSS, the n MOS transistor is the weak part of the output, since the total ESD voltage comes over the n MOS. This worst case test has been performed on the different outputs, in order to study the n MOS
Table 1. Mean failure voltage, standard deviation (sigma) and minimum failure voltage of input, output and supply protections. Mmn V Iwll
Slanclard Dwvlal~
Min. V kin1
TOG {stud conlacls)
4000 V
320V
3S00 V
TOO I k ~ e conkm)
.5100 V
49OV
450O V
sol i~t~tmmutm
7OOOv
7tov
6ooo v
1125 V
350V
750 V
1450
310V
1250V
141= 1.2p, DSffi 3.7p
1750 V
3SOV
1250 V
tliffi !.21a, DSffi 3.7p
1375 V
375V
1000 V
tg : !.2 p, DS : $1a
2200V
680V
ISOOV
ladder Lg = 1.2 p, DSffi 5la + dlod~ + n vndls
30SOV
1040V
1750V
te=Sp DS ffi 2.3 la I Waffle t0 = 2 p, DS m 2.3 la + diockn + nnlslor Waffle
+diodes Ladder
+diodes + dlodes
1549
Advanced CMOS technologies robustness for positive pulses. The outputs are step stressed with a step voltage of 250 V. A sample size of ten has been taken for the waffle 1 and 2, and five for the other outputs. The results of the ESD tests are shown in Table 1. As expected all outputs are failing for positive voltages. The waffle outputs with gate length Lg = 2 # m and spacing from drain contacts to poly gate DS = 2.3 p m seem to have very weak nMOS transistors, with the minimum failure voltage already at 750 and 1000 V. The same waffles, but now with a poly resistor of 30 t2 and two diodes, have a minimum failure voltage of 1250 V. As expected these results are slightly better than the previous ones, since the resistor limits the power dissipated in the nMOS that has gone into snapback for positive voltages vs VSS. The waffle output with a smaller gate length of 1.2 # m and a larger distance DS of 2.7/~m (and two diodes), behaves better than the first ones, although there is no resistor here: the minimum failure voltage is 1250 V. This improvement is because the smaller gate length lowers the snapback voltage of the nMOS, while a larger distance, DS, adds some drain resistance and more importantly, makes the current density more uniform over the drain perimeter. The ladder output with L g = 1.2pm and DS = 2.7 p m - - s i m i l a r to the waffle output discussed above---has a minimum failure voltage of 1000V, compared to the 1250 V for the similar waffle 3. This indicates that for these specific Lg and DS the waffle output has to be preferred over the ladder layout. However, for a larger DS (e.g. 5 #m) all the drain diffusions of a waffle layout become much larger, resulting in a much too large total transistor area. The advantage of the ladder layout here is that a DS of 5 # m results in a total transistor area which still is acceptable. The ladder layout with L g = 1.2#m and DS = 5 / ~ m gives a minimum failure voltage of 1500 V, while the same ladder with n-wells at the drain diffusions gives a minimum failure voltage of 1750 V. The n-wells at the drain diffusions should still be optimised in terms of overlap around the drain contacts, and distance from the n-well edge to the poly gate. We can conclude that positively stressing the n MOS vs the VSS gives failures at a minimum voltage of 1750 V for the best tested output. This is a ladder layout with Lg = 1.2/~m and DS = 5 # m with n-wells at the drain diffusions. This still could be optimised by adjusting the layout. However, these results do not characterise the total performance of outputs, since a supply protection can help to reduce the positive voltage on the drain of the n MOS as demonstrated below.
Supply protection and impact on I / 0 performance The output of the ring-oscillator buffer is tested vs the VSS for both polarities. Negative voltages
forwardly bias the drain diode of the n MOS (and the extra diode) and provide no problems. For positive pulses the n MOS can go into snapback, while a parallel path is present through the supply protection and the diode between the output pad and the VSS---as explained above (Fig. 2b). Positive pulses make this structure fail at a minimum failure voltage of 2000 V, as shown in Table 1. Stressing the output vs the VDD for both polarities has a similar working principle. Positive voltages bias the p M O S drain diode forwardly (together with the extra diode). For negative pulses the supply protection and the diode between the VSS and the output become a discharge path between the VDD and the output over the VSS (Fig. 2a). The minimum failure voltage of the ring oscillator is 2000 V for negative stresses. Stressing the supply pin of the ring oscillator vs the VSS for both polarities gives a failure at a minimum voltage of + 3500 V. This is comparable to the minimum failure voltage of the inputs protected by the same structure, so these results are consistent. The minimum failure voltage, for the output tests for this test structure, is lower than for the supply stress test, since there is a diode in series to the supply protection, and for positive pulses vs the VSS, the nMOS is in parallel with the protection. This supply protection can be enhanced by choosing the lateral SCR protection, as proposed for the input protection. This alternative will probably give better results for the stress of the output.
CONCLUSION We can conclude that by studying various versions of ESD protections in 1.2/~m CMOS, we gained insight into the most important parameters determining the ESD performance and which optimal protections could be selected. For the input protection, the lateral SCR protection gives the best results with a minimum failure voltage of 6000V, while the thick oxide device structure fails from 3500 V onwards. For outputs, the waffle layout has to be preferred over the ladder layout for small spacings between drain contacts and gate, but for larger spacings the ladder layout uses less area. One of the tested ladder buffers has a minimum failure voltage of 1750 V for stressing the n MOS vs the VSS. However, the output failure voltage can be increased by using a good supply protection that provides a parallel path for the discharge. An output with two diodes and a thick oxide device supply protection did not fail until 2000 V. Improving the layout of the output buffer and using the SCR structure as a supply protection should still lower the ESD sensitivity.
1550
N. MAENE et al. REFERENCES
1. C. Duvvury, R. A. McPhee, D. A. Baglee and R. N. Rountree, ESD Protection reliability in 1 p.m CMOS technologies, Proe. IRPS, pp. 199-205 (April, 1986). 2. L. Avery, Using SCRs as transient protection structures in integrated circuits, Proc. EOS/ESD Syrup. EOS-5, 177-180 (September, 1983). 3. C. Duvvury, T. Taylor, J. Lindgren, J. Morris and S. Kumar, Input protection design for overall chip reliability, Proe. EOS/ESD Syrup. EOS-11, 190-197 (September, 1989).
4. L. Baker, R. Currence, S. Law, M. Le, S. T. Lin and M. Teene, A waffle layout technique strengthens the ESD hardness of the nMOS output transistor, Proc. EOS/ESD Syrup. EOS-11, 175-181 (September, 1989). 5. N. Maene, J. Vandenbroeck and K. Allaert, 1.2#m CMOS ESD protection network optimisation for latchup and minimum area, Proc. ESREF '90, pp. 345-352. Valenzano (2-5 October, 1990). 6. T. Polgreen and A. Chatterjee, Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow, Proc. EOS/ESD Symp. EOS--ll, 167-174 (September, 1989).