A reliability analysis of the electrostatic discharge sensitivity of CMOS devices

Microelectron. Reliab., Vol. 29. No. 6, pp. 1051-1060, 1989. Printed in Great Britain.

A

RELIABILITY

0026-2714/8953.00+ .00 Pergamon Press plc

ANALYSIS OF THE ELECTROSTATIC SENSITIVITY OF CMOS DEVICES

DISCHARGE

D.M. BARRY, M. MENICONI and A.V. GURICAN Department of Electrical Engineering, Lakehead University, Thunder Bay, Ontario, Canada P7B 5El (Received for publication I0 March 1989)

Statistical submitted

samples

to

specifications. Failure

The

thresholds models

Exponential

a n d the

been

adjacent

quad

were

the

such

as

NAND

five

of

the

and

MIL

of ESD.

and

using

Two-Parameter

hazard

absorbed was

were

to

levels

measured,

reliability

analysis

(CMOS)

according

Normal,

functions

sensitivity

at

were

the

gates

(ESD)

performed

devices

as

iognormal,

generated circuit

2-input discharge

tests for

reliability

have

of

electrostatic

rate

power.

plots An

ESD

also performed.

INTRODUCTION

Electrostatic

Discharge

problematical

for

(ESD)

unprotected,

transistors.

However,

ESD

is m a k i n g

its p r e s e n c e

the

ones

in t h i s

As

the

800A

used

geometries

thick,

continued

of

these

CMOS

of be

There ESD;

are

Indirect is

errors

can

Direct

failure

part

of

the

devices

as

also

to

ESD

that

NAND

is in

of E S D

shrink, such

lengths With

um and

the

as

gates.

increased.

to 0.25

knowledge

effect

to

devices

4~m channel

down

a function

types

of

failures

failures,

falsely be

has

field

continue

CMOS

only

150

30-40V

of t h e

and the 0 A,

region

reliability

is e x t r e m e l y

important

and users.

failures

device

reach

to E S D

therefore

devices

three

indirect

such

considered

protected

2-input

of g e o m e t r i e s

seen

to m a n u f a c t u r e r s

quad

devices

susceptibility

It c a n

geometries

felt with

study,

once

insulated-gate

as d e v i c e

of C M O S

shrinking

susceptibility only.

was

or

direct

soft

clocked

recovered

results

device.

common

failures

errors, by an

occur

Direct

the

devices

exposed

and

latent

failures.

when

ESD pulse.

by electrical

from

to

1051

are

edge-sensitive

Often,

these

soft

reset.

physical

errors

an

to

destruction

therefore

of all

irreversible.

or

1052

D . M . BARRY et al. Latent

failures

occurs, manner

as to

latent

effects

Roughly oxide

will

speaking,

to

time

will

cause

t w o or m o r e

junctions.

There

are

various

three

most

Model

and

notable the

Human-Body reported

are

the

model

here,

is

was

constructed

This

represents

a standing

from

the

Usually

but

a

skin. series

voltages. the

skin

The

surface

the

the

high

surface

capacitor

and another

In the

the

study

devices

The

tested

failure

distributions.

power

are

DEVICE

Five

that

simulator

circuit

capacitor

charge

the

air

on

the

is i o n i z e d

continues

until

the

is d i s c h a r g e d .

ESD

CMOS

simulator

NAND

up

to

was

gates

by s u c c e s s i v l y

of E S D

hand

discharges

bulk

the

Human-Body

levels

the

to

is e x t i n g u i s h e d .

b y the

capacitor

lower

is c o u p l e d When

arc

process

of

discharge,

capacitor

the

(2).

directly

the

were

pulsing point

sensitivity

was

of

noted

pulsing.

data was

then

(3).

and hazard

This

fit.

tests provided

ESD

rates

modelled

using

nine

were

performed

local

models

degradation

curves

curves

statistical

are

as a f u n c t i o n

of

using

with

the

shown

and

absorbed

demonstrated.

TESTING

batches

exposed

the

Adjacent

as the b e s t

reliability

a

discharge

voltage,

samples

Goodness-of-fit

Kolmogorov-Smirnov lognormal

using

failure.

This

used study

successively

When

the b u l k

here,

higher

successive

device

and

in t h e

resistor.

and

sufficient

commonly

a single

of

recharged

occurs.

device

with

catastrophic the

produces

the

surface

resistance.

The

Charged-Device

which,

is not

value

the

is t h e n

value

Statistical

destructively

during

high

of

visible

simulation.

the

capacitance

resistance,

reported

constructed.

the

skin

discharge

touches

a

slowly,

capacitor

through

hand

via

result

to the M I L - S T D - 8 8 3 C

with

discharges bulk

between

device.

circuit

ESD

(i).

effects.

the

The m o s t

according

human

to the

the d e v i c e

through

the

are

Model,

individual

multiple

is due

capacitance

approaches rapidly

of

This

series

remelts

bridging

for E S D

[1,2].

a the

categories;

is u s u a l l y

decapsulated

Model

an L C R

silicon

remelts

Human-Body

Field-Induced

however,

by c h a r g i n g causes

use

failure

in s u c h

three

of d a m a g e

in c u r r e n t

of

prematurely.

into

heat

type

of the

models

fall

silicon

This

inspection

to fail

caused

when

type pulse

In time,

and bulk

usually

Bulk

overstress.

optical

device

occurs

this

an E S D

damage.

damage

is

damaging

from

to d e v i c e s

metalization

Metalization

upon

the

damage

When

power

apparent

the o x i d e

electrical

dependent.

absorb

s h o w no

damage,

Damage

are

a device

of

to five

statistical successively

samples higher

of

the

levels

of

NAND ESD.

gates

were

Figure

1

Electrostatic discharge sensitivity of C M O S devices

1053

(V PEAK)100%90% - -

t

vp

36.8% 10% 0

I~,- t . . . - ~ 1 ~

0

td

PEAK

TIME

Figure 1 Simulated ESD Pulsein accordance with MIL-STD-833c

shows

the

standard

rise time, 90% of p e a k The p u l s e

ESD p u l s e

t r of the amplitude,

decay

V(peak),

to g r o u n d

time t d s h o u l d be about

Figure

2

shows

r e p o r t e d here.

standard which

values given

ESD p u l s e

2282V. output 2-input

simulator

To

Figure

3

N A N D gates u s e d

J_ 12 Vdc f +

t

chosen

shows

used

the DUT w i t h an exact

s c a l i n g was made

in

decay

"

of

the

reproduction

of

the

five v o l t a g e s 1445V,

for the tests was diagram

for

SW, " { . ~ 214555 4 5

b

.22 # F

; " ",~4.7k

=ovoc-L+ T

Figure2

T

Mercury Wetted Relay

T

; 0o% _L

Simulated ESDcircuit Diagram

at

1521V and

input


I

test

pulse

1369V,

the p i n - o u t

study

in the

a

and the

1331V,

the

in the test.

100 k .,>

o

to

15 n a n o s e c o n d s .

for the e l e m e n t s

obtain

tested were

The pin c o m b i n a t i o n (-).

This 10%

exponential whose

circuit

to p r e s e n t

I.

some

for

150 n a n o s e c o n d s .

The

the d e v i c e s w e r e

is m e a s u r e d

s h o u l d not e x c e e d

ESD

in F i g u r e

to M I L - S T D - 8 8 3 C .

Vp,

is a single

the

circuit were calculated form shown

according

p u l s e voltage,

the

(+) to quad

1054

D . M . BARRY et al.

Quad 2-Input NAND Gate v

DE)

WWUWN

U Vss

Figure 3

Each

device

was as

was

defined the

manufactures

Defined

pulsed

as

input

a greater

as

the

as

reference 2.5

than

threshold

the

energy

for

each

ESD

9.98

x

1012j

1369V

level

-

10.5

x

1012j

1445V

leve]

-

11.7

x

1012j

1521V

level

-

12.9

x

1012j

2282V

level

- 29.1

x

1012j

Before

the

test

Vou t were device vs

was

5,10

15V.

Ioh

the

was

output

reference

the

energy

vs

at

1331V

of was

voltage were

total each

an

number

pulse.

input

tested

at

1331V. ESD

The

Figure

5

results

level

each

using

4 and

were

the

of Used

impedance

Iol

5 show

to

After

typical

at

Ioh

testing

Analyzer

the

performed

Analyzer

Vou t and

Parameter

compared

were

vs

device.

the

standardized

Parameter

Fixture.

for

tests

devices

Semiconductor

Vou t are

Figure

and

the

Test

pre-test

Figures

devices.

as

4145B

These

tested

degradation

the

Failure

was:

recharaterized

and

values.

and

failure.

in a

calclulations

16058A

measured

Vou t

tested

as

failure by

performed

a Hewlett-Packard

pre-test

for

were

a Hewlett-Packard

Iol

until

deviation Used

level

-

each

pulse

ohms.

level

vs

10%

of

multiplied

for

i0 II

energy

and

ESD

varied.

1331V

using

an

specifications.

of

The

with

voltage

pulses-to-failure

x

Connection Pin-out Diagram for the Devices-Under-Test

and

standardized Vcc

levels

degradation

of

curves

4 shows

Iol

vs

V o u t at

Vcc

=

10V,

shows

Ioh

vs

V o u t at

Vcc

=

10V,

generally

increased.

show

a

steady

level

of

1055

Electrostatic discharge sensitivity of CMOS devices Vcc = IOV

oo21 0o 1 . 6e -0.01

-0.02

-0.03 0

2

4

6

8

10

Vout Figure 4

Vou t V S l o l d e g r a d a t i o n test

Vcc - lOV

0.01

0.0

POST

IT..~

1

-0.01

-0.02

-0.03 0

2

4

6

8

10

Vout Figure5

Vou t v s l o h

d e g r a d a t i o n test

DISCUSSION OF RESULTS The results generally compare favorably with the results published by Amerasekera (4) in 1986. He found ESD degradation fell into the following categories; no change, degradation with negative gm at high Vgs, catastrophic failure and resistive changes. The results reported have clearly shown the two middle categories with only the no change and resistive characteristics categories not clearly evident. Two differences in the studies could explain the above, the Amerasekera study lacked commercial

1056

D . M . BARRY et al.

input

protection

input

significantly

There

was

level

the

levels

"Kink"

"healing" is alloy

which

can

to

spiking

fuse

used

in this

Also

Amerasekera

tested

in the

in the

at

the

1369V

level. At

towards

Then

with

at the

1521V

and

catastrophic

was

reported

by Avery

(i).

junction

filament

leaking.

If the

may not affect

overstress

A

20

15

You t - 8 v

10

0.0

-001

-Q02

0.03 I01

"Healing Effect" V(test) vs [ol

possible

its o p e r a t i o n

occurs.

25

Figure 6

failure.

damage

30

001

1445V 2282V

of the j u n c t i o n

V(test) (VX ~00)

002

the

6.

and e l e c t r o t h e r m o m i g r a t i o n

if another

tested to date.

testing.

level

the

study had

study

degradation 1331V

improve.

continued

in the

the r e s u l t i n g

even

the to

in Figure

phenomenon

result

noticed

seemed

the d e g r a d a t i o n

cause

slight

was

than were

degradation

continuing

devices

This may be seen

may

devices

slight

degradation

the NAND gates

protection.

more

An i n t e r e s t i n g

This

circuitry,

buffering

is and

Electrostatic discharge sensitivity of CMOS devices ESD A D J A C E N T

During

the

the g a t e s

CIRCUITRY

initial were

SENSITIVITY

threshold

failed

to the ESD pulse.

With

the quad

to find d e g r a d a t i o n

tested

one gate.

Four

(+) to c o m m o n

2.

Output

3.

Input

(+) to output

4.

V+(+)

to c o m m o n

were vs

performed

Analyzer

Figure

In all

shows

sensitivity

4

tests

each

remaining

gates

chosen

it

was

having

for

further

across

device.

output

that

exists

Adjacent

circuitry

gate,

The three

other

Vin,

Three

Iol vs Vout,

Semiconductor

combination

pin

Parameter

and a

plot

number

Ioh

Parameter

Analyzer.

of

in the

input

geometry

2 showed

3 showed

combination

the

2

Iol vs

the

least.

lacks

Pin Vou t

the

is

a

growing

3.800

before

I

I

after

/' .0000 .0000

vo

Figure 7

This

is to

protection

problem

devices.

(mA)

/.f

greatest

and Vdd pins.

Adjacent Circuitry Sensitivity Pin Combination #4 Chip #1

lo I

3800 /div

and

tests

drift.

sensitivity

smaller

same

sensitivities.

of the used

pin c o m b i n a t i o n

circuitry

the

the results.

has been

pin

because

increasingly

on

Vou t vs

to g e n e r a t e

a typical

while

applied

their

gate:

parameter

be e x p e c t e d

was

The H e w l e t t - P a c k a r d

number

three

gates

(+)

3500V

on each

was u s e d

7 shows

clearly

NAND

were

of

exposed

(-)

to e v a l u a t e

Vout).

combination

in all three

combination

tested

(Vdd -

CMOS

some

(-)

of

to pin

were

2-input

that

directly

(-)

(-) to c o m m o n

ESD pulse

according

noticed

being

T h e s e were:

Input

gates

it was

without

pin c o m b i n a t i o n s

i.

A single

testing

or d e g r a d e d

common

investigation.

1057

.5500/div

(v)

E x a m p l e of A d j a c e n t Circuitry Sensitivity

5.5oo

with

1058

D . M . BARRY et al.

DEVICE

RELIABILITY

It w a s

decided

in

terms

energy of

of

MODELLING

to m o d e l

reliability

absorbed

by

nine

reliability

typical

reliability

The

distributions

Lognormal

and

distribution

the

the

failure

of

the

devices

models vs

used

the

data

devices

during

were

the

employed

absorbed

energy

for

plot

the

Two-Parameter

functions

and

obtained as

this

a function

and

Figure

8 shows

shown

were

the

failure

Normal,

The

densities

are

1 Normal LpganrTiEalpone at ia I .......

0.4

0.2

I

0 e-10

,

1 e-10

2 e-10

I

3 e-10

,

4 e-10

I

5 e-10

I

6 e-10

,

7 e-10

Energy(Joules)

Figure 8

Reliability vs Power for Normal, Lognormal and 2-Parameter Exponential Distrulations.

below:

LOGNORMAL :

r(~) = ¢ [ log(~) n- log(~<)],

/(~)

-

-

--- exp --

s~

z>0

t

-

-

s~

~is

the

scale

parameter

sis

the

shape

paremter

J

a

the

cumulative

0.8

0.0

package

plot.

VOLTAGE = 2282V

rr

the

A

1.0

l i

of

tests.

Reliability versus Power

0.6

study

ESD

Exponential.

their

in

8 e-10

given

Electrostatic

TWO-PARAMETER

F(z)=

discharge sensitivity of CMOS

devices

1059

EXPONENTIAL:

II°l

1 - exp -

"~

,

z > c~

= ± exp/- (x- ~)

ais

the

location

8is

the

scale

parameter

parameter

NORMAL:

-%), where

standard

normal

exp

~is

the mean

6is

the

[---

standard

The p a r a m e t e r s

distribution

is:

dz

deviation

were

Kolmogrov-Smirnov

(x)

estimated

using

Goodness-of-fit

Maximum

test was

Likelihood employed

(3) and

a

(3).

CONCLUSIONS

Quad

2-input

higher

NAND

levels

(except

for

gates

the

The results

differences

being

NAND

gates

pulsed

A steady

effect")

compared

mainly

used

were

ESD.

"healing

increased.

CMOS

(CMOS)

of s i m u l a t e d

due

was

favourably

to sample

in this

study

with

level

size

succesively

of

degradation

found

as

with

other

and the

all had normal

ESD

fact

CMOS

level

authors, that

the

protection

at the gates.

A "healing Avery

effect"

(I).

junction noted.

leakage. Failure

the o t h e r located

was

This may

three

where

protection degradation.

noted be due

An a d j a c e n t

at one gate gates. no

due

i.e.

whose

alloy

to ESD has sensitive

circuitry inputs

geometries

to

spiking

circuitry

The most

protection

circuitry, Gates

and c o m p a r e d to

that r e p o r t e d and

sensitivity significant

was

also

effects

pin c o m b i n a t i o n s existed. Vcc,

showed

were

physically

on

were

Those

and

by

concomitant

with little

linked

to

1060

D . M . BARRY et al.

those failed

of

the failed

gate.

tests were

The

now m o d e l l e d

the L o g n o r m a l models

and

passed

providing

gate

showed

failure

similar

data o b t a i n e d

using

such

the best

the

distributions

the T w o - P a r a m e t e r

the

degradations

from

goodness-of-fit

to

the

simulated

ESD

as the

Exponential. test

with

Normal,

All the

local

Lognormal

fit.

ACKNOWLEDGEMENTS

The authors of the Canada

gratefully

Natural through

wish

Sciences

to a c k n o w l e d g e

and

Engineering

the a w a r d of NSERC Grant

No.

the f i n a n c i a l Research

support

Council

of

A6039.

REFERENCES

I.

Avery,

2.

"U.S.

L.R.,

"RCA Review",

Department

Vol.

of Defense",

45, pp.

291-302

MIL-STD-883C,

(1984).

Method

3015.2

(1983).

3.

4.

Mann,

N.R.,

Schafer,

R.L.

for S t a t i s t i c a l

Analysis

Wiley

New York,

and Sons,

Amerasekera, Reliability (1986).

E.A.

and

Engineering

and

Singpurwalla,

of R e l i a b i l i t y

N.D.,

and Fiber

"Methods

Data",

John

"Availability

and

1974.

Campbell,

D.S.,

International,

Vol.

2,

pp.

107-116