- Email: [email protected]
On the scaling of an ion-implanted silicon MESFET
Solid-Sfare EkcrronicsVol. 32, No. 2, pp. 119-123, 1989
0038-l101/89 $3.00+ 0.00 Copyright 0 1989Pergamon Press plc
Printed in Great Britain. All rights reserved
ON THE SCALING OF AN ION-IMPLANTED MESFET
SILICON
S. N. CHATTOPADHYAYand B. B. PAL Department of Electronics Engineering, Institute of Technology, Banaras Hindu University, Varanasi, 221 005, India (Received
6 January 1988; in revised form 21 June 1988)
Abstract-An ion-implanted silicon MESFET is scaled to smaller sizes assuming constant field within the device. Ion implantation is a leading technology for VLSI and scaling is an important tool for device miniaturization. A one-dimensional and fairly accurate analysis is carried out considering the effect of side walls in the space-charge region below the gate in the below pinch-off region. Different device parameters such as drain-source current, threshold voltage, time delay, frequency, d.c. power dissipation and switching energy are plotted and discussed with respect to scaling factor a. The results show how the ion-implanted silicon MESFET device can be optimised with the aid of scaling factor for better device performance.
INTRODUCTION
Silicon technology, at present, appears to be the most suitable technology for large scale integration and silicon MESFETs offer some advantages over MOS and GaAs devices[l]. Barnes et uZ.[2]have pointed out that GaAs MESFETs may oscillate when used as linear amplifiers due to a negative resistance region observed in the I-V characteristics. Unless it is eliminated by careful design, this effect could cause short channel GaAs MESFET to become less useful than the silicon MESFET as a linear amplifier. Device scaling is an important tool for device miniaturization. Scaling down of the MOSFET device shows a massive impact on both the cost and performance of VLSI circuits. In the last decade, the device scientists were engaged with the miniaturization limits of MOS devices. The scaling theory was first developed, identifying concise design criteria for small dimension FET in 1972[3]. It was proposed that if the device dimensions and applied potentials were scaled by a common factor l/a, and the impurity concentration was increased by CLwhere a > 1, the shape of the electric field within the device remained constant. The constant field[4,5] within the scaled device minimizes the effect of mobility degradation which is responsible for the degraded output characteristics in the triode region. The uniform field distribution within the scaled device is desirable, since the large parallel field causes the saturation of the drift velocity of carriers[6,7]. The device characteristics both in the triode region and in the saturation[8,9] are negatively influenced by the effect of source-drain contact resistances and spreading resistances. Such a degradation is more severe when the channel width and length are reduced according to the scaling rule. The first proposed theory on scaling was also confirmed experimentally on l pm channel devices which exhibited the expected,
properly-scaled characteristics with respect to those of a typical 5 pm FET technology[lO]. In the present paper, the constant-field scaling rule is applied to the ion-implanted silicon MESFET and the electrical characteristics have been studied. Such a study does not seem to be reported yet. During the last few years, silicon MESFETs have been intensively developed for high speed and low-power circuit applications[ 1l-l 51. Further, scaling schemes have already been utilised for silicon MESFETs with constant doping where first-order 1-D equations have been used[ 161. The design rule applied in this study is briefly described in the next section and the results and discussion are given in the subsequent section. DESIGN RULE OF SCALING OF ION IMPLANTED MESFET
The model considered here is 1-D which includes the effect of side walls of the gate[l7] and is shown in Fig. 1. The space-charge region below the gate consists of three sections: Sections I, II and III with charges Q,, Q2 and Q, respectively. Region I varies linearly with distance from source end to drain end and regions II and III are quarter arcs. Takada et a1.[17] have shown that the above mode1 agrees well with the results of 2-D computer analysis even for short channel devices. The extremely effective guidelines for MESFET miniaturization is based on scaling the geometrical dimensions by a factor l/a, where a > 1. A constant electric field within the device has been assumed and the operating voltages are also scaled by l/a. It is to be noted that as the scaling factor increases, the device dimensions become smaller and smaller. The substrate concentration N* is upscaled by a. Similarly the implanted parameters such as a and R,, are scaled by l/a, where Rp is the ion range and a is the straggle parameter of the 119
120
S. N. CHATTOPADHYAY
and B. B.
PAL
f
in the before pinch off region.
implanted profile. The ion dose Q is not scaled as it is a parameter concerned with the implantation technique. The implanted impurity concentration in the active region of the scaled device is given by: N’(x)
[-r3y]-N;, afJq2n)exp
= ___
= N(x) cc,
(1)
where N(X) is unscaled ion implanted concentration, x’, Ni, a’ and R; are the scaled quantities and Na = N,u, NA being the substrate concentration. The junction depth of the device is given by[l8]: xi= R,+J2a
switching characteristics can also be predicted for the scaled MESFET. The switching energy per device, E, is an important parameter of the device performance which is equal to the power consumed by the device at maximum clock frequency multiplied by the device delay[20]. From the scaling rule, it is scaled as:
In
,/(Zza
J% = &/a’, likewise the power dissipation in a single ion implanted MESFET is scaled as:
1’ (2)
NA
Applying the scaling rule we get, x,’ = xj/a, where xi is the scaled junction depth. The field and surface potentials in the scaled MESFET are obtained from the solution of the Poisson equation with appropriate boundary conditions[l9]. The threshold voltage is found to be scaled by l/a. The threshold voltage is evaluated for both enhancement and depletion devices in a scaled MESFET. In order to obtain the 1-V characteristics of the scaled MESFET device, the channel charge should be defined first. As the scaling factor tl increases, the geometrical dimensions shrink accordingly. In this modelling, for a greater accuracy the gate edge effect is also considered[l7]. The space charge region is divided into three sections. The total charge distribution can be obtained by the integration of the scaled concentration for the three regions of the scaled device. The channel current IDSis obtained by the integration of total charge density for the applied voltage Vu, and it is found that the channel current is scaled by l/a. In the scaled MESFET device, a significant effect of scaling on internal gate-source and gate-drain capacitances has been observed. The gate-to-source and gate-to-drain capacitances C, and C,, of the scaled device show a reduction by a factor l/a. However, the resistance is unchanged in the scaled device. From the capacitances and resistance, it may be predicted that the time delay will follow the scaling rule and it is found to decrease by a factor f/a. The cut-off frequency is observed to be increasing by a factor CI. Therefore, information regarding the
Pi = Pw/a2. RESULTSAND DISCUSSION ON THE EFFECT OF SCALING
The ion implanted device we have chosen for the purpose of scaling has a channel length of 4 pm and width of 20 pm. The unscaled implanted parameters are Rp= 0.053 x 10m6m and a = 0.038 x 10-6m[19]. For a better understanding of the effect of scaling we start with the plot of drain-source current against the
132 120
Q -2.0xfO’b”-P v, - 1.45v 2 - 20 x lo%-*
4
6
6
7
6
Fig. 2. Drain-source current of the scaled device vs scaling factor (G()for different drain-source
voltage.
Scaling of ion-implanted MESFET
121
Depletion a - 2.0
x tolS In-2
2 = 20 x lQsm
- 0.E -06 - 0.4 - 0.2 2 a
E 5
i 0.1
02
g rt
0.3
24 20 16 12 6
0.4 Q - 6.0
0.S
x 10’5m-2
4
0.6 .Enhoncemcnt
0
Fig. 3. Threshold voltage against scaling factor t( for different substrate concentration in both depletion and enhancement modes.
scaling factor tl for different drain-source voltages and is shown in Fig. 2. From the graph, it is found that as a increases from 1 to higher values the current falls rapidly, tending to saturate for a > 3. Thus a scaling factor larger than 3 is not of much significance. Figure 3 represents the plot of the threshold voltage vs a in both enhancement and depletion devices for different substrate concentrations. It is observed that Vr changes sharply for higher substrate concentration in the enhancement device and for lower substrate concentration in the depletion device when a varies from 1 to 2. However, for larger a the change in Vr in both the cases is very small.
1
2 L
3
4
(pm1
Fig. 5. Cut-off frequency fr vs channel length for different scaling factors.
Figure 4 shows the time delay vs channel length for the ion implanted silicon MESFET for different scaling factors. In this, the time delay includes the effect of both the gate-source and gate-drain capacitances and the channel resistance. It is observed that there is a significant reduction in time delay due to scaling. However, for scaling factor larger than 2 and for lower channel length, the time delay does not change appreciably. Figure 5 represents the plot of cut-off frequency against the channel length for different scaling factors. The cut-off frequency is
0.307
0.26 0.24
-2 C &O
0.22
Vos' 0.4v
0.20
v,,-
0.18
a - 8.0
0.16
2 = 20 x lo-%
0.14
/
0.2v
o-
x lo”m-z
/
1.5
/
2.0 E
0.12
2.5
0.10
3.0
0.06
3.5 4.0
0.06 0.04 0.02 1
g&g 1
2
3
4
L (pm)
0.1
a3
a5
0.7
0.9
1.1
1.3
1.5
VDS(V)
Fig. 4. Time delay Td [=R,,,(C, + C,)] where Rdr is drain-source resistance vs channel length for different scaling factors.
Fig. 6. d.c. Power dissipated per device vs drain-source voltage for different scaling factors in the depletion mode.
122
S. N.
CHATTOPADHYAY
defined as the ratio of transconductance and (2n) times the total gate capacitance C, (= C, + C,,)[21]. The cut-off frequency changes sharply as the channel length varies from 1 to 2 km. For length greater than 2pm, the frequency tends to be independent of channel length. Larger scaling factor leads to a larger change in the device cut-off frequency. Figure 6 shows the plot of d.c. power dissipation per device vs drain-source voltage VDs for different scaling factor and Fig. 7, the plot of power vs geometrical aspect ratio A(= W/L’) in both depletion and enhancement devices where L’ is the scaled channel length. In the scaled device, power dissipation is much less than the unscaled device. Power in the enhancement device is one order less than that in the depletion device in unscaled MESFET. However, in the scaled MESFET device, the ratio is of the order of 1:20 for a = 1.5 and 1:30 for a = 2.0. Figure 8 shows the plot of switching energy per device E, vs gate-source and drain-source voltages for different scaling factor in the enhancement mode. From the graphs one can estimate the switching energy per device at a particular scaling factor. Switching energy per device is less for larger scaling factor.
a6Ayy60 0.1
-
Scale: -
A-
Depletion
P-
2.0
-
x 10”ms’
-70
Scab:B-Enhancement---
0.6
-
V,,=O.6V,Z-20.01
10%
0.5
-
-60
-50
0.4
-
-40
‘;
;: E
=i ‘0
‘a’ 0.3
-
0.2
-
-30
-20 \ \
0.1
-
\
-10 ‘_
OL’
5
”
7.5
-.
--
”
10
12.5
x
15
and B. B. PAL
_
-I-+20
11.5
(=Z/L’)
Fig. 7. d.c. Power dissipated per device vs geometrical aspect ratio L (= W/L’) for both enhancement and depletion modes.
_ Enhancement
E 10
-13
~w,(-c,av,‘;) o-‘3
----
E .,,c-C,,VZs) 8x10’5m-2
Q-
lO-‘4
lo-l4
3
5 Yu c w
; W”
10
-15
10
-1s
lo-=
lo-l4
10-l'
10-l
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V,,(V) I
0
I
0.1
I
0.2
I
I
I
0.3
0.4
0.5
I 0.6
V,,(V) Fig. 8. Switching energy per device vs V, and V,, (in enhancement) for different scaling factors.
Scaling of ion-implanted From the above results it is possible to optimize
ion implanted
the
silicon MESFET device in the light of
scaling rule for better performance
in LSI and VLSI.
REFERENCES 1. A. Gruhle, G. Femholz and H. Beneking, IEEE Trans.
Electron Dm. ED-34, 872 (1987). 2. J. J. Barnes, R. J. Lomax and G. I. Haddad, IEEE Trans. Electron Dev. ED-23, 1042 (1976). 3. R. H. Dennard, F. H. Gaensslen, L. Kuhn and H. N. Yu, IEEE Electron Device Meet, Tech. Dig., p. 168 (1972). 4. F. F. Fang and A. B. Fowler, Physics 169, 619 (1968). 5. S. C. Sun and J. D. Plummer, IEEE Trans. He&on Dev. ED-27, 1497 (1980). 6. F. F. Fang and A. B. Fowler, J. appl. Phys. 41, 1825 (1970). 7. J. A. Cooper and D. F. Nelson, IEEE Electron Dev. Letr. EDL-2, 171 (1981). 8. P. K. Chatterjee, W. R. Hunter, T. C. Holloway and Y. T. Lin, IEEE Electron Dev. Lett. EDL-1,220 (1980). 9. Y. A. El-Mansy, IEEE Trans. Electron Deu. ED-29,567 (1982). 10. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L.
MESFET
123
Rideout, E. Bassons and A. Lc Blanc, IEEE J. Solid-St. Circ. SC-g, 256 (1974). 11. H. Muta, S. Suzuki, K. Yamada, Y. Nagahashi, T. Tanaka, H. Okabayashi and N. Kawamura. IEEE Trans. Electron Dee.-ED-U, 1023 (1976). 12. C. D. Hartgring, B. A. Rosario and J. M. Pickett, IEEE J. Solid-St. Circ. SC-la, 578 (1981). 13. T. W. Houston, C. L. Everett, H. M. Darley and G. W. Taylor, ISSCC Dig. Tech. Papers, p. 80 (1979). 14. W. R. Cady and S. P. Yu, Electrochemical Society Fall Meeting, Hollywood (1980). 15. J. Nulman and P. Krusius, IEEE Electron Dev. Lett. EDL-5, 159 (1984). 16. G. V. Ram and M. I. Elmasrv. IEEE Electron Dev. Len. EDLl, 259 (1980). ’ 17. T. Takada, K. Yokoyama, M. Ida and T. Sudo, IEEE Trans. MTT MTT-30. 719 (1982). 18. D. W. G. Ong, Modern kOS’ Technology: Process Devices and Design, p. 165. McGraw-Hill, New York (1983). 19. G. W. Taylor, H. M. Dariey, R. C. Frye and P. K. Chatterjee, IEEE Trans. Electron Dev. ED-26, 172 (1979). 20. C. Mead and L. Conway, Introduction to VLSI Systems, Chap. 9, p. 333. Addison-Wesley, Philippines (1980). 21. T. D. Mok and C. A. T. Salama, IEEE Trans. Electron Dew. ED-25, 1235 (1978).
0038-l101/89 $3.00+ 0.00 Copyright 0 1989Pergamon Press plc
Printed in Great Britain. All rights reserved
ON THE SCALING OF AN ION-IMPLANTED MESFET
SILICON
S. N. CHATTOPADHYAYand B. B. PAL Department of Electronics Engineering, Institute of Technology, Banaras Hindu University, Varanasi, 221 005, India (Received
6 January 1988; in revised form 21 June 1988)
Abstract-An ion-implanted silicon MESFET is scaled to smaller sizes assuming constant field within the device. Ion implantation is a leading technology for VLSI and scaling is an important tool for device miniaturization. A one-dimensional and fairly accurate analysis is carried out considering the effect of side walls in the space-charge region below the gate in the below pinch-off region. Different device parameters such as drain-source current, threshold voltage, time delay, frequency, d.c. power dissipation and switching energy are plotted and discussed with respect to scaling factor a. The results show how the ion-implanted silicon MESFET device can be optimised with the aid of scaling factor for better device performance.
INTRODUCTION
Silicon technology, at present, appears to be the most suitable technology for large scale integration and silicon MESFETs offer some advantages over MOS and GaAs devices[l]. Barnes et uZ.[2]have pointed out that GaAs MESFETs may oscillate when used as linear amplifiers due to a negative resistance region observed in the I-V characteristics. Unless it is eliminated by careful design, this effect could cause short channel GaAs MESFET to become less useful than the silicon MESFET as a linear amplifier. Device scaling is an important tool for device miniaturization. Scaling down of the MOSFET device shows a massive impact on both the cost and performance of VLSI circuits. In the last decade, the device scientists were engaged with the miniaturization limits of MOS devices. The scaling theory was first developed, identifying concise design criteria for small dimension FET in 1972[3]. It was proposed that if the device dimensions and applied potentials were scaled by a common factor l/a, and the impurity concentration was increased by CLwhere a > 1, the shape of the electric field within the device remained constant. The constant field[4,5] within the scaled device minimizes the effect of mobility degradation which is responsible for the degraded output characteristics in the triode region. The uniform field distribution within the scaled device is desirable, since the large parallel field causes the saturation of the drift velocity of carriers[6,7]. The device characteristics both in the triode region and in the saturation[8,9] are negatively influenced by the effect of source-drain contact resistances and spreading resistances. Such a degradation is more severe when the channel width and length are reduced according to the scaling rule. The first proposed theory on scaling was also confirmed experimentally on l pm channel devices which exhibited the expected,
properly-scaled characteristics with respect to those of a typical 5 pm FET technology[lO]. In the present paper, the constant-field scaling rule is applied to the ion-implanted silicon MESFET and the electrical characteristics have been studied. Such a study does not seem to be reported yet. During the last few years, silicon MESFETs have been intensively developed for high speed and low-power circuit applications[ 1l-l 51. Further, scaling schemes have already been utilised for silicon MESFETs with constant doping where first-order 1-D equations have been used[ 161. The design rule applied in this study is briefly described in the next section and the results and discussion are given in the subsequent section. DESIGN RULE OF SCALING OF ION IMPLANTED MESFET
The model considered here is 1-D which includes the effect of side walls of the gate[l7] and is shown in Fig. 1. The space-charge region below the gate consists of three sections: Sections I, II and III with charges Q,, Q2 and Q, respectively. Region I varies linearly with distance from source end to drain end and regions II and III are quarter arcs. Takada et a1.[17] have shown that the above mode1 agrees well with the results of 2-D computer analysis even for short channel devices. The extremely effective guidelines for MESFET miniaturization is based on scaling the geometrical dimensions by a factor l/a, where a > 1. A constant electric field within the device has been assumed and the operating voltages are also scaled by l/a. It is to be noted that as the scaling factor increases, the device dimensions become smaller and smaller. The substrate concentration N* is upscaled by a. Similarly the implanted parameters such as a and R,, are scaled by l/a, where Rp is the ion range and a is the straggle parameter of the 119
120
S. N. CHATTOPADHYAY
and B. B.
PAL
f
in the before pinch off region.
implanted profile. The ion dose Q is not scaled as it is a parameter concerned with the implantation technique. The implanted impurity concentration in the active region of the scaled device is given by: N’(x)
[-r3y]-N;, afJq2n)exp
= ___
= N(x) cc,
(1)
where N(X) is unscaled ion implanted concentration, x’, Ni, a’ and R; are the scaled quantities and Na = N,u, NA being the substrate concentration. The junction depth of the device is given by[l8]: xi= R,+J2a
switching characteristics can also be predicted for the scaled MESFET. The switching energy per device, E, is an important parameter of the device performance which is equal to the power consumed by the device at maximum clock frequency multiplied by the device delay[20]. From the scaling rule, it is scaled as:
In
,/(Zza
J% = &/a’, likewise the power dissipation in a single ion implanted MESFET is scaled as:
1’ (2)
NA
Applying the scaling rule we get, x,’ = xj/a, where xi is the scaled junction depth. The field and surface potentials in the scaled MESFET are obtained from the solution of the Poisson equation with appropriate boundary conditions[l9]. The threshold voltage is found to be scaled by l/a. The threshold voltage is evaluated for both enhancement and depletion devices in a scaled MESFET. In order to obtain the 1-V characteristics of the scaled MESFET device, the channel charge should be defined first. As the scaling factor tl increases, the geometrical dimensions shrink accordingly. In this modelling, for a greater accuracy the gate edge effect is also considered[l7]. The space charge region is divided into three sections. The total charge distribution can be obtained by the integration of the scaled concentration for the three regions of the scaled device. The channel current IDSis obtained by the integration of total charge density for the applied voltage Vu, and it is found that the channel current is scaled by l/a. In the scaled MESFET device, a significant effect of scaling on internal gate-source and gate-drain capacitances has been observed. The gate-to-source and gate-to-drain capacitances C, and C,, of the scaled device show a reduction by a factor l/a. However, the resistance is unchanged in the scaled device. From the capacitances and resistance, it may be predicted that the time delay will follow the scaling rule and it is found to decrease by a factor f/a. The cut-off frequency is observed to be increasing by a factor CI. Therefore, information regarding the
Pi = Pw/a2. RESULTSAND DISCUSSION ON THE EFFECT OF SCALING
The ion implanted device we have chosen for the purpose of scaling has a channel length of 4 pm and width of 20 pm. The unscaled implanted parameters are Rp= 0.053 x 10m6m and a = 0.038 x 10-6m[19]. For a better understanding of the effect of scaling we start with the plot of drain-source current against the
132 120
Q -2.0xfO’b”-P v, - 1.45v 2 - 20 x lo%-*
4
6
6
7
6
Fig. 2. Drain-source current of the scaled device vs scaling factor (G()for different drain-source
voltage.
Scaling of ion-implanted MESFET
121
Depletion a - 2.0
x tolS In-2
2 = 20 x lQsm
- 0.E -06 - 0.4 - 0.2 2 a
E 5
i 0.1
02
g rt
0.3
24 20 16 12 6
0.4 Q - 6.0
0.S
x 10’5m-2
4
0.6 .Enhoncemcnt
0
Fig. 3. Threshold voltage against scaling factor t( for different substrate concentration in both depletion and enhancement modes.
scaling factor tl for different drain-source voltages and is shown in Fig. 2. From the graph, it is found that as a increases from 1 to higher values the current falls rapidly, tending to saturate for a > 3. Thus a scaling factor larger than 3 is not of much significance. Figure 3 represents the plot of the threshold voltage vs a in both enhancement and depletion devices for different substrate concentrations. It is observed that Vr changes sharply for higher substrate concentration in the enhancement device and for lower substrate concentration in the depletion device when a varies from 1 to 2. However, for larger a the change in Vr in both the cases is very small.
1
2 L
3
4
(pm1
Fig. 5. Cut-off frequency fr vs channel length for different scaling factors.
Figure 4 shows the time delay vs channel length for the ion implanted silicon MESFET for different scaling factors. In this, the time delay includes the effect of both the gate-source and gate-drain capacitances and the channel resistance. It is observed that there is a significant reduction in time delay due to scaling. However, for scaling factor larger than 2 and for lower channel length, the time delay does not change appreciably. Figure 5 represents the plot of cut-off frequency against the channel length for different scaling factors. The cut-off frequency is
0.307
0.26 0.24
-2 C &O
0.22
Vos' 0.4v
0.20
v,,-
0.18
a - 8.0
0.16
2 = 20 x lo-%
0.14
/
0.2v
o-
x lo”m-z
/
1.5
/
2.0 E
0.12
2.5
0.10
3.0
0.06
3.5 4.0
0.06 0.04 0.02 1
g&g 1
2
3
4
L (pm)
0.1
a3
a5
0.7
0.9
1.1
1.3
1.5
VDS(V)
Fig. 4. Time delay Td [=R,,,(C, + C,)] where Rdr is drain-source resistance vs channel length for different scaling factors.
Fig. 6. d.c. Power dissipated per device vs drain-source voltage for different scaling factors in the depletion mode.
122
S. N.
CHATTOPADHYAY
defined as the ratio of transconductance and (2n) times the total gate capacitance C, (= C, + C,,)[21]. The cut-off frequency changes sharply as the channel length varies from 1 to 2 km. For length greater than 2pm, the frequency tends to be independent of channel length. Larger scaling factor leads to a larger change in the device cut-off frequency. Figure 6 shows the plot of d.c. power dissipation per device vs drain-source voltage VDs for different scaling factor and Fig. 7, the plot of power vs geometrical aspect ratio A(= W/L’) in both depletion and enhancement devices where L’ is the scaled channel length. In the scaled device, power dissipation is much less than the unscaled device. Power in the enhancement device is one order less than that in the depletion device in unscaled MESFET. However, in the scaled MESFET device, the ratio is of the order of 1:20 for a = 1.5 and 1:30 for a = 2.0. Figure 8 shows the plot of switching energy per device E, vs gate-source and drain-source voltages for different scaling factor in the enhancement mode. From the graphs one can estimate the switching energy per device at a particular scaling factor. Switching energy per device is less for larger scaling factor.
a6Ayy60 0.1
-
Scale: -
A-
Depletion
P-
2.0
-
x 10”ms’
-70
Scab:B-Enhancement---
0.6
-
V,,=O.6V,Z-20.01
10%
0.5
-
-60
-50
0.4
-
-40
‘;
;: E
=i ‘0
‘a’ 0.3
-
0.2
-
-30
-20 \ \
0.1
-
\
-10 ‘_
OL’
5
”
7.5
-.
--
”
10
12.5
x
15
and B. B. PAL
_
-I-+20
11.5
(=Z/L’)
Fig. 7. d.c. Power dissipated per device vs geometrical aspect ratio L (= W/L’) for both enhancement and depletion modes.
_ Enhancement
E 10
-13
~w,(-c,av,‘;) o-‘3
----
E .,,c-C,,VZs) 8x10’5m-2
Q-
lO-‘4
lo-l4
3
5 Yu c w
; W”
10
-15
10
-1s
lo-=
lo-l4
10-l'
10-l
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V,,(V) I
0
I
0.1
I
0.2
I
I
I
0.3
0.4
0.5
I 0.6
V,,(V) Fig. 8. Switching energy per device vs V, and V,, (in enhancement) for different scaling factors.
Scaling of ion-implanted From the above results it is possible to optimize
ion implanted
the
silicon MESFET device in the light of
scaling rule for better performance
in LSI and VLSI.
REFERENCES 1. A. Gruhle, G. Femholz and H. Beneking, IEEE Trans.
Electron Dm. ED-34, 872 (1987). 2. J. J. Barnes, R. J. Lomax and G. I. Haddad, IEEE Trans. Electron Dev. ED-23, 1042 (1976). 3. R. H. Dennard, F. H. Gaensslen, L. Kuhn and H. N. Yu, IEEE Electron Device Meet, Tech. Dig., p. 168 (1972). 4. F. F. Fang and A. B. Fowler, Physics 169, 619 (1968). 5. S. C. Sun and J. D. Plummer, IEEE Trans. He&on Dev. ED-27, 1497 (1980). 6. F. F. Fang and A. B. Fowler, J. appl. Phys. 41, 1825 (1970). 7. J. A. Cooper and D. F. Nelson, IEEE Electron Dev. Letr. EDL-2, 171 (1981). 8. P. K. Chatterjee, W. R. Hunter, T. C. Holloway and Y. T. Lin, IEEE Electron Dev. Lett. EDL-1,220 (1980). 9. Y. A. El-Mansy, IEEE Trans. Electron Deu. ED-29,567 (1982). 10. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L.
MESFET
123
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