Optimization of high performance BiCMOS buffer circuit for chip area, delay and power dissipation

Microelectronics Journal, 23 (1992) 3 8 7 - 4 0 2

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Optimization of High Performance BiCMOS Buffer Circuit for Chip Area, Delay and Power Dissipation D. AI-Khalili and M. O. Esonu Department of Electricalaad ComputerEngineering, RoyalMilitary Colkge, Kingston, Ontario, Canada KTK 5LO

Switchingdelay, chip area and power dissipationare conflicting criteria for designinghigh performanceVLSIlogic circuits.This paper describesthe optimizationof a BiCMOS buffer in terms of these criteria,by studyingthe influenceof differentMOS and bipolar device parameters on the switchingspeed and power dissipation of the buffer. An optimization problem has been formulatedwith the objectiveof minimizingthe product of the chip area and delay (AT), the powe,-delay product (PT) o r a combinationof these.

1. Introduction iCMOS is a relatively recent integrated circuit fabrication technology that is gaining popularity owing to its high performance qualities [1, 2]. It consists of both CMOS and bipolar technologies combined on the same integrated circuit chip [2]. BiCMOS devices benefit from most of the advantages of each technology, and few of the disadvantages [1, 3]. One of the most important components in any high speed digital system is the buffer. BiCMOS

buffer circuits are more and more used for driving large capacitances on-chip as well as off-chip. The speed advantage of the BiCMOS buffer compared with a CMOS buffer with the same area is about a factor of 2 [2]. BiCMOS buffer circuits can be custom designed or designed using standard cells. Since standard cells are not optimal, custom design is the only option for high performance applications. Because custom design is complex and time consuming, a software CAD tool, such as a module generator to perform the layouts automatically, greatly enhances the engineer's design capability.

B

The analytical treatments of the performance of a BiCMOS logic gate in steady state (DC) and transient operation have been reported in the literature [4-11]. Most of these works focused on the study of the effects of different MOS and bipolar device parameters on the switching speed of the BiCMOS buffer (4, 5, 8, 9]. However, nothing has been mentioned about how changes in the BiCMOS

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buffer parameters affect the power dissipation of the buffer. Most importantly, the relationship between the area, delay and power dissipation as the device parameters are varied has not been established. Also, CAD tools to analyze and design BiCMOS buffer circuits have not been developed. Therefore the objective of this paper is to study the effects of the variations of the device parameters on the area, speed and power consumption such that the buffer can be optimized by minimizing any of these criteria or a combination of' these. An optimization procedure has been proposed to design optimal BiCMOS buffer circuits. The optimization strategy focuses on minimizing the product of the total area and switching speed (AT) or power-delay product (PT) of the buffer. In the respective cases, for any given capacitive load, the product of the buffer area or power dissipation and the switching speed that will produce the otimum buffer performance (i.e. minimum A T or PT) is determined. The sizes of the transistors required to achieve such performance, constitute the optimal buffer circuit. A BiCMOS buffer compiler has been proposed in ref. 12. The optimization procedure discussed in this paper will be incorporated into this CAD tool (Module Generator) to enable the automatic layout generation of BiCMOS buffer circuits.

2. Transient Response of BiCMOS Buffer Some aspects of the BiCMOS buffer transient analysis have been reported previously [4-11]. The presented results provide the initial input to form a complete transient analysis involving all regions of operation of the buffer. Figure 1 shows a typical BiCMOS buffer circuit being driven by a CMOS inverter. This configuration represents a more realistic scenario whereby in practice the input of the BiCMOS buffer will be driven by another logic gate in the digital system. To obtain similar rise and fall times for the output signal, the ratio of the channel widths We (M1) and W,I (M3) is maintained at a constant value of 2. Also, the length of the emitter (L~) of Q1 is the same as that of Q2. Therefore, in this paper it will suffice to consider only the pull-up

388

response of the buffer. The bipolar transistors operate in three regions, namely the low-level, highlevel and saturation regimes. In the high-level regime, the bipolar transistors have high current to area ratio and hence exhibit optimal performance in this region. Consequently, we will concentrate on this region in our analysis. The approximate analytical closed-form solutions for the estimation of the propagation delay of the BiCMOS buffer, in the high-level injection, have been given in refs. 7 and 9. In both papers [7, 9] the delay equations have similar structure. However, through extensive studies, it has been found that the delay results obtained using the delay equations in ref. 9 do not closely match the simulation results. As a result, in our analysis in this paper we adopt the delay equations presented in ref. 7, which is given as follows: Tdh=

VBE(on)C 1 V (CL + Cp + Clm)A i 1D,., + 2(BolKID.,) '/2

(1)

where flo is the current gain under low-level injection conditions, V, is the voltage swing and IK is the knee current. C1 is the total parasitic capacitance at the base of the bipolar transistor (Q1), Clm is the MOS S/D parasitic capacitance plus base-.collector capacitance at the base of the bipolar transistor (Q1). Cp is the parasitic capacitance at the output of the buffer. In ref. 7 Ai is defined as an empirical constant; however, it has been found thatAi depends on We, LE and CL. The parameters o f A i (for a 2/1 m BiCMOS process) have been extracted from the SPICE simulation results. These parameters make the analytical delay equation results more in agreement with the simulation results. The expression for Ai is given by Ai = Po -- P1C °'331 + P2 CO's

where P0 = 20" 15 + 1-07 x 105 L E - 1-214 x l0 s Wp P1 = 193"103 + 6"0 x 108 LE-- 1"61 x 109 Wp

(2)

Microelectronics Journal, VoL 23, No. 5

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Pz = 8-5 + 2.06 x 101° L~ - 7.28 x 101° Wp By substituting Ai in eqn. (2) into eqn. (1) and expressing Ivsa,, IK, C1, Clm and Cp in terms of the MOS (M1) and bipolar (Q1) device parameters, the delay equation (eqn. (1)) becomes, Tdh = VBE(°")(klwP -}" k2LE)

k3Wp

(3)

V,[CL + k4We + ksLE] [k6 + kTWp + ksLE] + (,13okgLEWp)1/2 where the values ofki (for i = 1,2 . . . . . 9) depend on the design rules and device model parameters.

A comparison of the SPICE circuit simulation and calculated delay results of the buffer is given in Table 1 for CL ranging from 1 to 20 pF, L~ from 2 to 100om and for Wp--24pm. It is observed from Table 1 that the deviation is less than 10% for most cases and that the maximum error in some cases does not exceed 17%. The uniformity of the observed computation error indicates that the proposed approximation of Ai, and hence the delay model, is accurate over a wide range of the values of Wp and LE. Figure 2 consists of the circuit diagram used to simulate the case when, for example, LE (Q1 and Q2) is a factor of 3 more than the value of the minimum emitter length (i.e. LE = 3LEm,n = 6 pm). Figure 3 depicts the simulation and calculated delay results of

389

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D. AI-Khalili and M. O. Esonu/Optimization of a BiCMOS Buffer

TABLE 1 Comparison of the calculated and simulation propagation delay results for various load conditions (W v = 24 pm)

Load capacitance (pF)

Emitter length (I.lm)

1 1 3 3 5 5 10 10 10 20 20 20

2 12 6 24 6 30 6 40 100 6 12 60

Prise-to-50% delay time (ns) Simulation results

Theoretical results

Error (%)

0,8108 0.5236 1.0508 0.7517 1.4635 0-9246 2.3895 1,2590 1.2156 4-0427 2.9697 1.7300

0.9818 0.5315 1.1523 0-7771 1.5207 0.9553 2.2856 1.3178 1.4132 4.1090 3.0818 2.0623

17.4 1-5 8-8 3.3 3.8 3.2 --4.5 4.5 14.0 1-6 3.6 16-1

the buffer for a load of 10 pF and Wp = 24 pm. A comparison of the two results shows satisfactory agreement. The simulation results of the switching delay of the buffer versus the emitter length, for Wp = 24 p m, and for different capacitive load conditions, are shown in Fig. 4. It is observed that for any given load capacitance and Wp, the delay decreases as the emitter length increases. However, the delay increases with an increase in the load capacitance. Also, as LE is increased (such that the area of the bipolar transistors become relatively large), the delay of the buffer increases, as depicted in Fig. 5. This increase in delay is a result of the increase in the parasitic capacitance of the bipolar transistors. The buffer delay as a function of the MOS (M1) and BJT (Q1) areas is shown in Fig. 6. It can be seen that, as both areas are increased, the delay decreases. Since it takes a relatively larger transistor area to achieve a Vcc

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grid Fig. 2. Circuit diagram of a BiCMOS buffer for simulation when the minimum length of the emitter is tripled (L E = 3L D.

390

Microelectronics Journal, VoL 23, No. 5

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Microelectronics Journal, VoL 23, No. 5

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relatively small delay, it therefore becomes imperative to trade offbetween these conflicting features. Based on the results of the investigation of the influence of the device parameters on the buffer area and speed, an optimization approach for designing optimal BiCMOS buffer has been proposed. This procedure is discussed in the following section.

3. Area-Delay Optimization of BiCMOS Buffer In this section, the problem of selecting the MOS and BJT transistor sizes such that the product of the buffer area and delay (AT) is minimized, will be discussed. The optimization strategy employs an analytical model for the area and delay of the buffer, and circuit simulation. For the theoretical analysis, it has been assumed that the first term of the delay model (eqn. (3)) is negligible compared with the second term. Hence, the delay equation can be approximated by the second term. Expressing Wp and L~ in terms of the MOS and bipolar area, respectively, the delay equation becomes:

(4)

Tdla '~ ,~a, Vs[CL + (kl 0 + klIO~)AB] [k6 + (k12 + k13¢2)AB]

(~o/~14a)l/ZAs

where As is the area of the bipolar transistor (Q1) and a is the ratio of the area of MOS transistor (M1), A~, to the area of the bipolar transistor (Q1) (i.e. Ct= A M / A B ) . AB and a are functions of Wp and Lr. The equation for the AT (where A = AM + As = (1 + a)As) is given as follows:

ATah = (1 + a)ABZdh

(s)

By expanding eqn. (5) and rearranging the terms, the equation for ATah becomes, AYdh = k15 [(k,6 + klTA B + k18A2)ot -'/2

+ (k,6 + k~gAs + k20A~)a1/2 + (k21A B + kz2A2)ot 3/2 + kz3A2B)Ot5/2]

(6)

where kl (for i = 10, 11 . . . . . 23) depend on the same parameters as the other k~ s. The ATah equation (eqn. (6)) has two unknown parameters, a and AB. Since the objective is to minimize ATah, we need to obtain the partial derivatives of ATah with respect to a and AB, and equate them to zero (i.e. aATah/aa = O, aATah/ dAB = 0). To obtain the values o f a andAs, the two derivatives have to be solved simultaneously. However, owing to the complexity of the problem, it is difficult to obtain the values of a and As analytically by solving the two partial differential equations simultaneously. Consequently, it was determined to calculate the optimum value of a, for any given capacitive load, through simulations. Thus, by substituting the optimum value of a into the partial derivative of ATah with respect to a, we obtain one equation that depends only on As. The theoretical model for minimum ATah is given by

OATdh/Oa =

(kkzAs + kk3AZ)a 2 + (kk4 + kksA + kktA2)ot

(kklA2)~

3+

- (kk. + kkT& + kk,A 2) = 0

(7)

where kk, (forj = 1,2 . . . . . 8) depend on the design rules anc( device parameters. Substituting the value of aopt into eqn. (7) and solving the equation, the value of As that minimizes the ATdh can be obtained. Once the value of As is derived, and knowing the value of a, then the corresponding optimal transistor sizes of the buffer can be easily determined. Figure 7 depicts the plot of the SPICE simulation results of ATdh versus the MOS/BJT ratio, a, for CL = 10"0 pF. The value of a for which the Atah is the global minimum gives the optimum a. This method has been used to determine the optimum a for various load conditions, and to generate a lookup table for a opt. Thus, for any given load, the optimum a is obtained from the table and then used to evaluate eqn. (7) in order to determine the value of AB. Table 2 consists of the values of a opt and ATopt for various capacitive load conditions. The comparison

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D. AI-Khalili and M. O. Esonu/Optimization of a BiCMOS Buffer

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Comparison of the simulation and calculated results of Optimal A T TABLE 2

CL (pF)

aot.

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Theoretical

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(%)

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0.9 3.1 2.9 0.2 8.6

Comparison of the simulation and calculated results o f A M and AB

TABLE 3 CL

(pF) 1.0 3.0 5.0 10.0 20.0

394

of the SPICE simulation and theoretical results of a deviation of less than 10%. Table 3 shows the comparison of the simulation and the calculated results o f A M (M1) and AB (QI) for the various load conditions. It can be seen from the table that the agreement of the results is quite satisfactory. The optimal transistor sizes of the buffer have been calculated as shown in Table 4. It is observed that, in general, larger transistor sizes are required to drive larger loads. For instance, the optimal transistor sizes for CL = 3"0 pF are larger than those ofCr = 1"0 pF.

ATopt shows

Simulation results

opt

0.9570 0.9131 0.8518 0.7654 0.7592

Calculated results

AM,(pm 2)

Aqz(pm 2)

AM,(,um 2)

AQ,(pm 2)

110.1 195.0 181.4 163.0 161-7

115 213 213 213 213

110-9 194-9 181.3 163.0 161.8

115-9 213-4 212.9 213.0 213.1

Microelectronics Journal, VoL 23, No. 5

iiiii! ii!i!iil

TABLE 40ptimaltransistor sizes forAToptimizationusing2/amBiCMOStechnology CL

aoet

ATop,

(#mZ-ns)

AMI ([,lm2)

AM2 (,urn2)

AM3 ([dm2)

AM4 AQI ([,17712) (]din2)

AQ2

1-0 3.0 5-0 10.0 20.0

0.9570 0.9131 0.8518 0-7654 0.7592

166-04 338.93 431.40 621.9 1070.4

110.9 194.9 181.3 163.0 161.8

66 66 66 66 66

66 99 91 82 81

66 66 66 66 66

115.9 213.4 212-9 213.0 213.1

(pF)

115-9 213.4 212-9 213-0 213.1

(I.Im2)

Also, the results show that a given set of optimal transistor sizes can be used to drive a range of load capacitances. For example, the optimal transistor sizes for CL = 3"0 pF will also be sufficient to drive a load of either 5, 10 or 20 pF (see Table 4). The results indicate that, of the area-delay optimization, reasonable buffer transistor sizes can be used to drive considerably large loads. Thus, very large transistor sizes are not necessarily required for very large capacitive loads.

ref. 14. These expressions have been adopted and extended to the BiCMOS buffer design. In Fig. 1, there are four short circuit power dissipation components for the buffer. These are a result of the short circuit currents flowing through M2 (iaM2),M3 and Q2 (idM3 + iCQ2)during the charging, and through M1 (/aM,) and Q1 (iq~2)during the discharging phase of the capacitive load. We assume that the power dissipated in M4 is insignificant and hence is neglected.

It is worthwhile to mention that, although the lookup table of the optimal a values has been generated for one technology feature size (e.g. 2 p m technology), it can also be generalized to all feature size BiCMOS technologies. This is because, changing from one technology to the other merely scales down or scales up the sizes of the MOS and bipolar transistors. However, their ratio (a), fairly remains the same. Therefore this look-up table could be applicable to any BiCMOS technology, with slight inaccuracy being introduced in the particular buffer optimization.

Therefore, the short circuit power dissipation of the buffer is represented as:

4. Power Consumption of BiCMOS Buffer The dynamic power dissipation of the buffer consists of two components: the dynamic short circuit power dissipation, Psi, and the dynamic transient power dissipation, P~. The analytical expressions for calculating the short circuit power dissipation of a CMOS inverter, with or without a load, have been developed in ref. 13, while the expressions for the average transient power dissipation can be found in

P,c =

(iaM2(t)+ ia~3(t) + icQ2(t))dt

Vcc L

l1

(8)

+ f,[" (idM,(t)+ icQ,(t))dt] where idM,(t), idM2(t) and idM3(t)are the drain to source currents, while i~,(t) and ic 2(t) are the collector currents for the corresponding transistors, as a function oft. tl, t2, t3 and t4 are the time periods that all the transistors are conducting. The total average dynamic transient power dissipation during switching is also the sum of four components. The expression for the final result for this case is gwen as follows: Pt=~ -

(c, + CL + c.)

(9)

T is the period of the input signal.

395

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D. AI-Khalili and M. O. Esonu/Optimization of a BiCMOS Buffer

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396

Microelectronics Journal, Vol. 23, No. 5 i!i~iiiii iiii~iiii

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The simulation results for the total short circuit, transient and dynamic power dissipation of the buffer are respectively shown in Figs. 8(a), 8(b) and 8(c), for LEmin = 2/am. Similar results for L~ = 3LEmi. are shown in Figs. 9(a) and 9(b). It can be seen from Fig. 8(a) and Fig. 9(a) that, for each Wv (M1), the total short circuit power dissipation decreases as the load capacitance is increased. However, it increases with an increase in We. In general, the total dynamic power dissipation increases as both the load capacitance W v and LE are increased. This is illustrated in Figs. 10(a), and 10(b). It is important to note that as the values of Wp and LE are increased, the parasitic capacitances of the transistors are increased and hence the increase in power dissipation. Figure 11 depicts a 3D plot of the total power dissipation as a function of CL and Wp (for LE = 2/am). The results confirm the observations made in Figs. 10(a) and 1009). In the next section we discuss the power-delay (PT) optimization procedure of the buffer.

5. Power-Delay Optimization of BiCMOS Buffer

For the theoretical analysis, we approximate the total power by the transient power dissipation (eqn. (9)). By expressing eqn (9) in terms of the MOS and bipolar areas, we obtain: P = f -~c [ q + (h, + h2a)Ad

(10)

where hi and h2 also depend on the design rules and device parameters. The theoretical model for the power-delay product is obtained by multiplying eqn. (10) and eqn. (4). The equation for minimum P T is given as follows: aprdh/aa = (hh,A~)a 3 + (hheAB + hh3A~)a 2 + (hh4 + hhsAB + h h 6 A ~ ) a 2

(11)

-- (hhlA~ 1 + hh7 + hhsAB + hh9A 2) = 0

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D. AI-Khalili and M. O. Esonu/Optimization of a BiCMOS Buffer

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Fig. 11. 3D plot of total power dissipation as a function of load capacitance C~ and channel width W~ (for L E = 2 pm).

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400

25.8

Microelectronics Journal, VoL 23, No. 5

TABLE 5 Optimal transistor sizes for Fir optimization using 2# m BiCMOS technology

CL (pF)

aoet

PTort (rnW-ns)

AM1 (I.Im2)

AM2 (g m2)

AM3 (lam2)

AM4 (pm 2)

AQ! (pm 2)

AQ2 (lam2)

1-0 3.0 5.0 10.0

3.200 2.404 1.484 1.902

0.2608 0.7983 1-5617 3.8151

368 512 512 656

66 66 66 66

204 276 276 348

66 66 66 66

115 213 345 345

115 213 345 345

The same optimization procedure employed for A T is also utilized in this case. Figure 12 shows the plot o f the SPICE simulation results of P T versus the ratio, a, for CL-- 3" 0 pF. The optimum values of a for certain load conditions are shown in Table 5. The table also consists of the optimal transistor sizes for the P T optimization. It is observed that larger sizes of M1 and Q1 are required to drive larger loads for this optimization criterion. It is also noted that for each load condition, the MOS transistor area is larger than that of the bipolar transistor. This interesting phenomenon is due to the fact that, since bipolar transistors consume more power than MOS transistors, therefore to minimize the power dissipation less bipolar area is required. On the other hand, to provide more current driving capability while minimizing the power dissipation, larger MOS transistor area is necessary. As in the case of A T , the look-up table for a optgenerated in this case can be applied to any BiCMOS technology.

6. Conclusion A comprehensive view to the optimization o f a B i C M O S buffer is presented. The optimization of the buffer is performed in terms o f A T and PT. In the A T case, the results o f the optimal transistor sizes show that while larger transistor sizes are required to drive larger loads, a given buffer area will be sufficient to drive a range of capacitive loads. In the case of the P T optimization, larger transistor sizes are required for larger loads. Also, the area of the MOS transistor should be more than that of the bipolar transistors so as to provide the desired current driving capability while minimizing the power

dissipation of the buffer. The future work will focus on the area-power-delay ( A P T ) optimization and also the completion of the development of the B i C M O S buffer compiler, which will enable the automatic generation of a B i C M O S buffer layout.

Acknowledgments This work has been supported by a grant from the Department of National Defence, Canada. The paper was first presented at the Canadian Conference on Very Large Scale Integration CCVLSI'91, held at Kingston, Ontario, on 25-27 August 1991.

References [1] A. R. Alvarez, BiCMOS Technology and Applications, Kluwer Academic Publishers, Norwell, MA, 1989. [2] T. Hotta et al., 1.3/lm CMOS/bipolar macrocell library for VLSI computer, IEEE J. Solid-State Circuits, 23 (2) (April 1988) 500-506. [3] K. Oguie, M. Odaka, S. Miyaoka, I. Masuda, T. Ikeda and K. Tonomura, 13-ns, 500 mW, 64-Kbit ECL RAM using HI-BICMOS technology, IEEE J. Solid-State Circuits, SC-21 (Oct. 1986) 681-685. [4] H.J. De Los Santos and B. Hoefflinger, Optimization and scaling of CMOS-bipolar drivers for VI_SIinterconnects, IEEE Trans. Electron. Devices, ED-33 (Nov. 1986) 1722-1730. [5] E. W. Greeneich and K. L. McLaughlin, Analysis and characterization of BiCMOS for high-speed digital logic, IEEE J. Solid-State Circuits, 23 (2) (April 1988) 681-685. [6] P. L. Heedly and R. C. Joeger, An analytical model for BiCMOS logic transient response allowing parameter variations, IEEE 1989 CICC, 1989, pp. 1341-1344.

401

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D. AI-Khalili and M. O. Esonu/Optimization of a BiCMOS Buffer

[7] G. P. Rosseel et al., Delay analysis for BiCMOS drivers, Proc. IEEE 1988 Bipolar Circuits and Technology Meeting, Sept. 1988, pp. 220-222. [8] G. P. Rosseel and R. W. Dutton, Influence of device parameters on the switching speed of BiCMOS buffers, IEEEJ. Solid-State Circuits, 24 (1) (Feb. 1988) 681-685. [9] A. Bellaouar, S. K. Embabi and M. I. Elmasry, Scaling of digital BiCMOS circuits, IEEEJ. Solid-State Circuits, 25 (4) (August 1990) 681-685. [10] C. H. Diaz, S-M. Kung and Y. Leblebici, An accurate analytical delay model for BiCMOS driver circuits, IEEE Trans. Computer-Aided Design, 10 (5) (May 1991) 577-588.

402

[11] T. Kuroda et al., Analysis and optimization of BiCMOS gate circuits, IEEE Int. Conf. Circuits and Systems, Singapore, June 1991, pp. 2112-2115. [12] D. A1-Khalili, M. O. Esonu and S. Karlovits, Optimization of BiCMOS circuits for high performance digital logic, Proc. 34th Midwest Symposium on Circuits and Systems, Monterey CA, May 14-17, 1991. [13] N. Hedenstierna and K. O. Jeppson, CMOS circuit speed and buffer optimization, IEEE Trans. Computer-Aided Design, CAD-6 (Mar. 1987) 270-281. [14] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, Addison-Wesley, Reading, MA, 1985.