Selection of circuit geometry for miniaturized microwave components based on concurrent optimization of performance and layout area

Int. J. Electron. Commun. (AEÜ) 108 (2019) 287–294

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International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue

Regular paper

Selection of circuit geometry for miniaturized microwave components based on concurrent optimization of performance and layout area Piotr Kurgan ⇑, Slawomir Koziel Faculty of Electronics, Telecommunications and Informatics, Gdansk University of Technology, Narutowicza 11/12, 80–233 Gdansk, Poland

a r t i c l e

i n f o

Article history: Received 30 January 2019 Accepted 10 June 2019

Keywords: Coupler Circuit geometry selection Compact cell Miniaturization Simulation-driven design Electromagnetic simulation

a b s t r a c t The paper presents a framework for automated EM-driven circuit geometry selection of miniaturized microwave components. Selection of a particular layout is based directly on miniaturization rates achieved for a set of candidate circuit geometries. Size reduction of the considered structures is obtained by replacing their main building blocks (i.e., conventional transmission lines) with slow-wave composite cells and meander lines. The proposed method primarily aims at minimization of the structure layout area by adjusting all relevant geometry parameters of its compact building blocks. At the same time, the process ensures satisfying the assumed design requirements by means of a penalty function approach. The problem at hand is solved iteratively using a trust-region-embedded gradient search with the Jacobian matrix estimated at the level of a coarse-discretization EM model of individual circuit building blocks for improved computational efficiency. The proposed methodology is verified by two case studies involving branch-line and rat-race couplers. Each design example is considered in eight different layout versions. The miniaturization rates obtained for the considered circuit geometries range between 63.9% and 76% for the first application example, as well as 80.6% and 87.5% for the second one, respectively. Experimental data validate the reliability of the proposed approach. Ó 2019 Elsevier GmbH. All rights reserved.

1. Introduction Reliable design of distributed-element devices for space-limited applications is one of the major challenges of contemporary microwave engineering [1]. Longitudinal dimensions of conventional microwave components, primarily constructed from ordinary transmission lines (TLs), are comparable to the guided wavelength. This entails the traditional design solutions to be generally incapable of satisfying the rigid area constraints imposed on modern circuit realizations [2]. To address this issue, novel designs are most commonly based on folded TLs and/or composite structures (the so-called compact cells) used in place of conventional elements [3–5]. The aforementioned layout modifications introduce a slow-wave phenomenon, which permits a considerable size reduction of the circuit at hand, while enabling the achievement of similar electrical characteristics (within a limited frequency range) of its compact components [6]. The popularity of this approach is evidenced by numerous case studies that include branch-line couplers [7], rat-race couplers [8], Wilkinson power dividers [9], matching transformers [10], and Butler matrices [11]. ⇑ Corresponding author. E-mail addresses: [email protected] (P. Kurgan), [email protected] (S. Koziel). https://doi.org/10.1016/j.aeue.2019.06.009 1434-8411/Ó 2019 Elsevier GmbH. All rights reserved.

Probably the most important aspect of small-size structure design is a selection of a circuit geometry, whose parameter adjustment results in the best possible satisfaction of the assumed design objectives. The attainable size- and performance-related figures of merit are dependent on both the underlying structure geometry and the method of determining the final circuit dimensions [12]. Despite the significance of this issue, the selection of a particular circuit topology for a given application is done nowadays in a completely arbitrary manner – either by handpicking an already reported circuit geometry, or by devising a new one. A thorough assessment of compact structure geometries available in the literature is generally lacking. Existing comparison of a wide collection of composite cell topologies given in [13] relies on subjective userdefined parameters and assumptions, which severely limits its practical use in identifying the optimal circuit geometry for a specific design case. Early steps in the direction of systematic selection of slow-wave transmission lines have been reported in [12,14], offering new opportunities for the development of miniaturized microwave systems. This work is an extension of [14] and provides a framework for rapid and reliable selection of a compact circuit geometry that demonstrates the highest miniaturization ratio and satisfies the operating conditions of a given application device. The proposed

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process accomplishes this goal at a low computational cost by performing circuit decomposition and executing design optimization at the level of circuit building blocks instead of the entire structure. To expedite the process even further, linear expansion models primarily based on coarse-discretization simulation data samples, are used instead of high-fidelity EM models. The objective is to minimize the layout area of the device at hand, while ensuring electrical parameter values that are required for the proper circuit operation. The proof of concept is illustrated using branch-line and rat-race coupler design examples with several different circuit geometries considered in the process. The range and variety of investigated circuit configurations and design specifications allow us to argue that the presented strategy could be successfully applied also to other types of distributed-element microwave circuits. The advancements of this work over [14] include a generalization of the circuit component optimization process, substantial reduction of its computational cost, a generic formulation of a cost-efficient circuit fine-tuning procedure, and extended numerical case studies supplemented with experimental validation.

customized design optimization routine—aimed at the explicit minimization of circuit layout area—is iterated over considered circuit topologies. A proper operation of the circuit at hand is ensured through implicitly handled constraints. To reduce the time expenditure on the process, each considered circuit configuration is disassembled and the electrical performance parameters are evaluated at the level of circuit building blocks instead of the entire structure. At this stage, parasitic EM cross-coupling effects between adjacent circuit elements are intentionally neglected. This is a necessary trade-off between the process reliability and its overall computational cost. Owing to such a problem formulation, each circuit realization will satisfy the predefined performance requirements (under the assumption of a negligible influence of parasitic EM effects), thus enabling discrimination between the candidate topologies based exclusively on the obtained miniaturization ratios. The selected circuit solution is subsequently reassembled and verified using a high-fidelity EM simulation. Potential performance degradation is handled through a local fine tuning.

2. Methodology

2.2. Design procedure outline

In this section, we give a short overview of the proposed framework for automated selection of miniaturized circuit geometry, and describe its key components, including design optimization and fine-tuning algorithms.

A key component of the previously described framework is a simulation-driven miniaturization procedure applied to every circuit topology in the considered candidate pool. The procedure under discussion relies on the concept of size reduction via replacing ordinary TL sections of a conventional circuit by slow-wave structures, constructed in the form of folded lines as well as compact cells – the latter being typically intricate combinations of high- and low-impedance elements. The main benefits from simultaneously using folded lines and compact cells are twofold: (i) the ease of complementary fitting both types of slow-wave structures, and (ii) the possibility of expressing the layout area of the entire circuit as a function of compact cell designable parameters, with other necessary variables (e.g., a folded line width, a distance between circuit building blocks, tee-junction dimensions, etc.) being easy to fix without a notable loss of generality. In addition, the miniaturization procedure utilized here is fully compatible with the bottom-up design approach involving circuit disassembly, which is imperative for keeping the overall computational cost at a low level. An important element of this design strategy is translating performance requirements specific to the given application circuit into equivalent requirements pertaining to its building blocks in the form of the characteristic impedance and phase shift defined at the operating frequency. Taking all of the above into consideration, the problem of simulation-driven design of miniaturized microwave circuits can be approximately, yet conveniently simplified to the problem of adjusting geometry parameters of compact circuit building blocks (primarily composite cells). At a generic level, the design procedure consists of the following three stages:

2.1. Framework for compact circuit geometry selection A flow chart of the proposed framework is shown in Fig. 1. The purpose of the system is to provide a quantitative comparison of candidate compact circuit geometries. This allows for an informed selection of a particular circuit realization of a given application structure based on its miniaturization ratio. To this end, a

Fig. 1. Overview of the proposed framework for compact circuit geometry selection (the first termination condition refers to the number of candidate circuits; the second one is associated with the assumed performance criteria).

1. Compact cell optimization. This is the core of the design process, geared towards identification of the compact cell dimensions that minimize the layout area of the considered circuit topology, while ensuring the required electrical parameters by means of a penalty function approach. Other relevant parameters included in the circuit area calculation (e.g., a width of the folded line or a distance between the adjacent circuit components) are either specified by the user or easily determined in advance and fixed during the optimization process. 2. Folded line length adjustment. Having the topology of a folded line fixed, the task at hand is to adjust a small number of geometry parameters (typically one or two) related to the electrical length of the component. The width of the folded line, corresponding to the characteristic impedance, is determined before-

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hand and remains fixed in the course of the design process. It should be noted that an appropriate portion of the footprint is pre-allocated so that this step does not alter the overall circuit size. 3. EM simulation of the reassembled circuit. Once steps 1 and 2 are completed for all candidate circuit geometries, and the solution that features the highest miniaturization ratio has been selected, the final structure is reassembled from the determined building blocks and verified by means of a full-wave EM simulation. If the EM-evaluated frequency characteristics are acceptable, the design process is concluded. Otherwise, a local fine tuning may be applied to account for parasitic EM interactions between the circuit components or other deteriorating phenomena (e.g., tee-junction phase shifts).

r = [U(x(i+1))  U(x(i))]/[L(i)(x(i+1))  L(i)(x(i))] calculated upon solving (3) [15]. Here, we use the standard values of the gain ratio thresholds, that is, 0.25 for radius reduction, and 0.75 for radius enlargement. The algorithm is terminated upon convergence in argument or shrinking the TR radius below a user-defined level. The interested reader is referred to [15] for a detailed description of the trust-region framework. The model L(i) in Eq. (3) is a local (linear) approximation of the objective function U(x). Note that the design problem (2) can be classified as a problem with a low-cost objective function and expensive constraints that normally require accurate simulation models to be evaluated. Thus, the use of approximations is only limited to electrical performance parameters as shown below:

It should be reiterated that a meaningful comparison of different compact circuit geometries presented in this work is only possible due to circuit decomposition that essentially allows for replacing computationally expensive design problems of the entire miniaturized circuits with much less numerically demanding tasks of compact circuit building blocks design. A rigorous formulation of the design stages is given in Sections 2.3 and 2.4.

ð4Þ

2.3. Design problem formulation Let us denote by A(x) the circuit layout area, where x is a vector of adjustable geometry parameters of the circuit building blocks. By predetermining the remaining variables, such as the width of the folded line and the separation between the circuit components, the vector x exclusively describes compact cell parameters. The design task is formulated as a nonlinear minimization problem of the form

x
¼ argminfx : U ðxÞg

ð1Þ

where U(x) is an objective function defined as 2

2

UðxÞ ¼ AðxÞ þ b1  maxðSðx; f 0 Þ  Smax ; 0Þ þ b2  ðPðx; f 0 Þ  P0 Þ

ð2Þ The primary objective in (2) is reduction of the circuit size A(x). Electrical performance parameters are kept at the required levels using the two penalty terms, where S(x; f0) and P(x; f0) stand for the reflection coefficient magnitude and the phase shift of the considered compact cell at the operating frequency f0. The first term ensures that S(x; f0)  Smax with the reflection response recalculated for the characteristic impedance imposed by design specifications. Setting Smax to a sufficiently small value (e.g., 40 dB) results in allocating the reflection minimum in the vicinity of the operating frequency. The second term is to enforce the required phase shift P(x; f0) = P0. The values of the penalty coefficients b1 and b2 are not critical although they should be sufficiently high to make the contribution of the penalty terms significant if the design specifications are violated beyond acceptable levels. 2.4. Design optimization and fine-tuning algorithms Solution to Eq. (1) is found here by using a trust-region (TR) gradient search algorithm [15], which generates a sequence of approximations x(i), i = 0, 1, . . ., to the optimum design x*. The subsequent iteration points are obtained by solving

xðiþ1Þ ¼ arg

min

x; jjxxðiÞ jj6dðiÞ

LðiÞ ðxÞ

ð3Þ

More specifically, x(i+1) is identified in the vicinity of the current design x(i), defined as ||x  x(i)||  d(i), where d(i) is the TR radius at iteration i, updated using standard rules based on the gain ratio

 2  2 ðiÞ ðiÞ LðiÞ ðxÞ ¼ AðxÞ þ b1  max LS ðxÞ  Smax ; 0 þ b2  LP ðxÞ  P0

where LS(i)(x) = S(x(i)) + Jc.S(x(i))(x  x(i)), and LP(i)(x) = P(x(i)) + Jc. (i) (i) P(x )(x  x ) are first-order Taylor expansion models of S and P (i) at design x , respectively. For the sake of computational efficiency, the Jacobians Jc.S and Jc.P are estimated using finite differentiation of the coarse-discretization EM model instead of the high-fidelity one. It should be emphasized that, although both are misaligned, they are normally well correlated so that the Jacobian estimation involving coarse-discretization model samples is sufficiently reliable. It should be emphasized that the surrogate model L(i) benefits from using both low-fidelity (coarse) and high-fidelity EM simulation data samples. The former greatly reduce the overall computational cost of model construction, whereas the latter increase model accuracy. Compact cell design optimization (cf. Section 2.2, Step 1 of the design procedure) is realized as given by (2)–(4). The same algorithm may be employed for folded line optimization, however with the objective function lacking the term related to the circuit layout area. On the other hand, handling folded line length adjustment is a simple 1–2 parameter task that may be solved by almost any method in a timely manner. Since Steps 1 and 2 of the design procedure capitalize on the concept of circuit decomposition and evaluate circuit building blocks in separation from the rest of the structure, a design closure that accounts for proximity effects such as parasitic EM crosscoupling phenomena may be necessary to fine tune the performance of the entire compact device. One should note that other simplifications of the design process (e.g., neglecting tee-junction phase shifts) may also add to circuit performance degradation. Here, these potential issues can be conveniently addressed by adapting a surrogate-based optimization scheme of [22]. In more detail, the fine-tuning process is realized as

  yðiþ1Þ ¼ arg min H RsðiÞ ðyÞ y

ð5Þ

where y(i), i = 0, 1,. . ., is a series of concatenated vectors of cell parameters x1, x2, . . . and folded line length variables lf1,. . ., that approximate the direct solution to the circuit design problem of the form y* = argmin{y: H(Rf(y))}. The objective function H(y) comprises the circuit area as the primary component, but also performance requirements of the circuit at hand, as shown below

HðyÞ ¼ AðxÞ þ b1  c1 ðyÞ þ b2  c2 ðyÞ þ :::

ð6Þ

where b1, b2,. . . are penalty coefficients, and c1, c2, . . . are penalty functions that measure the violation of particular operating conditions. For example, Eq. (6) can be customized to satisfy the design specifications of a directional hybrid coupler by means of the following penalty functions: c1(y) = max(|fz(S11(y; f))  f0|, |fz(S41(y; f))  f0|)2, c2(y) = max(max(S11(y; f0), S41(y; f0))  Smax,0)2, and c3(y) = (S21(y;f0)  S31(y;f0))2. The aim of c1(y) is to bring the most

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ðiÞ RsðiÞ ðyÞ ¼ RðiÞ c ðy þ q Þ

ð7Þ

where q(i) is the shift vector identified through a standard extraction procedure q(i) = argmin{q: ||Rf(y(i))  Rc(y(i) + q)||} [23] that aims at minimizing the misalignment between Rc and Rf. The core of the surrogate is the coarse model Rc(i), constructed at each iteration from the local models of the circuit building block scattering parameters, and assembled based on the conventional circuit topology using ABCD matrices. Low-cost local models may include first-order Taylor expansions as in (4) or second-order polynomials without mixed terms as in [22]. The discussed design closure technique is very efficient, with the computational cost corresponding to a few EM simulations of the device. 3. Case studies The application design examples presented in this section are to demonstrate the operation and efficiency of the proposed approach to EM-driven selection of compact circuit geometries. Thus, let us consider conventional circuit solutions of branch-line and ratrace couplers shown in Fig. 2. Owing to their modular architecture primarily based on quarter-wavelength TL sections as well as the unoccupied interior of the circuit, they are probably the most widely represented class of devices that undergo miniaturization

Z1,P0

Z2,P0

d lf2

lf1

Z0,P0

1

3

d

wf d

3

4

This section contains numerical and experimental results obtained by applying the methodology of Section 2 to design examples described in Section 3. The proposed process aims at identifying a particular circuit geometry among a considered set of options and adjusting its designable parameters so that the resultant layout is characterized by the smallest area and acceptable frequency characteristics. The application circuits are to operate at the design frequency of 1 GHz, having all ports matched, and—when excited by port 1—exhibiting a specific in-phase or out-of-phase equal power division between ports 2 and 3 with no power being transferred to port 4 [19]. Note that this desired circuit performance is achieved when circuit building blocks demonstrate adequate values of the characteristic impedance and transmission phase (see Fig. 2). Naturally, dealing with a realistic design problem calls for consideration of tee-junction phase shifts or parasitic cross-coupling effects that are likely to deteriorate the performance of the device. Here, the computer-aided design process itself is realized using Keysight Momentum EM solver [20].

Z0,P0

d

2

4. Numerical and experimental results

Z2,P0

1

[16–18]. They also comprise elements that feature a wide range of characteristic impedances, which is another argument in favor for using them as versatile application examples. As already outlined in Section 2.2, the devices at hand will be miniaturized by substituting their original building blocks by folded lines and compact cells. We assume here that the former and latter slow-wave structures will be used in place of white and black elements, respectively (see the inset of Fig. 2 for illustration of this concept). Each application circuit is considered in eight different geometry configurations of compact cells, whose detailed parameterization is presented in Fig. 3. Alternative compact cell geometries can be found in the literature (e.g., [13]). An exemplary vector of cell geometry parameters is given by x = [x1 x2 x3 x4 x5 x6]T. Our objective is to choose a version of the compact circuits under discussion that leads to the smallest layout realization, and—at the same time—exhibits acceptable electrical performance.

Z0,P0

distant zero fz of S11 and S41 magnitudes (S-parameters related to return loss and isolation) to the operating frequency f0. The purpose of c2(y) is to ensure that the given S-parameters yield at least a value of the threshold Smax at f0. The function c3(y) is designed to force an equal power division between the output ports at f0. Note that the penalty functions ought to be properly modified in case of different applications. For the sake of computational efficiency, the system performance evaluation is realized in (5) by means of a fast surrogate model Rs instead of an expensive high-fidelity (fine) model Rf of the given device. The model Rs(i) at the ith iteration is constructed by correcting the low-fidelity (coarse) model Rc(i) using the input space mapping [23] as

2

4 wf

Z0,P0

Z1,P0 lf

Z0,P0

290

Z0,P0 Fig. 2. Application examples: branch-line coupler (left), and rat-race coupler (right). Electrical performance parameters of the circuit components (at the operating frequency f0): Z1 = 35.4 X, Z2 = 50.0 X, Z0 = 70.7 X, and P0 = –90°. The miniaturization concept employed in this work is illustrated using grey components placed inside the application circuit.

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x6 x5

x2

x6

x2 x3 x7

x4

x6

x3

x4

x4

x1

x1

x5

(b)

(a) x5 x6

x2

x3

x4

x6

x4

x6

x3

x1

x6

x5

x2

x4

x1 x4

(d)

(c) x6 x3

x6

x2 x4

x6

x4 x4

x1

x5 x1

x5

x2

x3

(f)

(e)

x4 x5

x6 x6

x3 x1

x5

x6 x6

x3

x4

x2

x1

(g)

x4 x4

x2

(h)

Fig. 3. Candidate pool of considered compact cells based on [13].

Computational models are implemented on the Rogers RO4350B dielectric substrate (er = 3.48, h = 0.762 mm) at two levels of discretization. Coarse meshing is utilized in case of circuit component simulations to efficiently estimate the Jacobian matrix, whereas fine meshing is applied to each structure and their respective building blocks to ensure a sufficient accuracy of the design process. Average simulation times of compact cells are 11 s for coarse models and 85 s for the fine ones using 16-core Intel Xeon 2.2 GHz processor with 32 GB of RAM. In contrast, the evaluation of fine EM models of the considered application circuits takes, approximately, 16 and 27 min for the branch-line and rat-race coupler, respectively. Conventional branch-line and rat-race coupler layout realizations, developed here for comparison purposes using the above specifications, consume areas of 46.35  50.81 and 76.80  93.91 mm2. The starting point of each compact cell optimization task is chosen arbitrary by setting all model geometry parameters related to gaps, widths, and lengths to 1, 0.5, and 3 mm, respectively. The relevant search space is defined by the lower bounds set to 0.1 mm (technology process limitations) and upper bounds fixed as 1 mm for gaps, 5 mm for widths, and 20 mm for lengths. The vectors of optimum cell geometry parameters, obtained for both investigated design problems, are listed in Tables 1 and 2. In each case, the userdefined distance between adjacent circuit building blocks is

291

d = 1.5 mm (see Fig. 2). Following the guidelines of Section 2.2, the specific circuit geometries and their optimum design solutions are picked based on the miniaturization ratios. For the first application example, due to a very close values of coupler layout areas provided by cells labeled as (g) and (h), both these solutions are found suitable for the subsequent circuit reassembly and verification. EM-simulated frequency characteristics of devices obtained this way are shown in Fig. 4(a)–(b). One can observe a 40-MHz and 70-MHz downshift in |S11| and |S41| minima for designs xcell * * (g) and xcell(h), respectively. To address this performance degradation, the fine-tuning procedure of Section 2.4 is employed, which leads to refined design solutions y*(g)=[0.1 4.72 1.74 0.1 1.19 0.2 2.73 6.94]T and y*(h)=[0.1 3.61 0.2 0.1 0.98 0.1 1.46 8.13]T (both included in Fig. 4(a)–(b) together with their corresponding layouts). Design tuning is realized by (5)–(7) using the exact penalty functions defined in Section 2.4 and Smax = 35 dB. Upon design refinement, the final miniaturization ratios increase from 75.9% to 77.3% (for cell (g): 535.7 mm2) and from 76.0% to 78.6% (for cell (h): 504.6 mm2). At the same time, both solutions exhibit |S11| and |S41| minima, with values below – 35 dB, at the center frequency of 1 GHz, and a power split of – 3.08 dB. In case of the second application example summarized in Table 2, the minimum circuit size of 549.6 mm2 (87.5% miniaturization ratio) is obtained for cell (c), hence, this component is selected as the main building block of the final rat-race coupler. As illustrated in Fig. 5(a), EM-simulated coupler performance shows a 4-MHz shift of |S41| minimum from the desired frequency, with the other figures of merit remaining intact. Despite this minor shortcoming, the center-frequency coupler performance parameters meet the expected standards (|S11| = 28.2 dB, |S21| = 3.05 dB, |S31| = –3.05 dB, |S41| = 44.8 dB), thus no additional design refinement is required. To decisively validate the obtained results, the minimum-size circuit solution is fabricated (see Fig. 5 (b)) and measured. The experimental data included in Fig. 5(a) exhibit a good agreement with the predicted results, with typical (minor) discrepancies being attributed primarily to manufacturing tolerances. In addition, some simplifications of the respective EM simulation models (e.g., connector modeling is lacking or isotropic dielectric is applied instead of anisotropic one [21]) may contribute to the observed differences. At the operating frequency of 1 GHz, the fabricated prototype offers |S11| = 27.2 dB, |S21| = 3.28 dB, |S31| = 3.48 dB, |S41| = 37.9 dB. An important aspect of the proposed design technique is its numerical efficiency. Depending on the quality of the starting point for the considered examples of compact cells, the optimization process requires from 5 to 12 iterations of (3) to reach convergence. This translates to 5–12 evaluations of the relevant fine model, and about 30–80 simulations of the coarse one. Having the width of the folded line fixed (in particular, 2.5 and 0.85 mm for the first and second application example, respectively), adjusting length parameters of this element involves merely a handful of EM simulations. On average, the computational cost of EM-driven circuit component optimization is 1.68Rf and 1.01Rf for the first and second application example, respectively, where Rf stands for the EM simulation of the entire compact circuit. This facilitates a comprehensive comparison of multiple compact circuit geometries at only a fraction of cost required for EM design optimization of compact circuits by means of standard algorithms, which can be estimated as 150–180Rf for a 10-variable design task. One should note that the design optimization technique used here has been specifically tailored for circuit geometry selection. This becomes evident when comparing the proposed technique to the state-of-the-art design optimization methods dedicated to compact microwave components (cf. Table 3). Its advantages lie in the smallest CPU cost per design, capability of explicit layout

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Table 1 Optimum Compact Cell Design Solutions: Branch-Line Coupler Design Example. Designable parameters [mm]

x*cell(a) x*cell(b) x*cell(c) x*cell(d) x*cell(e) x*cell(f) x*cell(g) x*cell(h) #

x1

x2

x3

x4

x5

x6

x7

3.06 2.03 6.80 0.10 1.85 1.39 0.10 0.10

13.54 13.34 5.20 16.93 16.39 4.99 4.69 3.49

1.54 2.30 1.71 0.10 1.71 5.01 1.82 0.10

0.17 0.53 0.11 0.14 0.96 1.68 0.10 0.10

2.49 0.34 0.50 1.40 0.41 0.16 1.19 1.03

0.20 0.10 0.10 0.10 0.10 3.15 0.20 0.10

0.10 – – – – – – –

Area [mm2]

Miniaturization# [%]

746.8 607.3 662.5 600.4 627.2 850.7 567.3 564.5

68.3 74.2 71.9 74.5 73.4 63.9 75.9 76.0

Area [mm2]

Miniaturization# [%]

674.2 724.7 549.6 702.9 755.1 854.2 652.5 772.2

84.7 83.5 87.5 84.0 82.8 80.6 85.2 82.4

Calculations made in reference to conventional branch-line coupler (46.35  50.81 mm2).

Table 2 Optimum Compact Cell Design Solutions: Rat-Race Coupler Design Example. Designable parameters [mm]

x*cell(a) x*cell(b) x*cell(c) x*cell(d) x*cell(e) x*cell(f) x*cell(g) x*cell(h) #

x1

x2

x3

x4

x5

x6

x7

1.49 8.50 3.82 5.35 7.20 3.07 4.65 14.77

16.60 7.70 8.99 13.15 10.50 5.54 5.45 1.43

0.1 1.03 0.24 0.14 1.84 8.90 0.81 1.27

0.12 0.10 0.10 0.10 0.29 0.92 0.19 0.18

1.59 0.41 0.12 0.91 0.33 0.18 0.32 0.11

0.99 0.1 0.13 0.10 0.19 0.86 0.20 0.19

0.18 – – – – – – –

Calculations made in reference to conventional rat-race coupler (46.80  93.91 mm2).

15.65 mm

0

34.23 mm

Magnitude (dB)

S21,S31 -10 -20 -30

S11

S41

-40 -50 0.8

S11

S41 0.9

w/o fine tuning with fine tuning 1.1 1.2

1 Frequency (GHz)

(a)

14.81 mm

0

34.07 mm

Magnitude (dB)

S21,S31 -10 -20 S11 -30

S41 S11,S41

-40 -50 0.8

0.9

1 Frequency (GHz)

w/o fine tuning with fine tuning 1.1 1.2

(b) Fig. 4. Branch-line coupler application example. Primary and refined minimum-size circuit solutions: (a) x*cell(g) (folded line parameters: wf = 2.5 mm, lf1 = 3.8 mm, lf2 = 6.88 mm) and y*(g) (wf = 2.5 mm, lf1 = 2.73 mm, lf2 = 6.94 mm), (b) x*cell(h) (wf = 2.5 mm, lf1 = 3.57 mm, lf2 = 7.77 mm) and y*cell(h) (wf = 2.5 mm, lf1 = 1.46 mm, lf2 = 8.13 mm). EM-simulated S-parameters (left) of the primary circuit solution (solid) and a refined one (dotted), with the final coupler layout (right).

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9.44 mm

0

-20

58.21 mm

Magnitude (dB)

S21,S31 -10

S11 -30 S41 -40 -50 0.8

0.9

1 Frequency (GHz)

EM simulation Measurement 1.1 1.2

(a)

(b)

Fig. 5. Rat-race coupler application example. (a) EM-simulated vs. measured S-parameters of minimum-size circuit solution x*cell(c) (wf = 0.85 mm, lf = 20.31 mm), and (b) its corresponding layout together with photograph of fabricated device.

Table 3 Comparison of design optimization methods of miniaturized microwave components. Ref.

Problem formulation

Algorithm

Area minimization

Model corrections

Models

CPU cost per design

[4]

Multi objective with penalty functions Multi objective

Pattern search

Yes Yes

Single objective with penalty function Single objective with penalty functions

Pattern search

No

None

Equivalent circuit models and high-fidelity models Equivalent circuit models and high-fidelity models High-fidelity EM models

3Rf

Evolutionary algorithm

Implicit and frequency space mapping Implicit space mapping

Trust-region gradient search

Yes

None

Linear models based on coarse-discretization EM models and high-fidelity EM models

1–2Rf

[10] [22] This work

area minimization, and convenience of use since it requires only one simulation tool. 5. Conclusion This paper presents an algorithmic framework for automated design optimization of miniaturized microwave structures. The key component of the proposed system is a process that rapidly adjusts geometry parameters of the considered circuit configurations in order to simultaneously minimize the circuit layout area and satisfy performance design specifications. This strategy allows for a conclusive comparison between the candidate compact circuit geometries and selection of the optimum solution that is subsequently verified and, if needed, fine-tuned. One of the important advantages of the proposed approach is that the final circuit miniaturization rate is not a by-product of designing a circuit with an arbitrarily devised topology (as largely exercised in prior works on the subject, e.g., [3–9,11,16,17,22,24]), but a direct result of a systematic procedure involving concurrent size and performance optimization. In addition, the proposed methodology is generic and can be applied to diverse design scenarios. Here, it is demonstrated using branch-line and rat-race coupler application examples with eight different circuit geometries considered in each case. The obtained miniaturization ratios ranging from 63.9% to 76% for the first design case, and from 80.6% to 87.5% for the second one, respectively, confirm the implicit assumption made here that the underlying circuit topology has a profound effect on the achievable size of the circuit at hand. Furthermore, as indicated by the collected numerical results, the optimum selection of a compact circuit geometry is largely dependent on the particular application, both in terms of the topology of a conventional circuit to be miniaturized as well as performance specifications imposed

3–5Rf 2–3Rf

on its building blocks. The proposed method is also geared towards handling potential circuit performance degradation by low-cost surrogate-based optimization scheme placed at the closing stage of the entire design process. The future work will be focused on handling both continuous optimization of circuit geometry parameters and discrete optimization of circuit topology within the same process. Declaration of Competing Interest The authors declare no conflict of interest. Acknowledgement The authors thank Keysight Technologies, Santa Rosa, CA, for making ADS available. This work is partially supported by the National Science Centre of Poland Grant 2015/17/B/ST6/01857. References [1] Ma T-G, Wang C-W, Lai C-H, Tseng Y-C. Synthesized transmission lines. Design, circuit implementations, and phased array applications. Wiley; 2017. [2] Martin F. Artificial transmission lines for RF and microwave applications. Wiley; 2015. [3] Koziel S, Bekasiewicz A. Implicit space mapping for variable-fidelity EM-driven design of compact circuits. IEEE Microw Wireless Comp Lett 2018;28 (4):275–7. [4] Koziel S, Bekasiewicz A, Kurgan P. Rapid multi-objective simulation-driven design of compact microwave circuits. IEEE Microw Wireless Comp Lett 2015;25(5):277–9. [5] Koziel S, Kurgan P. Inverse modeling for fast design optimization of small-size rat-race couplers incorporating compact cells. Int J RF Microw Comp Aid Eng 2018;28(5):1–8. E21240. [6] Zhou C, Yang HYD. Design considerations of miniaturized least dispersive periodic slow-wave structures. IEEE Trans Microw Theory Tech 2008;56 (2):467–74.

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[15] Conn AR, Gould NIM, Toint PL, Trust region methods. 2000 MPS-SIAM series on optimization; 2000. [16] Jung S-C, Negra R, Ghannouchi FM. A design methodology for miniaturized 3dB branch-line hybrid couplers using distributed capacitors printed in the inner area. IEEE Trans Microw Theory Techn Dec. 2008;56(12):2950–3. [17] Tseng C-H, Chang C-L. A rigorous methodology for compact planar branch-line and rat-race couplers with asymmetrical T-structures. IEEE Trans Microw Theory Techn Jul. 2012;60(7):2085–92. [18] Xu H-X, Wang G-M, Lu K. Microstrip rat-race couplers. IEEE Microw Mag Jun. 2011;12(4):117–29. [19] Mongia R, Bahl I, Bhartia P. RF and microwave coupled-line circuits. Artech House; 1999. [20] Advanced Design System (ADS). ver. 2011.10. 1400 Fountaingrove Parkway (Santa Rosa, CA 95403–1799): Keysight Technologies; 2011. [21] Rautio JC et al. The effect of dielectric anisotropy and metal surface roughness. In: Proc Asia-Pacific Microw Conf. p. 1777–80. [22] Koziel S, Kurgan P. Rapid design of miniaturized branch-line couplers through concurrent cell optimization and surrogate-assisted fine-tuning. IET Microw Ant Propag 2015;9(9):957–63. [23] Koziel S, Cheng QS, Bandler JW. Space mapping. IEEE Microw Mag 2008;9 (6):105–22. [24] Naderi M, Abbasi H. Design of compact microstrip branch line coupler using semi-circular and rectangular resonators with wide range suppressed harmonics. Int J Electron Commun (AEU) 2018;84(Feb.):171–6.