- Email: [email protected]
Origin of the improved stability under negative gate-bias illumination stress in various sputtering power fabricated ZnSnO TFTs
Accepted Manuscript Origin of the improved stability under negative gate-bias illumination stress in various sputtering power fabricated ZnSnO TFTs Chuan-Xin Huang, Jun Li, Yi-Zhou Fu, Jian-Hua Zhang, Xue-Yin Jiang, Zhi-Lin Zhang PII:
S0749-6036(15)30213-5
DOI:
10.1016/j.spmi.2015.09.036
Reference:
YSPMI 4000
To appear in:
Superlattices and Microstructures
Received Date: 10 July 2015 Revised Date:
27 September 2015
Accepted Date: 29 September 2015
Please cite this article as: C.-X. Huang, J. Li, Y.-Z. Fu, J.-H. Zhang, X.-Y. Jiang, Z.-L. Zhang, Origin of the improved stability under negative gate-bias illumination stress in various sputtering power fabricated ZnSnO TFTs, Superlattices and Microstructures (2015), doi: 10.1016/j.spmi.2015.09.036. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
ACCEPTED MANUSCRIPT
Origin of the improved stability under negative gate-bias illumination stress in various sputtering power fabricated ZnSnO TFTs
RI PT
Chuan-Xin Huang a, Jun Li a,b∗∗,Yi-Zhou Fu a, Jian-Hua Zhang b, Xue-Yin Jiang a, Zhi-Lin Zhang a, b a
School of Material Science and Engineering, Shanghai University, Jiading, Shanghai 201800, People’s Republic of China. b
Key Laboratory of Advanced Display and System Applications, Ministry of Education, Shanghai University,
SC
Shanghai 200072, People’s Republic of China.
Abstract
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In this work, we report the influence of ZnSnO channel layer sputtering power in the stability of ZnSnO TFTs under negative gate-bias illumination stress (NBIS). The origin of threshold voltage shift results from combined effect of two factors between the little defect-induced trap densities originated from oxygen vacancies and better channel-insulator interface. The kinetic energy of the ions at a proper rf sputtering
TE D
power is responsible for less defect-induced trap density and better channel-insulator interface. Therefore, the ZnSnO TFT fabricated at 75 W sputtering power shows a better
NBIS
stability.
In
addition,
the
trap
density
is
extracted
by
EP
temperature-dependent field-effect measurements and it is consistent with the change of stability under NBIS and thermal stress. Keywords: ZnSnO TFTs, rf sputtering power, ALD Al2O3, negative gate-bias
AC C
illumination stability.
1. Introduction
Amorphous oxide semiconductors (AOS) thin films are promising next generation
materials for use as active channel layers to replace conventional amorphous and polycrystalline silicon in thin film transistors (TFTs). Several groups have demonstrated various AOSs such as zinc oxide (ZO), indium oxide (IO), indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO) composition and surveyed ∗
Corresponding author: E-mail address: [email protected] 1
ACCEPTED MANUSCRIPT stabilizer ions (Hf, Zr, Li, Mg and Al et. al) in an oxide system [1-9]. Among this AOS material, IGZO TFTs have high field-effect mobility, a small subthreshold swing, good uniformity attributed to the amorphous structure, a low off current, good stability under electrical stress, and can be processed at low temperatures. However,
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the IGZO channel has also disadvantages such as cost, toxicity and scarcity. Thus, indium-free and gallium-free AOS channel materials such as zinc-tin-oxide (ZTO) have been studied. Several research groups have already reported ZTO semiconductor materials for use as active channel layers in TFTs because of its remarkable electrical, [10–12]
. Although ZTO semiconductor materials
SC
optical properties and smooth surface
as active channel layers in TFTs show significant advantages, some outstanding issues
M AN U
still remain to be resolved, such as stability under bias, temperature and illumination stress.
In general, the quality of the active channel layers has a great influence in stability of TFTs and it can be controlled by various sputtering parameters, such as substrate temperature, oxygen partial pressure, working pressure
[13]
, and in particular, the
TE D
sputtering power [14,15]. Several groups have reported the effect of sputtering power on stability of TFTs. Raja et al. [16] reported that the densification of the proper sputtering power fabricated a-IGZO film resulted in the reduction of its interface trap density,
EP
which contributed to the improvement in the bias stability. Kim et al. [15] reported that the IGZO TFTs with different rf sputtering power showed various temperature stability, which resulted from the trap densities in deep level extracted by MFM
AC C
method. However, the investigation of instability under negative gate-bias illumination stress for various sputtering power fabricated ZTO TFTs has never been reported, which is the most important issue for the practical applications, because most of the proposed uses of TFTs will expose the TFTs to a backlight or ambient light during operation. In this paper, for the first time, we investigate the stability under negative gate-bias illumination stress for various sputtering power fabricated ZTO TFTs. The origin of improved the stability under negative gate-bias illumination stress in proper sputtering power fabricated ZTO TFTs is attributed to two aspects, including the little 2
ACCEPTED MANUSCRIPT defect-induced trap density originated from oxygen vacancies and better channelinsulator interface. In addition, the stability under thermal stress is investigated by trap density. The trap density is extracted by temperature-dependent field-effect measurements method, which is a fast, simple and accurate method.
RI PT
2. Experimental details We fabricated the top-contact-type ZTO TFTs with Al2O3 gate insulators on the highly-doped Si substrate. Fig. 1 shows the schematic structure of the device. An Al2O3 gate insulator approximately 200 nm thick was deposited by ALD. ZTO films
SC
with a thickness of 36 nm were deposited by rf-magnetron sputtering at room temperature using a ZTO target at input power of A: 30 W, B: 50 W, C: 75 W and D:
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100 W. Chamber pressure before sputtering was 5×10-4 Pa, and total pressure was 0.5 Pa. After deposition of ZTO films, all devices were annealed at 350 °C for 1 h in atmosphere then about 200 nm Al was deposited by thermal evaporation to form the source and drain electrodes through a shadow-mask with the channel width (W) of 1000 µm and channel length (L) of 50 µm. Finally, all devices were capped with a PE
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passivation layer and sequentially annealed at 250 °C for 10 min in atmosphere. The thickness of the film was measured by the alpha step (Alpha-Step IQ). The electrical characteristics of ZTO-TFTs were measured using Agilent E3647A Dual output DC
EP
power supply and Keithley 6485 Picoammeter and related software. The capacitance characteristics were measured using Agilent E4980A LRC meter.
AC C
3. Result and discussion
Fig. 2 shows the evolution of the transfer curves as a function of the negative
gate-bias illumination stress time for devices A, B, C and D, respectively. A white light source with a photo intensity of 4000 lux. is used under identical -10 V negative gate-bias stress and 0 V drain-bias stress. As seen in Fig. 2, the off-state current increases and the transfer characteristics of all devices shift toward the negative direction as negative gate-bias illumination stress time increases. In particular, the device with different rf sputtering power shows various threshold voltage (VT) shift under negative gate-bias illumination stress and the Fig. 3 shows the negative 3
ACCEPTED MANUSCRIPT gate-bias illumination stress time dependence of threshold voltage shift (△VT = VT0s-VTxs) for ZTO TFTs with different sputtering power. In previous report, the instability of TFTs under negative gate-bias illumination stress is
attributed to the
following three mechanisms, including the oxygen photo-desorption model [18,19]
, the
and the photo-created
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photo-transition model from deep level [VO] to [VO2+]
[17]
hole carrier trapping model [20,21].
The oxygen photo-desorption model means the dynamic desorption of the adsorbed oxygen molecules on the ZTO back surface through the photon excitation
[17]
. When
SC
the devices without passivated layer are expected to the light and bias stress, the dynamic concentration of adsorbed oxygen molecules will be affected. For example, of negative
gate-bias
illumination
stress
will cause the
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the application
photo-desorption of adsorbed oxygen molecules, which will release the free electron and result in a negative VT shift. However, in our case, the devices are capped with a PE passivation layer, which will prevent the occurring of photo-desorption of adsorbed oxygen molecules. As seen in the Fig. 3, 75 W sputter power fabricated
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ZTO TFT without passivated layer (Unp.) shows larger △VT than 75 W sputter power fabricated ZTO TFT with a passivated layer (Pas.). This behavior indicates that the passivated layer has a very important role in restraining desorption of the adsorbed
EP
oxygen molecules. Therefore, the oxygen photo-desorption model is excluded. The second plausible model is related to the oxygen vacancies. It has been reported that in n-type Zn based oxide semiconductors, [VO] acts as a negative U defect center . Interestingly, photon energy can excite the transition of the [VO] ground state to
AC C
[22, 23]
the meta-stable [VO2+] excited states, resulting in the formation of delocalized free electrons in the conduction band. The photo-generated electrons are responsible for increasing of off-state current and the negative VT shift of the ZTO TFTs under negative gate-bias illumination stress
[22, 24, 25]
. Therefore, the different shift of VT can
be explained by the various [VO] densities in different sputtering power fabricated ZTO channel layer. In particular, it has been reported that defect-induced trap density are commonly originated from oxygen vacancies in oxide-based semiconductors 26, 27]
, and the sputtering power also has a great effect on the trap density 4
[8, 22, [15]
.
ACCEPTED MANUSCRIPT Therefore, trap density can be used to describe [VO] densities roughly and explain why the device with different sputtering power fabricated ZTO channel layer shows various shift of VT under negative gate-bias illumination stress. To further investigate the effect of the trap density originated from oxygen vacancies under different sputtering power on the stability of ZTO TFTs under
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negative gate-bias illumination stress, we have observed trap density by temperature-dependent field-effect measurements. Fig. 4 shows the transfer curves of different sputtering power fabricated ZTO TFTs under thermal stress from 298 k to 373 k in dark state. As shown in Fig. 4, the negative shift of VT and increasing of
SC
off-state current with increasing the temperature for all of ZTO TFTs result from the generation of thermally activated carrier from traps in the band gap of ZTO. In
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particular, the △VT for different rf sputtering power fabricated device is △VTA = 15.2 V, △VT B = 12 V, △VT C = 5.8 V and △VT D = 10 V under thermal stress, respectively. The reduction in △VT value with proper sputtering power is consistent well with that when the negative gate-bias illumination is stressed. The thermally activated drain current in the subthreshold region is given as
(1)
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I D = I D 0 ⋅ exp(− Ea kT )
Where Ea is the activation energy, ID0 the prefactor, k the Boltzmann constant and T the temperature. ID0 and Ea at different gate voltages (VGS) can be easily derived by plotting logarithm ID versus 1/kT, as shown in Fig. 5. The curves of activation energy
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with gate voltage for different rf sputtering power fabricated ZTO TFTs is shown in
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Fig. 6 (a). From the Fig. 6 (a), we estimated the falling rates ( d (E a ) d (VGS ) of the various rf sputtering power fabricated ZTO TFTs. The values are 0.25, 0.50, 0.65 and 0.75 eV/V, respectively. The thermal excitation of the trapped charge can be calculated by the falling rate d (E a ) d (VGS ) , which should have the same magnitude as the rate of increase in EF and moreover the rising rate of EF with respect to VGS is roughly inversely proportional to the magnitude of the bulk and interface trap density [4]
, so the trap density is roughly inversely proportional to falling rates
( d (E a ) d (VGS ) and the detailed distribution of trap density within energy band gap in ZTO TFTs can be described by the following equation [28]: 5
ACCEPTED MANUSCRIPT g ( Ea ) = −
εi
d (Ea ) qdi t d (VGS )
(2)
Where ε i and di are the permittivity and the thickness of the gate insulator, q is the
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electron charge, and t is the thickness of the channel layer. Fig. 6 (b) shows the trap density in the energy band gap of ZTO TFTs. It is observed that the trap density of ZTO TFTs decreases firstly from 2.0×1016 eV-1cm-3 to 5.0×1015 eV-1cm-3 and then increases to 8.0×1015 eV-1cm-3 as the rf sputtering power increases from 30 W to 100
SC
W. This result is consistent with the findings of previous studies that better temperature stability of proper sputtering power fabricated IGZO and SZTO TFTs is [15, 29]
. The certain asperities insufficient to be removed by
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due to less trap densities
the kinetic energy of the ions at smaller sputtering power and etching effect of increasing high energetic ions at large rf sputtering power are responsible for the increasing trap density
[16]
. Moreover, defect-induced trap density are commonly
originated from oxygen vacancies in oxide-based semiconductors, so there are less
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oxygen vacancies in 75 W sputter power fabricated ZTO TFTs. Therefore, from [VO] densities aspect, the trap density can be used to explain why the device with different sputtering power fabricated ZTO channel layer shows various shift of VT under
EP
negative gate-bias illumination stress.
The photo-created hole carrier trapping model is explained from aspect of interfacial trap densities, so the sub-threshold swing (SS) related to interfacial trap
AC C
densities is investigated. The SS of device A, B, C and D can be deduced by the follow relation from the initial transfer curves (0 min) in Fig. 2. SS =
dVGS d (logI DS )
(3)
Here, we evaluate the SS values to be 0.54, 0.45, 0.35 and 0.42 V/dec. From SS, we can infer the maximum density of surface states at the channel- insulator interface as:
SS log(e ) Ci max N SS = − 1 kT q q 6
(4)
ACCEPTED MANUSCRIPT max Given the value of Ci, N SS of 1.51×1012, 1.35×1012, 1.0×1012 and 1.25×1012 cm-2
are calculated for the various rf sputtering power fabricated ZTO TFTs. since the kinetic energy of the ions at smaller sputtering power is insufficient to remove certain asperities and hence the channel-insulator interface is not very smooth. However,
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further increasing the rf sputtering power to 100 W causes the surface of film to become ragged with largest interface trap density of 1.25×1012 cm-2. These phenomena are resulted from the etching of the surface by increasing high energetic ions. This result shows that the interface trap density reduces firstly and then increases
SC
as the rf sputtering power increases from 30 W to 100 W, and it is consistent with the change trend of interface trap density in IGZO TFTs reported by Raja et al.
[16]
. The
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surface morphology of ZTO films with various sputtering power confirm these behaviors and their AFM image is shown in Fig. 7. As seen in the figure, with the increase of sputtering powers, the morphology of ZTO films are improved firstly and then declines dramatically. The RMS for 30, 50, 75, and 100 W ZTO films is 7.36, 5.07, 3.46 and 4.22 nm, respectively.
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In particular, the electron-hole pairs as a result of photoexcitation will be generated in the channel region under the light illumination. The generated hole carrier will be attracted toward the interface of the channel layer and gate dielectric layer due to the
EP
negative charge at the gate electrode under a negative-gate bias. This accumulated hole can be trapped at the interfacial trap sites or injected into the underlying gate
AC C
dielectric layer, which leads to a negative VTH shift. Because the device C with 75 W sputtering power fabricated ZTO film shows the least interface trap density of 1.0×1012 cm-2, there are the least hole trapped at channel-insulator interface. Therefore, the device C shows little shift of VT than device A, B, D and we suggest that the better stability of device C under a negative-gate bias can also be attributed to the least interfacial trap densities. 4. Conclusion
The origin of VT shift with various rf sputtering power fabricated ZTO TFTs under a negative-gate bias is experimentally provided and analyzed through combined effect 7
ACCEPTED MANUSCRIPT of two factors between the little defect-induced trap density originated from oxygen vacancies and better channel-insulator interface. The kinetic energy of the ions at proper rf sputtering power is responsible for little defect-induced trap density and better channel-insulator interface. Since the certain asperities insufficient to be
RI PT
removed by the kinetic energy of the ions at smaller sputtering power and etching effect of increasing high energetic ions at large rf sputtering power result in the increasing of trap density and worse channel-insulator interface. Therefore, the stability under a negative-gate bias is improved with proper sputtering power and the
SC
TFTs fabricated by rf sputter should be carefully optimized to provide better stability
5. Acknowledgements
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for ZTO in terms of power.
The authors would like to acknowledge the financial support given by the Natural Science Foundation of China (51302165, 61274082, 61077013), 863 project (2010AA3A337, 2008AA03A336), Innovation Fund of shanghai University,
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Shanghai Municipal Education Commission (ZZSD13047), China Postdoctoral Science Special Fund (2015T50837) and Shanghai Science and Technology
References
EP
Commission (15JC1402000).
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ACCEPTED MANUSCRIPT [7] K. H. Lim, K. Kim, S. Kim, S. Y. Park, H. Kim, Y. S. Kim, Adv. Mater. 25, (2013) 2994. [8] G. H. Kim, W. H. Jeong, B. D. Ahn, H. S. Shin, H. J. Kim, H. J. Kim, M. K. Ryu, K. B. Park, J. B. Seon, S. Y. Lee, Appl. Phys. Lett. 96, (2010) 163506. [9] J. H. Jeon, Y. H. Hwang, B. S. Bae, H. L. Kwon, H. J. Kang, Appl. Phys. Lett. 96, (2010)
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Appl. Phys. Lett. 99, (2011)102103.
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Electrochem. Solid-State Lett. 11, (2008) H157.
[14] J. K. Jeong, J. H. Jeong, H. W. Yang, J. S. Park, Y. G. Mo, H. D. Kim, Appl. Phys. Lett. 91, (2007) 113505.
[15] B. Kim, E. Chong, D. H. Kim, Y. W. Jeon, D. H. Kim, S. Y. Lee, Appl. Phys. Lett. 99, (2011) 062108.
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[16] J. Raja, K. Jang , H. H. Nguyen, T. T. Trinh, W. Choi, J. Yi, Curr. Appl. Phys. 13, (2013) 246.
[17] S. Yang, D.H. Cho, M.K. Ryu, S.H.K. Park, C.S. Hwang, J. Jang, J.K. Jeong, Appl. Phys.
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Lett. 96, (2010) 213511.
[18] H. Oh, S. M. Yoon, M. K. Ryu, C. S. Hwang, S. Yang, S. H. K. Park, Appl. Phys. Lett. 97,
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(2010) 183502.
[19] M. D. H. Chowdhury, P. Migliorato, J. Jang, Appl. Phys. Lett. 97, (2010) 173506. [20] J. H. Shin, J. S. Lee, C. S. Hwang, S. H. K. Park, W. S. Cheong, M. Ryu, C. W. Byun, J. I. Lee, H. Y. Chu, ETRI J. 31, (2009) 62.
[21] K. H. Lee, J. S. Jung, K. S. Son, J. S. Park, T. S. Kim, R. Choi, J. K. Jeong, J. Y. Kwon, B. Koo, S. Lee, Appl. Phys. Lett. 95, (2009) 232106. [22] A. JanottiChris, G. Van de Walle, Appl. Phys. Lett. 87, (2005) 122102. [23] W. J. Lee, B. Ryu, K. J. Chang, Physica B 404, (2009) 4823. [24] S. Lany Alex Zunger, Phys. Rev. B 72, (2005) 035215. [25] A. Janotti, G. Van de Walle Chris, Phys. Rev. B 76, (2007) 165202. 9
ACCEPTED MANUSCRIPT [26] T. Kamiya, K. Nomura, M. Hirano, H. Hosono, Phys. Status. Solidi. A 206, (2009) 860. [27] H. Seo, C. J. Park, Y. J. Cho, Y. B. Kim, D. K. Choi, Appl. Phys. Lett. 96, (2010) 232101. [28] Y. H. Tai, H. L. Chiu, L. S. Chou, J. Electrochem. Soc. 159, (2012) 200.
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[29] K. M. Ko, S. Y. Lee, IEEJ T. Electr. Electr. 15, (2014) 328.
Figures
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Fig. 1. Schematic structure of the ZTO TFTs.
Fig. 2. Evolution of the transfer curves for various sputtering power, under negative gate-bias illumination stress for 3600s, (a) 30 W ZTO TFTs, (b) 50 W ZTO TFTs, (c) 75 W ZTO TFTs, (d) 100 W ZTO TFTs.
Fig. 3. The negative gate-bias illumination stress time dependence of △VT for ZTO TFTs with
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different sputtering power, Pas. and Unp. are various sputter power fabricated ZTO TFT with and without passivated layer, respectively. Fig. 4. Evolution of the transfer curves for devices with various sputtering power at different
EP
temperatures ranging from 293 k to 373k. (a) 30 W ZTO TFTs, (b) 50 W ZTO TFTs, (c) 75 W ZTO TFTs, (d) 100 W ZTO TFTs.
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Fig. 5. The relation between ID and 1/kT. Fig. 6 (a). Activation energy ( Ea ) as a function of gate voltage. (b). DOS of the ZTO TFTs for various sputtering power.
Fig. 7. The top-view AFM image of ZTO active layer. (a) 30 W ZTO TFTs (b) 50 W ZTO TFTs, (c) 75 W ZTO TFTs, (d) 100 W ZTO TFTs.
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in defect-induced trap densities channel-insulator interface trap densities
S0749-6036(15)30213-5
DOI:
10.1016/j.spmi.2015.09.036
Reference:
YSPMI 4000
To appear in:
Superlattices and Microstructures
Received Date: 10 July 2015 Revised Date:
27 September 2015
Accepted Date: 29 September 2015
Please cite this article as: C.-X. Huang, J. Li, Y.-Z. Fu, J.-H. Zhang, X.-Y. Jiang, Z.-L. Zhang, Origin of the improved stability under negative gate-bias illumination stress in various sputtering power fabricated ZnSnO TFTs, Superlattices and Microstructures (2015), doi: 10.1016/j.spmi.2015.09.036. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
ACCEPTED MANUSCRIPT
Origin of the improved stability under negative gate-bias illumination stress in various sputtering power fabricated ZnSnO TFTs
RI PT
Chuan-Xin Huang a, Jun Li a,b∗∗,Yi-Zhou Fu a, Jian-Hua Zhang b, Xue-Yin Jiang a, Zhi-Lin Zhang a, b a
School of Material Science and Engineering, Shanghai University, Jiading, Shanghai 201800, People’s Republic of China. b
Key Laboratory of Advanced Display and System Applications, Ministry of Education, Shanghai University,
SC
Shanghai 200072, People’s Republic of China.
Abstract
M AN U
In this work, we report the influence of ZnSnO channel layer sputtering power in the stability of ZnSnO TFTs under negative gate-bias illumination stress (NBIS). The origin of threshold voltage shift results from combined effect of two factors between the little defect-induced trap densities originated from oxygen vacancies and better channel-insulator interface. The kinetic energy of the ions at a proper rf sputtering
TE D
power is responsible for less defect-induced trap density and better channel-insulator interface. Therefore, the ZnSnO TFT fabricated at 75 W sputtering power shows a better
NBIS
stability.
In
addition,
the
trap
density
is
extracted
by
EP
temperature-dependent field-effect measurements and it is consistent with the change of stability under NBIS and thermal stress. Keywords: ZnSnO TFTs, rf sputtering power, ALD Al2O3, negative gate-bias
AC C
illumination stability.
1. Introduction
Amorphous oxide semiconductors (AOS) thin films are promising next generation
materials for use as active channel layers to replace conventional amorphous and polycrystalline silicon in thin film transistors (TFTs). Several groups have demonstrated various AOSs such as zinc oxide (ZO), indium oxide (IO), indium zinc oxide (IZO) and indium gallium zinc oxide (IGZO) composition and surveyed ∗
Corresponding author: E-mail address: [email protected] 1
ACCEPTED MANUSCRIPT stabilizer ions (Hf, Zr, Li, Mg and Al et. al) in an oxide system [1-9]. Among this AOS material, IGZO TFTs have high field-effect mobility, a small subthreshold swing, good uniformity attributed to the amorphous structure, a low off current, good stability under electrical stress, and can be processed at low temperatures. However,
RI PT
the IGZO channel has also disadvantages such as cost, toxicity and scarcity. Thus, indium-free and gallium-free AOS channel materials such as zinc-tin-oxide (ZTO) have been studied. Several research groups have already reported ZTO semiconductor materials for use as active channel layers in TFTs because of its remarkable electrical, [10–12]
. Although ZTO semiconductor materials
SC
optical properties and smooth surface
as active channel layers in TFTs show significant advantages, some outstanding issues
M AN U
still remain to be resolved, such as stability under bias, temperature and illumination stress.
In general, the quality of the active channel layers has a great influence in stability of TFTs and it can be controlled by various sputtering parameters, such as substrate temperature, oxygen partial pressure, working pressure
[13]
, and in particular, the
TE D
sputtering power [14,15]. Several groups have reported the effect of sputtering power on stability of TFTs. Raja et al. [16] reported that the densification of the proper sputtering power fabricated a-IGZO film resulted in the reduction of its interface trap density,
EP
which contributed to the improvement in the bias stability. Kim et al. [15] reported that the IGZO TFTs with different rf sputtering power showed various temperature stability, which resulted from the trap densities in deep level extracted by MFM
AC C
method. However, the investigation of instability under negative gate-bias illumination stress for various sputtering power fabricated ZTO TFTs has never been reported, which is the most important issue for the practical applications, because most of the proposed uses of TFTs will expose the TFTs to a backlight or ambient light during operation. In this paper, for the first time, we investigate the stability under negative gate-bias illumination stress for various sputtering power fabricated ZTO TFTs. The origin of improved the stability under negative gate-bias illumination stress in proper sputtering power fabricated ZTO TFTs is attributed to two aspects, including the little 2
ACCEPTED MANUSCRIPT defect-induced trap density originated from oxygen vacancies and better channelinsulator interface. In addition, the stability under thermal stress is investigated by trap density. The trap density is extracted by temperature-dependent field-effect measurements method, which is a fast, simple and accurate method.
RI PT
2. Experimental details We fabricated the top-contact-type ZTO TFTs with Al2O3 gate insulators on the highly-doped Si substrate. Fig. 1 shows the schematic structure of the device. An Al2O3 gate insulator approximately 200 nm thick was deposited by ALD. ZTO films
SC
with a thickness of 36 nm were deposited by rf-magnetron sputtering at room temperature using a ZTO target at input power of A: 30 W, B: 50 W, C: 75 W and D:
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100 W. Chamber pressure before sputtering was 5×10-4 Pa, and total pressure was 0.5 Pa. After deposition of ZTO films, all devices were annealed at 350 °C for 1 h in atmosphere then about 200 nm Al was deposited by thermal evaporation to form the source and drain electrodes through a shadow-mask with the channel width (W) of 1000 µm and channel length (L) of 50 µm. Finally, all devices were capped with a PE
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passivation layer and sequentially annealed at 250 °C for 10 min in atmosphere. The thickness of the film was measured by the alpha step (Alpha-Step IQ). The electrical characteristics of ZTO-TFTs were measured using Agilent E3647A Dual output DC
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power supply and Keithley 6485 Picoammeter and related software. The capacitance characteristics were measured using Agilent E4980A LRC meter.
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3. Result and discussion
Fig. 2 shows the evolution of the transfer curves as a function of the negative
gate-bias illumination stress time for devices A, B, C and D, respectively. A white light source with a photo intensity of 4000 lux. is used under identical -10 V negative gate-bias stress and 0 V drain-bias stress. As seen in Fig. 2, the off-state current increases and the transfer characteristics of all devices shift toward the negative direction as negative gate-bias illumination stress time increases. In particular, the device with different rf sputtering power shows various threshold voltage (VT) shift under negative gate-bias illumination stress and the Fig. 3 shows the negative 3
ACCEPTED MANUSCRIPT gate-bias illumination stress time dependence of threshold voltage shift (△VT = VT0s-VTxs) for ZTO TFTs with different sputtering power. In previous report, the instability of TFTs under negative gate-bias illumination stress is
attributed to the
following three mechanisms, including the oxygen photo-desorption model [18,19]
, the
and the photo-created
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photo-transition model from deep level [VO] to [VO2+]
[17]
hole carrier trapping model [20,21].
The oxygen photo-desorption model means the dynamic desorption of the adsorbed oxygen molecules on the ZTO back surface through the photon excitation
[17]
. When
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the devices without passivated layer are expected to the light and bias stress, the dynamic concentration of adsorbed oxygen molecules will be affected. For example, of negative
gate-bias
illumination
stress
will cause the
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the application
photo-desorption of adsorbed oxygen molecules, which will release the free electron and result in a negative VT shift. However, in our case, the devices are capped with a PE passivation layer, which will prevent the occurring of photo-desorption of adsorbed oxygen molecules. As seen in the Fig. 3, 75 W sputter power fabricated
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ZTO TFT without passivated layer (Unp.) shows larger △VT than 75 W sputter power fabricated ZTO TFT with a passivated layer (Pas.). This behavior indicates that the passivated layer has a very important role in restraining desorption of the adsorbed
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oxygen molecules. Therefore, the oxygen photo-desorption model is excluded. The second plausible model is related to the oxygen vacancies. It has been reported that in n-type Zn based oxide semiconductors, [VO] acts as a negative U defect center . Interestingly, photon energy can excite the transition of the [VO] ground state to
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[22, 23]
the meta-stable [VO2+] excited states, resulting in the formation of delocalized free electrons in the conduction band. The photo-generated electrons are responsible for increasing of off-state current and the negative VT shift of the ZTO TFTs under negative gate-bias illumination stress
[22, 24, 25]
. Therefore, the different shift of VT can
be explained by the various [VO] densities in different sputtering power fabricated ZTO channel layer. In particular, it has been reported that defect-induced trap density are commonly originated from oxygen vacancies in oxide-based semiconductors 26, 27]
, and the sputtering power also has a great effect on the trap density 4
[8, 22, [15]
.
ACCEPTED MANUSCRIPT Therefore, trap density can be used to describe [VO] densities roughly and explain why the device with different sputtering power fabricated ZTO channel layer shows various shift of VT under negative gate-bias illumination stress. To further investigate the effect of the trap density originated from oxygen vacancies under different sputtering power on the stability of ZTO TFTs under
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negative gate-bias illumination stress, we have observed trap density by temperature-dependent field-effect measurements. Fig. 4 shows the transfer curves of different sputtering power fabricated ZTO TFTs under thermal stress from 298 k to 373 k in dark state. As shown in Fig. 4, the negative shift of VT and increasing of
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off-state current with increasing the temperature for all of ZTO TFTs result from the generation of thermally activated carrier from traps in the band gap of ZTO. In
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particular, the △VT for different rf sputtering power fabricated device is △VTA = 15.2 V, △VT B = 12 V, △VT C = 5.8 V and △VT D = 10 V under thermal stress, respectively. The reduction in △VT value with proper sputtering power is consistent well with that when the negative gate-bias illumination is stressed. The thermally activated drain current in the subthreshold region is given as
(1)
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I D = I D 0 ⋅ exp(− Ea kT )
Where Ea is the activation energy, ID0 the prefactor, k the Boltzmann constant and T the temperature. ID0 and Ea at different gate voltages (VGS) can be easily derived by plotting logarithm ID versus 1/kT, as shown in Fig. 5. The curves of activation energy
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with gate voltage for different rf sputtering power fabricated ZTO TFTs is shown in
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Fig. 6 (a). From the Fig. 6 (a), we estimated the falling rates ( d (E a ) d (VGS ) of the various rf sputtering power fabricated ZTO TFTs. The values are 0.25, 0.50, 0.65 and 0.75 eV/V, respectively. The thermal excitation of the trapped charge can be calculated by the falling rate d (E a ) d (VGS ) , which should have the same magnitude as the rate of increase in EF and moreover the rising rate of EF with respect to VGS is roughly inversely proportional to the magnitude of the bulk and interface trap density [4]
, so the trap density is roughly inversely proportional to falling rates
( d (E a ) d (VGS ) and the detailed distribution of trap density within energy band gap in ZTO TFTs can be described by the following equation [28]: 5
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εi
d (Ea ) qdi t d (VGS )
(2)
Where ε i and di are the permittivity and the thickness of the gate insulator, q is the
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electron charge, and t is the thickness of the channel layer. Fig. 6 (b) shows the trap density in the energy band gap of ZTO TFTs. It is observed that the trap density of ZTO TFTs decreases firstly from 2.0×1016 eV-1cm-3 to 5.0×1015 eV-1cm-3 and then increases to 8.0×1015 eV-1cm-3 as the rf sputtering power increases from 30 W to 100
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W. This result is consistent with the findings of previous studies that better temperature stability of proper sputtering power fabricated IGZO and SZTO TFTs is [15, 29]
. The certain asperities insufficient to be removed by
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due to less trap densities
the kinetic energy of the ions at smaller sputtering power and etching effect of increasing high energetic ions at large rf sputtering power are responsible for the increasing trap density
[16]
. Moreover, defect-induced trap density are commonly
originated from oxygen vacancies in oxide-based semiconductors, so there are less
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oxygen vacancies in 75 W sputter power fabricated ZTO TFTs. Therefore, from [VO] densities aspect, the trap density can be used to explain why the device with different sputtering power fabricated ZTO channel layer shows various shift of VT under
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negative gate-bias illumination stress.
The photo-created hole carrier trapping model is explained from aspect of interfacial trap densities, so the sub-threshold swing (SS) related to interfacial trap
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densities is investigated. The SS of device A, B, C and D can be deduced by the follow relation from the initial transfer curves (0 min) in Fig. 2. SS =
dVGS d (logI DS )
(3)
Here, we evaluate the SS values to be 0.54, 0.45, 0.35 and 0.42 V/dec. From SS, we can infer the maximum density of surface states at the channel- insulator interface as:
SS log(e ) Ci max N SS = − 1 kT q q 6
(4)
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are calculated for the various rf sputtering power fabricated ZTO TFTs. since the kinetic energy of the ions at smaller sputtering power is insufficient to remove certain asperities and hence the channel-insulator interface is not very smooth. However,
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further increasing the rf sputtering power to 100 W causes the surface of film to become ragged with largest interface trap density of 1.25×1012 cm-2. These phenomena are resulted from the etching of the surface by increasing high energetic ions. This result shows that the interface trap density reduces firstly and then increases
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as the rf sputtering power increases from 30 W to 100 W, and it is consistent with the change trend of interface trap density in IGZO TFTs reported by Raja et al.
[16]
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surface morphology of ZTO films with various sputtering power confirm these behaviors and their AFM image is shown in Fig. 7. As seen in the figure, with the increase of sputtering powers, the morphology of ZTO films are improved firstly and then declines dramatically. The RMS for 30, 50, 75, and 100 W ZTO films is 7.36, 5.07, 3.46 and 4.22 nm, respectively.
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In particular, the electron-hole pairs as a result of photoexcitation will be generated in the channel region under the light illumination. The generated hole carrier will be attracted toward the interface of the channel layer and gate dielectric layer due to the
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negative charge at the gate electrode under a negative-gate bias. This accumulated hole can be trapped at the interfacial trap sites or injected into the underlying gate
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dielectric layer, which leads to a negative VTH shift. Because the device C with 75 W sputtering power fabricated ZTO film shows the least interface trap density of 1.0×1012 cm-2, there are the least hole trapped at channel-insulator interface. Therefore, the device C shows little shift of VT than device A, B, D and we suggest that the better stability of device C under a negative-gate bias can also be attributed to the least interfacial trap densities. 4. Conclusion
The origin of VT shift with various rf sputtering power fabricated ZTO TFTs under a negative-gate bias is experimentally provided and analyzed through combined effect 7
ACCEPTED MANUSCRIPT of two factors between the little defect-induced trap density originated from oxygen vacancies and better channel-insulator interface. The kinetic energy of the ions at proper rf sputtering power is responsible for little defect-induced trap density and better channel-insulator interface. Since the certain asperities insufficient to be
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removed by the kinetic energy of the ions at smaller sputtering power and etching effect of increasing high energetic ions at large rf sputtering power result in the increasing of trap density and worse channel-insulator interface. Therefore, the stability under a negative-gate bias is improved with proper sputtering power and the
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TFTs fabricated by rf sputter should be carefully optimized to provide better stability
5. Acknowledgements
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for ZTO in terms of power.
The authors would like to acknowledge the financial support given by the Natural Science Foundation of China (51302165, 61274082, 61077013), 863 project (2010AA3A337, 2008AA03A336), Innovation Fund of shanghai University,
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Shanghai Municipal Education Commission (ZZSD13047), China Postdoctoral Science Special Fund (2015T50837) and Shanghai Science and Technology
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Figures
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Fig. 1. Schematic structure of the ZTO TFTs.
Fig. 2. Evolution of the transfer curves for various sputtering power, under negative gate-bias illumination stress for 3600s, (a) 30 W ZTO TFTs, (b) 50 W ZTO TFTs, (c) 75 W ZTO TFTs, (d) 100 W ZTO TFTs.
Fig. 3. The negative gate-bias illumination stress time dependence of △VT for ZTO TFTs with
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different sputtering power, Pas. and Unp. are various sputter power fabricated ZTO TFT with and without passivated layer, respectively. Fig. 4. Evolution of the transfer curves for devices with various sputtering power at different
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temperatures ranging from 293 k to 373k. (a) 30 W ZTO TFTs, (b) 50 W ZTO TFTs, (c) 75 W ZTO TFTs, (d) 100 W ZTO TFTs.
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Fig. 5. The relation between ID and 1/kT. Fig. 6 (a). Activation energy ( Ea ) as a function of gate voltage. (b). DOS of the ZTO TFTs for various sputtering power.
Fig. 7. The top-view AFM image of ZTO active layer. (a) 30 W ZTO TFTs (b) 50 W ZTO TFTs, (c) 75 W ZTO TFTs, (d) 100 W ZTO TFTs.
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in defect-induced trap densities channel-insulator interface trap densities